Concave PGaN gate enhanced HEMT and preparation method thereof

Abstract

The invention discloses a concave PGaN gate enhanced HEMT (High Electron Mobility Transistor) and a preparation method thereof, and belongs to the technical field of semiconductors. The epitaxial structure is located on the surface of the substrate; the concave PGaN gate structure is located on the surface of the barrier layer in the epitaxial structure; the concave PGaN gate structure comprises a concave PGaN layer, a dielectric layer and a gate from bottom to top; the source electrode and the drain electrode are located on the surface of the barrier layer and located on the two sides of the concave PGaN gate structure respectively; and the passivation layer covers the surfaces of the source electrode, the drain electrode, the concave PGaN gate structure and the barrier layer. Due to the fact that the introduced concave PGaN gate structure is an MIS structure, the device saturation current is large, the insulated dielectric layer can reduce the gate leakage current of the device, the gate withstand voltage is increased, and the threshold voltage is more stable. Besides, the shape of the PGaN layer is changed through two times of etching in the preparation process, so that after the PGaN exhausts two-dimensional electron gas below the PGaN, a certain current is recovered through etching the middle part of the PGaN, and the on resistance of the device is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a concave PGaN gate enhanced HEMT and a preparation method thereof. Background Art

[0002] As power electronic systems develop towards higher operating frequencies and power densities, the demand for power semiconductor devices with high reliability, low power consumption and low cost is becoming more significant. Gallium nitride (GaN), as a third-generation semiconductor material, has many advantages such as large bandgap, high temperature and high pressure resistance, and high electron saturation velocity. GaN-based high electron mobility transistor devices generate a conductive channel by forming a high-concentration, high-mobility two-dimensional electron gas at the heterojunction, thereby achieving device conduction. Due to its excellent characteristics such as high thermal conductivity, low on-resistance, and tolerance to high-frequency and high-voltage conditions, it is widely used in power supplies, automotive electronics, 5G base stations and other fields. GaN-based HEMT devices have become a research hotspot in the field of high-frequency and high-power devices and switching devices.

[0003] At present, GaN-based HEMTs are divided into depletion-mode HEMTs and enhancement-mode HEMTs according to whether the channel exists when the gate is not biased. Depletion-mode GaN-based HEMTs will cause higher switching losses without external bias, and also require additional negative bias to maintain the non-working state (off state), which increases circuit power consumption and greatly limits their applications. On the contrary, in the field of power electronics applications, enhancement-mode devices can avoid the risk of false start-up and reduce the complexity of gate drive, which has greater advantages. Therefore, enhancement-mode GaN-based HEMT devices have become the main research direction at present.

[0004] Specifically, the mainstream preparation technologies for enhanced GaN-based HEMT devices include: fluorine (F) ion implantation technology, recessed gate structure, common source and common gate cascade structure and P-GaN gate structure. Among them, the P-GaN gate structure is the most widely used and most promising preparation method for enhanced HEMT devices, but it still has some limitations in performance and preparation process, such as low saturation leakage current, weak gate control ability and reliability issues such as threshold voltage drift of P-GaN gate HEMT. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a concave PGaN gate enhanced HEMT and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] In a first aspect, the present invention provides a concave PGaN gate enhancement mode HEMT, comprising:

[0007] substrate;

[0008] An epitaxial structure located on the surface of the substrate; the epitaxial structure at least comprises a barrier layer;

[0009] A concave PGaN gate structure is located on the surface of the barrier layer away from the substrate; the concave PGaN gate structure comprises: a concave PGaN layer, a dielectric layer and a gate, wherein the concave PGaN layer comprises a groove, the dielectric layer is located on the surface of the groove, and the gate is located on the surface of the dielectric layer away from the barrier layer;

[0010] A source electrode and a drain electrode are located on the surface of the barrier layer away from the substrate, and the source electrode and the drain electrode are respectively located on two sides of the concave PGaN gate structure;

[0011] A passivation layer covers the surfaces of the source electrode, the drain electrode, the concave PGaN gate structure and the barrier layer.

[0012] In one embodiment of the present invention, the material of the concave PGaN layer includes GaN doped with P-type impurities, and the P-type impurities include Mg.

[0013] In one embodiment of the present invention, the material of the dielectric layer includes at least one of Al2O3, AlTiO, AlON, SiO2, Si3N4 and HfO2, and the thickness of the dielectric layer is less than 100 nm.

[0014] In one embodiment of the present invention, the epitaxial structure further includes a channel layer located on the surface of the barrier layer close to the substrate, and the material of the channel layer includes GaN, and the thickness is less than 500 nm.

[0015] In one embodiment of the present invention, it further comprises a first ion implantation region and a second ion implantation region disposed oppositely at two ends of the epitaxial structure to separate the active regions of each concave PGaN gate enhancement type HEMT; wherein,

[0016] The first ion implantation region and the second ion implantation region both penetrate downward from the barrier layer to a portion of the channel layer.

[0017] In one embodiment of the present invention, the material of the barrier layer includes AlGaN or InGaN, and the thickness of the barrier layer is less than 100 nm.

[0018] In one embodiment of the present invention, the material of the passivation layer includes: Al2O3, Al 0.5 Ti 0.5 O, AlON, SiO2, Si3N4 or HfO2, and the thickness of the passivation layer is less than 300nm.

[0019] In a second aspect, the present invention provides a method for preparing a concave PGaN gate enhancement mode HEMT, comprising:

[0020] Providing a wafer substrate, the wafer substrate comprising, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a PGaN layer;

[0021] Performing a first step of etching on the PGaN layer to remove a portion of the PGaN layer at both ends, and then performing a second step of etching on the remaining PGaN layer to form a groove to obtain a concave PGaN layer;

[0022] Depositing an insulating material on the surface of the groove of the concave PGaN layer to form a dielectric layer;

[0023] Prepare a source electrode and a drain electrode on the surface of the barrier layer, respectively, so that the source electrode and the drain electrode are located on two sides of the concave PGaN layer respectively;

[0024] Prepare a gate on the surface of the dielectric layer to form a concave PGaN gate structure;

[0025] A passivation layer is grown on the surface of the device, and holes are opened in the passivation layer on the surface of the source, drain and gate to achieve metal interconnection, thereby obtaining the concave PGaN gate enhanced HEMT.

[0026] In one embodiment of the present invention, before the step of preparing a gate on the surface of the dielectric layer to form a concave PGaN gate structure, the method further includes:

[0027] Ion implantation is performed at two ends of the barrier layer to form a first ion implantation region and a second ion implantation region; the implantation depths of the first ion implantation region and the second ion implantation region are greater than the thickness of the barrier layer.

[0028] In one embodiment of the present invention, the implanted ions are nitrogen ions or fluorine ions.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The present invention provides a concave PGaN gate enhanced HEMT, which introduces a concave PGaN gate structure, which includes a concave PGaN layer, a dielectric layer and a gate from bottom to top, and the formed MIS structure has a large device saturation current. The insulating dielectric layer can reduce the gate leakage current of the device, increase the gate withstand voltage, and make the threshold voltage more stable. In addition, the PGaN on the two side walls of the concave PGaN layer can adjust the electric field and improve the dynamic resistance.

[0031] In addition, the present invention also provides a method for preparing a concave PGaN gate enhanced HEMT. In the process of etching the PGaN layer to form the concave PGaN layer, the shape of the PGaN is changed by etching twice. The first etching removes the parts at both ends of the PGaN layer until the barrier layer is exposed, and the second etching reduces the thickness of the middle part of the remaining PGaN layer. That is, after using PGaN to deplete the two-dimensional electron gas below, a certain current is restored by etching the PGaN in the middle part, which can reduce the depletion effect on the two-dimensional electron gas in the channel layer, increase the concentration of the two-dimensional electron gas when the channel is turned on, and thus reduce the on-resistance of the device.

[0032] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic structural diagram of a concave PGaN gate enhancement mode HEMT provided by an embodiment of the present invention;

[0034] Figure 2 is a flow chart of a method for preparing a concave PGaN gate enhancement mode HEMT provided by an embodiment of the present invention;

[0035] Figures 3 to 10 It is a schematic diagram of the preparation process of the concave PGaN gate enhancement mode HEMT provided in this embodiment. DETAILED DESCRIPTION

[0036] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0037] Figure 1 Schematic diagram of the structure of a concave PGaN gate enhancement type HEMT provided by an embodiment of the present invention. Figure 1 As shown, an embodiment of the present invention provides a concave PGaN gate enhancement mode HEMT, comprising:

[0038] Substrate 1;

[0039] The epitaxial structure 2 is located on the surface of the substrate 1; the epitaxial structure 2 at least includes a barrier layer 201;

[0040] The concave PGaN gate structure 3 is located on the surface of the barrier layer 201 away from the substrate 1; the concave PGaN gate structure 3 includes: a concave PGaN layer 301, a dielectric layer 302 and a gate G, wherein the concave PGaN layer 301 includes a groove, the dielectric layer 302 is located on the surface of the groove, and the gate G is located on the surface of the dielectric layer 302 away from the barrier layer 201;

[0041] The source S and the drain D are located on the surface of the barrier layer 201 away from the substrate 1, and the source S and the drain D are respectively located on two sides of the concave PGaN gate structure 3;

[0042] The passivation layer 4 covers the surface of the source S, the drain D, the concave PGaN gate structure 3 and the barrier layer 201 .

[0043] Specifically, the epitaxial structure 2 includes a nucleation layer 202, a buffer layer 203, a channel layer 204 and a barrier layer 201 from bottom to top. The above-mentioned concave PGaN gate enhancement HEMT introduces a concave PGaN gate structure 3, which includes: a concave PGaN layer 301, a dielectric layer 302 and a gate G, wherein the dielectric layer 302 is located in the groove of the concave PGaN layer 301, and the gate G is located on the upper surface of the dielectric layer 302, forming a metal-insulating layer-semiconductor layer structure (MIS structure). The MIS structure has a large device saturation current, and the insulating dielectric layer 302 can reduce the gate leakage current of the device, increase the gate withstand voltage, and make the threshold voltage more stable.

[0044] In addition, the PGaN on the two side walls of the concave PGaN layer 301 can participate in depleting the two-dimensional electron gas, which is beneficial to reducing the electric field peak and improving the dynamic resistance.

[0045] Optionally, the material of the concave PGaN layer 301 includes GaN doped with P-type impurities, the P-type impurities include Mg, and the thickness of the concave PGaN layer 301 is less than 200 nm and the width is less than 50 nm.

[0046] Optionally, the material of the barrier layer 201 includes AlGaN or InGaN, and the thickness of the barrier layer 201 is less than 100 nm. Further, the material of the dielectric layer 302 includes at least one of Al2O3, AlTiO, AlON, SiO2, Si3N4 and HfO2, and the thickness of the dielectric layer 302 is less than 100 nm. The material of the passivation layer 4 includes: Al2O3, Al 0.5 Ti 0.5 O, AlON, SiO2, Si3N4 or HfO2, the thickness of the passivation layer 4 is less than 300nm.

[0047] In this embodiment, the epitaxial structure 2 further includes a channel layer 204 located on the surface of the barrier layer 201 close to the substrate 1 . The material of the channel layer 204 includes GaN, and the thickness is less than 500 nm.

[0048] Optionally, the concave PGaN gate enhancement type HEMT further includes a first ion implantation region 501 and a second ion implantation region 502 which are relatively arranged at two ends of the epitaxial structure 2 to separate the active regions of each concave PGaN gate enhancement type HEMT; wherein both the first ion implantation region 501 and the second ion implantation region 502 penetrate downward from the barrier layer 201 to a portion of the channel layer 204.

[0049] Figure 2 is a flow chart of a method for preparing a concave PGaN gate enhancement mode HEMT provided by an embodiment of the present invention, Figures 3 to 10 FIG. 1 is a schematic diagram of the preparation process of the concave PGaN gate enhancement mode HEMT provided in this embodiment. Figures 2 to 10 As shown, an embodiment of the present invention further provides a method for preparing a concave PGaN gate enhancement mode HEMT, comprising:

[0050] S1. Provide a wafer substrate, which includes, from bottom to top, a substrate 1, a nucleation layer 202, a buffer layer 203, a channel layer 204, a barrier layer 201 and a PGaN layer;

[0051] S2, performing a first step of etching on the PGaN layer to remove part of the PGaN layer at both ends, and then performing a second step of etching on the remaining PGaN layer to form a groove, thereby obtaining a concave PGaN layer 301;

[0052] S3, depositing an insulating material on the surface of the groove of the concave PGaN layer 301 to form a dielectric layer 302;

[0053] S4, preparing a source electrode S and a drain electrode D on the surface of the barrier layer 201, respectively, so that the source electrode S and the drain electrode D are located on both sides of the concave PGaN layer 301;

[0054] S5, preparing a gate G on the surface of the dielectric layer 302 to form a concave PGaN gate structure 3;

[0055] S6. A passivation layer 4 is grown on the surface of the device, and holes are opened in the passivation layer 4 on the surfaces of the source S, the drain D and the gate G to achieve metal interconnection, thereby obtaining a concave PGaN gate enhancement type HEMT.

[0056] Specifically, in the process of preparing the concave PGaN gate enhancement mode HEMT, firstly, a wafer substrate is provided, such as Figure 3As shown, the wafer substrate includes a substrate 1, a nucleation layer 202, a buffer layer 203, a channel layer 204, a barrier layer 201 and a PGaN layer from bottom to top; wherein, the substrate 1 material can be one of sapphire, SOI (silicon on insulator), Si, GaN, SiC, diamond and other composite substrate 1 materials, the nucleation layer 202 material includes AlN or AlGaN, and the thickness is less than 10nm, the buffer layer 203 material includes GaN, AlN, AlGaN or InGaN, and its thickness is less than 2um, the channel layer 204 material is GaN, and the thickness is less than 500nm, and the barrier layer 201 material includes AlGaN or InGaN, and its thickness is less than 100nm.

[0057] The wafer substrate is cleaned to remove organic ion impurities and pollutants on the wafer surface, and the corresponding mask is used for Mark layer lithography and etching. ICP (inductively coupled plasma) dry etching is used for etching GaN materials, and a certain proportion of Cl2 and BCl3 are selected as ICP etching gas. A mark layer for subsequent photolithography layer shell is formed on the wafer substrate.

[0058] Next, a concave PGaN gate structure 3 is prepared. Figures 4-5 As shown, in step S2, the wafer substrate is cleaned to wash away the residual photoresist and other impurities on the surface of the wafer substrate, and then the corresponding mask is used to perform PGaN Cap (cap layer) photolithography and etching. For example, ICP (inductively coupled plasma) dry etching is selectively used to perform the first step of etching on both ends of the PGaN layer. The ICP etching gas selects a certain proportion of Cl2, BCl3, O2, and N2. This process requires a higher PGaN / AlGaN selectivity and strictly controls the etching depth. The PGaN at both ends is etched just to the AlGaN barrier layer 201 to prevent over-etching, otherwise it will cause the saturation current of the device to decrease.

[0059] Further, the remaining PGaN layer is etched in the second step. First, the wafer substrate is cleaned to remove the residual photoresist and other impurities, and then the concave PGaN layer 301 is photolithographically and etched using a corresponding mask, and the process is similar to the first step of etching. It should be noted that the etching depth should be strictly controlled in the second step of etching to retain a certain thickness of the PGaN layer to prevent over-etching, otherwise the ability of PGaN to deplete the two-dimensional electron gas will be reduced, thereby reducing the threshold voltage and even turning it into a depletion-type device.

[0060] It can be seen that in the process of etching the PGaN layer to form the concave PGaN layer 301, the shape of the PGaN is changed by etching twice in this embodiment. In the first etching, parts of the two ends of the PGaN layer are removed until the barrier layer 201 is exposed, and the remaining PGaN layer is rectangular. The second etching reduces the thickness of the middle part of the remaining PGaN layer to obtain the concave PGaN layer 301. That is, after using PGaN to deplete the two-dimensional electron gas below and then etching part of the PGaN to restore the current, this method can reduce the depletion effect on the two-dimensional electron gas in the channel layer 204, increase the two-dimensional electron gas concentration when the channel is turned on, and thus increase the saturation current of the device. The MIS structure formed after the dielectric layer 302 is deposited in the groove can reduce etching damage, effectively reduce the gate leakage of the device, and improve the gate withstand voltage capability of the device, so that the device can operate at a higher voltage with lower energy consumption.

[0061] It should be noted that in the prior art, MIS-HEMT can only realize depletion-type GaN devices. If an enhanced GaN device is to be realized, the AlGaN barrier layer under the gate needs to be etched until the channel is cut off. Therefore, the etching damage is large, which will lead to increased gate leakage, poor process repeatability, unstable threshold voltage and poor controllability. In this embodiment, the barrier layer is not etched during the preparation process, but the enhanced device is realized by using PGaN to deplete the two-dimensional electron gas. Although the PGaN layer is etched for the second time, the etching damage can be effectively repaired after a dielectric layer is deposited in the groove, and the gate is farther away from the channel, so the gate leakage is reduced and the gate breakdown voltage is higher. In addition, the main advantages of this patent in realizing the enhanced type compared to the existing MIS-HEMT are that the channel current density is larger, the gate leakage is lower, and the breakdown voltage is higher.

[0062] In step S3, the residual photoresist and impurities on the surface of the wafer substrate are first washed away, and then the sample is placed in a PEALD (plasma enhanced atomic layer deposition) reaction chamber, and then a thin layer of Al2O3 is deposited on the entire wafer substrate, and then a corresponding mask is used to perform photolithography and etching outside the groove to form Figure 6 The dielectric layer 302 is shown.

[0063] See also Figure 7In step S4, firstly, the photoresist and impurities remaining on the surface of the wafer substrate are washed away, and then the corresponding mask is used for Ohmic Metal photolithography, deposition and stripping. For example, E-Beam electron beam evaporation equipment can be used for deposition. The stacked layers of Ohmic Metal are Ti / Al or Ti / Al / Ni / Au, and Ni can also be replaced by Ti, Cr, Pt, Pd, Mo; then, annealing is performed at 850°C for 30s to form a good Ohmic contact. Among them, the source and drain D Ohmic metals are titanium / aluminum or titanium / aluminum / nickel. Of course, a combination of multi-layer alloys such as titanium / aluminum / nickel / gold can also be used.

[0064] Optionally, before the step of preparing a gate G on the surface of the dielectric layer 302 to form a concave PGaN gate structure 3, the process further includes:

[0065] Ion implantation is performed at both ends of the barrier layer 201 to form a first ion implantation region 501 and a second ion implantation region 502 . The implantation depths of the first ion implantation region 501 and the second ion implantation region 502 are greater than the thickness of the barrier layer 201 .

[0066] Specifically, see Figure 8 , wash away the residual photoresist and impurities on the surface of the wafer substrate, and then use the corresponding mask to perform photolithography and ion implantation. In this embodiment, the implanted ions are nitrogen ions or fluorine ions, which are used to form isolation regions between various devices and separate the active areas between various devices.

[0067] In step S5, the photoresist and impurities remaining on the surface of the wafer substrate are washed away. Since ion implantation may cause a certain degree of denaturation of the photoresist, there is still a certain amount of residue after cleaning, so it is necessary to use an ion glue device to remove the glue and then clean it again; then, Fig. 9 As shown, the corresponding mask is used to perform Gate Metal (gate G metal) lithography, deposition and stripping, and the metal deposition process still uses E-Beam electron beam evaporation equipment to deposit metal.

[0068] Optionally, the stacked layers of the gate G metal are Ni / Au or Pt / Au, and the gate G is in Schottky contact with the concave PGaN layer 301 .

[0069] like Fig.10 As shown, in step S6, after washing away the residual photoresist and other impurities on the surface of the wafer substrate, the sample is placed in a plasma chemical vapor deposition (PECVD) reaction chamber, and a certain thickness of SiO2 or SiN4 is deposited on the surface of the entire wafer substrate to form a passivation layer 4 for protecting the device surface. Specifically, the passivation layer 4 can reduce surface trap defects and thereby reduce surface leakage.

[0070] The wafer substrate is cleaned, and the corresponding mask is used for contact lithography and etching. Here, the RIE (reactive ion etching) etching process is selectively used. The main etching gas is CF4. The appropriate power and etching time are selected to directly go down the passivation layer 4 until the gate G, source S and drain D are exposed, and the metal electrodes are interconnected to form Figure 2 The recessed PGaN gate enhancement mode HEMT shown.

[0071] It can be seen from the above embodiments that the beneficial effects of the present invention are:

[0072] The present invention provides a concave PGaN gate enhanced HEMT, which introduces a concave PGaN gate structure, which includes a concave PGaN layer, a dielectric layer and a gate from bottom to top, and the formed MIS structure has a large device saturation current. The insulating dielectric layer can reduce the gate leakage current of the device, increase the gate withstand voltage, and make the threshold voltage more stable. In addition, the PGaN on the two side walls of the concave PGaN layer can adjust the electric field and improve the dynamic resistance.

[0073] In addition, the present invention also provides a method for preparing a concave PGaN gate enhanced HEMT. In the process of etching the PGaN layer to form the concave PGaN layer, the shape of the PGaN is changed by etching twice. The first etching removes parts of the two ends of the PGaN layer until the barrier layer is exposed, and the second etching reduces the thickness of the middle part of the remaining PGaN layer. That is, after using PGaN to deplete the two-dimensional electron gas below and then etching part of the PGaN to restore the current, the depletion effect on the two-dimensional electron gas in the channel layer can be reduced, and the concentration of the two-dimensional electron gas when the channel is turned on is increased, thereby increasing the saturation current of the device.

[0074] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0075] The description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0076] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A concave PGaN gate enhancement mode HEMT, characterized in that: include: substrate; An epitaxial structure, located on the surface of the substrate; The epitaxial structure comprises at least a barrier layer; A concave PGaN gate structure is located on the surface of the barrier layer away from the substrate; The concave PGaN gate structure comprises: a concave PGaN layer, a dielectric layer and a gate, wherein the concave PGaN layer comprises a groove, the dielectric layer is located on the surface of the groove, and the gate is located on the surface of the dielectric layer away from the barrier layer; A source electrode and a drain electrode are located on the surface of the barrier layer away from the substrate, and the source electrode and the drain electrode are respectively located on two sides of the concave PGaN gate structure; A passivation layer covers the surfaces of the source electrode, the drain electrode, the concave PGaN gate structure and the barrier layer.

2. The recessed PGaN gate enhancement mode HEMT according to claim 1, characterized in that: The material of the concave PGaN layer includes GaN doped with P-type impurities, and the P-type impurities include Mg.

3. The recessed PGaN gate enhancement mode HEMT according to claim 2, characterized in that: The material of the dielectric layer includes at least one of Al2O3, AlTiO, AlON, SiO2, Si3N4 and HfO2, and the thickness of the dielectric layer is less than 100nm.

4. The recessed PGaN gate enhancement mode HEMT according to claim 1, characterized in that: The epitaxial structure further includes a channel layer located on the surface of the barrier layer close to the substrate. The material of the channel layer includes GaN and has a thickness of less than 500 nm.

5. The recessed PGaN gate enhancement mode HEMT according to claim 4, characterized in that: It also includes a first ion implantation region and a second ion implantation region disposed oppositely at two ends of the epitaxial structure to separate the active regions of each concave PGaN gate enhanced HEMT; wherein, The first ion implantation region and the second ion implantation region both penetrate downward from the barrier layer to a portion of the channel layer.

6. The recessed PGaN gate enhancement mode HEMT according to claim 1, characterized in that: The material of the barrier layer includes AlGaN or InGaN, and the thickness of the barrier layer is less than 100 nm.

7. The recessed PGaN gate enhancement mode HEMT according to claim 1, characterized in that: The materials of the passivation layer include: Al2O3, Al 0.5 Ti 0.5 O, AlON, SiO2, Si3N4 or HfO2, and the thickness of the passivation layer is less than 300nm.

8. A method for preparing a concave PGaN gate enhanced HEMT, characterized in that: include: Providing a wafer substrate, the wafer substrate comprising, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a PGaN layer; Performing a first step of etching on the PGaN layer to remove a portion of the PGaN layer at both ends, and then performing a second step of etching on the remaining PGaN layer to form a groove to obtain a concave PGaN layer; Depositing an insulating material on the surface of the groove of the concave PGaN layer to form a dielectric layer; Prepare a source electrode and a drain electrode on the surface of the barrier layer, respectively, so that the source electrode and the drain electrode are located on two sides of the concave PGaN layer respectively; Prepare a gate on the surface of the dielectric layer to form a concave PGaN gate structure; A passivation layer is grown on the surface of the device, and holes are opened in the passivation layer on the surface of the source, drain and gate to achieve metal interconnection, thereby obtaining the concave PGaN gate enhanced HEMT.

9. The method for preparing a recessed PGaN gate enhanced HEMT according to claim 8, characterized in that: Before the step of preparing a gate on the surface of the dielectric layer to form a concave PGaN gate structure, the method further includes: Ion implantation is performed at two ends of the barrier layer to form a first ion implantation region and a second ion implantation region; the implantation depths of the first ion implantation region and the second ion implantation region are greater than the thickness of the barrier layer.

10. The method for preparing a recessed PGaN gate enhanced HEMT according to claim 9, characterized in that: The implanted ions are nitrogen ions or fluorine ions.

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