LDMOS device and method for forming the same

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and in particular to an LDMOS device and a method for forming the same. The LDMOS device comprises: a substrate comprising a front surface and a back surface relatively distributed along a first direction; a body region located within the substrate, the body region comprising a trench; a source region located within the body region, the source region being distributed on the sidewalls and bottom surface of the trench, the source region comprising a body contact region located on the bottom surface of the trench and a source doping region distributed around the periphery of the body contact region, the source doping region being in a bent shape and continuously distributed on the sidewalls and part of the bottom surface of the trench; a drift region located within the substrate, the drift region being distributed outside the body region along a second direction, the second direction being perpendicular to the first direction; and a drain region located within the drift region. The present invention can reduce the specific on-resistance of the LDMOS device while ensuring the overcurrent capability of the LDMOS device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an LDMOS device and a method for forming the same. Background Art

[0002] BCD (Bipolar-CMOS-DMOS) process technology is an advanced semiconductor manufacturing process that combines bipolar transistors, CMOS (complementary metal oxide semiconductor), and DMOS (double diffused metal oxide semiconductor) transistor technologies on a single chip. Bipolar transistors are primarily used for analog signal control, while CMOS and DMOS are used for digital signal control and high-power processing. Compared to traditional processes, BCD technology integrates three processes (bipolar transistor, CMOS, and DMOS) on a single chip, reducing the number of components and the rate of connection failure. Furthermore, BCD technology helps semiconductor devices dissipate heat more effectively, reducing reliability issues caused by overheating. The BCD process shortens the interconnect length between internal device structures, reducing parasitic inductance and thus electromagnetic interference generated by high-frequency switching. BCD technology also facilitates smaller chip areas.

[0003] The power output stage DMOS transistor is the core of the BCD chip circuitry, often occupying 1 / 2 to 2 / 3 of the total chip area. It is crucial for the entire integrated circuit. DMOS devices have a similar structure to CMOS devices, with source, drain, and gate electrodes, but the drain side has a higher breakdown voltage. There are two main types of DMOS: the vertical double-diffused MOSFET (VDMOSFET) and the lateral double-diffused MOSFET (LDMOSFET). LDMOS is widely adopted due to its greater compatibility with CMOS processes. LDMOS is a double-diffused power device that can withstand higher voltages and currents than CMOS while also offering lower on-resistance and switching losses. In theory, when the on-resistance is low, LDMOS devices offer excellent switching characteristics. This low on-resistance between the drain and source leads to higher output currents, resulting in stronger driving capabilities. However, current LDMOS devices have a high on-resistance, which limits their performance.

[0004] Therefore, how to reduce the specific on-resistance of the LDMOS device, thereby improving the switching characteristics of the LDMOS device and improving the performance of the LDMOS device, is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] The present invention provides an LDMOS device and a method for forming the same, which are used to reduce the on-resistance of the LDMOS device, thereby enhancing the switching characteristics of the LDMOS device and improving the performance of the LDMOS device.

[0006] According to some embodiments, the present invention provides an LDMOS device, comprising:

[0007] a substrate comprising a front surface and a back surface oppositely distributed along a first direction;

[0008] a body region located in the substrate, wherein the body region has a trench;

[0009] a source region located in the body region, the source region comprising a body contact region located on the bottom surface of the trench and a source doping region distributed around the periphery of the body contact region, the source doping region being in a meandering shape and continuously distributed on the sidewalls of the trench and a portion of the bottom surface of the trench;

[0010] a drift region located in the substrate and distributed outside the body region along a second direction, wherein the second direction intersects the first direction perpendicularly;

[0011] The drain region is located in the drift region.

[0012] In some embodiments, the substrate and the body region both include first-type dopant ions, the drift region and the drain region both include second-type dopant ions, and the conductivity type of the first-type dopant ions is opposite to the conductivity type of the second-type dopant ions;

[0013] The body contact region includes the first type of dopant ions, and the source dopant region includes the second type of dopant ions.

[0014] In some embodiments, an angle between a sidewall of the trench and a bottom surface of the trench is an obtuse angle.

[0015] In some embodiments, a width of the trench is smaller than a width of the body region, and a depth of the trench is greater than a depth of the drain region and smaller than a depth of the body region.

[0016] In some embodiments, the width of the groove is 0.3 μm to 0.4 μm, and the depth of the groove is 1500 Å to 2500 Å.

[0017] In some embodiments, further comprising:

[0018] A gate structure is located on the front surface of the substrate and is distributed between the drain region and the source region along the second direction. The gate structure includes a gate dielectric layer covering the front surface of the substrate, a gate conductive layer covering the surface of the gate dielectric layer, and a gate isolation layer covering the sidewalls of the gate dielectric layer and the sidewalls of the gate conductive layer.

[0019] In some embodiments, it further includes:

[0020] an interlayer dielectric layer covering the front surface of the substrate and filling the trench;

[0021] a source lead-out structure, penetrating the interlayer dielectric layer along the first direction and electrically connected to the source region;

[0022] a drain lead-out structure, penetrating the interlayer dielectric layer along the first direction and electrically connected to the drain region;

[0023] A gate lead-out structure penetrates the interlayer dielectric layer along the first direction and is electrically connected to the gate structure.

[0024] In some embodiments, it further includes:

[0025] a source contact layer, covering the surface of the source region and electrically connected to the source lead-out structure;

[0026] a drain contact layer, covering the surface of the drain region and electrically connected to the drain lead-out structure;

[0027] The gate contact layer covers the surface of the gate conductive layer and is electrically connected to the gate lead structure.

[0028] According to some other embodiments, the present invention further provides a method for forming an LDMOS device, comprising the following steps:

[0029] Providing a substrate, the substrate comprising a front surface and a back surface oppositely distributed along a first direction;

[0030] forming a body region and a drift region in the substrate, wherein the drift region is distributed outside the body region along a second direction, and the second direction is perpendicular to the first direction;

[0031] forming a trench in the body region;

[0032] A source region is formed on the sidewalls and the bottom surface of the trench, and a drain region is formed in the drift region. The source region includes a body contact region located on the bottom surface of the trench and a source doping region distributed around the periphery of the body contact region. The source doping region is in a bent shape and is continuously distributed on the sidewalls of the trench and part of the bottom surface of the trench.

[0033] In some embodiments, the substrate includes first type dopant ions; and the specific steps of forming the body region and the drift region in the substrate include:

[0034] implanting the first type of dopant ions into the substrate from the front surface of the substrate to form the body region, wherein the top surface of the body region is flush with the front surface of the substrate;

[0035] Second type dopant ions are injected into the substrate from the front surface of the substrate to form the drift region, the top surface of the drift region is flush with the front surface of the substrate, and the conductivity type of the first type dopant ions is opposite to the conductivity type of the second type dopant ions.

[0036] In some embodiments, the steps of forming the trench in the body region include:

[0037] The body region is etched from the top surface of the body region using a photochemical etching process to form the groove.

[0038] In some embodiments, the step of etching the body region from the top surface of the body region to form the trench further includes:

[0039] The etching parameters of the photochemical etching process are adjusted so that the angle between the sidewall of the formed trench and the bottom surface of the trench is an obtuse angle.

[0040] In some embodiments, the width of the groove is 0.3 μm to 0.4 μm, and the depth of the groove is 1500 Å to 2500 Å.

[0041] In some embodiments, before forming a source region on the sidewalls and the bottom of the trench and forming a drain region in the drift region, the method further includes the following steps:

[0042] The first type of dopant ions are implanted into the body region along the trench.

[0043] In some embodiments, the steps of forming a source region on the sidewalls and the bottom of the trench, and forming a drain region in the drift region include:

[0044] The source region including the body contact region and the source doping region is formed on the sidewalls of the trench and on the bottom surface of the trench, and the drain region is formed in the drift region, the body contact region includes the first type of doping ions, the source doping region includes the second type of doping ions, and the drain region includes the second type of doping ions.

[0045] In some embodiments, the front surface of the substrate further comprises a gate structure distributed along the second direction between the drain region and the source region, the gate structure comprising a gate dielectric layer covering the front surface of the substrate, a gate conductive layer covering the surface of the gate dielectric layer, and a gate isolation layer covering the sidewalls of the gate dielectric layer and the sidewalls of the gate conductive layer; after forming the source region on the sidewalls and the bottom surface of the trench and forming the drain region in the drift region, the following steps are further included:

[0046] A source contact layer electrically connected to the source region is formed on the surface of the source region, a drain contact layer electrically connected to the drain region is formed on the surface of the drain region, and a gate contact layer electrically connected to the gate conductive layer is formed on the surface of the gate conductive layer.

[0047] In some embodiments, after forming a source region on the sidewalls and the bottom of the trench and forming a drain region in the drift region, the method further includes the following steps:

[0048] forming an interlayer dielectric layer covering the front surface of the substrate and filling the trench;

[0049] A source lead-out structure is formed which penetrates the interlayer dielectric layer along the first direction and is electrically connected to the source contact layer, a drain lead-out structure is formed which penetrates the interlayer dielectric layer along the first direction and is electrically connected to the drain contact layer, and a gate lead-out structure is formed which penetrates the interlayer dielectric layer along the first direction and is electrically connected to the gate contact layer.

[0050] The LDMOS device and its formation method provided by the present invention achieve a three-dimensional LDMOS structure by providing a trench within a body region and distributing a source region on the sidewalls and bottom surface of the trench. The source region includes a body contact region located on the bottom surface of the trench and a source doping region distributed peripherally around the body contact region. The source doping region has a zigzag shape and is continuously distributed on the sidewalls of the trench and a portion of the bottom surface of the trench. Furthermore, because the trench can increase the area of ​​the source region, while ensuring the LDMOS device's saturation, the distance between the source and drain regions in the LDMOS device (i.e., the LDMOS pitch) can be reduced by reducing the size of the body region, thereby reducing the specific on-resistance of the LDMOS device and improving the performance of the LDMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly describes the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0052] Figure 1 2 is a schematic structural diagram of an LDMOS device in a specific embodiment of the present invention;

[0053] Figure 2 is a schematic structural diagram of the body region and the source region in a specific embodiment of the present invention;

[0054] Figure 3 is a flow chart of a method for forming an LDMOS device in a specific embodiment of the present invention;

[0055] Figure 4 is a schematic structural diagram after a body region and a drift region are formed in a substrate in a specific embodiment of the present invention;

[0056] Figure 5 is a schematic diagram of the structure after a trench is formed in the body region in a specific embodiment of the present invention;

[0057] Figure 6 is a schematic structural diagram after the source region and the drain region are formed in a specific embodiment of the present invention;

[0058] Figure 7 is a schematic structural diagram after forming a source contact layer, a drain contact layer, and a gate contact layer in a specific embodiment of the present invention;

[0059] Figure 8 A schematic diagram of the structure after forming an interlayer dielectric layer in a specific embodiment of the present invention;

[0060] Figure 9 It is a schematic structural diagram after forming a source contact hole, a drain contact hole and a gate contact hole in a specific embodiment of the present invention.

[0061] Description of Reference Numerals

[0062] 10 substrate

[0063] 11 body areas

[0064] 12 Drift Zone

[0065] 13. Drain region

[0066] 141 Body contact area

[0067] 142 source doping region

[0068] 15 grooves

[0069] 16 shallow trench isolation structure

[0070] 171 gate dielectric layer

[0071] 172 gate conductive layer

[0072] 173 gate isolation layer

[0073] 181 source contact layer

[0074] 182 drain contact layer

[0075] 183 gate contact layer

[0076] 184 substrate contact layer

[0077] 19 substrate contact area

[0078] 20 interlayer dielectric layers

[0079] 211 source lead structure

[0080] 212 drain lead structure

[0081] 213 gate lead structure

[0082] 214 substrate lead structure

[0083] 221 source lead pad

[0084] 222 drain lead pad

[0085] 223 gate lead pad

[0086] 224 substrate lead pad

[0087] 911 source contact hole

[0088] 912 drain contact hole

[0089] 913 gate contact hole

[0090] 914 substrate contact hole DETAILED DESCRIPTION

[0091] The specific implementation of the LDMOS device and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0092] This specific embodiment provides an LDMOS device, Figure 1 is a schematic structural diagram of an LDMOS device in a specific embodiment of the present invention, Figure 2 FIG is a schematic diagram of the structure of the body region and the source region in a specific embodiment of the present invention. Figure 1 and Figure 2 As shown, the LDMOS device includes:

[0093] The substrate 10 includes a front surface and a back surface that are opposite to each other along a first direction D1;

[0094] A body region 11 is located in the substrate 10 and has a trench 15 therein;

[0095] a source region located in the body region 11 , the source region including a body contact region 141 located on the bottom surface of the trench 15 and a source doping region 142 distributed around the periphery of the body contact region 141 , the source doping region 142 being in a meandering shape and continuously distributed on the sidewalls of the trench 15 and a portion of the bottom surface of the trench 15 ;

[0096] a drift region 12 located in the substrate 10 and distributed outside the body region 11 along a second direction D2, wherein the second direction D2 is perpendicular to the first direction D1;

[0097] The drain region 13 is located in the drift region 12 .

[0098] For example, the substrate 10 is a silicon substrate. The substrate 10 has multiple active regions arranged at intervals, and adjacent active regions are isolated from each other by shallow trench isolation structures 16. Each active region is used to form a unit structure in the LDMOS device. The multiple mentioned in this specific embodiment refers to more than two. In one example, the active region includes the body region 11 and the two drift regions 12 distributed on opposite sides of the body region 11 along the second direction D2, and the drain region 13 is provided in each drift region 12. The top surface of the body region 11 is flush with the front surface of the substrate 10. The trench 15 is recessed from the top surface of the body region 11 to the interior of the body region 11, and the trench 15 does not penetrate the body region 11 (for example, the trench 15 does not penetrate the body region 11 along both the first direction D1 and the second direction D2). The source region includes a body contact region 141 located on the bottom surface of the trench 15 and a source doped region 142 distributed around the periphery of the body contact region 141. The source doped region 142 has a meandering shape and is continuously distributed on the sidewalls of the trench 15 and a portion of the bottom surface of the trench 15. Thus, the recessed trench 15 allows the entire source region to be configured in a meandering shape, effectively increasing the area of ​​the source region and ensuring the flow capacity of the LDMOS device. Furthermore, because the trench ensures the flow capacity of the LDMOS device by ensuring the area of ​​the source region, it is no longer limited by the minimum feature size of the photoresist in the ion implantation process. Therefore, the size of the body region can be further reduced, thereby reducing the distance between the source and drain regions in the LDMOS device (i.e., the LDMOS pitch), thereby reducing the specific on-resistance of the LDMOS device and improving the performance of the LDMOS device.

[0099] In some embodiments, the substrate 10 and the body region 11 both include first-type dopant ions, the drift region 12 and the drain region 13 both include second-type dopant ions, and the conductivity type of the first-type dopant ions is opposite to the conductivity type of the second-type dopant ions.

[0100] The body contact region 141 includes the first type of dopant ions, and the source dopant region 142 includes the second type of dopant ions.

[0101] Specifically, the source region includes the body contact region 141 located on the bottom surface of the trench 15 and the source doping region 142 symmetrically distributed around the periphery of the body contact region 141. The source doping region 142 is continuously distributed on the sidewalls of the trench 15 and a portion of the bottom surface of the trench 15, so that the source doping region 142 is bent. In one example, the body contact region 141 is in contact with the source doping region 142. The body contact region 141 and the body region 11 both include the first type of dopant ions, and the doping concentration of the first type of dopant ions in the body contact region 141 is greater than the doping concentration of the first type of dopant ions in the body region 11, that is, the body contact region 141 is heavily doped, so that the body contact region 141 can serve as a lead-out terminal of the body region 11 to reduce the contact resistance of the body region 11.

[0102] In one example, the first type of dopant ions are P-type ions, and the second type of dopant ions are N-type ions. In another example, the first type of dopant ions are N-type ions, and the second type of dopant ions are P-type ions.

[0103] In some embodiments, the angle between the sidewall of the trench 15 and the bottom surface of the trench 15 is an obtuse angle.

[0104] Specifically, the angle between the sidewall of the trench 15 and the bottom surface of the trench 15 is an obtuse angle, that is, the angle between the sidewall of the trench 15 and the bottom surface of the trench 15 is greater than 90 degrees. On the one hand, it can reduce the tip discharge effect at the bottom corner of the trench 15 (that is, the connection between the sidewall of the trench 15 and the bottom surface of the trench 15), thereby further improving the performance of the LDMOS device; on the other hand, it also facilitates the injection of the second type of dopant ions into the sidewall and bottom surface of the trench 15, thereby simplifying the operation of forming the source doping region 142, reducing the difference between the dopant ion concentration in the source doping region 142 located on the sidewall of the trench 15 and the dopant ion concentration in the source doping region 142 located on the bottom surface of the trench 15, thereby further improving the performance of the LDMOS device.

[0105] In some embodiments, the width of the trench 15 is smaller than the width of the body region 11 , and the depth of the trench 15 is greater than the depth of the drain region 13 and smaller than the depth of the body region 11 .

[0106] In some embodiments, the width of the trench 15 is 0.3 μm to 0.4 μm, and the depth of the trench 15 is 1500 Å to 2500 Å.

[0107] Specifically, by setting the width of the trench 15 (e.g., the width of the trench 15 along the second direction D2) to 0.3 μm to 0.4 μm and the depth of the trench 15 (e.g., the depth of the trench 15 along the first direction D1) to 1500 Å to 2500 Å, the size of the body region 11 can be further reduced, thereby further reducing the specific on-resistance of the LDMOS device, while also meeting the requirements of trench etching and ion implantation processes. In one example, the width of the trench 15 is 0.36 μm, and the depth of the trench 15 is 2000 Å.

[0108] In some embodiments, the LDMOS device further comprises:

[0109] The gate structure is located on the front surface of the substrate 10 and is distributed between the drain region 13 and the source region along the second direction D2. The gate structure includes a gate dielectric layer 171 covering the front surface of the substrate 10, a gate conductive layer 172 covering the surface of the gate dielectric layer 171, and a gate isolation layer 173 covering the side walls of the gate dielectric layer 171 and the side walls of the gate conductive layer 172.

[0110] For example, the active region of the substrate 10 includes two gate structures distributed along the second direction D2 on opposite sides of the body region 11, and each gate structure is located between the source region and one of the drain regions 13 along the second direction D2. The gate structure includes a gate dielectric layer 171 covering the front surface of the substrate 10, a gate conductive layer 172 covering the surface of the gate dielectric layer 171, and a gate isolation layer 173 continuously covering the sidewalls of the gate dielectric layer 171 and the sidewalls of the gate conductive layer 172. In one example, the material of the gate dielectric layer 171 can be an oxide material, the material of the gate conductive layer 172 can be a polysilicon material, and the material of the gate isolation layer 173 can be either an oxide material or a nitride material, or a combination of the two.

[0111] In some embodiments, the LDMOS device further comprises:

[0112] an interlayer dielectric layer 20 covering the front surface of the substrate 10 and filling the trench 15;

[0113] a source lead-out structure 211, penetrating the interlayer dielectric layer 20 along the first direction D1 and electrically connected to the source region;

[0114] a drain lead-out structure 212 extending along the first direction D1 through the interlayer dielectric layer 20 and electrically connected to the drain region 13;

[0115] The gate lead-out structure 213 penetrates the interlayer dielectric layer 20 along the first direction D1 and is electrically connected to the gate structure.

[0116] In some embodiments, the LDMOS device further comprises:

[0117] a source contact layer 181 covering the surface of the source region and electrically connected to the source lead-out structure 211;

[0118] a drain contact layer 182 covering the surface of the drain region 13 and electrically connected to the drain lead-out structure 212;

[0119] The gate contact layer 183 covers the surface of the gate conductive layer 172 and is electrically connected to the gate lead structure 213 .

[0120] For example, the substrate 10 further includes a substrate contact region 19, and the substrate contact region 19 includes the first type of dopant ions, and the doping concentration of the first type of dopant ions in the substrate contact region 19 is greater than that of the substrate 10. The substrate contact region 19 is electrically isolated from the drift region 12 by a shallow trench isolation structure 16. The LDMOS device further includes a source contact layer 181 continuously covering the body contact region 141 and the source doped region 142, a drain contact layer 182 covering the drain region 13, a gate contact layer 183 covering the gate conductive layer 172, and a substrate contact layer 184 covering the substrate contact region 19. In one example, the source contact layer 181, the drain contact layer 182, the gate contact layer 183, and the substrate contact layer 184 are all made of silicide materials. The interlayer dielectric layer 20 is located on the front surface of the substrate 10 and continuously covers the front surface of the substrate 10, the source contact layer 181, the drain contact layer 182, the gate contact layer 183, and the substrate contact layer 184. The interlayer dielectric layer 20 completely fills the trench 15. In one example, the material of the interlayer dielectric layer 20 can be an insulating material such as oxide.

[0121] The LDMOS device also includes a source lead-out structure 211 that penetrates the interlayer dielectric layer 20 along the first direction D1 and is in contact with and electrically connected to the source contact layer 181, a drain lead-out structure 212 that penetrates the interlayer dielectric layer 20 along the first direction D1 and is in contact with and electrically connected to the drain contact layer 182, a gate lead-out structure 213 that penetrates the interlayer dielectric layer 20 along the first direction D1 and is in contact with and electrically connected to the gate contact layer 183, and a substrate lead-out structure 214 that penetrates the interlayer dielectric layer 20 along the first direction D1 and is in contact with and electrically connected to the substrate contact layer 184. The source contact layer 181 is used to reduce the contact resistance between the source lead-out structure 211 and the source region, the drain contact layer 182 is used to reduce the contact resistance between the drain lead-out structure 212 and the drain region 13, the gate contact layer 183 is used to reduce the contact resistance between the gate lead-out structure 213 and the gate conductive layer 172, and the substrate contact layer 184 is used to reduce the contact resistance between the substrate lead-out structure 214 and the substrate 10.

[0122] In one example, the LDMOS device further includes a source lead-out pad 221, a drain lead-out pad 222, a gate lead-out pad 223, and a substrate lead-out pad 224 located above the interlayer dielectric layer 20, the source lead-out pad 221 being electrically connected to the source lead-out structure 211, the drain lead-out pad 222 being electrically connected to the drain lead-out structure 212, the gate lead-out pad 223 being electrically connected to the gate lead-out structure 213, and the substrate lead-out pad 224 being electrically connected to the substrate lead-out structure 214.

[0123] The specific on-resistance of the LDMOS device is proportional to the distance (i.e., pitch) between the source lead-out structure 211 and the drain lead-out structure 212. By reducing the size of the body region 11, the distance between the source lead-out structure 211 and the drain lead-out structure 212 can be reduced, thereby reducing the specific on-resistance of the LDMOS device. However, as the size of the body region 11 decreases, the size of the source region within the body region 11 decreases, which not only increases the difficulty of forming the source region but also affects the current handling capability of the LDMOS device. This specific embodiment forms the trench 15 within the body region 11, distributing the source region on the sidewalls and bottom surface of the trench 15. This reduces the size of the body region 11 to reduce the specific on-resistance of the LDMOS device while ensuring the current handling capability of the LDMOS device, thereby improving the overall performance of the LDMOS device.

[0124] This specific embodiment also provides a method for forming an LDMOS device. Figure 3The structure of the LDMOS device formed in this embodiment can be seen in FIG. Figure 1 and Figure 2 .like Figure 1-Figure 3 As shown, the method for forming the LDMOS device includes the following steps:

[0125] Step S31, providing a substrate 10, wherein the substrate 10 includes a front surface and a back surface that are oppositely distributed along a first direction D1;

[0126] Step S32: forming a body region 11 and a drift region 12 in the substrate 10, wherein the drift region 12 is distributed outside the body region 11 along a second direction D2, and the second direction D2 is perpendicular to the first direction D1;

[0127] Step S33, forming a trench 15 in the body region 11;

[0128] In step S34, a source region is formed on the sidewalls of the trench 15 and on the bottom surface of the trench 15, and a drain region 13 is formed in the drift region 12. The source region includes a body contact region 141 located on the bottom surface of the trench 15 and a source doping region 142 distributed around the periphery of the body contact region 141. The source doping region 142 is bent in shape and continuously distributed on the sidewalls of the trench 15 and on part of the bottom surface of the trench 15.

[0129] Figure 4 Schematic diagram of the structure after forming the body region and drift region in a substrate in a specific embodiment of the present invention. In some embodiments, the substrate 10 includes first-type dopant ions; the specific steps of forming the body region 11 and drift region 12 in the substrate 10 include:

[0130] implanting the first type of dopant ions into the substrate 10 from the front surface of the substrate 10 to form the body region 11 , wherein the top surface of the body region 11 is flush with the front surface of the substrate 10 ;

[0131] Second type dopant ions are injected into the substrate 10 from the front surface of the substrate 10 to form the drift region 12. The top surface of the drift region 12 is flush with the front surface of the substrate 10. The conductivity type of the first type dopant ions is opposite to the conductivity type of the second type dopant ions.

[0132] For example, after forming a plurality of active regions and the shallow trench isolation structure 16 for separating adjacent active regions in the substrate 10, a gate structure is formed above the active regions of the substrate 10, the gate structure including a gate dielectric layer 171 covering the front surface of the substrate 10, a gate conductive layer 172 covering the surface of the gate dielectric layer 171, and a gate isolation layer 173 continuously covering the sidewalls of the gate dielectric layer 171 and the sidewalls of the gate conductive layer 172. Then, the first type of dopant ions are injected into the substrate 10 from the front surface of the substrate 10, and the second type of dopant ions are injected into the substrate 10 from the front surface of the substrate 10 to form the body region 11 including the first type of dopant ions and the drift region 12 including the second type of dopant ions, as shown in FIG. Figure 4 The order in which the body region 11 and the drift region 12 are formed can be adjusted according to actual needs.

[0133] Figure 5 1 is a schematic diagram of a structure after a trench is formed in the body region in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the trench 15 in the body region 11 include:

[0134] The body region 11 is etched from the top surface of the body region 11 using a photochemical etching process to form the trench 15 .

[0135] Specifically, in order to reduce the specific on-resistance of the LDMOS device, the characteristic size of the body region 11 is reduced (for example, the width of the body region 11 along the second direction D2 is reduced). The photochemical etching process can accurately form the trench 15 that meets preset requirements (for example, morphology requirements and size requirements) in the smaller body region 11, thereby ensuring that the subsequent process of forming the source region in the trench 15 can proceed smoothly.

[0136] In some embodiments, the step of etching the body region 11 from the top surface of the body region 11 to form the trench 15 further includes:

[0137] The etching parameters of the photochemical etching process are adjusted so that the angle β between the sidewall of the formed trench 15 and the bottom surface of the trench 15 is an obtuse angle.

[0138] Specifically, the angle β between the sidewall of the trench 15 and the bottom surface of the trench 15 is an obtuse angle, that is, the angle β between the sidewall of the trench 15 and the bottom surface of the trench 15 is greater than 90 degrees. On the one hand, it can reduce the tip discharge effect at the bottom corner of the trench 15 (that is, the connection between the sidewall of the trench 15 and the bottom surface of the trench 15), thereby further improving the performance of the LDMOS device; on the other hand, it also facilitates the injection of the second type of dopant ions into the sidewall and bottom surface of the trench 15, thereby simplifying the operation of forming the source doping region 142, reducing the difference between the dopant ion concentration in the source doping region 142 located on the sidewall of the trench 15 and the dopant ion concentration in the source doping region 142 located on the bottom surface of the trench 15, thereby further improving the performance of the LDMOS device.

[0139] In some embodiments, the width of the trench 15 is 0.3 μm to 0.4 μm, and the depth of the trench 15 is 1500 Å to 2500 Å.

[0140] Specifically, by setting the width of the trench 15 (e.g., the width of the trench 15 along the second direction D2) to 0.3 μm to 0.4 μm and the depth of the trench 15 (e.g., the depth of the trench 15 along the first direction D1) to 1500 Å to 2500 Å, the size of the body region 11 can be further reduced, thereby further reducing the specific on-resistance of the LDMOS device, while also meeting the requirements of trench etching and ion implantation processes. In one example, the width of the trench 15 is 0.36 μm, and the depth of the trench 15 is 2000 Å.

[0141] In some embodiments, before forming the source region on the sidewalls of the trench 15 and the bottom surface of the trench 15 and forming the drain region 13 in the drift region 12 , the following steps are further included:

[0142] The first type dopant ions are implanted into the body region 11 along the trench 15 .

[0143] Specifically, in the process of etching the body region 11 to form the groove 15, the etching process (such as a photochemical etching process) will affect the concentration and distribution of the first type of dopant ions in the body region 11. In order to repair the impact of the trench etching process on the body region 11, before forming the source region on the side wall of the trench 15 and on the bottom surface of the trench 15, and forming the drain region 13 in the drift region 12, the first type of dopant ions are injected into the body region 11 along the trench 15, thereby compensating for the impact of the etching process on the ion doping concentration and distribution in the body region 11.

[0144] Figure 6 Schematic diagram of the structure after forming the source region and the drain region in a specific embodiment of the present invention. Figure 6 As shown, the specific steps of forming the source region on the sidewalls of the trench 15 and the bottom surface of the trench 15 and forming the drain region 13 in the drift region 12 include:

[0145] The source region including the body contact region 141 and the source doping region 142 is formed on the sidewalls of the trench 15 and on the bottom surface of the trench 15, and the drain region 13 is formed in the drift region 12, the body contact region 141 includes the first type of doping ions, the source doping region 142 includes the second type of doping ions, and the drain region 13 includes the second type of doping ions.

[0146] In one example, the first type of dopant ions are P-type ions, and the second type of dopant ions are N-type ions. In another example, the first type of dopant ions are N-type ions, and the second type of dopant ions are P-type ions. For example, the substrate 10 and the body region 11 both include P-type ions, and the drift region 12 includes N-type ions. After forming the trench 15, N-type ions are implanted into the drift region 12, the substrate 10, the sidewalls of the trench 15, and a portion of the bottom surface of the trench 15 to form the drain region 13 in the drift region 12, the substrate 10, the substrate contact region 19 in the substrate 10, and the source doped region 142 on the sidewalls and a portion of the bottom surface of the trench 15. Thereafter, P-type ions are implanted into the bottom surface of the trench 15 to form the body region contact region 141. The order of implanting the N-type ions and the P-type ions can be adjusted according to actual needs.

[0147] Figure 7 Schematic diagram of the structure after forming the source contact layer, drain contact layer, and gate contact layer in a specific embodiment of the present invention. In some embodiments, the front surface of the substrate 10 further comprises a gate structure distributed along the second direction D2 between the drain region 13 and the source region, the gate structure comprising a gate dielectric layer 171 covering the front surface of the substrate 10, a gate conductive layer 172 covering the surface of the gate dielectric layer 171, and a gate isolation layer 173 covering the sidewalls of the gate dielectric layer 171 and the sidewalls of the gate conductive layer 172. After forming the source region on the sidewalls and bottom surface of the trench 15 and forming the drain region 13 in the drift region 12, the following steps are further included:

[0148] A source contact layer 181 electrically connected to the source region is formed on the surface of the source region, a drain contact layer 182 electrically connected to the drain region 13 is formed on the surface of the drain region 13, and a gate contact layer 183 electrically connected to the gate conductive layer 172 is formed on the surface of the gate conductive layer 172. Figure 7 shown.

[0149] Specifically, a metal material is deposited on the front surface of the substrate 10 and the surface of the source region, and a metal silicide layer is formed by a heat treatment process covering the surface of the source region, the surface of the drain region 13, the surface of the gate conductive layer 172, and the surface of the substrate contact region 19. The metal silicide layer located on the surface of the source region and electrically connected to the source region serves as the source contact layer 181, the metal silicide layer located on the surface of the drain region 13 and electrically connected to the drain region 13 serves as the drain contact layer 182, the metal silicide layer located on the surface of the gate conductive layer 172 and electrically connected to the gate conductive layer 172 serves as the gate contact layer 183, and the metal silicide layer located on the surface of the substrate contact region 19 and electrically connected to the substrate contact region 19 serves as the substrate contact layer 184. The source contact layer 181, the drain contact layer 182, the gate contact layer 183, and the substrate contact layer 184 are independent of each other. Figure 7 shown.

[0150] Figure 8 A schematic diagram of the structure after forming an interlayer dielectric layer in a specific embodiment of the present invention, Figure 9 Schematic diagram of the structure after forming the source contact hole, drain contact hole, and gate contact hole in a specific embodiment of the present invention. In some embodiments, after forming the source region on the sidewalls and bottom surface of the trench 15 and forming the drain region 13 in the drift region 12, the following steps are also included:

[0151] An interlayer dielectric layer 20 is formed covering the front surface of the substrate 10 and filling the trench 15, as shown in FIG. Figure 8 As shown;

[0152] A source lead-out structure 211 is formed along the first direction D1 through the interlayer dielectric layer 20 and in contact with and electrically connected to the source contact layer 181, a drain lead-out structure 212 is formed along the first direction D1 through the interlayer dielectric layer 20 and in contact with and electrically connected to the drain contact layer 182, and a gate lead-out structure 213 is formed along the first direction D1 through the interlayer dielectric layer 20 and in contact with and electrically connected to the gate contact layer 183. Figure 1 shown.

[0153] For example, an insulating material such as an oxide material is deposited on the front surface of the substrate 10 to form the interlayer dielectric layer 20 that continuously covers the front surface of the substrate 10, the source contact layer 181, the drain contact layer 182, the gate contact layer 183, and the substrate contact layer 184, and the interlayer dielectric layer 20 fully fills the trench 15. The interlayer dielectric layer 20 is etched to form a source contact hole 911 that penetrates the interlayer dielectric layer 20 along the first direction D1 and exposes the source contact layer 181, a drain contact hole 912 that penetrates the interlayer dielectric layer 20 along the first direction D1 and exposes the drain contact layer 182, a gate contact hole 913 that penetrates the interlayer dielectric layer 20 along the first direction D1 and exposes the gate contact layer 183, and a substrate contact hole 914 that penetrates the interlayer dielectric layer along the first direction D1 and exposes the substrate contact layer 184, as shown in FIG. Figure 9 As shown. Copper or tungsten and other metal materials are deposited, and at the same time, the source lead-out structure 211 filled in the source contact hole 911, the drain lead-out structure 212 filled in the drain contact hole 912, the gate lead-out structure 213 filled in the gate contact hole 913, and the substrate lead-out structure 214 filled in the substrate contact hole 914 are formed. Then, a source lead-out pad 221, a drain lead-out pad 222, a gate lead-out pad 223 and a substrate lead-out pad 224 are formed above the interlayer dielectric layer 20, the source lead-out pad 221 is electrically connected to the source lead-out structure 211, the drain lead-out pad 222 is electrically connected to the drain lead-out structure 212, the gate lead-out pad 223 is electrically connected to the gate lead-out structure 213, and the substrate lead-out pad 224 is electrically connected to the substrate lead-out structure 214, as shown. Figure 1 shown.

[0154] The LDMOS device and its formation method provided in this embodiment achieve a three-dimensional LDMOS structure by providing a trench within the body region and distributing the source region on the sidewalls and bottom surface of the trench. The curved shape of the source region effectively increases the area of ​​the source region, ensuring the flow capacity of the LDMOS device. Furthermore, because the trench increases the area of ​​the source region, the flow capacity of the LDMOS device can be ensured while reducing the size of the body region to reduce the distance between the source and drain regions in the LDMOS device (i.e., the LDMOS pitch), thereby reducing the specific on-resistance of the LDMOS device and improving the performance of the LDMOS device.

[0155] It should be noted that the terms "including," "having," and their variations, as used in this document, are intended to cover non-exclusive inclusions. Terms such as "first," "second," and the like are used to distinguish similar items and are not necessarily used to describe a specific order or precedence, unless the context clearly indicates otherwise. Such usage should be understood to be interchangeable where appropriate. The term "one or more" may be used to describe a feature, structure, or characteristic in the singular, or in the plural, depending at least in part on the context, to describe a feature, structure, or combination of features. The term "based on" should be understood as not necessarily intended to express an exclusive set of factors, but may alternatively, also depending at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, the embodiments of the present invention and the features therein may be combined with one another, unless there is a conflict. Furthermore, descriptions of well-known components and technologies have been omitted from the above description to avoid unnecessary confusion regarding the concepts of the present invention. In each of the above embodiments, each embodiment focuses on its differences from the other embodiments, and reference may be made to the same or similar parts between the embodiments.

[0156] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An LDMOS device, characterized in that: include: a substrate comprising a front surface and a back surface oppositely distributed along a first direction; a body region located in the substrate, wherein the body region has a trench; a source region located within the body region, the source region comprising a body contact region located on the bottom surface of the trench and a source doped region symmetrically distributed around the periphery of the body contact region, the source doped region being in a meandering shape and continuously distributed on the sidewalls of the trench and a portion of the bottom surface of the trench, the body contact region being in contact and connected to the source doped region, wherein the trench increases the area of ​​the source region to ensure the current flow capability of the LDMOS device; and, by reducing the size of the body region, the distance between the source region and the drain region in the LDMOS device is reduced to reduce the specific on-resistance of the LDMOS device; a drift region located in the substrate and distributed outside the body region along a second direction, wherein the second direction intersects the first direction perpendicularly; The drain region is located in the drift region.

2. The LDMOS device according to claim 1, wherein: The substrate and the body region both include first-type dopant ions, the drift region and the drain region both include second-type dopant ions, and the conductivity type of the first-type dopant ions is opposite to the conductivity type of the second-type dopant ions; The body contact region includes the first type of dopant ions, and the source dopant region includes the second type of dopant ions.

3. The LDMOS device according to claim 1, wherein: An included angle between the sidewall of the groove and the bottom surface of the groove is an obtuse angle.

4. The LDMOS device according to claim 1, wherein: A width of the trench is smaller than a width of the body region, and a depth of the trench is greater than a depth of the drain region and smaller than a depth of the body region.

5. The LDMOS device according to claim 4, wherein: The width of the groove is 0.3 μm to 0.4 μm, and the depth of the groove is 1500 Å to 2500 Å.

6. The LDMOS device according to claim 1, wherein: Also includes: A gate structure is located on the front surface of the substrate and is distributed between the drain region and the source region along the second direction. The gate structure includes a gate dielectric layer covering the front surface of the substrate, a gate conductive layer covering the surface of the gate dielectric layer, and a gate isolation layer covering the sidewalls of the gate dielectric layer and the sidewalls of the gate conductive layer.

7. The LDMOS device according to claim 6, wherein: Also includes: an interlayer dielectric layer covering the front surface of the substrate and filling the trench; a source lead-out structure, penetrating the interlayer dielectric layer along the first direction and electrically connected to the source region; a drain lead-out structure, penetrating the interlayer dielectric layer along the first direction and electrically connected to the drain region; A gate lead-out structure penetrates the interlayer dielectric layer along the first direction and is electrically connected to the gate structure.

8. The LDMOS device according to claim 7, wherein: Also includes: a source contact layer, covering the surface of the source region and electrically connected to the source lead-out structure; a drain contact layer, covering the surface of the drain region and electrically connected to the drain lead-out structure; The gate contact layer covers the surface of the gate conductive layer and is electrically connected to the gate lead structure.

9. A method for forming an LDMOS device, characterized in that: The steps include: Providing a substrate, the substrate comprising a front surface and a back surface oppositely distributed along a first direction; forming a body region and a drift region in the substrate, wherein the drift region is distributed outside the body region along a second direction, and the second direction is perpendicular to the first direction; forming a trench in the body region; A source region is formed on the sidewalls and bottom surface of the trench, and a drain region is formed in the drift region. The source region includes a body contact region located on the bottom surface of the trench and a source doping region symmetrically distributed around the periphery of the body contact region. The source doping region has a meandering shape and is continuously distributed on the sidewalls of the trench and a portion of the bottom surface of the trench. The body contact region is in contact with and connected to the source doping region. The trench increases the area of ​​the source region to ensure the current flow capability of the LDMOS device. At the same time, by reducing the size of the body region, the distance between the source region and the drain region in the LDMOS device is reduced to reduce the specific on-resistance of the LDMOS device.

10. The method for forming an LDMOS device according to claim 9, wherein: The substrate includes first type dopant ions; and the specific steps of forming a body region and a drift region in the substrate include: implanting the first type of dopant ions into the substrate from the front surface of the substrate to form the body region, wherein the top surface of the body region is flush with the front surface of the substrate; Second type dopant ions are injected into the substrate from the front surface of the substrate to form the drift region, the top surface of the drift region is flush with the front surface of the substrate, and the conductivity type of the first type dopant ions is opposite to the conductivity type of the second type dopant ions.

11. The method for forming an LDMOS device according to claim 10, wherein: The specific steps of forming a trench in the body region include: The body region is etched from the top surface of the body region using a photochemical etching process to form the groove.

12. The method for forming an LDMOS device according to claim 11, wherein: The specific step of etching the body region from the top surface of the body region to form the trench further includes: The etching parameters of the photochemical etching process are adjusted so that the angle between the sidewall of the formed trench and the bottom surface of the trench is an obtuse angle.

13. The method for forming an LDMOS device according to claim 9, wherein: The width of the groove is 0.3 μm to 0.4 μm, and the depth of the groove is 1500 Å to 2500 Å.

14. The method for forming an LDMOS device according to claim 10, wherein: Before forming a source region on the sidewalls and the bottom surface of the trench and forming a drain region in the drift region, the method further includes the following steps: The first type of dopant ions are implanted into the body region along the trench.

15. The method for forming an LDMOS device according to claim 10, wherein: The specific steps of forming a source region on the sidewalls and the bottom surface of the trench, and forming a drain region in the drift region include: The source region including the body contact region and the source doping region is formed on the sidewalls of the trench and on the bottom surface of the trench, and the drain region is formed in the drift region, the body contact region includes the first type of doping ions, the source doping region includes the second type of doping ions, and the drain region includes the second type of doping ions.

16. The method for forming an LDMOS device according to claim 9, wherein: The front surface of the substrate further comprises a gate structure distributed along the second direction between the drain region and the source region, the gate structure comprising a gate dielectric layer covering the front surface of the substrate, a gate conductive layer covering the surface of the gate dielectric layer, and a gate isolation layer covering the sidewalls of the gate dielectric layer and the sidewalls of the gate conductive layer; after forming the source region on the sidewalls and the bottom surface of the trench and forming the drain region in the drift region, the following steps are further included: A source contact layer electrically connected to the source region is formed on the surface of the source region, a drain contact layer electrically connected to the drain region is formed on the surface of the drain region, and a gate contact layer electrically connected to the gate conductive layer is formed on the surface of the gate conductive layer.

17. The method for forming an LDMOS device according to claim 16, wherein: After forming a source region on the sidewalls and the bottom surface of the trench and forming a drain region in the drift region, the method further includes the following steps: forming an interlayer dielectric layer covering the front surface of the substrate and filling the trench; A source lead-out structure is formed which penetrates the interlayer dielectric layer along the first direction and is electrically connected to the source contact layer, a drain lead-out structure is formed which penetrates the interlayer dielectric layer along the first direction and is electrically connected to the drain contact layer, and a gate lead-out structure is formed which penetrates the interlayer dielectric layer along the first direction and is electrically connected to the gate contact layer.

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