SOI substrate and manufacturing method thereof, SOI power device, chip and electronic component

Abstract

The invention provides an SOI substrate and a manufacturing method thereof, an SOI power device, a chip and an electronic component. The SOI power device comprises a first substrate, a buried layer and a second substrate which are stacked in sequence; a body region and a drift region are arranged in the second substrate, a source end is arranged in the body region, a drain end is arranged in the drift region, and a gate structure is arranged on the surfaces of the body region and the drift region; a plurality of grooves are formed in the buried layer below the drift region, first media are arranged in the grooves and are in contact with the second substrate, and the dielectric constant of the first media is smaller than that of the buried layer. According to the invention, the performance of the SOI power device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an SOI substrate and a manufacturing method thereof, an SOI power device, a chip, and an electronic component. Background Art

[0002] Laterally Double-diffused Metal Oxide Semiconductor (LDMOS) devices are widely used in various modern electronic devices due to their mature technology, easy integration and relatively high breakdown voltage. Silicon-On-Insulator technology has the advantages of low leakage current, good isolation performance and low parasitic effects. Therefore, junction power devices combining the above two, that is, lateral power semiconductor devices based on SOI technology, have also been widely used in some application scenarios.

[0003] However, the performance of lateral power semiconductor devices based on SOI technology needs to be further improved to cope with more demanding application scenarios. Summary of the invention

[0004] The present application provides an SOI power device. The SOI power device comprises a first substrate, a buried layer and a second substrate stacked in sequence; A body region and a drift region are provided in the second substrate, a source terminal is provided in the body region, a drain terminal is provided in the drift region, and a gate structure is provided on the surface of the body region and the drift region; A plurality of grooves are arranged in the buried layer under the drift region, a first medium is arranged in the grooves and contacts the second substrate, and the dielectric constant of the first medium is smaller than the dielectric constant of the buried layer.

[0005] Optionally, the first medium includes air.

[0006] Optionally, one of the grooves is provided in the buried layer close to the drain terminal and below the drift region.

[0007] Optionally, a plurality of the grooves are spaced apart and arranged in a buried layer close to the drain end and below the drift region.

[0008] Optionally, the length of the groove along a plane direction perpendicular to the channel is less than or equal to the length of the drift region.

[0009] Optionally, the maximum depth of the groove is less than or equal to the thickness of the buried layer.

[0010] Optionally, the SOI power device is an LDMOS power device.

[0011] Based on another aspect of the present application, an SOI substrate is also provided, comprising a first substrate, a buried layer and a second substrate stacked in sequence, wherein the buried layer is provided with a plurality of grooves facing the second substrate, a first medium is provided in the grooves and contacts the second substrate, and the dielectric constant of the first medium is smaller than the dielectric constant of the buried layer.

[0012] Optionally, the first medium includes air.

[0013] According to another aspect of the present application, a method for manufacturing an SOI substrate is also provided, comprising: Providing a first substrate, and forming a buried layer on the first substrate; forming a plurality of grooves in the buried layer, and forming a first dielectric in the grooves, wherein the dielectric constant of the first dielectric is smaller than the dielectric constant of the buried layer; A second substrate is provided, and the second substrate is bonded on the buried layer.

[0014] According to another aspect of the present application, a chip is further provided, wherein the chip includes the SOI power device as described above.

[0015] According to another aspect of the present application, an electronic component is further provided, wherein the electronic component includes the chip as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0017] Figure 1 A schematic diagram of the structure of a SOI power device provided in an embodiment of the present application; FIG. 2A to FIG. 2C Schematic diagram of several SOI power devices provided in embodiments of the present application; Figure 3 A schematic diagram of an SOI substrate provided in an embodiment of the present application; Figure 4 A flow chart of a method for manufacturing an SOI substrate provided in an embodiment of the present application; Figure 5A to Figure 5C A schematic structural diagram corresponding to the corresponding steps of the method for manufacturing an SOI substrate provided in this embodiment.

[0018] In the accompanying drawings: 10-first substrate; 20-buried layer; 30-second substrate; 21-groove; 22-first dielectric; 31-body region; 32-drift region; 33-source terminal; 33a-first N-type heavily doped region; 33b-first metal terminal; 34-drain terminal; 34a-second N-type heavily doped region; 34b-second metal terminal; 35-gate structure; 35a-gate dielectric layer; 35b-gate conductive layer; 36-P-type heavily doped region. DETAILED DESCRIPTION

[0019] As described in the background technology, in lateral power semiconductor devices based on SOI technology, the buried layer can improve the longitudinal breakdown voltage of the power device, but due to process limitations, the thickness of the buried layer cannot be continuously increased. Therefore, how to further improve the breakdown voltage of the power device within the thickness limit of the buried layer is the key to making the power device more widely used.

[0020] To this end, the present application provides an SOI substrate and a manufacturing method thereof, an SOI power device, a chip, and an electronic component. In the SOI power device provided in the present application, a plurality of grooves are provided in the buried layer under the drift region, and a first medium is provided in the grooves to contact the second substrate. The dielectric constant of the first medium is smaller than the dielectric constant of the buried layer. The electric field peak generated by the interface between the drift region and the first medium (different from the electric field at the interface between the buried layer and the drift region) is utilized. The electric field peak will be conducted to the device surface, affecting and adjusting the surface electric field of the drift region, thereby changing the longitudinal electric field distribution of the drift region, thereby improving the breakdown voltage of the lateral power semiconductor device based on SOI technology.

[0021] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0022] It should be understood that when an element or layer is referred to as "on...", "connected to" other elements or layers, it can be directly on other elements or layers, connected to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on...", "directly connected to" other elements or layers, there is no intervening element or layer. Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be expressed as a second element, component, region, layer or part. Spatial relationship terms such as "under...", "below", "below", "above...", "above", "above", etc., can be used here for the convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the devices in use and operation. For example, if the device in the accompanying drawings is turned over, then, the elements or features described as "under...", "below", "below" will be oriented to be "on" other elements or features. The device can be oriented in other ways (rotated 90 degrees or other orientations) and the spatial descriptors used here are interpreted accordingly. The purpose of the terms used here is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used here, the singular forms of "one", "one" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "including" is used to determine the existence of features, steps, operations, elements and / or parts, but does not exclude the existence or addition of one or more other features, steps, operations, elements, parts and / or groups. When used here, the term "and / or" includes any and all combinations of the relevant listed items.

[0023] An embodiment of the present application provides a SOI power device.

[0024] Figure 1 A schematic diagram of the structure of a SOI power device provided in an embodiment of the present application.

[0025] like Figure 1As shown, the SOI power device provided in the embodiment of the present application is a power device formed on (based on) SOI technology, that is, a power device formed on an SOI substrate. The SOI substrate may include a first substrate 10, a buried layer 20, and a second substrate 30 stacked in sequence. The first substrate 10 is used to carry the power device, and may be a carrier wafer, and its conductivity type may be, for example, P-type. The second substrate 30 is used to form a power device, and may be a device wafer. The second substrate 30 may be provided with a body region 31 and a drift region 32 connected to each other, the body region 31 is provided with a source terminal 33 of the power device, the drift region 32 is provided with a drain terminal 34 of the power device, and the gate structure 35 is provided on the surface of the body region 31 and the drift region 32 and is located between the source terminal 33 and the drain terminal 34. Among them, a plurality of grooves 21 are provided in the buried layer 20 under the drift region 32, and a first dielectric 22 is provided in the groove 21 to contact the second substrate 30, and the dielectric constant of the first dielectric 22 is less than the dielectric constant of the buried layer 20.

[0026] Please continue to refer to Figure 1 In the present application, the power device may be an LDMOS device, the body region 31 may be a P-type doped region, the source terminal 33 is disposed on a side of the body region 31 away from the drift region 32, the source terminal 33 may include a first N-type heavily doped region 33a and a first metal terminal 33b disposed on the first N-type heavily doped region 33a, the first metal terminal 33b is used to electrically lead out the first N-type heavily doped region 33a, and a P-type heavily doped region 36 may be further provided on the side of the first N-type heavily doped region 33a away from the drift region 32 for leading out the body region 31 (i.e., the body contact region), the P-type heavily doped region 36 is connected to the first metal terminal 33b. The drift region 32 may be an N-type lightly doped region, the width of the drift region 32 may be greater than the width of the body region 31, the drain terminal 34 is disposed on a side of the drift region 32 away from the body region 31, the drain terminal 34 may include a second N-type heavily doped region 34a and a second metal terminal 34b disposed on the second N-type heavily doped region 34a, the second metal terminal 34b is used to electrically lead out the second N-type heavily doped region 34a. The gate structure 35 extends from the surface of the body region 31 on the first N-type heavily doped region 33a to the surface of the drift region 32, the gate structure 35 maintains a preset spacing distance from the second N-type heavily doped region 34a, and the gate structure 35 may include a gate dielectric layer 35a covering the surface of the body region 31 and the drift region 32, and a gate conductive layer 35b located on the gate dielectric layer 35a.

[0027] Please continue to refer to Figure 1 The buried layer 20 is disposed between the first substrate 10 and the second substrate 30. A plurality of grooves 21 are disposed in the buried layer 20 under the drift region 32. The grooves 21 are filled with a first dielectric 22 and contact the second substrate 30. The first dielectric 22 is substantially flush with the top surface of the buried layer 20. The dielectric constant of the first dielectric 22 is smaller than the dielectric constant of the buried layer 20. Figure 1In the example shown, the material of the buried layer 20 includes silicon oxide, and the material of the first medium 22 can be air (the dielectric constant of air is about 1), that is, the groove 21 forms a cavity in the buried layer 20 under the drift region 32. Among them, the number of the groove 21 can be one, and the groove 21 is provided in the buried layer 20 close to the drain terminal 34. The position and width of the groove 21 in the buried layer 20 can be obtained by simulation according to the specific parameters of the power device.

[0028] In this application Figure 2A In the example shown, a plurality of grooves 21 (at least two, for example, three grooves 21 in this example) arranged at intervals may be provided in the buried layer 20 below the drift region 32 (i.e., below the channel), and the widths of the plurality of grooves 21 may be the same or different. Of course, how to specifically arrange the plurality of grooves 21 may be obtained by simulation according to the specific parameters of the power device. Figure 2B In the example shown, unlike the aforementioned grooves 21 that all penetrate the buried layer 20 (the maximum depth of the grooves 21 is equal to the thickness of the buried layer 20), the maximum depth of at least some of the plurality of grooves 21 is less than the thickness of the buried layer 20, that is, at least some of the grooves 21 do not penetrate the buried layer 20. Of course, in the above examples, it is also feasible that the groove 21 extends to the side close to the drain terminal 34 below the drain terminal 34.

[0029] In addition, the above examples all show longitudinal cross-sectional views (vertical direction) of power devices, such as Figure 2C As shown, in the transverse cross-sectional views (in the plane direction) of the above examples, the length L1 of the groove 21 along the plane direction perpendicular to the channel is less than or equal to the length L2 of the drift region 32 (ie, the length of the gate structure).

[0030] It is understandable that, in addition to air, the first medium filled in the above groove can also be other insulating materials with lower dielectric constants (low dielectric constant medium or extremely low dielectric constant medium, such as silicon oxide doped with carbon and nitrogen), and the electric field peak generated by the interface between the drift region and the first medium (different from the electric field at the interface between the buried layer and the drift region) will be transmitted to the device surface (drift region surface), affecting and adjusting the surface electric field of the drift region, thereby changing the longitudinal electric field distribution of the drift region. In this way, the solution of the present application can break away from the limitation of the buried layer thickness and improve the breakdown voltage of the lateral power semiconductor device based on SOI technology. In addition, the solution of the present application can also be combined with other RESURF (Reduced Surface Field) technologies, such as setting a field plate on the surface of the drift region.

[0031] The embodiments of the present application also provide an SOI substrate for manufacturing a power device.

[0032] Figure 3 A schematic diagram of an SOI substrate provided in an embodiment of the present application.

[0033] like Figure 3 As shown, the SOI substrate provided in the embodiment of the present application includes a first substrate 10, a buried layer 20 and a second substrate 30 stacked in sequence, wherein the buried layer 20 is provided with a plurality of grooves 21 facing the second substrate 30, and a first medium 22 is provided in the groove 21 to contact the second substrate 30, and the dielectric constant of the first medium 22 is less than the dielectric constant of the buried layer 20. Among them, the first substrate 10 can be a carrier wafer for carrying power devices, and the second substrate 30 can be a device wafer for forming power devices. The arrangement of the groove 21 in the buried layer 20 and the first medium 22 in the groove 21 can be set according to the parameters of the power device. In one example, the material of the buried layer 20 can include silicon oxide, and the material of the first medium 22 can be air (the dielectric constant of air is about 1), that is, the groove 21 forms a cavity in the buried layer 20 under the drift region 32. In another example, the maximum depth of the groove 21 is less than or equal to the thickness of the buried layer 20, that is, the groove 21 penetrates or does not penetrate the buried layer 20.

[0034] The embodiment of the present application also provides a method for manufacturing an SOI substrate.

[0035] Figure 4 A flow chart of a method for manufacturing an SOI substrate provided in an embodiment of the present application.

[0036] like Figure 4 As shown, the method for manufacturing an SOI substrate provided in an embodiment of the present application includes: S01: providing a first substrate, and forming a buried layer on the first substrate; S02: forming a plurality of grooves in the buried layer, and forming a first dielectric in the grooves, wherein a dielectric constant of the first dielectric is smaller than a dielectric constant of the buried layer; S03: providing a second substrate, and bonding the second substrate on the buried layer.

[0037] Figure 5A to Figure 5C The structural schematic diagram corresponding to the corresponding steps of the method for manufacturing the SOI substrate provided in this embodiment, next, Figure 5A to Figure 5C The method for manufacturing the SOI substrate will be described in detail.

[0038] First, please refer to Figure 5A , perform step S01, provide a first substrate 10, and form a buried layer 20 on the first substrate 10.

[0039] The first substrate 10 is used to carry power devices and can be a carrying wafer. Its conductivity type can be, for example, P-type. An oxidation process can be used to form an oxide layer on the surface of the first substrate 10 as a buried layer 20. The thickness of the buried layer 20 can be 500 nanometers to 5000 nanometers.

[0040] Next, please refer to Figure 5B , executing step S02 , forming a plurality of grooves 21 in the buried layer 20 , and forming a first dielectric 22 in the grooves 21 , wherein the dielectric constant of the first dielectric 22 is smaller than the dielectric constant of the buried layer 20 .

[0041] The patterning process can be performed with the orientation angle of the first substrate 10 as a reference (as a mark), and a groove 21 is formed in the buried layer 20. The position and size of the groove 21 can match the power device to be formed. The maximum depth of the groove 21 is less than or equal to the thickness of the buried layer 20, that is, the groove 21 penetrates or does not penetrate the buried layer 20. Then, the first dielectric 22 is filled in the groove 21, and then the buried layer 20 and the first dielectric 22 are subjected to a grinding process to form a flat surface suitable for bonding, and the thickness of the remaining buried layer 20 meets the process requirements. In this example, the material of the buried layer 20 may include silicon oxide, and the first dielectric 22 may be air, that is, after the groove 21 is formed, the buried layer 20 is subjected to a grinding process. Compared with grinding other dielectrics with lower dielectric constants or the entire surface of the buried layer 20, using air as the first dielectric 22 not only has a lower dielectric constant, but also grinds the surface with cavities, which is more conducive to grinding the surface of the buried layer 20 to a flat state, thereby reducing the difficulty of grinding and subsequent bonding. Of course, it is also feasible to fill the groove 21 with a dielectric with a lower dielectric constant other than air.

[0042] Next, please refer to Figure 5C , execute step S03 to bond the second substrate 30 on the buried layer 20 .

[0043] The second substrate 30 is used to form power devices and other devices, and may be a device wafer. Before bonding, the buried layer 20, the first dielectric 22 and the surface of the second substrate 30 may be cleaned and surface treated, and then the first substrate 10 and the second substrate 30 are bonded. The bonding steps may include, for example, aligning the first substrate 10 and the second substrate 30, pre-bonding and high-temperature annealing.

[0044] In addition, an embodiment of the present application further provides a chip, including the SOI power device as described above. By way of example, the chip may be a power chip or other types of chips integrated with a power device.

[0045] The present application also provides an electronic component, including the chip as described above. The electronic component of the present application may include various devices with computing functions, such as mobile phones, tablet computers, televisions, desktop computers, laptop computers, handheld computers, notebook computers, ultra-mobile personal computers (UMPC), netbooks, and cellular phones, personal digital assistants (PDAs), augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, smart wearable devices (e.g., smart watches, smart bracelets), vehicle-mounted devices, smart home devices and / or smart city devices. The present application does not impose any special restrictions on the specific types of the electronic components.

[0046] In summary, the present application provides an SOI substrate and a manufacturing method thereof, an SOI power device, a chip, and an electronic component. The SOI power device of the present application includes a first substrate, a buried layer, and a second substrate stacked in sequence; a body region and a drift region are provided in the second substrate, a source terminal is provided in the body region, a drain terminal is provided in the drift region, and a gate structure is provided on the surface of the body region and the drift region; a plurality of grooves are provided in the buried layer under the drift region, a first medium is provided in the groove to contact the second substrate, and the dielectric constant of the first medium is less than the dielectric constant of the buried layer. In the SOI power device provided in the present application, a plurality of grooves are provided in the buried layer under the drift region, a first medium is provided in the groove to contact the second substrate, and the dielectric constant of the first medium is less than the dielectric constant of the buried layer, and the electric field peak value generated by the interface between the drift region and the first medium (different from the electric field at the interface between the buried layer and the drift region) is used. The electric field peak value will be conducted to the device surface, affecting and adjusting the surface electric field of the drift region, thereby changing the longitudinal electric field distribution of the drift region, thereby improving the breakdown voltage of the lateral power semiconductor device based on SOI technology.

[0047] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A SOI power device, characterized in that: It includes a first substrate, a buried layer and a second substrate which are stacked in sequence; A body region and a drift region are provided in the second substrate, a source terminal is provided in the body region, a drain terminal is provided in the drift region, and a gate structure is provided on the surface of the body region and the drift region; A plurality of grooves are arranged in the buried layer under the drift region, a first medium is arranged in the grooves and contacts the second substrate, and the dielectric constant of the first medium is smaller than the dielectric constant of the buried layer.

2. The SOI power device according to claim 1, characterized in that: The first medium includes air or other low dielectric constant medium.

3. The SOI power device according to claim 1, characterized in that: One of the grooves is disposed in the buried layer near the drain terminal and below the drift region.

4. The SOI power device according to claim 1, characterized in that: A plurality of the grooves are arranged at intervals in the buried layer close to the drain end and under the drift region.

5. The SOI power device according to claim 3 or 4, characterized in that: The length of the groove along a plane direction perpendicular to the channel is less than or equal to the length of the drift region.

6. The SOI power device according to claim 3 or 4, characterized in that: The maximum depth of the groove is less than or equal to the thickness of the buried layer.

7. The SOI power device according to claim 1, characterized in that: The SOI power device is an LDMOS power device.

8. An SOI substrate for manufacturing a power device, characterized in that: It comprises a first substrate, a buried layer and a second substrate stacked in sequence, wherein the buried layer is provided with a plurality of grooves facing the second substrate, a first medium is provided in the grooves and contacts the second substrate, and the dielectric constant of the first medium is smaller than the dielectric constant of the buried layer.

9. The SOI substrate according to claim 8, characterized in that The first medium includes air.

10. A method for manufacturing an SOI substrate, characterized in that: include: Providing a first substrate, and forming a buried layer on the first substrate; forming a plurality of grooves in the buried layer, and forming a first dielectric in the grooves, wherein the dielectric constant of the first dielectric is smaller than the dielectric constant of the buried layer; A second substrate is provided, and the second substrate is bonded on the buried layer.

11. A chip, characterized in that: The chip includes the SOI power device according to any one of claims 1 to 7.

12. An electronic component, characterized in that: The electronic component includes the chip according to claim 11.

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