Method of forming semiconductor device

Abstract

A method for forming a stacked transistor device includes depositing a dummy material, such as by spin-on deposition, to process a first transistor with a second transistor different from the stacked transistor device. Multi-Vt patterning, in which different transistors in the stacked device may have different threshold voltages (Vt), may be implemented by depositing dummy materials prior to patterning to selectively control the Vt of each transistor without affecting the other transistors. In a top-bottom FET stack, by depositing a dummy material, the process may be optimized to ensure that each transistor in the stack is formed to have desired characteristics. The embodiment of the invention also relates to a method for forming the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to methods of forming semiconductor devices. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] Recently, multi-gate devices have been introduced to improve gate control. Multi-gate devices have been observed to increase gate-channel coupling, reduce off-state current and / or reduce short channel effect (SCE). One such multi-gate device is a gate-all-around (GAA) device, which includes a gate structure that can extend partially or completely around a channel region to provide access to the channel region on at least two sides. GAA devices enable aggressive scaling of IC technology, maintain gate control and mitigate SCE, while seamlessly integrating with other IC manufacturing processes. As GAA devices continue to scale, challenges arise when manufacturing gate structures for GAA devices, which have been observed to reduce the performance of GAA devices and increase GAA processing complexity. Therefore, while existing GAA devices and methods of manufacturing such devices have generally been adequate for their intended purposes, they are not completely satisfactory in all respects.

[0004] As the semiconductor industry moves further to smaller technology process nodes in pursuit of higher device density, higher performance and / or lower cost, challenges from manufacturing and design issues have led to stacked device structure configurations, such as complementary field effect transistors (C-FETs), in which an n-type multi-gate transistor and a p-type multi-gate transistor are vertically stacked, one above the other. While existing C-FET structures are generally adequate for their intended purposes, they are not satisfactory in all respects. Summary of the invention

[0005] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: providing a first channel nanostructure group and a second channel nanostructure group stacked in a vertical direction above a semiconductor substrate; providing an opening above the semiconductor substrate; using spin coating deposition to deposit a dummy material in the opening adjacent to one of the first channel nanostructure group or the second channel nanostructure group; performing a process when the dummy material is located in the opening; after performing the process, removing the dummy material; and forming a first gate surrounding the first channel nanostructure group and a second gate surrounding the second channel nanostructure group.

[0006] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: receiving a substrate having a plurality of vertically stacked channel layers; forming a first transistor of a first type having a channel region in a first channel layer among the plurality of vertically stacked channel layers, and forming a second transistor of a second type having a channel region in a second channel layer among the plurality of vertically stacked channel layers; using spin coating deposition to deposit a dummy material laterally adjacent to the first channel layer among the plurality of vertically stacked channel layers and laterally adjacent to the second channel layer among the plurality of vertically stacked channel layers; and etching back the deposited dummy material to provide a top surface of the dummy material below the second channel layer among the plurality of vertically stacked channel layers; and implementing a process for the second transistor.

[0007] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a trench in a source / drain region of a transistor stack, the trench extending through source / drain regions of an upper transistor and a lower transistor; depositing a dummy material filling the trench; etching back the dummy material to form an opening in the trench in the source / drain region of the upper transistor, and the etched-back dummy material is disposed in the source / drain region of the lower transistor; depositing a dielectric liner on the sidewalls of the opening in the source / drain region of the upper transistor; removing the etched-back dummy material; and forming a first epitaxial region associated with the lower transistor when the dielectric liner is located on the sidewalls of the opening in the source / drain region of the upper transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1A flow chart illustrating an embodiment of a method of forming a dielectric material according to one or more aspects of the embodiments of the present disclosure is shown.

[0010] Figure 2 One or more aspects of the present disclosure are shown. Figure 1 A flowchart of an embodiment of a method.

[0011] Figure 3 A partial top view of a device 300 is shown in accordance with one or more aspects of an embodiment of the present disclosure.

[0012] Figures 4 to 15 Each shows a partial cross-sectional view of a device 300 according to one or more aspects of an embodiment of the present disclosure.

[0013] Fig.16 One or more aspects of the present disclosure are shown. Figure 1 A flowchart of an embodiment of a method.

[0014] Figures 17 to 24 Each shows a partial cross-sectional view of a device 2300 according to one or more aspects of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0017] In addition, when "about," "approximately," or the like is used to describe a numerical value or a range of numerical values, as understood by one of ordinary skill in the art, the term is intended to encompass numerical values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the numerical values, the numerical value or range of numerical values ​​encompasses a reasonable range that includes the described numerical value, such as within + / - 10% of the described numerical value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer known to one of ordinary skill in the art is + / - 15%. Further, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] The disclosed embodiments show a configuration for forming a GAA device including vertically stacked transistors. When the top multi-gate device and the bottom multi-gate device have different conductivity types, the stacked multi-gate device can be a complementary field effect transistor (C-FET). The disclosed embodiments provide a method for manufacturing a semiconductor device such as a C-FET. However, the disclosed embodiments are not limited thereto. Those skilled in the art will recognize that various aspects of the disclosed embodiments are also applied to the formation of dielectric materials in other device types.

[0019] In the semiconductor industry, the development of high performance transistors has been a key driver of technological progress. One way to improve transistor performance is to stack multiple transistors on top of each other, forming a 3D structure that allows for more efficient use of spacing and improved power efficiency. However, stacking transistors also presents challenges in terms of process control and device performance. To address these challenges, methods for forming stacked transistor devices have been developed, including depositing dummy materials such as by spin-on deposition.

[0020] One application of these methods is in multi-Vt patterning, where different transistors in a stacked device can have different threshold voltages (Vt). By depositing dummy materials prior to patterning, the process can be tailored to selectively control the Vt of each transistor without affecting the other transistors. This can allow for greater flexibility in designing stacked devices with optimized performance characteristics.

[0021] Another application is in top-bottom FET stacks, where different types of transistors are stacked vertically to achieve specific performance goals. By depositing dummy materials, the process can be optimized to ensure that each transistor in the stack is formed with the desired characteristics. This can improve overall device performance and reliability.

[0022] Therefore, methods for forming stacked transistor devices (including depositing dummy materials) have many applications in the semiconductor industry. From multi-Vt patterning to top-bottom FET stacks, these methods can help improve transistor performance and reliability in various applications. Such examples are provided in the following discussion.

[0023] Figure 1 1 is a flow chart illustrating a method 100 for forming a semiconductor structure such as a C-FET. The method 100 is merely an example and is not intended to limit the disclosed embodiments to those explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. The method 100 may be applied to Figures 2 to 15 The process depicted in the embodiments shown in Figures 2 to 15 is a flowchart describing in detail an embodiment of the method 100 and Figure 2 1 and 2 are corresponding partial top views and cross-sectional views of a device 300 fabricated according to various aspects of the method.

[0024] In an embodiment, the method 100 may also be applied to Figures 16 to 24 The process depicted in the embodiments shown in Figures 16 to 24 is a flow chart detailing an embodiment of the method 100 and a corresponding partial cross-sectional view of the device 2300 . Figures 2 to 15 Examples and Figures 16 to 24 The components and steps of the embodiments can be used in combination with each other. In other words, it is possible to apply Figure 2 Method 200 and Fig.16 The method 2200 of manufacturing a single device. To this end, it should be noted that although device 300 and device 2300 include some different reference numerals, they can be the same workpiece or different regions of the same workpiece. In addition, throughout this application, the same reference numerals represent the same components unless otherwise specified.

[0025] Go to Figure 1, the method 100 includes a block 102, in which a substrate is received. The substrate may include: an elemental (single element) semiconductor, such as silicon (Si), germanium (Ge), and / or other suitable materials; a compound semiconductor (i.e., an alloy semiconductor), such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), and / or other suitable materials. The substrate may be a single layer of material having a uniform composition. Alternatively, the substrate may include multiple material layers having similar or different compositions suitable for IC device manufacturing. In one example, the substrate may be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a buried silicon oxide (BOX) layer. In some embodiments, the substrate includes various doped regions, such as an n-type well or a p-type well. The doped region may be doped with an n-type dopant (such as phosphorus (P) or arsenic (As)) and / or a p-type dopant (such as boron (B) or BF2), depending on design requirements. The doped region may be formed by implantation of dopant atoms, in-situ doping epitaxial growth, and / or other suitable techniques.

[0026] The method 100 also includes a block 104, in which a device structure is formed. In some embodiments, the device structure is a transition structure for forming a C-FET device. The transition structure may include an active region having one or more components of a formed or partially formed transistor. Some components that have been formed in whole or in part on the substrate may include, for example, active regions, dielectric isolation components, gate structures, source / drain regions, contact structures, and / or other components.

[0027] In an embodiment, the device structure includes an opening. In an implementation, the opening may be defined in a channel region of the device, such as an opening provided by removing a dummy gate in a replacement gate process (see, e.g., Fig.13 In embodiments, openings may be defined in the source / drain regions, such as openings provided by recessing the source / drain regions of the active region in preparation for forming regions for growth of epitaxial source / drain material (see, e.g. Fig.17 and the accompanying embodiments). In other embodiments, the openings may be formed at other regions of the device structure, such as a contact layer or an interconnect layer. In an embodiment, the openings may have an aspect ratio where the depth is greater than the width. That is, the openings may have an aspect ratio (depth: width) greater than 1:1. In further embodiments, the openings filled with dummy material may have an aspect ratio greater than 4.

[0028] In block 106 of method 100, a dummy material is deposited on the device structure and within the opening. The dummy material is deposited to form a dummy material layer. The dummy material layer is a sacrificial layer that is later removed from the substrate. In some embodiments, the dummy material layer is used to mask certain regions of the device (e.g., the lower transistor region of a C-FET) while processing is performed on another region of the device (e.g., the upper transistor region of a C-FET).

[0029] In an embodiment, the dummy material layer comprises a carbon-based dielectric. In an embodiment, the dummy material layer comprises: a dielectric material comprising silicon (Si), oxygen (O) and carbon (C), such as SiOC. In an embodiment, the dummy material layer is SiO x Base dielectric.

[0030] In some embodiments, the dummy material layer is formed by depositing one or more materials of Table 1 below. In further embodiments, these precursors (e.g., Table 1) form carbon-based materials, SiOC-based materials, or SiO x Base material.

[0031] Exemplary materials for forming the dummy material layer are included in Table 1 below:

[0032]

[0033]

[0034] or a combination thereof. In some embodiments, two, three, four, or more of the materials in Table 1 may be provided together to form the dummy material deposited in block 106. The materials of Table 1 may be prepared for deposition by spin coating deposition.

[0035] In an embodiment, depositing the dummy material to form the dummy material layer may be performed by a spin coating deposition process (also referred to as spin coating). In an embodiment, the spin coating deposition process is performed at a deposition temperature between about 120° C. and about 250° C. Therefore, using spin coating deposition allows for a relatively low impact on the thermal budget.

[0036] After spin coating deposition, a hard bake step may be performed at a temperature between about 250° C. and about 350° C. Functional groups (e.g., Si-OR) of the components including those shown in the above table will form Si-OH groups, and then two Si-OH groups may form Si-O-Si bonds. As shown in the components in Table 1, Si-C bonds are provided by the reactive polymers of Table 1.

[0037] Spin coating deposition can be performed at a speed of about 1000 and 8000 revolutions per minute (rpm). Spin coating deposition can be performed for about 30 seconds to about 60 seconds. In some embodiments, a soft baking process is performed after spin coating. The soft baking can be, for example, a low temperature bake at about 100° C. or less. Other drying processes can also be implemented.

[0038] In an embodiment, spin coating deposition allows the openings to be filled with dummy material, forming a uniform and consistent dummy material layer. In other words, the dummy material layer is formed without seams or gaps. The uniformity provides several advantages, including providing a uniform etch rate in subsequent processing.

[0039] Method 100 includes frame 108, wherein the pseudo material layer is etched back. In other words, the pseudo material layer is reduced in thickness. In some embodiments, the pseudo material layer is etched back by a chemical mechanical planarization (CMP) process, a wet etching process, a dry etching process, a combination thereof, and / or other suitable removal processes. In an embodiment, multiple etch-back processes are implemented. For example, the CMP process may be followed by an etching process. The etching process may include dry etching, wet etching, reactive ion etching (RIE), various plasma etchings, and / or other suitable processes. For example, the dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. The wet etching process may include etching in dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3) and / or acetic acid (CH3COOH); or other suitable wet etchants.

[0040] As discussed above, block 106 may form a substantially uniform dummy material layer, providing a dummy material layer without voids or seams. Thus, the etch-back process may also be substantially uniform, since a constant etch rate is provided throughout the material of the dummy material layer.

[0041] The method 100 then continues to block 110 where the manufacturing process continues. In some embodiments, after further processing, the dummy material may be removed from the substrate. In an embodiment, the method 100 may continue with additional deposition (block 106) and etching back (block 108) of the dummy material layer. In some embodiments, the method 100 continues to complete the fabrication of the C-FET device, providing a stack of transistors, e.g., a first transistor type (e.g., p-type) as a bottom transistor and a second transistor type (e.g., n-type) as a top transistor. Various interconnects may be formed to interconnect multiple transistors.

[0042] The method 100 is now described with respect to various embodiments of forming a semiconductor device, such as being performed during the formation of a C-FET device. In a first exemplary embodiment, Figure 2 The method 200 provides an implementation of the method 100. In particular, as discussed below, in an exemplary device in block 104, a C-FET device (in transitional fabrication) having source / drain recesses or openings is provided, and in block 106, a dummy material layer is formed within the source / drain recesses or openings.

[0043] Figure 2 is a flow chart of a method 200 for fabricating a C-FET device according to various aspects of an embodiment of the present disclosure. Figures 3 to 15 A view of a device 300 is shown, providing an exemplary illustration of the steps of method 200. For ease of description and understanding, the Figures 3 to 15 Additional steps may be provided before, during, and after method 200, and some steps may be provided before, during, and after method 200. Figures 3 to 15 Additional components are added to the C-FET device 300, and some of the following components may be replaced, modified, or eliminated in other embodiments.

[0044] The method 200 includes block 202 , in which active regions and isolation features are formed. The active regions and isolation regions may be formed on a substrate, substantially similar to the substrate discussed above with reference to block 102 of the method 100 .

[0045] First go to Figure 3 , the top view shows a plurality of active regions 302 extending in the x-direction. Isolation regions 304 are interposed between the active regions 302. A plurality of gate structures 306 or gate lines extend in the y-direction perpendicular to the active regions 302. Along the x-direction, channel regions are provided below the gate structures 306 in the active regions 302, and source / drain regions are located in the active regions 302 between the gate structures 306. The active regions 302, isolation regions 304, and gate structures 306 are formed on a substrate, substantially similar to the substrate discussed above with reference to block 102.

[0046] In an embodiment, the active region 302 includes a vertical stack of nanostructures (or channel members) stacked in the z direction. In some embodiments, the active region 302 can be referred to as a fin because they extend above the substrate. In an embodiment, the device 300 is configured as a C-FET, and each of the gate structures 306 includes a bottom segment and a top segment above the bottom segment. The top segment and the bottom segment can include different work function layer arrangements or different dipole components to form a first type of bottom transistor and a second type of top transistor.

[0047] Figure 4Shown along Figure 3 4. The top view of the active region 302 is a corresponding cross-sectional view of the cutting line BB'. In an embodiment, the active region 302 can be formed by epitaxially growing an epitaxial stack of a first semiconductor layer (e.g., Si) 406 and a second semiconductor layer (e.g., SiGe) 404 alternately disposed on each other over the substrate 402. The semiconductor layer 406 is a nanostructure that provides a channel region of the transistor device; the semiconductor layer 404 is a sacrificial layer that is removed to form a gap, and then the gate structure of the device is formed in the gap.

[0048] Substrate 402 is similar to the above bonding Figure 1 The substrate 402 is a substrate as described in the method 100 of the present invention. The substrate 402 includes: an elemental semiconductor, such as silicon and / or germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or a combination thereof; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; or a combination thereof. In the depicted embodiment, the substrate 402 is a silicon substrate. In some embodiments, the substrate 402 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate 402 (and the mesa 402') may include various doped regions, such as a p-type doped region (e.g., a p-well), an n-type doped region (e.g., an n-well), or a combination thereof. The n-type doped region includes an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. The p-type doped region includes a p-type dopant, such as boron, indium, other p-type dopants, or combinations thereof. In some embodiments, the doped region includes a combination of a p-type dopant and an n-type dopant.

[0049] Semiconductor layer 406 and semiconductor layer 404 are epitaxially grown on substrate 402. The composition of semiconductor layer 406 is different from the composition of semiconductor layer 404 to achieve etching selectivity and / or different oxidation rates during subsequent processing. Semiconductor layer 404 and semiconductor layer 406 include different materials, component atomic percentages, component weight percentages, thicknesses, or combinations thereof to achieve a desired etching selectivity during an etching process, such as an etching process implemented to form a suspended channel layer in the channel region (discussed below). For example, semiconductor layer 404 includes silicon germanium, semiconductor layer 406 includes silicon, and for a given etchant, the silicon etching rate of semiconductor layer 406 is different from the silicon germanium etching rate of semiconductor layer 404. The disclosed embodiments contemplate that semiconductor layer 404 and semiconductor layer 406 include any combination of semiconductor materials that provide a desired etching selectivity, a desired oxidation rate difference, a desired performance characteristic (e.g., a material that increases current), or a combination thereof, including any semiconductor material disclosed herein. Within the stack of semiconductor layers 404, 406, a layer suitable for forming an insulating layer 606 discussed below is provided. This layer may include the same material as semiconductor layer 404, but with a changed atomic percentage that provides an increased oxidation rate. In some embodiments, this layer is silicon germanium with an increased germanium percentage. This layer is subsequently modified to provide an isolation layer between the upper transistor and the lower transistor (as discussed below with respect to 606). Figure 4 A plurality of channel layers 406 for the lower transistor region 408B and a plurality of channel layers 406 for the upper transistor region 408T are shown. The number of channel layers 406 for each of the lower transistor and the upper transistor is not limited to the number shown. Instead, any number of layers may be provided, depending on the desired device performance for the respective transistors.

[0050] After growing across the substrate 402, the stack of semiconductor layers 404, 406 is then patterned to define the active area 302. In some embodiments, the upper region of the substrate 402 is also patterned to form a mesa. The active area 302 can be patterned by any suitable method, such as by one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a pitch that is less than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the active area 302 by etching the epitaxial semiconductor layers 404, 406. The etching process can include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes. For example, the dry etching process can be implemented with oxygen-containing gas, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBR3), iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. For example, the wet etching process can include etching in dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3) and / or acetic acid (CH3COOH); or other suitable wet etchants.

[0051] Again, in the illustrated embodiment, the bottom portion of semiconductor layer stack 408B includes channel member 406 that will form the bottom transistor of C-FET device 300 , and the top portion of semiconductor layer stack 408T includes channel member 406 that will form the top transistor of C-FET device 300 .

[0052] like Figure 3As shown in , the isolation component 304 electrically isolates the active device region 302 and / or the passive device region of the device from each other. The isolation component 304 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including, for example, silicon, oxygen, nitrogen, carbon, other suitable isolation components, etc.) or a combination thereof. The isolation component 304 can have a multilayer structure. For example, the isolation component 304 includes a bulk dielectric (for example, an oxide layer) above a dielectric liner (including, for example, silicon nitride, silicon oxide, silicon oxynitride, carbon oxynitride silicon or a combination thereof). In another example, the isolation component 304 includes a dielectric layer above a doped liner, such as a borosilicate glass (BSG) liner and / or a phosphosilicate glass (PSG) liner. The size and / or characteristics of the isolation component 304 are configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structures or a combination thereof. In an embodiment, the isolation component 304 can provide STI.

[0053] The method 200 includes block 204, wherein a dummy gate structure extending over the isolation region is formed over the active region. The dummy gate structure may be substantially similar to Figure 4 The gate structure shown in FIG. 1 and the gate structure 306 are Figure 3 Extends in the y direction.

[0054] refer to Figure 4 In an example, a gate structure 306 including a dummy gate 502 is formed. The dummy gate 502 may include a dummy gate electrode and a dummy gate dielectric layer. The dummy gate includes a dummy gate electrode and a dummy gate dielectric. Exemplary dummy gate materials include a dummy gate electrode of polysilicon or amorphous silicon and a dummy gate dielectric of silicon oxide. The gate structure 502 is formed above the channel region C and defines adjacent source / drain regions S / D in the active region 302.

[0055] Provided above the gate structure 502 Figure 4 504A and 504C for protection and patterning purposes. In an embodiment, hard mask layer 504A is a first dielectric material, such as SiN, SiCN, SiOCN or other suitable materials. In an embodiment, hard mask layer 504C includes a second dielectric material, such as SiN, SiCN, SiOCN or other suitable materials. In some embodiments, hard mask layer 504A and hard mask layer 504C are different materials. In an embodiment, hard mask layer 504C may also include an oxide component. Layer 504C may include a layer (e.g., a single material), a dual layer, a multilayer, and / or other configurations including those that provide suitable etch selectivity.

[0056] A gate spacer 506 is formed adjacent to and along the sidewall of the dummy gate 502. The gate spacer 506 may include a sealing spacer, an offset spacer, a sacrificial spacer, a dummy spacer, a main spacer, other suitable spacers, or a combination thereof. The gate spacer 506 may have a single-layer structure or a multi-layer structure. The gate spacer 506 includes a dielectric material, which may include silicon, oxygen, carbon, nitrogen, other suitable components, or a combination thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, carbon oxynitride, etc.).

[0057] The method 200 includes box 206, in which the source / drain region of the device is etched to form a groove or opening. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, the dry etching process may be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. For example, the wet etching process may include etching in dilute hydrofluoric acid (DHF); a potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchants. Reference Figure 4 In the example of FIG. 5 , a recess or opening 602 is etched in the S / D region of the active region 302 . The etch of the opening 602 is selective such that it removes the semiconductor layers 406 , 404 relative to the spacers 506 and the hard mask layer 504 .

[0058] The method 200 includes block 208, where isolation features are formed. The isolation region of block 208 may include internal spacers formed to provide isolation between a gate structure (formed subsequently) and source / drain features of the device. In forming the device 300 as a C-FET device, the isolation region of block 208 may also provide an isolation layer between the channel region group 408B of the bottom transistor and the channel region group 408T of the top transistor. Reference Figure 4In an example, after forming the opening 602, an internal spacer 604 is formed on the now exposed edge of the semiconductor layer 404. In some embodiments, forming the internal spacer 604 includes: laterally etching the semiconductor layer 404 to form a gap between the semiconductor layers 406; and filling the gap with a dielectric material. In other embodiments, an oxidation process is performed that converts the edge region of the semiconductor layer 404 into a dielectric material that forms the internal spacer 604. An insulating layer 606 is formed. In some embodiments, the insulating layer 606 is formed by oxidation. In some embodiments, the etching rate of the semiconductor layer is such that it can be selectively removed, forming a gap, and then filling the gap with a dielectric material. In some embodiments, the internal spacer 604 and / or the insulating layer 606 is SiGeO x , silicon oxide or other suitable dielectrics.

[0059] The method 200 then proceeds to block 210, where a dummy material is deposited in the source / drain openings to form a dummy material layer. In some embodiments, the deposition of the dummy material and / or the formation of the dummy material layer may be substantially similar to the above referenced Figure 1 As discussed above with respect to block 106 of method 100. For example, in some embodiments, the pseudo material is deposited by spin coating deposition. Exemplary materials for deposition include those provided in Table 1 above. In some embodiments, the pseudo material layer formed includes a carbon-based material, a SiOC-based material, a SiO x Base materials and / or combinations thereof. Figure 5 In an example, a pseudo material layer 702 is formed. In an embodiment, the pseudo material layer 702 is SiO x Or SiOC. The dummy material 702 is formed such that it fills the opening 602 .

[0060] The method 200 then proceeds to block 212, where the dummy material layer is etched back so that it is reduced in thickness. In some embodiments, etching the dummy material layer can be substantially similar to the method described above with reference to Figure 1 As discussed above with respect to block 108 of method 100. In some implementations, block 212 includes a multi-step process that provides, for example, a planarization step, a wet etch step, and / or a dry etch step.

[0061] The etching back of the dummy material layer 702 reduces the thickness of the dummy material layer to form a dummy material layer 702'. Figure 6. The etch-back of the pseudo material layer 702' provides an opening extending in the source / drain region of the upper transistor region of the device 300. That is, the channel layer 406 of the upper transistor is adjacent to the opening. In particular, the channel layer 406 of the upper transistor is adjacent to the opening laterally or adjacent to the opening in the x-direction. In an embodiment, the sidewalls of the channel layer 406 of the upper transistor are exposed in the opening. The etched-back pseudo material 702' maintains the channel component 406 of the lower device region of the device 300 laterally adjacent. In an embodiment, the etched-back pseudo material 702' is directly disposed on the sidewalls of the channel layer 406 of the lower transistor.

[0062] In an embodiment, etching back the dummy material layer 702 to form the dummy material layer 702' may include a plasma etching process. In an embodiment, the etching process is performed at a temperature between about -10°C and about 250°C. In an embodiment, a reaction gas of the etching process includes HF, NH3, Ar, N2 and / or other suitable gases. In an embodiment, the etching is performed at about 100 mTorr to about 3500 mTorr.

[0063] The method 200 includes block 214, where a dielectric liner is formed. The dielectric liner may be disposed on the etched-back dummy material layer. In an embodiment, the dielectric liner is disposed on the sidewalls of the opening in the source / drain region in the upper transistor region, such that the dielectric liner covers the semiconductor layer 406 of the upper transistor region. Figure 6 In an example, a dielectric liner 1002 is formed on the sidewalls of the opening. The dielectric liner 1002 is disposed on the sidewalls of the semiconductor layer 406, which forms a channel region of the top transistor (300T) of the device 300, as discussed in the following steps. The dielectric liner 1002 may include SiN, SiCN, SiOCN, and / or other suitable materials. The dielectric liner 1002 may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable deposition methods. In some embodiments, after deposition, the dielectric liner 1002 is etched to remove the deposited material from a horizontally arranged surface (e.g., the center of the surface of the hard mask 504B and the etched back pseudo material layer 702').

[0064] After forming the dielectric liner 1002, the dummy material layer 702' is removed from the substrate 402, as shown in FIG. Figure 7 As shown in . In an embodiment, the removal of the dummy material layer 702' may be performed by plasma etching. In an embodiment, the etching process is performed at a temperature between about -10°C and about 250°C. In an embodiment, the reaction gas of the etching process includes HF, NH3, Ar, N2 and / or other suitable gases. In an embodiment, the etching is performed at about 100 mTorr to about 3500 mTorr.

[0065] Method 200 also includes box 216, in which an epitaxial layer is formed to form the source / drain region of the bottom transistor of the C-FET. The source / drain component can be deposited using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. When the source / drain component is n-type, it can include silicon (Si) doped with an n-type dopant (such as phosphorus (P) or arsenic (As)). When the source / drain component is p-type, it can include silicon germanium (SiGe) doped with a p-type dopant (such as boron (B) or boron difluoride (BF2)). In an embodiment, the source / drain component may include multiple layers. Reference Figure 8 1, a source / drain epitaxial feature 1204 is provided. The source / drain epitaxial feature 1204 is associated with the lower transistor of the device 300. The source / drain epitaxial feature 1204 grows from the seed region of the substrate 402 and the exposed sidewalls of the channel region 406 of the lower transistor. While the epitaxial material of the source / drain feature 1204 grows, the channel region 406 of the upper transistor region is covered by the dielectric liner 1002, thereby inhibiting epitaxial growth.

[0066] like Figure 8 As shown in the example of , after growing the epitaxial material for the source / drain of the bottom transistor, the dielectric liner 1002 can be removed by a suitable etching process. The etching process can include a suitable wet etch or dry etch that is selective to the dielectric liner 1002.

[0067] The method 200 includes block 218, where another isolation layer is formed. The isolation layer of block 218 can provide isolation between the source / drain region of the lower transistor of the C-FET and the source / drain region of the upper transistor of the C-FET. The isolation layer can include a multi-layer structure, such as an inter-layer dielectric (ILD) and a contact etch stop layer (CESL). Fig. 9 In an example, ILD 1404B and CESL 1402B are formed over substrate 402. In an embodiment, CESL 1402B may include silicon nitride, and ILD 1404B may include silicon oxide. Other exemplary compositions of CESL 1402B include silicon carbonitride or silicon carbon oxynitride. Other exemplary compositions of ILD 1404B include, for example, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, oxide formed from tetraethyl orthosilicate (TEOS), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), Black 1402B, the ILD 1404B and / or the CESL 1402B may be deposited using PECVD, FCVD, spin coating, or a suitable deposition technique. After depositing the materials for the ILD 1404B and CESL 1402B, the materials are etched back to provide openings 1502 in the source / drain regions of the upper transistors of the device 300.

[0068] Method 200 includes box 220, in which an epitaxial layer is formed to form the source / drain region of the top transistor of the C-FET. The source / drain component can be deposited using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. When the source / drain component is n-type, it can include silicon (Si) doped with an n-type dopant (such as phosphorus (P) or arsenic (As)). When the source / drain component is p-type, it can include silicon germanium (SiGe) doped with a p-type dopant (such as boron (B) or boron difluoride (BF2)). In an embodiment, the source / drain component may include multiple layers. The source / drain component of the upper transistor may include a different dopant type (e.g., n-type and p-type) than the source / drain component of the lower transistor. Reference Fig.10 , forming source / drain epitaxial component 1602. Source / drain epitaxial component 1602 provides a source / drain for an upper transistor of device 300. Source / drain epitaxial component 1602 may include a first dopant type, and source / drain epitaxial component 1204 may include a second dopant type. In some embodiments, the first dopant type is a p-type dopant, and the second dopant type is an n-type dopant.

[0069] The method 200 includes block 222, where another isolation layer is formed. The isolation layer may include another interlayer dielectric (ILD) and another contact etch stop layer (CESL). The isolation layer may be substantially similar to the isolation layer discussed above with reference to block 218. Fig.11In an example, an ILD 1404T and a CESL 1402T are formed over the substrate 402. In an embodiment, the CESL 1402T may include silicon nitride, and the ILD 1404T may include silicon oxide. Other exemplary compositions of the CESL 1402T include silicon carbonitride or silicon carbon oxynitride. Other exemplary compositions of the ILD 1404T include, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, oxide formed of tetraethyl orthosilicate (TEOS), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), Black 204T and CESL 1402T provided in block 218 may be the same or different compositions as those provided in block 222.

[0070] The method 200 includes block 224, where a replacement gate is formed. The replacement gate is formed by a process including removing the dummy gate, releasing the channel layer, and forming a metal gate having an upper portion associated with the upper transistor and a lower portion associated with the lower transistor. Fig.12 In the example of FIG. 4 , the dummy gate 502 is removed to form a gate opening 1802 exposing the upper channel layer 406. The gate opening 1802 has a sidewall formed by the gate spacer 506. After removing the dummy gate, as shown in FIG. Fig.13 As shown in , the semiconductor layer 406 forming the channel layer of the device is released. The channel release process may include selectively removing the semiconductor layer 404 to form a gap 1902 between the semiconductor layers 406 and between the semiconductor layer 406 and the substrate 402, thereby suspending the semiconductor layer 406 in the channel region of the device 300. The suspended semiconductor layer 406 is provided in two groups - one group for the lower transistor channel region and one group for the upper transistor channel region. In the illustrated embodiment, two suspended semiconductor layers 406 are stacked vertically in the z direction and provide two channels through which current can flow between the epitaxial source / drain features 1204 for the bottom transistor, and two suspended semiconductor layers 406 are stacked vertically in the z direction and provide two channels through which current can flow between the source / drain features 1602 for the top transistor. However, in other embodiments, any number of suspended semiconductor layers may be provided. The suspended semiconductor layer 406 is hereinafter referred to as a channel layer or a channel member or a channel nanostructure.

[0071] After the channel is released, a gate structure for the device is formed. The gate structure may be a metal gate structure and includes a lower portion or lower gate stack and an upper portion or upper gate stack for a lower transistor and an upper transistor of the device, respectively. The gate stack includes a gate electrode layer and a gate dielectric layer. In an embodiment, the gate electrode of the bottom transistor provides a first work function and the gate electrode of the top transistor provides a second work function.

[0072] like Fig.14 As shown in the example of , a gate dielectric layer 2002 is formed on the channel region 406. The gate dielectric layer 2002 for the bottom device 300B is labeled 2002B, and the gate dielectric layer 2002 for the top device 300A is labeled 2002T. In some embodiments, the gate dielectric layers 2002T, 2002B include the same material. The gate dielectric layer 2002 may include an interfacial layer and / or a high-k dielectric layer. High-k dielectric materials generally refer to dielectric materials having a dielectric constant greater than the dielectric constant of silicon dioxide (k≈3.9), such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba, Sr)TiO3 (BST), Si3N4, HfO2-Al2O3, other high-k dielectric materials or combinations thereof.

[0073] A first gate electrode layer 2004B is formed in the bottom transistor 300B. Fig.15 As shown in , a second gate electrode layer 2004T is formed in the top transistor 300T. In one embodiment, the first work function layer 2004B is a p-type work function layer, and the second work function layer 2004T is an n-type work function layer. In another example, the first work function layer 2004B is an n-type work function layer, and the second work function layer 2004T is a p-type work function layer. Exemplary n-type work function materials include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, or TiAlN. Exemplary p-type work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or WN. The gate electrode layer 2004 and the gate dielectric layer 2002 together form a gate structure 306, see Figure 3 .

[0074] The method 200 may continue to block 226, where additional processing is performed. In some embodiments, various interconnects of a multi-layer interconnect (MLI) component are formed to facilitate operation of the C-FET device 300. The MLI component electrically couples various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate structures and / or source / drain components) of the device 300 so that the various devices and / or components can operate as dictated by the design requirements of the C-FET device. The MLI component includes a combination of dielectric layers (such as ILD layers) and conductive layers configured to form various interconnects. During operation of the C-FET device 300, the interconnects are configured to route signals between devices and / or components of the C-FET 300 (including routing to the lower transistor 300B and the upper transistor 300A) and / or distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to devices and / or components of the device 300. The conductive layers are configured to form vertical interconnects (such as device level contacts and / or vias) and / or horizontal interconnects (such as conductive lines).Vertical interconnects typically connect horizontal interconnects in different layers (or different planes) of an MLI component.

[0075] Thus, the C-FET device 300 includes a first, lower transistor 300B and a second, upper transistor 300A. In other embodiments, transistors of a stacked transistor structure (such as the stacked transistors 300A and 300B of the device 300) may be manufactured individually, monolithically, or sequentially. When manufactured individually, the top transistor and the bottom transistor may be manufactured individually, and then the top transistor is joined / attached to the bottom transistor. When manufactured sequentially, the first semiconductor layer group may be processed to form the bottom transistor, and then the second semiconductor layer group is attached / joined to the bottom transistor and processed to form the top transistor (i.e., the top transistor is manufactured on the bottom transistor). In the manufacturing method, one or more dummy material layers may be formed according to various aspects of methods 100 and 200, wherein the dummy material layers are used to mask certain portions of the device while processing other portions of the device.

[0076] exist Figure 1 In another exemplary embodiment of the method 100, Fig.16 The method 2200 of the present invention provides an embodiment of the method 100. In particular, as discussed below, in the exemplary device in block 104 of the method 100, a C-FET device at a transition point in manufacturing is provided, which has an opening for receiving a dummy material layer. As shown below, the method 2200 provides an opening in the channel region of the device by removing the dummy gate structure, and forms a dummy material layer within the opening, such as described in block 106 of the method 100.

[0077] Fig.16is a flow chart of a method 2200 for fabricating a C-FET device according to various aspects of an embodiment of the present disclosure. Additional steps may be provided before, during, and after the method 2200, and some steps may be provided before, during, and after the method 2200. Figures 17 to 24 A cross-sectional view of device 2300 is shown, providing an exemplary illustration of the steps of method 2200 . Figure 3 A top schematic view of a C-FET device corresponding to C-FET device 2300 is also shown. Figures 17 to 24 is partial and simplified for ease of description and understanding. Figures 17 to 24 Additional components are added to the C-FET device 2300, and some of the following components may be replaced, modified, or eliminated in other embodiments.

[0078] The method 2200 includes a block 2202 in which a transition structure of a C-FET device is provided. During the manufacture of the C-FET device, the transition structure provided in block 2202 may be within a gate cycle process (e.g., formation of a gate structure). In an embodiment, components (e.g., gate and source / drain terminals) of a bottom transistor of the C-FET have been formed. And with respect to a top transistor of the C-FET, source / drain components have been formed, and a step of forming a gate structure of the top transistor is to be performed.

[0079] refer to Fig.17 In an example of the present invention, a device 2300 is provided. Fig.17 2 shows a transition structure during the manufacture of a C-FET device 2300, and in particular a transition structure provided during a gate stack formation cycle. The device 2300 may be substantially similar to the device 300. In particular, in an embodiment, the transition structure of the device 2300 shares the transition structure discussed above with reference to the method 200. Fig.15 In other words, the steps of forming and releasing the channel layer 406 in the channel region have been performed, and the source / drain features 1204 and 1602 have been formed in the source / drain region. A gate structure including a gate electrode 2004B and a gate dielectric 2002B for the bottom transistor (labeled 2300B) of the device 2300 has been fabricated.

[0080] Method 2200 provides an example of forming a gate structure of an upper device of C-FET device 2300. Fig.17 In an example, an opening 2302 is provided above the channel region of the device 2300. In an embodiment, the opening 2302 is provided by removing a dummy gate structure. The dummy gate structure removed to form the opening 2302 can be substantially similar to the dummy gate 502 and its removal to form the opening 1802, which is discussed above with reference to the method 200 and the device 300. Fig.17 In the transition phase of the top device 2300A, the gate structure of the top device 2300A has not yet been formed. Therefore, the top device 2300A includes a dummy plug 2304 located between the channel components 406. In an embodiment, the dummy plug 2304 includes a dielectric material such as aluminum oxide. The dummy plug 2304 can protect the channel component 406 of the upper transistor 2300T during the processing of the gate structure of the bottom transistor 2300B. Similarly, a hard mask layer 2306 can be formed on the uppermost channel component 406.

[0081] The method 2200 includes block 2204, wherein a dummy material is deposited to form a dummy material layer in an opening of the transition device structure. Referring to the example of device 2300, Fig.18 Provides along Fig.17 2300T and the lower transistor 2300B. Any number of channel layers 406 may be implemented, depending on the design of the C-FET device 2300.

[0082] In an embodiment, the dummy material layer 2402 is formed in the opening 2302. The dummy material layer 2402 can be formed according to various aspects of the method 100. That is, in some embodiments, according to Figure 1 In various aspects of block 106 of method 100, a dummy material layer 2402 is deposited in opening 2302. For example, in some embodiments, dummy material layer 2402 is formed by a spin-on deposition process. In an embodiment, dummy material layer 2402 includes SiO x In some embodiments, the dummy material layer 2402 is SiO formed by depositing one or more of the materials in Table 1 discussed above. x or SiOC. The deposition method provided by block 106 of method 100 may provide the dummy material layer 2402 in the opening 2302 such that the layer is formed to have a uniform structure (eg, without seams or gaps).

[0083] The method 2200 includes block 2206, where the dummy material layer is etched back so that it is reduced in thickness. The etch back process can be provided by a planarization process, a wet etching process, a dry etching process, and / or other suitable methods. In some embodiments, block 2206 includes a multi-step process, for example, a planarization step, a wet etching step, and / or a dry etching step are provided in combination. Fig.19In the example of device 2300 in FIG. 2 , the pseudo material layer 2402 has been etched back to form a pseudo material layer 2402′. In an embodiment, the pseudo material layer 2402 is etched back so that it is laterally adjacent to the channel region 406 of the lower transistor and is removed from an area adjacent to the channel region 406 of the upper transistor. In an embodiment, etching back the pseudo material layer to form the pseudo material layer 2402′ may be plasma etching. In an embodiment, the etching process is performed at a temperature between about -10°C and about 250°C. In an embodiment, the reaction gas of the etching process includes HF, NH3, Ar, N2 and / or other suitable gases. In an embodiment, etching is performed at about 100 mTorr to about 3500 mTorr.

[0084] The method 2200 includes block 2208, where the first type of gate material is removed from the upper transistor region. Fig. 20 In the example of FIG. 2 , metal layer 2004 is removed from the region of the upper transistor, leaving metal layer 2004B adjacent to channel region 406 of lower transistor 2300B. In some embodiments, gate dielectric layer 2002 remains in the region of lower transistor 2300B and in the region of upper transistor 2300T.

[0085] In some embodiments, the metal gate 2004B can have a work function adjusted to a first device type (e.g., a p-type work function) associated with the bottom transistor 2300B. Since a second device type (e.g., an n-type work function) is desired for the top device 2300A, it is desirable to remove the metal gate material 2004. The metal gate 2004B can be removed in an etching process performed at a temperature between about 20° C. and about 75° C. In an embodiment, the metal gate 2004B is removed by an etching process (e.g., plasma etching) including an etching gas of H2O, H2O2, NH4OH, and / or other suitable gases. The etching process can be a selective etching process for the conductive material of the metal gate 2004B.

[0086] The method 2200 then proceeds to block 2210 where the dummy material layer is removed from the substrate after the metal gate is removed from the upper transistor region. Fig.21 In an example, the dummy material layer 2402' is removed. In an embodiment, the removal of the dummy material layer 2402' is performed using an etching process at a temperature between about -10°C and about 250°C. In an embodiment, the dummy material layer 2402' is removed by an etching process that implements a reaction gas (and carrier gas) of HF, NH3, Ar, N2, and / or other suitable gases. In an embodiment, the dummy material 2402' is removed at a process pressure between about 10 mTorr and about 3500 mTorr.

[0087] The method 2200 then proceeds to block 2212 where the dummy plug and hard mask layer are removed to release the channel layer of the upper transistor. Fig. 22 In the example of FIG. 23, the hard mask 2306 and the dummy plug 2304 are removed from the device 2300. In an embodiment, the removal is performed by a selective etching process such as a selective wet etching process. After removing the hard mask 2306 and the dummy plug 2304, the upper channel member 406 is surrounded by a gap, such as Fig. 22 as shown in .

[0088] The method 2200 then proceeds to block 2214, where a second type of gate material is deposited. The second type of gate material may be selected to provide a work function for the upper transistor of the device. Referring to the example of device 2300, a metal gate electrode material, labeled 2004T, is deposited. Fig.23 As shown in . The metal gate electrode 2004T can provide a different work function than the metal gate material previously deposited to form the metal gate 2004B. In one embodiment, the first work function layer provides the metal gate 2004B, which is a p-type work function layer, and the second work function layer provides the metal gate 2004T as an n-type work function layer. In another example, the first work function layer provides the metal gate 2004B as an n-type work function layer, and the second work function layer provides the metal gate 2004T as a p-type work function layer. Exemplary n-type work function materials include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC or TiAlN. Exemplary p-type work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2 or WN. Fig.23 A cross-sectional view of the channel region cut along CC′ is shown, providing an upper channel layer 406 surrounded by a gate stack of gate electrode 2004T and gate dielectric 2002T and a lower channel layer 406 surrounded by a gate stack of gate electrode 2004B and gate dielectric 2002B.

[0089] Fig.24 A corresponding cross-sectional view along the channel (e.g., the cutting direction between the two source / drain components) of the C-FET device 2300 is shown. The method 2200 then continues with additional fabrication. The additional fabrication may be substantially similar to that described above with reference to Figure 2 As discussed in block 226 of method 200 .

[0090] As described above, the top device of the C-FET and the bottom device of the C-FET have different composition requirements to affect different performance. Therefore, they need to be processed differently. One way to provide differentiated processing is to use a dummy material layer, such as the dummy material layer 2402 described in the embodiment of the C-FET device 2300 and the dummy material layer 702 described in the embodiment of the C-FET device 300. As described in detail above, according to Figure 1 The method 100 forms the dummy material layer 702 and / or the dummy material layer 2402 to provide a uniform composition of the dummy material layer.

[0091] In one exemplary aspect, the disclosed embodiments relate to a method. The method includes: providing a first channel nanostructure group and a second channel nanostructure group stacked in a vertical direction on a semiconductor substrate. Providing an opening above the semiconductor substrate. Using spin coating deposition, a dummy material is deposited in the opening adjacent to one of the first channel nanostructure group or the second channel nanostructure group. A process is performed when the dummy material is located in the opening. After performing the process, the dummy material is removed, and a first gate surrounding the first channel nanostructure group and a second gate surrounding the second channel nanostructure group are formed.

[0092] In an embodiment, the dummy material is SiOC or SiO x One of: wherein x is greater than 0. In some embodiments, depositing the dummy material comprises introducing at least one of the following compounds:

[0093] Wherein, R, R1, R2, R3 are each an alkyl series, and each of n, l and m is greater than 0. In an embodiment, providing an opening comprises etching an opening in the source / drain region. The opening can be provided by removing a dummy gate structure to provide an opening. In an embodiment, the dummy material is etched back before performing the process.

[0094] In some embodiments, the process includes depositing a liner layer on sidewalls of the opening. In some embodiments, the process includes removing a portion of the metal gate layer adjacent to the second channel nanostructure group when the dummy material is adjacent to the first channel nanostructure group.

[0095] In another broader embodiment of the present disclosure, a method is provided, the method comprising receiving a substrate having a plurality of vertically stacked channel layers. Forming a first transistor of a first type having a channel region in a first of the plurality of vertically stacked channel layers and a second transistor of a second type having a channel region in a second of the plurality of vertically stacked channel layers. Depositing a dummy material laterally adjacent to the first of the plurality of vertically stacked channel layers and laterally adjacent to the second of the plurality of vertically stacked channel layers using spin-on deposition. Etching back the deposited dummy material to provide a top surface of the dummy material below the second of the plurality of vertically stacked channel layers. Performing a process for the second transistor.

[0096] In an embodiment, the process of the method includes removing a metal layer adjacent to a second one of the plurality of vertically stacked channel layers. And another metal layer may be formed around the second one of the plurality of vertically stacked channel layers. The other metal layer has a different work function than the metal layer. In an embodiment, the process of the method includes etching a dielectric liner layer deposited on the second one of the plurality of vertically stacked channel layers. In an embodiment, the dielectric liner layer is disposed directly on the dummy material. The spin coating deposition includes depositing at least one compound from the group of compounds consisting of:

[0097] And wherein, R, R1, R2, R3 are each an alkyl series, and each of n, l and m is greater than 0.

[0098] In another more extensive method discussed herein, a trench is formed in the source / drain region of the transistor stack. The trench extends through the source / drain region of the upper transistor and the lower transistor. A dummy material is deposited, filling the trench. The dummy material is etched to form an opening in the trench in the source / drain region of the upper transistor, and the etched-back dummy material is disposed in the source / drain region of the lower transistor. A dielectric liner is deposited on the sidewalls of the opening in the source / drain region of the upper transistor. The etched-back dummy material is removed, and a first epitaxial region associated with the lower transistor is formed when the dielectric liner is located on the sidewalls of the opening in the source / drain region of the upper transistor.

[0099] In a further embodiment, the dielectric liner is removed and an isolation layer is formed on the first epitaxial region in the trench. A second epitaxial region associated with the upper transistor is formed above the isolation layer. In a further embodiment, the method includes forming a metal gate structure for each of the lower transistor and the upper transistor. In an embodiment, depositing the dummy material includes a spin-on deposition process. And the spin-on deposition provides at least one compound of the group of compounds consisting of:

[0100] And wherein each of R, R1, R2, and R3 is an alkyl group, and each of n, l, and m is greater than 0. In some embodiments of the method, etching back the dummy material includes a planarization process and a subsequent plasma etching process.

[0101] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: providing a first channel nanostructure group and a second channel nanostructure group stacked in a vertical direction on a semiconductor substrate; providing an opening above the semiconductor substrate; using spin coating deposition to deposit a dummy material in the opening adjacent to one of the first channel nanostructure group or the second channel nanostructure group; performing a process when the dummy material is in the opening; after performing the process, removing the dummy material; and forming a first gate surrounding the first channel nanostructure group and a second gate surrounding the second channel nanostructure group. In some embodiments, the dummy material is SiOC or SiO x In some embodiments, depositing the dummy material comprises introducing at least one of the following compounds: And wherein each of R, R1, R2, R3 is an alkyl series, and each of n, l and m is greater than 0. In some embodiments, providing the opening includes etching the opening in the source / drain region. In some embodiments, providing the opening includes removing a dummy gate structure to provide the opening. In some embodiments, the method further includes: etching back the dummy material before implementing the process. In some embodiments, implementing the process includes depositing a liner layer on the sidewalls of the opening. In some embodiments, implementing the process includes removing a portion of the metal gate layer adjacent to the second channel nanostructure group when the dummy material is adjacent to the first channel nanostructure group.

[0102] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: receiving a substrate having a plurality of vertically stacked channel layers; forming a first transistor of a first type having a channel region in a first channel layer of the plurality of vertically stacked channel layers, and forming a second transistor of a second type having a channel region in a second channel layer of the plurality of vertically stacked channel layers; using spin-on deposition to deposit a dummy material laterally adjacent to the first channel layer of the plurality of vertically stacked channel layers and laterally adjacent to the second channel layer of the plurality of vertically stacked channel layers; and etching back the deposited dummy material to provide a top surface of the dummy material below the second channel layer of the plurality of vertically stacked channel layers; and performing a process for the second transistor. In some embodiments, the process includes removing a metal layer adjacent to the second channel layer of the plurality of vertically stacked channel layers. In some embodiments, the method further includes: forming another metal layer surrounding the second channel layer of the plurality of vertically stacked channel layers, wherein the another metal layer has a different work function than the metal layer. In some embodiments, the process includes etching a deposited dielectric liner layer on the second channel layer of the plurality of vertically stacked channel layers. In some embodiments, the dielectric liner layer is disposed directly on the dummy material. In some embodiments, the spin coating deposition comprises depositing at least one compound from the group consisting of: And wherein, R, R1, R2, R3 are each an alkyl series, and each of n, l and m is greater than 0.

[0103] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a trench in a source / drain region of a transistor stack, the trench extending through the source / drain region of an upper transistor and a lower transistor; depositing a dummy material filling the trench; etching back the dummy material to form an opening in the trench in the source / drain region of the upper transistor, and the etched-back dummy material is disposed in the source / drain region of the lower transistor; depositing a dielectric liner on the sidewall of the opening in the source / drain region of the upper transistor; removing the etched-back dummy material; and forming a first epitaxial region associated with the lower transistor when the dielectric liner is located on the sidewall of the opening in the source / drain region of the upper transistor. In some embodiments, the method further comprises: removing the dielectric liner; forming an isolation layer on the first epitaxial region in the trench; and forming a second epitaxial region associated with the upper transistor above the isolation layer. In some embodiments, the method further comprises: forming a metal gate structure for each of the lower transistor and the upper transistor. In some embodiments, depositing the dummy material comprises a spin coating deposition process. In some embodiments, the spin coating deposition process provides at least one compound selected from the group consisting of: And wherein each of R, R1, R2, and R3 is an alkyl series, and each of n, l, and m is greater than 0. In some embodiments, etching back the dummy material includes a planarization process and a subsequent plasma etching process.

[0104] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: Providing a first channel nanostructure group and a second channel nanostructure group stacked in a vertical direction over a semiconductor substrate; providing an opening above the semiconductor substrate; using spin coating deposition to deposit a dummy material in the opening adjacent to one of the first channel nanostructure group or the second channel nanostructure group; performing a process while the dummy material is in the opening; After performing the process, removing the dummy material; as well as A first gate surrounding the first channel nanostructure group and a second gate surrounding the second channel nanostructure group are formed.

2. The method according to claim 1, wherein: The pseudo material is SiOC or SiO x One of them.

3. The method according to claim 1, wherein: Depositing the dummy material includes introducing at least one of the following compounds: And wherein, R, R1, R2, R3 are each an alkyl series, and each of n, l and m is greater than 0.

4. The method according to claim 1, wherein: Providing the opening includes etching the opening in the source / drain region.

5. The method according to claim 1, wherein: Providing the opening includes removing a dummy gate structure to provide the opening.

6. The method according to claim 1, further comprising: Before performing the process, the dummy material is etched back.

7. The method according to claim 1, wherein: Performing the process includes depositing a liner layer on sidewalls of the opening.

8. The method according to claim 1, wherein: Performing the process includes removing a portion of the metal gate layer adjacent to the second channel nanostructure group when the dummy material is adjacent to the first channel nanostructure group.

9. A method of forming a semiconductor device, comprising: receiving a substrate having a plurality of vertically stacked channel layers; forming a first transistor of a first type having a channel region in a first channel layer of the plurality of vertically stacked channel layers, and forming a second transistor of a second type having a channel region in a second channel layer of the plurality of vertically stacked channel layers; depositing a dummy material using spin-on deposition laterally adjacent to the first channel layer of the plurality of vertically stacked channel layers and laterally adjacent to the second channel layer of the plurality of vertically stacked channel layers; as well as etching back the deposited dummy material to provide a top surface of the dummy material below the second channel layer of the plurality of vertically stacked channel layers; as well as A process for the second transistor is performed.

10. A method of forming a semiconductor device, comprising: forming a trench in a source / drain region of the transistor stack, the trench extending through the source / drain regions of the upper transistor and the lower transistor; depositing a dummy material filling the trench; etching back the dummy material to form an opening in the trench in the source / drain region of the upper transistor, and the etched-back dummy material is disposed in the source / drain region of the lower transistor; depositing a dielectric liner on sidewalls of the opening in the source / drain region of the upper transistor; removing the etched-back dummy material; as well as A first epitaxial region associated with the lower transistor is formed while the dielectric liner is located on the sidewalls of the opening in the source / drain region of the upper transistor.

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