Display panel

Abstract

A display panel is provided. The display panel includes: a base layer; a light shielding pattern on the base layer; a semiconductor pattern not overlapping the light shielding pattern; a lower capacitor pattern including a first portion overlapping the light shielding pattern and a second portion protruding from the first portion in the first direction and overlapping the semiconductor pattern; an upper capacitor pattern overlapping the lower capacitor pattern; and a light emitting element connected to the semiconductor pattern. The light shielding pattern includes a lower surface facing the base layer, an upper surface opposite to the lower surface, and a side surface connecting the lower surface and the upper surface. The upper capacitor pattern overlaps a side surface facing the semiconductor pattern in the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0152697 filed in the Korean Intellectual Property Office on November 7, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Herein, the present disclosure relates to a display panel, and more particularly, to a display panel including circuit elements having improved reliability. Background Art

[0004] The display panel includes a plurality of pixels and a driving circuit (e.g., a scan driving circuit and a data driving circuit) for controlling the plurality of pixels. Each of the plurality of pixels includes a display element and a pixel driving circuit for controlling the display element. The pixel driving circuit may include a plurality of transistors and at least one capacitor connected to each other. Summary of the invention

[0005] The present disclosure provides a display panel with improved display quality. More specifically, the present disclosure provides a display panel with reduced occurrence of bright spots.

[0006] One or more embodiments of the present disclosure provide a display panel, which includes: a substrate layer; a shading pattern on the substrate layer; a semiconductor pattern that does not overlap with the shading pattern; a lower capacitor pattern including a first part and a second part, the first part overlaps with the shading pattern, and the second part protrudes from the first part in a first direction and overlaps with the semiconductor pattern; an upper capacitor pattern overlapping with the lower capacitor pattern; and a light-emitting element connected to the semiconductor pattern, wherein the shading pattern includes a lower surface facing the substrate layer, an upper surface opposite to the lower surface, and a side surface connecting the lower surface and the upper surface, and the upper capacitor pattern overlaps with the side surface facing the semiconductor pattern in the first direction.

[0007] In one or more embodiments, an angle between a lower surface and a side surface of the light shielding pattern may be about 60 degrees to about 80 degrees.

[0008] In one or more embodiments, the display panel may include: a first insulating layer on the base layer and covering the light-shielding pattern; a second insulating layer on the first insulating layer and covering the semiconductor pattern; a third insulating layer on the second insulating layer and covering the lower capacitor pattern; a fourth insulating layer on the third insulating layer and covering the upper capacitor pattern; and a fifth insulating layer on the fourth insulating layer and including an organic material.

[0009] In one or more embodiments, the display panel may further include a bridging pattern overlapping the semiconductor pattern and the second portion of the lower capacitor pattern, wherein one end of the bridging pattern may be connected to the semiconductor pattern via a first contact hole passing through the second insulating layer and the third insulating layer, and the other end of the bridging pattern may be connected to the second portion of the lower capacitor pattern via a second contact hole passing through the third insulating layer.

[0010] In one or more embodiments, the first insulating layer, the second insulating layer, the lower capacitor pattern, the third insulating layer, the upper capacitor pattern, and the fourth insulating layer may be on a side surface of the light shielding pattern facing the semiconductor pattern in the first direction.

[0011] In one or more embodiments, a portion of the upper capacitor pattern overlapping a side surface of the light shielding pattern facing the semiconductor pattern in the first direction may be inclined at an angle corresponding to an inclined angle of the side surface.

[0012] In one or more embodiments, the display panel may include a first power line extending along a first direction and spaced apart from each other along a second direction intersecting the first direction, a scan line, a sensing line, and a data line extending along the second direction, wherein a shading pattern may be located between the scan line and the sensing line.

[0013] In one or more embodiments, the scan line may further include a scan pattern protruding in the second direction, and the scan pattern may overlap the semiconductor pattern.

[0014] In one or more embodiments, a portion of the scan pattern overlapping the semiconductor pattern may include a gate of a transistor including the semiconductor pattern.

[0015] In one or more embodiments, the scan pattern may be on the second insulating layer and covered by the third insulating layer, and a portion of the scan pattern may be connected to the scan line through a contact hole in the third insulating layer.

[0016] In one or more embodiments, the display panel may further include a data pattern having one end overlapping the semiconductor pattern and the other end overlapping the data line, wherein one end of the data pattern can be connected to the semiconductor pattern via a third contact hole passing through the second insulating layer and the third insulating layer, and the other end of the data pattern can be connected to the data line via a fourth contact hole passing through the first insulating layer to the third insulating layer.

[0017] In one or more embodiments, the light-emitting element may include a first electrode, a second electrode, and a common layer located between the first electrode and the second electrode on a fifth insulating layer, and the first electrode may be connected to the upper capacitor pattern through a fifth contact hole passing through the fourth insulating layer and a sixth contact hole passing through the fifth insulating layer and overlapping with the fifth contact hole.

[0018] In one or more embodiments, the display panel may further include an encapsulation layer on the light emitting element and including a plurality of inorganic layers and an organic layer between the plurality of inorganic layers.

[0019] In one or more embodiments, the display panel may further include a light control layer on the encapsulation layer and including a color control pattern including quantum dots and a color filter pattern on the color control pattern.

[0020] In one or more embodiments of the present disclosure, a display panel includes: a base layer; a light shading pattern on the base layer; a data line spaced apart from the light shading pattern along a first direction and extending along a second direction intersecting the first direction; a capacitor including a lower capacitor pattern overlapping the light shading pattern and an upper capacitor pattern overlapping the lower capacitor pattern; and a pixel including a light emitting element and a first transistor, a second transistor, and a third transistor, each of the first to third transistors including a semiconductor pattern, wherein the semiconductor pattern included in the second transistor is connected to the data line, and a side surface of the light shading pattern facing the semiconductor pattern in the second transistor in the first direction is covered by the upper capacitor pattern.

[0021] In one or more embodiments, an angle between the base layer and a side surface of the light shielding pattern may be about 60 degrees to about 80 degrees.

[0022] In one or more embodiments, the display panel may include first power lines extending along a first direction and spaced apart from each other along a second direction intersecting the first direction, scan lines and sensing lines, and an initial line extending along the second direction, wherein a shading pattern may be located between the scan lines and the sensing lines.

[0023] In one or more embodiments, the semiconductor pattern in the first transistor may be connected to the first power line.

[0024] In one or more embodiments, the semiconductor pattern included in the third transistor may be connected to the initial line.

[0025] In one or more embodiments, a portion of the upper capacitor pattern overlapping a side surface of the light shielding pattern may be inclined at a predetermined angle. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0027] Figure 1A is a perspective view of a display panel according to one or more embodiments of the present disclosure;

[0028] Figure 1B is a perspective view of a curved display panel according to one or more embodiments of the present disclosure;

[0029] Figure 2A is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0030] Figure 2B is a plan view of a display panel according to one or more embodiments of the present disclosure;

[0031] Figure 3 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure;

[0032] Figure 4 is an enlarged plan view of a display area according to one or more embodiments of the present disclosure;

[0033] Figure 5A is a plan view illustrating that conductive patterns included in a pixel unit according to one or more embodiments of the present disclosure are stacked in a stacking order;

[0034] Figure 5B is along Figure 5A A cross-sectional view taken along line II' in FIG.

[0035] FIG. 6A to FIG. 6I is a plan view illustrating, for each layer, a stacking order of conductive patterns included in a pixel unit according to one or more embodiments of the present disclosure;

[0036] Fig. 7A is an enlarged plan view of a region of a pixel unit according to one or more embodiments of the present disclosure;

[0037] Figure 7B is along Fig. 7A A cross-sectional view taken along line III-III';

[0038] Fig. 8A is a plan view of a comparative example; and

[0039] Figure 8B is along Fig. 8A A cross-sectional view taken along line IV-IV'. DETAILED DESCRIPTION

[0040] In the present disclosure, it will be understood that when an element (or region, layer, part and / or the like) is referred to as being "on," "connected to" or "coupled to" another element, it can be directly arranged on, directly connected to or directly coupled to the other element, or intervening elements may be arranged therebetween.

[0041] Throughout the text, similar reference numerals or symbols refer to similar elements. In addition, in the accompanying drawings, for the effective description of the technical content, the thickness, ratio and size of the elements are exaggerated. The term "and / or" includes all of one or more combinations that the associated elements can define.

[0042] Although the terms first, second, etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the spirit or scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may also be referred to as a first element. Unless the context clearly indicates otherwise, the singular also includes the plural.

[0043] In addition, terms such as "below", "lower", "above", and "upper" are used to describe the relationship of elements illustrated in the drawings. These terms have relative concepts and are described based on the directions indicated in the drawings.

[0044] It will be understood that terms such as “include” or “have”, when used in this document, are intended to specify the presence of stated features, integers, steps, operations, elements, components or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an overly idealized or overly formal sense, unless explicitly defined as such in this article.

[0046] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0047] Figure 1A is a perspective view of a display panel according to one or more embodiments of the present disclosure. Figure 1B is a perspective view of a curved display panel according to one or more embodiments of the present disclosure. Figure 2A is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure. Figure 2B is a plan view of a display panel according to one or more embodiments of the present disclosure. Figure 3 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure. Figure 4 is an enlarged plan view of a display area according to one or more embodiments of the present disclosure.

[0048] Figure 1A or Figure 1B The display panel DP or DP-1 shown in the figure may be a light-emitting display panel, and may be a liquid crystal display panel, an electrophoretic display panel, a micro-electromechanical system (MEMS) display panel, an electrowetting display panel, an organic light-emitting display panel, an inorganic light-emitting display panel and / or a quantum dot display panel. In addition, the display panel DP or DP-1 according to one or more embodiments of the present disclosure may include ultra-small light-emitting elements. For example, the display panel DP or DP-1 may include micro-LED elements and / or nano-LED elements, but the present disclosure is not particularly limited thereto.

[0049] refer to Figure 1A , the display panel DP may display an image through the display surface DP-IS. The upper surface of the member arranged on the uppermost side of the display panel DP may be defined as the display surface DP-IS. According to one or more embodiments, Figure 2A An upper surface of the window panel WD illustrated in FIG. 4 may be provided as a display surface DP-IS of the display panel DP.

[0050] The display surface DP-IS may be parallel to a plane defined by the first direction DR1 and the second direction DR2. A normal direction of the display surface DP-IS, which is a thickness direction of the display panel DP, indicates a third direction DR3. A front surface (or upper surface) and a rear surface (or lower surface) of each layer or unit to be described below are distinguished from each other based on the third direction DR3.

[0051] The display panel DP may include a display area DA and a non-display area NDA arranged along an edge or periphery of the display area DA. Figure 2B ) is arranged in the display area DA, and the pixel PXnm (see Figure 2B ) is not arranged in the non-display area NDA. The non-display area NDA is defined along the edge of the display surface DP-IS. The non-display area NDA may be around the display area DA (e.g., may surround the display area DA). In one or more embodiments, the non-display area NDA may be omitted or arranged on only one side of the display area DA.

[0052] refer to Figure 1B According to one or more embodiments, the display panel DP-1 may be bent along the first direction DR1 relative to a virtual axis AX extending in the second direction DR2. However, the present disclosure is not limited thereto, and the axis may extend in the first direction DR1, or the display panel DP-1 may be bent relative to a plurality of axes extending in different directions.

[0053] The display panel DP or DP-1 according to one or more embodiments may be a rollable display panel, a foldable display panel and / or a slidable display panel. Here, the display panel DP or DP-1 may have flexible characteristics and may be foldable and / or rollable while being mounted on a display device. Therefore, the display panel DP or DP-1 may also include a curved display surface and / or a stereoscopic display surface DP-IS. The stereoscopic display surface DP-IS may also include a plurality of display areas indicating different directions.

[0054] Figure 1A and Figure 1B The pixel units PXU are illustrated to be arranged in the display area DA along the first direction DR1 and the second direction DR2. One pixel unit PXU may be a region in which pixels providing source light are arranged. The emission region, shape and / or arrangement of each of the pixels included in the pixel unit PXU is not limited to any one emission region, shape and / or arrangement. For example, the corresponding emission regions of the pixels included in the pixel unit PXU may be different from each other. In addition, the light-emitting regions (e.g., emission regions) may each have a circular or polygonal shape on a plane.

[0055] refer to Figure 2A and Figure 2B , the display panel DP according to one or more embodiments includes a base layer BS, a circuit element layer DP-CL arranged on the base layer BS, a display element layer DP-OLED, an encapsulation layer TFE, a light control layer OSL and a window panel WD. The display panel DP may further include a functional layer such as an anti-reflection layer and / or a refractive index adjustment layer. The circuit element layer DP-CL includes at least a plurality of insulating layers and circuit elements. The insulating layer to be described below may include an organic layer and / or an inorganic layer.

[0056] The base layer BS may include a synthetic resin film. The synthetic resin film may include a thermosetting resin. Specifically, the synthetic resin film may include at least one of an acrylate resin, a methacrylate resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, the base layer BS may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, and / or the like.

[0057] In the circuit element layer DP-CL, the insulating layer, the semiconductor layer and / or the conductive layer are formed by a process such as coating or deposition. Then, the insulating layer, the semiconductor layer and / or the conductive layer can be selectively patterned by a photolithography and / or etching process. Through such a process, a semiconductor pattern, a conductive pattern, a signal line, etc. are formed. The patterns arranged on the same layer can be formed by the same process.

[0058] The circuit element layer DP-CL includes signal lines or driving circuits constituting pixels. The display element layer DP-OLED may include a pixel definition layer PDL (see Figure 5B ) and a light emitting element OLED included in each of the pixels (see Figure 3 ).

[0059] The encapsulation layer TFE may be arranged on the display element layer DP-OLED to protect the light emitting element OLED. The encapsulation layer TFE may include an inorganic layer and an organic layer arranged between the inorganic layers. The inorganic layer may protect the light emitting element OLED from moisture and oxygen, and the organic layer may protect the light emitting element OLED from foreign matter such as dust particles.

[0060] The light control layer OSL may include a light control pattern capable of converting optical characteristics of source light generated from the light emitting element. The light control pattern may include quantum dots, and may include a color filter pattern to allow light transmitted through the light control pattern to be selectively transmitted.

[0061] The window panel WD may be disposed in an upper portion of the display panel DP, and may transmit an image provided from the display panel DP to the outside. Figure 1A As illustrated in FIG. 1 , in the window panel WD, a display area DA and a non-display area NDA of the display surface DP-IS may be distinguished from each other. A boundary between the display area DA and the non-display area NDA may be defined by a bezel pattern disposed under the window panel WD and absorbing light.

[0062] The window panel WD may include a base layer and a functional layer arranged on the base layer. The functional layer may include a protective layer, an anti-fingerprint layer, etc. The base layer of the window panel WD may include glass, sapphire, plastic, and / or the like. According to one or more embodiments, the components included in the light control layer OSL may be arranged on the rear surface of the window panel WD. The light control layer OSL arranged on the window panel WD may be coupled to the encapsulation layer TFE with a suitable space (e.g., a predetermined space) therebetween.

[0063] Figure 2B The diagram illustrates a planar arrangement relationship of signal lines SL1 to SLn and DL1 to DLm and pixels PX11 to PXnm included in the display panel DP. The signal lines SL1 to SLn and DL1 to DLm may include a plurality of scan lines SL1 to SLn and a plurality of data lines DL1 to DLm.

[0064] The pixels PX11 to PXnm may be arranged in the display area DA. Each of the pixels PX11 to PXnm is connected to a corresponding scan line among a plurality of scan lines SL1 to SLn and a corresponding data line among a plurality of data lines DL1 to DLm. Each of the pixels PX11 to PXnm may include a pixel driving circuit and a light emitting element. According to the configuration of the pixel driving circuit of the pixels PX11 to PXnm, various types of signal lines may be further included in the display panel DP.

[0065] The gate driving circuit GDC may be disposed in the non-display area NDA. The gate driving circuit GDC may be integrated into the display panel DP through an oxide silicon gate (OSG) driver circuit process or an amorphous silicon gate (ASG) driver circuit process.

[0066] As an example, Figure 3 A circuit diagram of one pixel PXij among the pixels PX11 to PXnm is shown.

[0067] The pixel PXij may include a pixel circuit PC and a light emitting element OLED. The pixel circuit PC may include a plurality of transistors T1 to T3 and a capacitor Cst.

[0068] The plurality of transistors T1 to T3 may be formed by a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process. Each of the first to third transistors T1 to T3 may include a silicon semiconductor or an oxide semiconductor. Here, the oxide semiconductor may include a crystalline or amorphous oxide semiconductor, and the silicon semiconductor may include amorphous silicon, polycrystalline silicon, or the like, but the present disclosure is not limited thereto.

[0069] Hereinafter, the first transistor T1 to the third transistor T3 are described as N-type transistors, but the present disclosure is not limited thereto. Therefore, each of the first transistor T1 to the third transistor T3 may be a P-type transistor or an N-type transistor according to a signal applied thereto. Here, the source and drain of the P-type transistor may correspond to the drain and source of the N-type transistor, respectively.

[0070] As an example, Figure 3 A pixel PXij connected to an i-th scan line SCLi, an i-th sensing line SSLi, a j-th data line DLj, and a j-th initial line ILj is illustrated.

[0071] The pixel circuit PC may include a first transistor T1 (eg, a driving transistor), a second transistor T2 (eg, a switching transistor), a third transistor T3 (eg, a sensing transistor), and a capacitor Cst. However, the pixel circuit PC may further include additional transistors and additional capacitors and is not limited to any one embodiment.

[0072] The light emitting element OLED may be an inorganic light emitting element or an organic light emitting element including an anode (e.g., a first electrode) and a cathode (e.g., a second electrode). The anode of the light emitting element OLED may receive a first voltage ELVDD through a first transistor T1, and the cathode of the light emitting element OLED may receive a second voltage ELVSS. Upon receiving the first voltage ELVDD and the second voltage ELVSS, the light emitting element OLED may emit light.

[0073] The first transistor T1 may include a drain D1 receiving the first voltage ELVDD, a source S1 connected to the anode of the light emitting element OLED, and a gate G1 connected to the capacitor Cst. The first transistor T1 may control a driving current flowing from the first voltage ELVDD through the light emitting element OLED in response to a value of a voltage stored in the capacitor Cst.

[0074] The second transistor T2 may include a drain D2 connected to the jth data line DLj, a source S2 connected to the capacitor Cst, and a gate G2 receiving the i-th first scan signal SCi. The second transistor T2 supplies the data voltage Vd to the first transistor T1 in response to the i-th first scan signal SCi.

[0075] The third transistor T3 may include a source S3 connected to the jth initial line ILj, a drain D3 connected to the anode of the light emitting element OLED, and a gate G3 receiving the i-th second scan signal SSi. The jth initial line ILj may receive the initial voltage Vintit.

[0076] The capacitor Cst may store a voltage difference of various values ​​according to an input signal. For example, the capacitor Cst may store a voltage equal to a difference between a voltage transmitted from the second transistor T2 and the first voltage ELVDD.

[0077] like Figure 4 As shown in FIG. 1 , light generated from the first pixel PX-G may be provided to the first pixel region PXA-G, light generated from the second pixel PX-R may be provided to the second pixel region PXA-R, and light generated from the third pixel PX-B may be provided to the third pixel region PXA-B. The first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B may be defined in the reference Figure 5B The described opening PDL-OP in the pixel defining film PDL corresponds.

[0078] The peripheral area NPXA is arranged between the first pixel area PXA-G, the second pixel area PXA-R, and the third pixel area PXA-B. The peripheral area NPXA sets the boundary of the first pixel area PXA-G, the second pixel area PXA-R, and the third pixel area PXA-B, and prevents color mixing between the first pixel area PXA-G, the second pixel area PXA-R, and the third pixel area PXA-B. According to one or more embodiments, the peripheral area NPXA may be included in the light control layer OSL (e.g., reference numeral 24). Figure 2A ) and includes overlapping dams of light-shielding material.

[0079] Each of the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B may include a light emitting element (eg, see Figure 5B The light emitting element OLED-G in the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B may generate source light of the same color. However, the present disclosure is not limited thereto, and the light generated from the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B may have different colors.

[0080] From the light emitting elements of the first pixel PX-G, the second pixel PX-R and the third pixel PX-B (for example, see Figure 5B The source light generated by the light emitting element OLED-G) in the reference Figure 2A The light may be converted into light of any one color among red light, green light and blue light by the color control pattern in the light control layer OSL described above. The converted light may be emitted through the first pixel area PXA-G, the second pixel area PXA-R and the third pixel area PXA-B.

[0081] refer to Figure 4 , the second pixel region PXA-R and the third pixel region PXA-B are arranged in the same row, and the first pixel region PXA-G is arranged in a row different from the row in which the second pixel region PXA-R and the third pixel region PXA-B are arranged. For example, the second pixel region PXA-R and the third pixel region PXA-B may be spaced apart from each other along the first direction DR1, and the first pixel region PXA-G may be spaced apart from the second pixel region PXA-R and the third pixel region PXA-B in respective oblique directions of the first direction DR1 and the second direction DR2.

[0082] According to one or more embodiments, the area of ​​the first pixel region PXA-G may be smaller than the area of ​​the second pixel region PXA-R and larger than the area of ​​the third pixel region PXA-B. However, in one or more other embodiments, the area of ​​the first pixel region PXA-G may be larger than the area of ​​the second pixel region PXA-R, and the area of ​​the second pixel region PXA-R may be larger than the area of ​​the third pixel region PXA-B.

[0083] In the present embodiment, the first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B having a square shape are illustrated as an example, but the arrangement and area of ​​the pixel regions are not limited thereto.

[0084] Figure 4 The arrangement structure of the first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B in the pixel unit PXU illustrated in the figure is only an example, and the present disclosure is not limited thereto. In one or more embodiments, the first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B may be arranged along the first direction DR1 and arranged in the same row. In addition, the arrangement of the first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B in the corresponding pixel unit PXU does not necessarily need to be the same.

[0085] Figure 5A 2 is a plan view illustrating that conductive patterns included in a pixel unit according to one or more embodiments of the present disclosure are stacked in a stacking order. Figure 5B is along Figure 5A A cross-sectional view taken along line II'.

[0086] refer to Figure 5A , a pixel unit PXU may include a first pixel PX-G, a second pixel PX-R, and a third pixel PX-B. Each of the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B may include a reference pixel. Figure 3 The pixel circuit PC and the light emitting element OLED are described.

[0087] Each of the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B is connected to the first power line ED, the second power line EL, the initial line IL, the scan line SCL, and the sense line SSL. In addition, the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B can be connected to the corresponding data lines DL-G, DL-R, and DL-B. The first power line ED can provide a first voltage ELVDD (see Figure 3 ), and the second power line EL can provide a second voltage ELVSS lower than the first voltage ELVDD (see Figure 3 ).

[0088] According to one or more embodiments, the data lines DL-G, DL-R, and DL-B, the initial line IL, and the second power line EL may be spaced apart from each other along the first direction DR1, and may each extend along the second direction DR2. The first power line ED, the scan line SCL, and the sensing line SSL may be spaced apart from each other along the second direction DR2, and may each extend along the first direction DR1. The first power line ED may be spaced apart from the sensing line SSL along the second direction DR2 with the scan line SCL therebetween. The pixel circuit PC (see FIG. 1 ) included in the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B Figure 3 ) can be arranged between the sensing line SSL and the scanning line SCL.

[0089] refer to Figure 5B , the display panel DP according to one or more embodiments includes a base layer BS, a circuit element layer DP-CL arranged on the base layer BS, a display element layer DP-OLED, an encapsulation layer TFE, a light control layer OSL, and a window panel WD.

[0090] The circuit element layer DP-CL is arranged on the base layer BS. The circuit element layer DP-CL may include insulating layers 10, 20, 30, 40 and 50 arranged on the base layer BS and conductive patterns EBR, BML-G, A2-G, B-P1, C-G2, SS-P and DL-B arranged between the insulating layers 10, 20, 30, 40 and 50. According to one or more embodiments, each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30 and the fourth insulating layer 40 may be provided as an inorganic layer. The first insulating layer 10, the second insulating layer 20, the third insulating layer 30 and the fourth insulating layer 40 may be provided as a single inorganic layer or a plurality of layers including inorganic layers different from each other, but are not limited to any one embodiment. The fifth insulating layer 50 may be provided as an organic layer.

[0091] For example, in the first insulating layer 10, inorganic layers including silicon nitride and silicon oxide may be stacked. The second insulating layer 20 may include a single inorganic layer of silicon oxide. The third insulating layer 30 may include a single inorganic layer containing silicon oxynitride. In the fourth insulating layer 40, inorganic layers including silicon nitride may be stacked. However, the present disclosure is not limited thereto, and the materials and layer structures of the inorganic layers included in the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may vary. The above-mentioned conductive patterns EBR, BML-G, A2-G, B-P1, C-G2, SS-P, and DL-B will be described later.

[0092] The first light shielding pattern BML-G may be disposed on the base layer BS and may be connected to the first transistor T1 (eg, reference 1 to FIG. 1 ) included in the first pixel PX-G. Figure 3) source, receiving a signal applied to the source, and forming a synchronization (sync) structure under the semiconductor pattern. The first light shielding pattern BML-G may overlap the first semiconductor pattern and receive a bias voltage. The first light shielding pattern BML-G may also receive a first voltage ELVDD (see Figure 3 ).

[0093] The first light shielding pattern BML-G may prevent the potential caused by polarization from affecting the first transistor T1. In addition, the first light shielding pattern BML-G may prevent external light from reaching the first transistor T1. In one or more embodiments, the first light shielding pattern BML-G may be a floating electrode isolated from another electrode or wiring. The description of the first light shielding pattern BML-G may also be applied to the reference Fig. 6A The second light-shielding pattern BML-R and the third light-shielding pattern BML-B are described. Other conductive patterns will be described in detail later.

[0094] The display element layer DP-OLED may include a pixel definition film PDL and a light emitting element OLED-G. The pixel definition film PDL may be disposed on the fifth insulating layer 50. The pixel definition film PDL may include a pixel definition film PDL and a light emitting element OLED-G. Figure 4 The pixel areas PXA-G, PXA-R, and PXA-B are described as corresponding to the openings PDL-OP. Figure 5B The light emitting element OLED-G illustrated in FIG. Figure 4 Described is the first pixel PX-G.

[0095] According to one or more embodiments, the pixel defining film PDL may have light absorption characteristics, and for example, the pixel defining film PDL may have a black color. The pixel defining film PDL may include a black colorant. The black colorant may include a black dye and / or a black pigment. The black colorant may include carbon black, a metal such as chromium, and / or an oxide thereof. The pixel defining film PDL may correspond to a shading pattern having a shading characteristic.

[0096] The first electrode AE-G of the first light emitting element OLED-G may be arranged on the fifth insulating layer 50. The second electrode CE-G may be arranged on the first electrode AE-G. The common layer CL-G may be arranged between the first electrode AE-G and the second electrode CE-G. The common layer CL-G may include a light emitting layer including an organic material, a hole control layer arranged between the first electrode AE-G and the light emitting layer, and an electron control layer arranged between the light emitting layer and the second electrode CE-G. The hole control layer may include a hole transport layer and a hole injection layer. The electron control layer may include an electron transport layer and an electron injection layer. According to one or more embodiments, the common layer CL-G and the second electrode CE-G may be a common layer formed together in the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B, and may overlap with the pixel defining film PDL. The pixel defining film PDL may partially overlap with the first electrode AE-G of the first light emitting element OLED-G.

[0097] The encapsulation layer TFE may cover the display element layer DP-OLED. The encapsulation layer TFE may include an organic material or an inorganic material. The encapsulation layer TFE may have a multilayer structure in which an inorganic layer / organic layer is repeatedly stacked. In the present embodiment, the encapsulation layer TFE may include a first inorganic layer, an organic layer, and a second inorganic layer stacked in sequence. The first inorganic layer and the second inorganic layer may protect the light-emitting element OLED (for example, referring to Figure 3 ) is protected from external moisture, and the organic layer can prevent dent defects of the light emitting element OLED that may be caused by foreign matter introduced during the manufacturing process.

[0098] The first inorganic layer and the second inorganic layer may each include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. Each of the first inorganic layer and the second inorganic layer may also have a multilayer structure. The organic layer may include an acrylate organic layer, but the present disclosure is not limited thereto. The inorganic layer may protect the first light-emitting element OLED-G from moisture and oxygen, and the organic layer may protect the first light-emitting element OLED-G from foreign matter such as dust particles.

[0099] The light control layer OSL may be arranged on the encapsulation layer TFE. The light control layer OSL may be arranged between the encapsulation layer TFE and the window panel WD. The rear surface of the window panel WD may provide a base surface on which components included in the light control layer OSL are formed. For ease of description, the components included in the light control layer OSL will be described in the order in which the components are formed on the rear surface of the window panel WD.

[0100] The color filter layer CFL may be arranged on the rear surface of the window panel WD. The color filter layer CFL may include a first color filter CF1 that transmits the first light, a second color filter CF2 that transmits the second light, and a third color filter CF3 that transmits the third light. In one or more embodiments, the first color filter CF1 may be a green filter, the second color filter CF2 may be a red filter, and the third color filter CF3 may be a blue filter.

[0101] Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 includes a polymer photosensitive resin and a colorant. The first color filter CF1 may include a green colorant, the second color filter CF2 may include a red colorant, and the third color filter CF3 may include a blue colorant. The first color filter CF1 may include a green pigment and / or a green dye, the second color filter CF2 may include a red pigment and / or a red dye, and the third color filter CF3 may include a blue pigment and / or a blue dye.

[0102] The first color filter CF1 may overlap with the opening PDL-OP corresponding to the first pixel area PXA-G, the second color filter CF2 may overlap with the opening PDL-OP corresponding to the second pixel area PXA-R, and the third color filter CF3 may overlap with the opening PDL-OP corresponding to the third pixel area PXA-B. In addition, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged to correspond to the first to third light-controlling patterns, respectively.

[0103] According to one or more embodiments, at least two color filters among the first color filter CF1, the second color filter CF2, and the third color filter CF3 may overlap with the pixel definition film PDL. A plurality of color filters CF1, CF2, and CF3 may be arranged to overlap each other in a third direction DR3, which is a thickness direction of the base layer BS, to define a boundary between adjacent light-emitting areas. Color filters overlapping each other along the third direction DR3 may be used to block light. Therefore, it is possible to prevent color mixing of light passing through the color control pattern.

[0104] In one or more embodiments, the color filter layer CFL may include a light shielding portion to define a boundary between adjacent first color filters CF1, second color filters CF2, and third color filters CF3. The light shielding portion may be formed of a blue filter, or may be formed with an inorganic or organic light shielding material including a black pigment and / or a black dye.

[0105] The low refractive layer LR may be disposed between the barrier layer CAP1 and the color filter layer CFL. In one or more embodiments, the low refractive layer LR may be disposed between the first color control pattern and the color filter layer CFL. The low refractive layer LR may cover the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0106] The low refractive layer LR may include at least one inorganic layer. For example, the low refractive layer LR may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide and / or silicon oxynitride, and / or a metal film with light transmittance, etc.

[0107] However, the present disclosure is not limited thereto, and the low refractive layer LR may include an organic film. For example, the low refractive layer LR may have a structure in which a plurality of hollow particles are dispersed in an organic polymer resin. The low refractive layer LR may be composed of a single layer or a plurality of layers.

[0108] The low refractive layer LR may be covered by the barrier layer CAP1. According to one or more embodiments, the barrier layer CAP1 may be provided as a multi-layer inorganic layer. The barrier layer CAP1 may prevent moisture / oxygen from penetrating into the color control layer CCL-G and improve film durability.

[0109] The embankment BMP may be arranged below the barrier layer CAP1. The embankment BMP may overlap with the pixel definition film PDL in the third direction DR3. The embankment BMP may include a base resin and / or an additive. The base resin may be composed of various resin compositions that may be generally referred to as adhesives. The additive may include a coupling agent and / or a photoinitiator. The additive may further include a dispersant. The embankment BMP may include a black colorant for shading. The embankment BMP may include a black pigment and / or a black dye mixed in the base resin. In one or more embodiments, the black colorant may include carbon black, a metal such as chromium, and / or an oxide thereof.

[0110] The levee BMP includes a levee opening corresponding to the opening PDL-OP. The color control layer CCL-G may be arranged in the levee opening. The color control layer CCL-G may include quantum dots for changing the optical properties of the source light (e.g., the source light generated from the light emitting element OLED-G). The color control layer CCL-G may include quantum dots for converting the source light into light with a different wavelength. In the color control layer CCL-G, the quantum dots may convert the blue light that is the source light into green light. According to one or more embodiments, the color control layer including quantum dots that convert the blue source light into green light may be arranged in the levee opening overlapping the first color filter CF1.

[0111] The additional barrier layer CAP2 may cover the bank BMP and the color control layer CCL-G. The additional barrier layer CAP2 may be provided as an inorganic layer. The additional barrier layer CAP2 may encapsulate the bank BMP and the color control layer together with the barrier layer CAP1. The additional barrier layer CAP2 and the barrier layer CAP1 may include the same material.

[0112] The filling layer FML may be arranged between the additional barrier layer CAP2 and the encapsulation layer TFE. The filling layer FML may be used as a buffer between the display element layer DP-OLED and the light control layer OSL. In one or more embodiments, the filling layer FML may be used to absorb impacts, etc., and may improve the strength of the display panel DP. The filling layer FML may be formed of a filling resin including a polymer resin. For example, the filling layer FML may be formed of a filling layer resin including an acrylate resin, an epoxy resin, and / or the like.

[0113] The filling layer FML can be a component separated from the encapsulation layer TFE arranged thereunder and the additional barrier layer CAP2 arranged thereon, and thus the filling layer FML, the encapsulation layer TFE and the additional barrier layer CAP2 can be formed by separate processing steps, respectively. The filling layer FML can be formed of a material different from that of the encapsulation layer TFE and the additional barrier layer CAP2.

[0114] FIG. 6A to FIG. 6I is a plan view illustrating, for each layer, a stacking order of conductive patterns included in a pixel unit according to one or more embodiments of the present disclosure.

[0115] refer to FIG. 5A to FIG. 6A , the first conductive layer MSL1 may be disposed on the base layer BS and covered by the first insulating layer 10. The first conductive layer MSL1 may include the second power line EL, the initial line IL, the power line EBR, the first light shielding pattern BML-G, the second light shielding pattern BML-R and the third light shielding pattern BML-B, and the first data line DL-G, the second data line DL-R and the third data line DL-B.

[0116] The second power line EL, the initial line IL, the power line EBR, and the first data line DL-G, the second data line DL-R, and the third data line DL-B may be spaced apart from each other along the first direction DR1, and may each extend along the second direction DR2. The initial line IL may be disposed between the second power line EL and the power line EBR. The second data line DL-R may be disposed between the first data line DL-G and the third data line DL-B.

[0117] The first light-shielding pattern BML-G, the second light-shielding pattern BML-R, and the third light-shielding pattern BML-B may be spaced apart from each other along the second direction DR2. The first light-shielding pattern BML-G, the second light-shielding pattern BML-R, and the third light-shielding pattern BML-B may be arranged between the power line EBR and the first data line DL-G, the second data line DL-R, and the third data line DL-B.

[0118] refer to FIG. 5A to FIG. 6B , the second conductive layer MSL2 may be disposed on the first insulating layer 10 and covered by the second insulating layer 20 .

[0119] The second conductive layer MSL2 may include a first semiconductor pattern A1-G, a second semiconductor pattern A2-G, and a third semiconductor pattern A3-G included in the first pixel PX-G, a first semiconductor pattern A1-R, a second semiconductor pattern A2-R, and a third semiconductor pattern A3-R included in the second pixel PX-R, and a first semiconductor pattern A1-B, a second semiconductor pattern A2-B, and a third semiconductor pattern A3-B included in the third pixel PX-B. The second semiconductor patterns A2-G, A2-R, and A2-B may not overlap with the first light-shielding pattern BML-G, the second light-shielding pattern BML-R, and the third light-shielding pattern BML-B.

[0120] refer to FIG. 5A to FIG. 6C , the third conductive layer MSL3 may be disposed on the second insulating layer 20 and covered by the third insulating layer 30 .

[0121] The third conductive layer MSL3 may include a sensing pattern SS-P, a scanning pattern SC-P, and first, second, and third lower capacitor patterns C-G1, C-R1, and C-B1. The sensing pattern SS-P may be connected to a sensing line SSL (see FIG. 1 ) to be described later. Fig. 6E ) and along the second direction DR2 from the sensing line SSL (see Fig. 6E ) protruding portion. The scanning pattern SC-P may be connected to a scanning line SCL (see Fig. 6E ) and along the second direction DR2 from the scan line SCL (see Fig. 6E ) protruding part.

[0122] A portion of the sensing pattern SS-P overlapping the third semiconductor patterns A3-G, A3-R, and A3-B may be defined as a third transistor T3 (see Figure 3 ) The portion of the scan pattern SC-P overlapping the second semiconductor patterns A2-G, A2-R, and A2-B may be defined as a second transistor T2 (see Figure 3 ) of the gate.

[0123] The first lower capacitor pattern C-G1, the second lower capacitor pattern C-R1, and the third lower capacitor pattern C-B1 may be spaced apart from each other along the second direction DR2. Each of the first lower capacitor pattern C-G1, the second lower capacitor pattern C-R1, and the third lower capacitor pattern C-B1 may include a first portion C1 and a second portion C2. The first portion C1 and the second portion C2 are substantially integrated with each other as a single pattern, but will be distinguished for ease of description.

[0124] The first portion C1 may overlap the corresponding first, second, and third light-shielding patterns BML-G, BML-R, and BML-B. The second portion C2 may protrude from the first portion C1 in the first direction DR1 and overlap the corresponding second semiconductor patterns A2-G, A2-R, and A2-B.

[0125] A portion of the first portion C1 that overlaps the corresponding first semiconductor patterns A1-G, A1-R, and A1-B may be defined as a first transistor T1 (see Figure 3 ) of the gate.

[0126] Fig.6D A contact hole defined by passing through at least one of the first insulating layer 10 , the second insulating layer 20 , and the third insulating layer 30 is illustrated.

[0127] The first contact hole CNT1 may be defined by passing through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The conductive pattern of the first conductive layer MSL1 overlapping the first contact hole CNT1 may be connected to the fourth conductive layer MSL4 (see Fig. 6E ) conductive pattern.

[0128] The second contact hole CNT2 may be defined by passing through the second insulating layer 20 and the third insulating layer 30. The conductive pattern of the second conductive layer MSL2 overlapping the second contact hole CNT2 may be connected to the fourth conductive layer MSL4 (see Fig. 6E ) conductive pattern.

[0129] The third contact hole CNT3 may be defined by penetrating the third insulating layer 30. The conductive pattern of the third conductive layer MSL3 overlapping the third contact hole CNT3 may be connected to the fourth conductive layer MSL4 (see Fig. 6E ) conductive pattern.

[0130] refer to FIG. 5A to FIG. 6E , the fourth conductive layer MSL4 may be disposed on the third insulating layer 30 and covered by the fourth insulating layer 40 .

[0131] The fourth conductive layer MSL4 may include a first power line ED, a scan line SCL, a sensing line SSL, a power pattern EL-P, an initial pattern IL-P, a first power line pattern E-P1, a second power line pattern E-P2, and a third power line pattern E-P3, a first upper capacitor pattern C-G2, a second upper capacitor pattern C-R2, and a third upper capacitor pattern C-B2, a first bridge pattern B-P1, a second bridge pattern B-P2, and a third bridge pattern B-P3, and a first data pattern D-P1, a second data pattern D-P2, and a third data pattern D-P3.

[0132] The first power line ED, the scan line SCL, and the sensing line SSL may be spaced apart from each other in the second direction DR2, and may each extend in the first direction DR1. According to the present embodiment, the first power line ED may be disposed between the scan line SCL and the sensing line SSL. Figure 3 The described pixel circuit PC may be disposed between the sensing line SSL and the scanning line SCL. The scanning line SCL may be connected to the scanning pattern SC-P through the third contact hole CNT3, and the sensing line SSL may be connected to the sensing pattern SS-P through the third contact hole CNT3.

[0133] The power pattern EL-P may overlap the second power line EL and may be connected to the second power line EL through the first contact hole CNT1.

[0134] The preliminary pattern IL-P may overlap the preliminary line IL and may be connected to the preliminary line IL through the first contact hole CNT1.

[0135] The first power line pattern E-P1, the second power line pattern E-P2, and the third power line pattern E-P3 may overlap the power line EBR. The first power line pattern E-P1, the second power line pattern E-P2, and the third power line pattern E-P3 may be spaced apart from each other along the second direction DR2. The first power line pattern E-P1, the second power line pattern E-P2, and the third power line pattern E-P3 may be connected to the power line EBR through the first contact hole CNT1.

[0136] One end of the first power line pattern E-P1 may be connected to the power line EBR through a first contact hole CNT1, and the other end of the first power line pattern E-P1 may be connected to the first semiconductor pattern A1-G through a second contact hole CNT2.

[0137] One end of the second power line pattern E-P2 may be connected to the power line EBR through the first contact hole CNT1, and the other end of the second power line pattern E-P2 may be connected to the first semiconductor pattern A1-R through the second contact hole CNT2.

[0138] One end of the third power line pattern E-P3 may be connected to the power line EBR through the first contact hole CNT1, and the other end of the third power line pattern E-P3 may be connected to the first semiconductor pattern A1-B through the second contact hole CNT2.

[0139] The first upper capacitor pattern C-G2, the second upper capacitor pattern C-R2, and the third upper capacitor pattern C-B2 may overlap with the corresponding first lower capacitor pattern C-G1, the second lower capacitor pattern C-R1, and the third lower capacitor pattern C-B1. The first lower capacitor pattern C-G1, the second lower capacitor pattern C-R1, and the third lower capacitor pattern C-B1 and the first upper capacitor pattern C-G2, the second upper capacitor pattern C-R2, and the third upper capacitor pattern C-B2 may be connected to each other through the first contact hole CNT1. The lower capacitor pattern and the upper capacitor pattern overlapping each other may define a reference Figure 3 Capacitor Cst is described.

[0140] The first, second, and third bridge patterns B-P1, B-P2, and B-P3 may connect the second semiconductor patterns A2-G, A2-R, and A2-B with the first, second, and third lower capacitor patterns C-G1, C-R1, and C-B1.

[0141] One end of the first bridge pattern B-P1 may be connected to the second semiconductor pattern A2-G through a second contact hole CNT2, and the other end of the first bridge pattern B-P1 may be connected to the second portion C2 of the first lower capacitor pattern C-G1 through a third contact hole CNT3.

[0142] One end of the second bridge pattern B-P2 may be connected to the second semiconductor pattern A2-R through a second contact hole CNT2, and the other end of the second bridge pattern B-P2 may be connected to the second portion C2 of the second lower capacitor pattern C-R1 through a third contact hole CNT3.

[0143] One end of the third bridge pattern B-P3 may be connected to the second semiconductor pattern A2-B through the second contact hole CNT2, and the other end of the third bridge pattern B-P3 may be connected to the second portion C2 of the third lower capacitor pattern C-B1 through the third contact hole CNT3.

[0144] The first, second, and third data patterns D-P1, D-P2, and D-P3 may connect the second semiconductor patterns A2-G, A2-R, and A2-B with the first, second, and third data lines DL-G, DL-R, and DL-B.

[0145] One end of the first data pattern D-P1 may be connected to the first data line DL-G through a first contact hole CNT1, and the other end of the first data pattern D-P1 may be connected to the second semiconductor pattern A2-G through a second contact hole CNT2.

[0146] One end of the second data pattern D-P2 may be connected to the second data line DL-R through the first contact hole CNT1, and the other end of the second data pattern D-P2 may be connected to the second semiconductor pattern A2-R through the second contact hole CNT2.

[0147] One end of the third data pattern DP3 may be connected to the third data line DL-B through the first contact hole CNT1, and the other end of the third data pattern DP3 may be connected to the second semiconductor pattern A2-B through the second contact hole CNT2.

[0148] Fig. 6F A fourth contact hole CNT4 defined by passing through the fourth insulating layer 40 is illustrated.

[0149] The fourth contact hole CNT4 may overlap the power pattern EL-P and the first, second, and third upper capacitor patterns C-G2, C-R2, and C-B2.

[0150] Figure 6G A fifth contact hole CNT5 defined by passing through the fifth insulating layer 50 is illustrated.

[0151] The fifth contact hole CNT5 may overlap the power pattern EL-P and the first upper capacitor pattern C-G2, the second upper capacitor pattern C-R2, and the third upper capacitor pattern C-B2. The fifth contact hole CNT5 may overlap the fourth contact hole CNT4. The fifth insulating layer 50 may be provided as an organic layer.

[0152] refer to FIG. 5A to FIG. 6H , the fifth conductive layer MSL5 may be disposed on the fifth insulating layer 50 and covered by the pixel defining layer PDL.

[0153] The fifth conductive layer MSL5 may include first electrodes AE-G, AE-R, and AE-B respectively included in the pixels. The first electrodes AE-G, AE-R, and AE-B may be connected to the first upper capacitor electrode C-G2, the second upper capacitor electrode C-R2, and the third upper capacitor electrode C-B2 through corresponding fourth contact holes CNT4 and fifth contact holes CNT5.

[0154] The fifth conductive layer MSL5 may further include an additional power pattern EL-S. The additional power pattern EL-S may be connected to the power pattern EL-P through corresponding fourth and fifth contact holes CNT4 and CNT5.

[0155] Fig.6I Reference Figure 5B For ease of description, the reference pixel definition film PDL is illustrated with dark hatching. Figure 5B The opening PDL-OP described above. The opening PDL-OP (see Figure 5B ) may be defined in the pixel definition layer PDL. The opening PDL-OP (see Figure 5B ) may correspond to the first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B. The first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B may be a region from the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B (see Figure 5A ) is provided to the area to which the source light generated is provided.

[0156] An additional opening EL-OP exposing at least a portion of the additional power pattern EL-S may be defined in the pixel defining film PDL. The second electrode CE-G (see Figure 5B ) may be arranged in the additional opening EL-OP and connected to the second power line EL.

[0157] Fig. 7A is an enlarged plan view of one region of a pixel unit according to an embodiment of the inventive concept.

[0158] Figure 7B is along Fig. 7A A cross-sectional view taken along line III-III'. Fig. 8A It is a plan view of a comparative example.

[0159] Figure 8B is along Fig. 8A A cross-sectional view taken along line IV-IV'.

[0160] Fig. 7A It is a reference Figure 5A An enlarged portion of the pixel unit PXU is depicted, and Fig. 8A FIG. 1 illustrates a pixel unit PXU-S according to a comparative example different from the embodiment of the present disclosure, and ... Fig. 7A The same district in the district.

[0161] refer to Fig. 7A and Figure 7B , the first light-shielding pattern BML-G according to one or more embodiments may include a lower surface BB contacting the base layer BS, an upper surface BU opposite to the lower surface BB, and a side surface BS connecting the lower surface BB and the upper surface BU.

[0162] According to one or more embodiments, an angle θ between the lower surface BB and the side surface BS may be about 60 degrees to about 80 degrees. The side surface BS of the first light-shielding pattern BML-G may have a predetermined angle θ, and cracks may thus occur in some of the insulating layers formed on the side surface BS to overlap the side surface BS.

[0163] The lower capacitor pattern C-G1 may include a first portion C1 overlapping the first light-shielding pattern BML-G and a second portion C2 protruding from the first portion C1 and overlapping the second semiconductor pattern A2-G in the third direction DR3.

[0164] The upper capacitor pattern C-G2 may be disposed on at least a portion of the first portion C1 and the second portion C2. The first bridge pattern B-P1 may overlap the second semiconductor pattern A2-G in the third direction DR3.

[0165] According to one or more embodiments, the upper capacitor pattern C-G2 may overlap with a side surface BS of the first light-shielding pattern BML-G facing the second semiconductor pattern A2-G in the first direction DR1. That is, on a plane, the upper capacitor pattern C-G2 may protrude farther than an outer side of the first light-shielding pattern BML-G and cover a side surface BS of the first light-shielding pattern BML-G facing the second semiconductor pattern A2-G in the first direction DR1.

[0166] According to one or more embodiments, the first insulating layer 10, the second insulating layer 20, the lower capacitor pattern C-G1, the third insulating layer 30, the upper capacitor pattern C-G2, and the fourth insulating layer 40 may be arranged on the side surface BS. However, the present disclosure is not limited thereto, and at least one of the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 may be omitted.

[0167] The fourth insulating layer 40 disposed on the upper capacitor pattern C-G2 may be formed on the side surface BS while having a relatively gentle slope in a region overlapping the side surface BS due to the upper capacitor pattern C-G2.

[0168] Reference Comparative Example Fig. 8A and Figure 8B , the upper capacitor pattern C-G2' in the comparative example may not overlap with the side surface BS of the first light shielding pattern BML-G'. That is, on a plane, the upper capacitor pattern C-G2' may be arranged on the inner side of the first light shielding pattern BML-G'. Here, the first insulating layer 10, the second insulating layer 20, the lower capacitor pattern C-G1', the third insulating layer 30 and the fourth insulating layer 40 may be arranged on the side surface BS of the first light shielding pattern BML-G'.

[0169] The side surface BS of the first light-shielding pattern BML-G' may have a slope, and a crack CR may thus occur in a region overlapping the side surface BS of the fourth insulating layer 40. When the crack CR occurs in the fourth insulating layer 40, hydrogen included in the etchant may penetrate into the second semiconductor pattern A-G2' and cause corrosion and a negative shift of the Vth of the transistor (e.g., a negative shift of the threshold voltage of the transistor), and a bright spot may thus occur in an off state of the display panel.

[0170] Return to reference Fig. 7A and Figure 7B , the upper capacitor pattern C-G2 according to one or more embodiments may cover the side surface BS of the first light shielding pattern BML-G facing the second semiconductor pattern A2-G in the first direction DR1. That is, since the fourth insulating layer 40 overlapping the side surface BS may be disposed on the upper capacitor pattern C-G2 instead of on the third insulating layer 30, even if cracks occur in the fourth insulating layer 40, the upper capacitor pattern C-G2 may block a path for the etchant to penetrate into the second semiconductor pattern A2-G. In addition, since the fourth insulating layer 40 overlapping the side surface BS may be disposed on the upper capacitor pattern C-G2 and may thus be formed on the upper capacitor pattern C-G2 while having a relatively gentle slope, cracks may be prevented from occurring in the fourth insulating layer 40, compared to a case in which the fourth insulating layer 40 is directly formed on the third insulating layer 30.

[0171] Therefore, the display panel DP according to one or more embodiments of the present disclosure can prevent and / or reduce bright spot defects that may otherwise occur in the off state of the display panel (such as the display panel of the comparative example). Therefore, a display panel DP with improved display quality can be provided.

[0172] The description of the upper capacitor pattern C-G2 made above is made as an example and can be commonly applied to the reference Figure 5A The first pixel PX-G, the second pixel PX-R and the third pixel PX-B described above. In addition, the fourth conductive layer MSL4 (see Fig. 6E ) may cover the side surface of the light shielding pattern in a region as long as the fourth insulating layer 40 is formed in the region and the light shielding pattern faces the semiconductor pattern.

[0173] According to one or more embodiments of the present disclosure, the upper capacitor pattern can cover the side surface of the light shielding pattern, thereby preventing corrosion of the semiconductor pattern and reducing the occurrence of bright spots in the off state of the display panel. Therefore, a display panel with improved display quality can be provided.

[0174] Although the embodiments of the present disclosure have been described, it is to be understood that the present disclosure is not limited to these embodiments and that one of ordinary skill in the art can make various changes and modifications within the spirit and scope of the present disclosure as claimed hereto.

[0175] Therefore, the technical scope of the present disclosure is not limited to the embodiments described herein, but may be defined by the appended claims and their equivalents.

Claims

1. A display panel, comprising: Basal layer; a light-shielding pattern on the base layer; a semiconductor pattern that does not overlap with the light shielding pattern; a lower capacitor pattern including a first portion overlapping the light shielding pattern and a second portion protruding from the first portion in a first direction and overlapping the semiconductor pattern; an upper capacitor pattern overlapping the lower capacitor pattern; as well as a light emitting element connected to the semiconductor pattern, The light shielding pattern includes a lower surface facing the base layer, an upper surface opposite to the lower surface, and a side surface connecting the lower surface and the upper surface, and wherein the upper capacitor pattern overlaps the side surface facing the semiconductor pattern in the first direction.

2. The display panel according to claim 1, wherein: An angle between the lower surface and the side surface of the light shielding pattern is 60 degrees to 80 degrees.

3. The display panel according to claim 1, further comprising: a first insulating layer on the base layer and covering the light shielding pattern; a second insulating layer on the first insulating layer and covering the semiconductor pattern; a third insulating layer on the second insulating layer and covering the lower capacitor pattern; a fourth insulating layer on the third insulating layer and covering the upper capacitor pattern; as well as A fifth insulating layer is on the fourth insulating layer and includes an organic material.

4. The display panel according to claim 3, further comprising: a bridge pattern overlapping the semiconductor pattern and the second portion of the lower capacitor pattern, One end of the bridge pattern is connected to the semiconductor pattern through a first contact hole passing through the second insulating layer and the third insulating layer, and the other end of the bridge pattern is connected to the second portion of the lower capacitor pattern through a second contact hole passing through the third insulating layer.

5. The display panel according to claim 3, wherein: The first insulating layer, the second insulating layer, the lower capacitor pattern, the third insulating layer, the upper capacitor pattern, and the fourth insulating layer are on the side surface of the light shielding pattern facing the semiconductor pattern in the first direction.

6. The display panel according to claim 5, wherein: A portion of the upper capacitor pattern overlapping the side surface of the light shielding pattern facing the semiconductor pattern in the first direction is inclined at an angle corresponding to an inclination angle of the side surface.

7. The display panel according to claim 3, further comprising: first power lines, scan lines, and sensing lines extending in the first direction and spaced apart from each other in a second direction crossing the first direction, and data lines extending in the second direction, Wherein, the light shielding pattern is located between the scanning line and the sensing line.

8. The display panel according to claim 7, wherein: The scanning line further includes a scanning pattern protruding in the second direction, and Wherein, the scanning pattern overlaps with the semiconductor pattern.

9. The display panel according to claim 8, wherein: A portion of the scan pattern overlapping the semiconductor pattern includes a gate of a transistor including the semiconductor pattern.

10. The display panel according to claim 9, wherein: The scanning pattern is on the second insulating layer and covered by the third insulating layer, and Portions of the scan pattern are connected to the scan line through contact holes in the third insulating layer.

11. The display panel according to claim 7, further comprising: a data pattern having one end overlapping the semiconductor pattern and another end overlapping the data line, One end of the data pattern is connected to the semiconductor pattern through a third contact hole passing through the second insulating layer and the third insulating layer, and the other end of the data pattern is connected to the data line through a fourth contact hole passing through the first insulating layer to the third insulating layer.

12. The display panel according to claim 3, wherein: The light emitting element includes a first electrode, a second electrode, and a common layer located between the first electrode and the second electrode on the fifth insulating layer, and The first electrode is connected to the upper capacitor pattern through a fifth contact hole passing through the fourth insulating layer and a sixth contact hole passing through the fifth insulating layer and overlapping the fifth contact hole.

13. The display panel according to claim 1, further comprising: An encapsulation layer is on the light emitting element and includes a plurality of inorganic layers and an organic layer between the plurality of inorganic layers.

14. The display panel according to claim 13, further comprising: A light control layer is on the encapsulation layer and includes a color control pattern including quantum dots and a color filter pattern on the color control pattern.

15. A display panel, comprising: Basal layer; a light-shielding pattern on the base layer; a data line spaced apart from the light shielding pattern along a first direction and extending along a second direction crossing the first direction; a capacitor including a lower capacitor pattern overlapping the light shielding pattern and an upper capacitor pattern overlapping the lower capacitor pattern; as well as A pixel including a light emitting element, a first transistor, a second transistor, and a third transistor, each of the first to third transistors including a semiconductor pattern, wherein the semiconductor pattern in the second transistor is connected to the data line, and Wherein, a side surface of the light shielding pattern facing the semiconductor pattern in the second transistor in the first direction is covered by the upper capacitor pattern.

16. The display panel according to claim 15, wherein: An angle between the base layer and the side surface of the light shielding pattern is 60 degrees to 80 degrees.

17. The display panel according to claim 15, further comprising: first power lines, scan lines, and sensing lines extending in the first direction and spaced apart from each other in a second direction crossing the first direction, and an initial line extending in the second direction, Wherein, the light shielding pattern is located between the scanning line and the sensing line.

18. The display panel according to claim 17, wherein: The semiconductor pattern in the first transistor is connected to the first power line.

19. The display panel according to claim 18, wherein: The semiconductor pattern in the third transistor is connected to the initial line.

20. The display panel according to claim 18, wherein: A portion of the upper capacitor pattern overlapping the side surface of the light shielding pattern is inclined at a predetermined angle.

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