Light detection device, distance measurement device, and control method for light detection device

Abstract

The present invention reduces the circuit area of a light detection device in which a plurality of pixels are arranged. The first detection circuit detects incidence of photons based on a voltage of one of an anode and a cathode of the first photoelectric conversion element during a period that is not a predetermined detection stop period. The second detection circuit detects incidence of photons based on a voltage of one of an anode and a cathode of the second photoelectric conversion element during a period that is not the detection stop period. The common circuit controls the voltage of the gating pulse indicating the detection stop period.

Description

Technical Field

[0001] The present technology relates to a light detection device, and more particularly to a light detection device for measuring a distance to an object, a distance measuring device, and a control method of the light detection device. Background Art

[0002] Generally, in an electronic device having a distance measurement function, a distance measurement method called a time-of-flight (ToF) method is known. The ToF method is a method of measuring distance by irradiating an object with irradiation light from an electronic device and obtaining a round-trip time until the irradiation light is reflected and returns to the electronic device. In order to detect reflected light relative to the irradiation light, a single-photon avalanche diode (SPAD) is generally used as a photoelectric conversion element. For example, a light detection device is proposed in which a pixel having a SPAD with a wide light receiving area and a pixel having a SPAD with a narrow light receiving area are provided (for example, see patent document 1).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2022-092345 Summary of the invention

[0006] Problems to be solved by the present invention

[0007] In the above conventional technology, the dynamic range is extended by processing signals from two types of SPADs with different light receiving areas. However, in the above device, in addition to the SPAD for each pixel, a large number of elements such as current sources and switches must be arranged, and it is difficult to reduce the circuit area of ​​each pixel.

[0008] The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the circuit area in a photodetection device in which a plurality of pixels are arranged.

[0009] Solution to the problem

[0010] The present technology has been made to solve the above-mentioned problems, and its first aspect is a light detection device including: a first detection circuit that detects the incidence of photons based on the voltage of one of the anode and cathode of a first photoelectric conversion element in a period not corresponding to a predetermined detection stop period; a second detection circuit that detects the incidence of photons based on the voltage of one of the anode and cathode of a second photoelectric conversion element in a period not corresponding to the detection stop period; and a common circuit that controls the voltage of a gate pulse indicating the detection stop period and a control method of the light detection device. This brings about an effect of reducing the circuit area of ​​each pixel.

[0011] In addition, in the first aspect, the first detection circuit and the second detection circuit can output at least one of the first pulse signal and the second pulse signal according to the selection signal when the incidence of the photon is detected, and the common circuit can include a gate control circuit that controls the voltage of the gate pulse, and a selection circuit that generates the selection signal and supplies the selection signal to the first detection circuit and the second detection circuit. This brings about the effect of further reducing the circuit area.

[0012] In addition, in the first aspect, the gate control circuit may include: a front-stage inverter that inverts the gate pulse and outputs an inverted signal; and a rear-stage inverter that inverts the inverted signal and supplies the result to the first detection circuit and the second detection circuit, and the power supply voltages of the front-stage inverter and the rear-stage inverter may be different from each other. This brings about the effect of controlling the power supply voltage of the gate pulse.

[0013] Furthermore, in the first aspect, the gate control circuit may include: an inverter that inverts a gate pulse and outputs the inverted gate pulse as an enable signal; a logic gate that performs a logic operation on a pulse signal from each of the first detection circuit and the second detection circuit and outputs an operation result; and a trigger that supplies a signal of a predetermined level to the first detection circuit and the second detection circuit in synchronization with the operation result when the enable signal has a predetermined value. This brings about an effect of reducing the circuit scale of the detection path.

[0014] In addition, in the first aspect, the common circuit may further include: a recharging circuit that performs recharging of one of the first photoelectric conversion element and the second photoelectric conversion element; an active quenching switch that connects the recharging circuit and the reference voltage during the active quenching period according to an active quenching enable signal indicating a predetermined active quenching period; and an active quenching pulse generating circuit that generates the active quenching enable signal. This brings about the effect of further reducing the circuit area.

[0015] In addition, in the first viewpoint, the light detection device may also have: a recharge switching switch, which selects one of the first photoelectric conversion element and the second photoelectric conversion element, and connects the selected one light spot conversion element to the recharging circuit. The recharging circuit may include an active recharging current source, a passive recharging current source, an active recharging switch that opens and closes the path between the active recharging current source and the recharging switching switch according to an active recharging enable signal, and a passive recharging switch that opens and closes the path between the passive recharging current source and the recharging switching switch, and the common circuit may further include an active recharging pulse generating circuit that generates an active recharging enable signal. This brings about the effect of reducing instantaneous power consumption.

[0016] In addition, in the first aspect, the common circuit may further include an active recharge start signal generating circuit, which generates an active recharge start signal when the active quenching period has passed or when the recharge switching switch is switched, and the active recharge pulse generating circuit may generate an active recharge enable signal based on the active recharge start signal. This brings about the effect of reducing the active quenching period.

[0017] Furthermore, in the first aspect, the detection circuit may include: an active recharge current source; an active recharge switch that opens and closes a path between the active recharge current source and a predetermined node according to an active recharge enable signal; an active quench switch that connects a predetermined node and a reference voltage within a predetermined active quench period; and an active recharge pulse generating circuit that generates an active recharge enable signal when the detection stop period has passed or when the active quench period has passed. This brings about an effect of shortening the dead time.

[0018] Furthermore, in the first aspect, the photoelectric conversion element may be a single photon avalanche diode (SPAD). This brings about an effect of detecting the incidence of photons.

[0019] In addition, a second aspect of the present technology is a distance measuring device including a light emitting unit and a light detecting element, the light detecting element including: a first detection circuit that detects the incidence of photons based on a voltage of one of an anode and a cathode of a first photoelectric conversion element during a period that does not correspond to a predetermined detection stop period; a second detection circuit that detects the incidence of photons based on a voltage of one of an anode and a cathode of a second photoelectric conversion element during a period that does not correspond to a detection stop period; a common circuit that controls a voltage of a gate pulse that indicates a detection stop period; and a distance measuring unit that performs distance measurement based on a light emission timing of the light emitting unit and an incidence timing of photons detected by each of the first detection circuit and the second detection circuit. This brings about an effect of reducing the circuit area of ​​each pixel in the distance measuring device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 : is a block diagram showing a configuration example of a distance measurement module in the first embodiment of the present technology.

[0021] Figure 2 It is a diagram showing an example of a stacked structure of a light detecting element in the first embodiment of the present technology.

[0022] Figure 3 : is a plan view showing a configuration example of a pixel chip in the first embodiment of the present technology.

[0023] Figure 4 : is a block diagram showing a configuration example of a circuit chip in the first embodiment of the present technology.

[0024] Figure 5 It is a plan view showing an example of a circuit layout in a circuit block in the first embodiment of the present technology.

[0025] Figure 6 : is a diagram showing a configuration example of a pixel in the first embodiment of the present technology.

[0026] Figure 7 : is a block diagram showing a configuration example of a detection circuit in the first embodiment of the present technology.

[0027] Figure 8 : is a circuit diagram showing a configuration example of a gate control circuit and a latch signal generating circuit in the first embodiment of the present technology.

[0028] Fig. 9 : is a circuit diagram showing a configuration example of an AR pulse generating circuit, an AQ pulse generating circuit, and an output control circuit in the first embodiment of the present technology.

[0029] Fig.10 is a circuit diagram showing a configuration example of a common circuit in the first embodiment of the present technology.

[0030] Fig.11 This is a timing chart showing an example of pixel operation in the first embodiment of the present technology.

[0031] Fig.12 It is a diagram for describing an example of control of the decoder in the first embodiment of the present technology.

[0032] Fig.13 is a diagram showing an example of wiring of a signal line for transmitting a gate pulse in the first comparative example.

[0033] Fig.14 : is a diagram showing a wiring example of a signal line for transmitting a gate pulse in the first embodiment of the present technology.

[0034] Fig.15 : is a diagram showing a wiring example of a signal line for transmitting a gate pulse in a common block in the first embodiment of the present technology.

[0035] Fig.16 is a diagram showing an example of wiring of a signal line for transmitting a decoded signal in the first comparative example.

[0036] Fig.17 : is a diagram showing a wiring example of a signal line for transmitting a decoded signal in the first embodiment of the present technology.

[0037] Fig.18: is a diagram showing a wiring example of a signal line for transmitting a decoded signal in a common block in the first embodiment of the present technology.

[0038] Fig.19 : is a diagram showing a wiring example of a signal line for transmitting a gate pulse when a common circuit is shared by 16 pixels in the first embodiment of the present technology.

[0039] Fig. 20 : is a diagram showing a wiring example of a signal line for transmitting a decoded signal when a common circuit is shared by 16 pixels in the first embodiment of the present technology.

[0040] Fig.21 : is a circuit diagram showing a configuration example of a detection circuit and a common circuit in a first modification example of the first embodiment of the present technology.

[0041] Fig. 22 : is a circuit diagram showing a configuration example of a detection circuit and a common circuit in a second modification example of the first embodiment of the present technology.

[0042] Fig.23 : is a block diagram showing a configuration example of a detection circuit in a second embodiment of the present technology.

[0043] Fig.24 : is a circuit diagram showing a configuration example of an AR pulse generating circuit and an AQ pulse generating circuit in a second embodiment of the present technology.

[0044] Fig.25 is an example of a timing chart showing each of the active recharging control in the second embodiment of the present technology and the active recharging control in the first embodiment.

[0045] Fig.26 : is a circuit diagram showing a configuration example of a detection circuit in a third embodiment of the present technology.

[0046] Fig. 27 : is a block diagram showing a configuration example of a common circuit in a third embodiment of the present technology.

[0047] Fig.28 It is a diagram showing an example of the operation of the recharge switching control unit in the third embodiment of the present technology.

[0048] Fig.29 1 is a timing chart showing an example of operation of the detection circuit in the second comparative example.

[0049] Fig.30 This is a timing chart showing an example of the operation of the common circuit when photons are sequentially incident on each pixel in the third embodiment of the present technology.

[0050] Fig.31 This is a timing chart showing an example of the operation of the common circuit when photons are incident on two pixels almost simultaneously in the third embodiment of the present technology.

[0051] Fig.32 : is a timing chart showing an example of the operation of the common circuit in the case where photons are incident on two pixels almost simultaneously and then the photons are incident on one pixel in the third embodiment of the present technology.

[0052] Fig.33 2 is a diagram showing an example of a circuit layout in a detection circuit of a second comparative example.

[0053] Fig.34 It is a diagram showing an example of a circuit layout in a common circuit in the third embodiment of the present technology.

[0054] Fig.35 : is a circuit diagram showing a configuration example of a common circuit in a modification example of the third embodiment of the present technology.

[0055] Fig.36 : is a circuit diagram showing a configuration example of an AR start signal generation circuit in a modification example of the third embodiment of the present technology.

[0056] Fig.37 1 is a timing chart showing an example of the operation of the common circuit when one of two pixels detects a photon in the modification of the third embodiment of the present technology.

[0057] Fig.38 : is a timing chart showing an example of the operation of the common circuit when the other of the two pixels detects a photon in the modification of the third embodiment of the present technology.

[0058] Fig.39 1 is a timing chart showing an example of the operation of the common circuit when one of two pixels reacts during the active quenching period of the other pixel in the modification of the third embodiment of the present technology.

[0059] Fig.40 : is a timing chart showing an example of the operation of the common circuit in the case where photons are incident on two pixels almost simultaneously and then the photons are incident on one pixel in the modification of the third embodiment of the present technology.

[0060] Fig.41 This is a timing chart showing an example of the operation of the common circuit when one of two pixels reacts during the recharging period of the other pixel in the modification of the third embodiment of the present technology.

[0061] Fig.42This is a block diagram showing a schematic configuration example of a vehicle control system.

[0062] Fig.43 It is an explanatory diagram showing an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0063] Modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described below. The description will be given in the following order.

[0064] 1. First Embodiment (Example of Sharing Gate Control Circuit)

[0065] 2. Second Embodiment (Example of Sharing a Gate Control Circuit and Performing Active Recharging When a Stop Period Has Elapsed)

[0066] 3. Third Embodiment (Example of Sharing Gate Control Circuit, Recharging Circuit, etc.)

[0067] 4. Application examples for mobile objects

[0068] <1. First Embodiment>

[0069] [Configuration Example of Distance Measurement Module]

[0070] Figure 1 1 is a block diagram showing a configuration example of the distance measurement module 100 in the first embodiment of the present technology. The distance measurement module 100 measures the distance to an object, and includes a light emitting unit 110, a synchronization control unit 120, and a light detection element 200. The distance measurement module 100 is mounted on a smartphone, a personal computer, a vehicle-mounted device, etc., and is used to measure the distance.

[0071] The synchronization control unit 120 synchronizes the operation of the light emitting unit 110 and the light detecting element 200. The synchronization control unit 120 supplies a clock signal of a predetermined frequency (eg, 10 to 20 MHz) as a synchronization signal CLKp to the light emitting unit 110 and the light detecting element 200 via signal lines 128 and 129.

[0072] The light emitting unit 110 provides intermittent light as irradiation light in synchronization with the synchronization signal CLKp from the synchronization control unit 120. For example, near infrared light or the like is used as the irradiation light. When the irradiation light is reflected by the measurement target, the reflected light is hereinafter referred to as "ToF light".

[0073] The light detection element 200 receives ToF light through a photoelectric conversion element (SPAD, etc.) and measures the round-trip time from the light emission timing indicated by the synchronization signal CLKp to the light reception timing of the ToF light. The light detection element 200 calculates the distance to the target based on the round-trip time, generates and outputs distance data indicating the distance.

[0074] In addition, when the irradiated light is reflected inside the housing of the distance measurement module 100 without hitting the target, the reflected light is hereinafter referred to as "stray light". By obtaining the light detection element 200 of the difference between the light reception timing of the stray light and the light reception timing of the ToF light, signal delay in the distance measurement module 100 can be eliminated, and the distance measurement accuracy can be improved.

[0075] However, due to the characteristics of SPAD, when a photon incident is detected, it is impossible to detect the incidence of a new photon within a certain dead time from the timing of detection. For this reason, if the SPAD detects stray light, the ToF light reflected at a short distance cannot be detected due to the occurrence of dead time, and it becomes difficult to measure short distances. For this reason, it is necessary to perform control to forcibly stop the detection of photons within a specific period in which stray light occurs. This control is called "gating", and the period in which photon detection is forcibly stopped by gating is called a "detection stop period".

[0076] In addition, the light emitting unit 110, the light detecting element 200 and the synchronization control unit 120 in the distance measuring module 100 are arranged in the same module, but can also be arranged in different devices. The device equipped with the light detecting element 200 is an embodiment of the light detecting device described in the claims.

[0077] [Configuration Example of Light Detection Element]

[0078] Figure 2 2 is a diagram showing an example of a stacked structure of a light detecting element 200 in the first embodiment of the present technology. The light detecting element 200 includes a circuit chip 202 and a pixel chip 201 stacked on the circuit chip 202. These chips are electrically connected to each other via a connection unit such as a via. Note that the chips may be connected by Cu-Cu bonding or bumps instead of through holes.

[0079] Figure 3 2 is a plan view showing a configuration example of a pixel chip 201 in the first embodiment of the present technology. The pixel chip 201 is provided with a rectangular light receiving unit 210, and a plurality of photoelectric conversion elements (such as photoelectric conversion elements 211, 212, 213, and 214) are arranged in a two-dimensional lattice pattern in the light receiving unit 210. As the photoelectric conversion element, an avalanche photodiode such as a SPAD is used.

[0080] Figure 4 2 is a block diagram showing a configuration example of the circuit chip 202 in the first embodiment of the present technology. The circuit chip 202 includes a timing generation unit 220, an H decoder 231, a V decoder 232, a circuit block 300, a multiplexer 240, a time-to-digital converter 250, a histogram generation unit 260, and an output interface 270.

[0081] The timing generation unit 220 generates various control signals in synchronization with the synchronization signal CLKp. The timing generation unit 220 provides these signals to the circuit block 300. The control signal includes, for example, a gate pulse indicating a photon detection stop period.

[0082] In the circuit block 300 , a plurality of detection circuits (not shown) are arranged. Each of the detection circuits detects the incidence of photons, generates a pulse signal, and supplies the pulse signal to the multiplexer 240 .

[0083] The H decoder 231 and the V decoder 232 drive the circuits in the pixel block 300 in units of rows or columns.

[0084] The multiplexer 240 sequentially selects each row and supplies a pulse signal of the row to the time-to-digital converter 250 .

[0085] The time-to-digital converter 250 converts the rise time of the pulse signal into a digital signal for each line. The digital signal indicates the photon detection timing. The time-to-digital converter 250 provides the digital signal to the histogram generation unit 260.

[0086] The histogram generation unit 260 generates a histogram based on the digital signal from the time digital converter 250. Here, the histogram is a graph indicating the detection frequency as the frequency of each detection timing indicated by the digital signal. The histogram generation unit 260 generates a histogram for each imaging pixel and obtains the timing of each peak as the light reception timing of the reflected light. Then, the histogram generation unit 260 converts the round-trip time from the irradiation timing of the irradiation light indicated by the synchronization signal to the light reception timing of the reflected light into the distance to the object for each imaging pixel. The histogram generation unit 260 generates distance data representing the obtained distance for each pixel and outputs the distance data to the outside via the output interface 270. Note that the circuit including the time digital converter 250 and the histogram generation unit 260 is an embodiment of the distance measurement unit described in the claims. In addition, a device having a light emitting unit 110 and a light detection element 200 is an embodiment of the distance measurement device described in the claims.

[0087] [Configuration Example of Circuit Block]

[0088] Figure 5 3 is a plan view showing an example of a circuit layout in a circuit block 300 in the first embodiment of the present technology. In the circuit block 300, a plurality of detection circuits such as detection circuits 311, 312, 313, and 314 are arranged in a two-dimensional grid pattern. These detection circuits are provided to each photoelectric conversion element. In the case where the pixel chip 201 is a chip on the circuit chip 202, the detection circuit is arranged directly below the corresponding photoelectric conversion element.

[0089] Furthermore, one common circuit 400 is arranged for every four detection circuits of 2 rows×2 columns in the circuit block 300. The common circuit 400 is a circuit shared by the four detection circuits, and is arranged at the center of the 2 rows×2 columns.

[0090] Figure 6 4 is a diagram showing a configuration example of a pixel in the first embodiment of the present technology. As described above, four detection circuits such as the detection circuits 311, 312, 313, and 314 share one common circuit 400. In addition, each detection circuit is connected to a corresponding photoelectric conversion element.

[0091] For example, the detection circuit 311 is connected to the photoelectric conversion element 211 , and the detection circuit 312 is connected to the photoelectric conversion element 212 . Furthermore, the detection circuit 313 is connected to the photoelectric conversion element 213 , and the detection circuit 314 is connected to the photoelectric conversion element 214 .

[0092] The detection circuit 311 and the like detect the incidence of photons outside the detection stop period based on the cathode voltage of the corresponding photoelectric conversion element. In the common circuit 400, a circuit for controlling the voltage of a gate pulse and the like is arranged.

[0093] The connected photoelectric conversion element, detection circuit and common circuit 400 are used as one pixel. For example, the photoelectric conversion element 211, the detection circuit 311 and the common circuit 400 are used as the first pixel, and the photoelectric conversion element 212, the detection circuit 312 and the common circuit 400 are used as the second pixel. The photoelectric conversion element 213, the detection circuit 313 and the common circuit 400 are used as the third pixel, and the photoelectric conversion element 214, the detection circuit 314 and the common circuit 400 are used as the fourth pixel. As shown in the figure, the common circuit 400 is shared by four pixels. The four pixels that share the common circuit 400 are called a "common block".

[0094] Since the common circuit 400 is shared by a plurality of pixels, the circuit area of ​​each pixel can be reduced compared to a case where a plurality of pixels do not share the common circuit.

[0095] [Configuration Example of Detection Circuit]

[0096] Figure 73 is a block diagram showing a configuration example of the detection circuit 311 in the first embodiment of the present technology. The detection circuit 311 includes a passive recharge (PR) current source 321, a PR switch 322, a gate switch 323, a PR pulse generation circuit 324, a gate circuit 350, and a latch signal generation circuit 360. In addition, the detection circuit 311 includes an active recharge (AR) current source 325, an AR switch 326, an active quenching (AQ) switch 327, an AR pulse generation circuit 330, and an AQ pulse generation circuit 340. In addition, the detection circuit 311 includes inverters 381 and 382, ​​buffers 383 and 384, and an output control circuit 370. Note that the circuit configuration of the detection circuits other than the detection circuit 311 (such as the detection circuits 312, 313, and 314) is similar to the circuit configuration of the detection circuit 311.

[0097] The passive recharge (PR) current source 321 supplies a constant current to the cathode of the photoelectric conversion element 211. The PR switch 322 opens and closes a path between the PR current source 321 and the cathode of the photoelectric conversion element 211 according to a PR enable signal XPR_EN from a PR pulse generation circuit 324. As the PR switch 322, for example, a P-channel metal oxide semiconductor (pMOS) transistor is used.

[0098] The PR pulse generating circuit 324 generates a PR enable signal XPR_EN. For example, a negative AND (NAND) gate that obtains a signal from the gating circuit 350 and an inverted value of the AQ enable signal AQ_EN from the AQ pulse generating circuit 340 is used as the PR pulse generating circuit 324. The NAND gate provides a negative OR signal to the PR switch 322 as the PR enable signal XPR_EN.

[0099] In addition, the AR current source 325 supplies a constant current to the cathode of the photoelectric conversion element 211. The AR switch 326 opens and closes the path between the AR current source 325 and the cathode of the photoelectric conversion element 211 according to the AR enable signal XAR_EN from the AR pulse generation circuit 330. For example, a pMOS transistor is used as the AR switch 326.

[0100] The AR pulse generation circuit 330 generates an AR enable signal XAR_EN and provides the generated signal to the AR switch 326 .

[0101] The gate switch 323 opens and closes the path between the cathode of the photoelectric conversion element 211 and a reference potential (ground potential, etc.) according to a gate pulse Gat from the gate circuit 350. As the gate switch 323, for example, an n-channel MOS (nMOS) transistor is used.

[0102] The gate control circuit 350 generates a gate control pulse Gat from the gate control pulse Gat_HV from the timing generation unit 220 and the latch signal LAT_HV, and supplies the gate control pulse Gat to the gate control switch 323 .

[0103] The latch signal generating circuit 360 generates latch signals LAT_HV and LAT_LV based on signals from the H decoder 231 and the V decoder 232. The latch signal LAT_HV is provided to the gate control circuit 350, and the latch signal LAT_LV is provided to the output control circuit 370. The H decoder 231 and the V decoder 232 can select pixels in units of rows and columns. The latch signal LAT_LV of the selected pixel is set to, for example, a high level.

[0104] The AQ switch 327 opens and closes a path between the cathode of the photoelectric conversion element 211 and a reference potential according to an AQ enable signal AQ_EN from the AQ pulse generation circuit 340. As the AQ switch 327, for example, an nMOS transistor is used.

[0105] The AQ pulse generation circuit 340 generates an AQ enable signal AQ_EN based on the signal from the inverter 381 , and supplies the AQ enable signal AQ_EN to the AQ switch 327 and the PR pulse generation circuit 324 .

[0106] Here, the gate pulse is a signal indicating a detection stop period for forcibly stopping photon detection (in other words, performing gating). For example, during the detection stop period, the gate pulse is set to a high level.

[0107] In addition, the AR enable signal XAR_EN is a signal indicating whether active recharging is enabled. For example, when active recharging is enabled, a low level is set to the AR enable signal XAR_EN.

[0108] The AQ enable signal AQ_EN is a signal indicating whether active quenching is enabled. For example, the AQ enable signal is set to a high level when active quenching is enabled.

[0109] The above-mentioned active recharging and active quenching are functions for avoiding the latching phenomenon of pixels. The latching phenomenon is a phenomenon that after detecting photons, the SPAD current caused by avalanche multiplication does not decrease to a predetermined latching current, and a balanced state is obtained when the current flows. In the case where the charging current for charging the SPAD is large, the voltage stagnates immediately before quenching, and latching may occur. When the latching phenomenon occurs, the recharging current and the SPAD current caused by avalanche multiplication continue to balance, and the cathode potential does not change. In this state, photons cannot be detected and the dead time is significantly increased.

[0110] In response to this, in the light detection element 200, active quenching is performed as a countermeasure to suppress locking during quenching. While the charging current is continuously allowed to flow, if the charging current and the SPAD current are balanced, the latch cannot be released for a period of time. However, by detecting the reaction of the SPAD, stopping the charging current for a certain period in the detection circuit 311, and performing "active quenching" that forcibly drops the cathode voltage to 0 volts (V), the latch can be released. Then, if the cathode voltage exceeds the threshold of the first-stage inverter 381 during quenching, latching does not occur.

[0111] In addition, in the light detection element 200, as a countermeasure against latching during charging, active recharging is performed. In order to avoid the equilibrium state, after the SPAD reaction, the light detection element 200 generates an AR enable signal XAR_EN, and performs "active recharging" that causes the charging current to flow for a necessary time. Therefore, even if latching occurs during recharging, when the recharging period by the AR enable signal XAR_EN ends, the recharging current becomes zero, the cathode voltage drops the SPAD current, and the latch is released.

[0112] On the other hand, in the case where active recharging is not performed, the charging current from the PR current source 321 is always provided. This control is called "passive recharging". Then, in the case where active quenching is not performed, the cathode voltage drops in response to the incidence of photons, and if latching does not occur, the SPAD current stops when the voltage becomes less than the breakdown voltage. This phenomenon is called "passive quenching".

[0113] Inverter 381 inverts the signal of cathode voltage CAT_HV of photoelectric conversion element 211 and supplies the inverted signal to inverter 382 and AQ pulse generation circuit 340. Inverter 382 inverts the signal from inverter 381 and supplies the inverted signal as CAT_LV to output control circuit 370 and buffers 383 and 384.

[0114] The output control circuit 370 generates output enable signals OUT_ENA and OUT_ENB based on the latch signal LAT_LV and the signal CAT_LV from the inverter 382. The output enable signals OUT_ENA and OUT_ENB are signals for enabling one of the outputs of the A system and the B system. For example, when the A system is turned on, the output enable signal OUT_ENA is set to a high level and the output enable signal OUT_ENB is set to a low level. When the B system is enabled, the output enable signal OUT_ENA is set to a low level and the output enable signal OUT_ENB is set to a high level.

[0115] When the output enable signal OUT_ENA is at a high level (enabled), the buffer 383 outputs the signal from the inverter 382 as a pulse signal PFOUT_A to the multiplexer 240. When the output enable signal OUT_ENB is at a high level (enabled), the buffer 384 outputs the signal from the inverter 382 as a pulse signal PFOUT_B to the multiplexer 240. Note that the pulse signals PFOUT_A and PFOUT_B are examples of the first and second pulse signals described in the claims.

[0116] Furthermore, the detection circuit 311 is divided into a high voltage domain whose power supply voltage is VDDH and a low voltage domain whose power supply voltage is VDDL lower than VDDH.

[0117] In the high voltage domain, a PR current source 321, a PR switch 322, a gate switch 323, a PR pulse generating circuit 324, and a gate circuit 350 are arranged. In addition, an AR current source 325, an AR switch 326, an AQ switch 327, an AR pulse generating circuit 330, an AQ pulse generating circuit 340, an inverter 381, and a portion of a latch signal generating circuit 360 are arranged in the high voltage domain.

[0118] On the other hand, in the low voltage domain, the latch signal generating circuit 360 , the inverter 382 , the buffer 383 , the buffer 384 , and the rest of the output control circuit 370 are arranged.

[0119] Note that the circuit configuration of the detection circuit 311 is not limited to the structure shown in the figure, as long as the detection circuit can detect the incidence of photons. For example, in the case where active recharging and active quenching are not performed, the AR current source 325, the AR switch 326, the AQ switch 327, the AR pulse generation circuit 330, and the AQ pulse generation circuit 340 are unnecessary. In addition, in the case where pixels are not selected in units of rows and columns, the latch signal generation circuit 360 becomes unnecessary. In addition, in the case where only one system is used for output instead of two systems, the buffer 383, the buffer 384, and the output control circuit 370 are unnecessary. In addition, in the case where it is not divided into a high voltage domain and a low voltage domain, one of the inverters 381 and 382 can be reduced. In addition, the detection circuit 311 and the like detect the incidence of photons outside the detection stop period based on the cathode voltage, but the incidence of photons can also be detected based on the anode voltage.

[0120] Figure 8 3 is a circuit diagram showing a configuration example of a gate control circuit 350 and a latch signal generating circuit 360 in the first embodiment of the present technology. The gate control circuit 350 includes a NAND gate 351 and a NOR (negative OR) gate 352. In addition, the latch signal generating circuit 360 includes a latch circuit 361 and a level shifter 362.

[0121] The latch circuit 361 latches the decoded signals HDEC_NS and SET_EW from the H decoder 231 and the V decoder 232 to generate a latch signal LAT_LV. The latch signal LAT_LV is provided to the output control circuit 370 and the level shifter 362 in the low voltage domain. The H decoder 231 and the V decoder 232 can set whether to drive on a pixel basis through the decoded signals HDEC_NS and SET_EW. A high level is set to the latch signal LAT_LV of the pixel to be driven by the decoded signals HDEC_NS and SET_EW.

[0122] The level shifter 362 shifts the high level of the latch signal LAT_LV from VDDL to VDDH. The level shifter 362 provides the shifted latch signal as LAT_HV to the NOR gate 352.

[0123] The NOR gate 352 obtains a negative OR of the latch signal LAT_HV and the gate pulse Gat_HV. The NOR gate 352 supplies a negative OR signal as XGat to the NAND gate 351 and the PR pulse generation circuit 324.

[0124] The NAND gate 351 provides the negative AND of XGat and the test signal XTEST as the gate pulse Gat to the gate control switch 323. Here, the test signal XTEST is a signal set by a predetermined test circuit (not shown), and is used to forcibly turn on the gate control switch 323 when a test related to gating is performed. When the turned-on state is forcibly set, for example, a low level is set as the test signal XTEST.

[0125] Furthermore, in the latch signal generating circuit 360 , a part of the level shifter 362 and the latch circuit 361 are arranged in the low voltage domain, and the rest of the level shifter 362 is arranged in the high voltage domain.

[0126] Fig. 9 1 is a circuit diagram showing a configuration example of an AR pulse generating circuit 330, an AQ pulse generating circuit 340, and an output control circuit 370 in the first embodiment of the present technology. The AR pulse generating circuit 330 includes a NAND gate 331 and an inverter 332. The AQ pulse generating circuit 340 includes a NOR gate 341, an inverter 342, and a delay circuit 343. The output control circuit 370 includes a flip-flop 371 and AND gates 372, 373, and 374.

[0127] In the output control circuit 370, the flip-flop 371 extracts and holds a high-level signal in synchronization with the signal CAT_LV from the inverter 382. In addition, the inversion value of the gate pulse Gat_LV from the common circuit 400 is input to the enable terminal of the flip-flop 371. When the inversion value is at a high level, the flip-flop 371 supplies the held signal to the AND gate 372.

[0128] The AND gate 372 provides a logical product of the latch signal LAT_LV and the signal from the flip-flop 371 to AND gates 373 and 374 .

[0129] The AND gate 373 supplies the logical product of the selection signal SEL_A from the common circuit 400 and the signal from the AND gate 372 to the buffer 383 as the output enable signal OUT_ENA.

[0130] The AND gate 374 provides the logical product of the selection signal SEL_B from the common circuit 400 and the signal from the AND gate 372 to the buffer 384 as the output enable signal OUT_ENB.

[0131] In the AQ pulse generating circuit 340 , the delay circuit 343 delays the signal from the inverter 381 within a predetermined period and supplies the delayed signal to the NOR gate 341 and the AR pulse generating circuit 330 .

[0132] The inverter 342 inverts the signal from the inverter 381 and provides the inverted signal to the NOR gate 341 .

[0133] The NOR gate 341 supplies the negative OR of the signal from the delay circuit 343, the signal from the inverter 342, and the control signal XHOFF_EN as the AQ enable signal AQ_EN to the AQ switch 327. Here, the control signal XHOFF_EN is a signal for forcibly turning off the AQ switch 327 regardless of the signal from the inverter 381, and is generated by a control circuit (not shown) outside the detection circuit 311. For example, when the off state is forcibly set, a high level is set to the control signal XHOFF_EN.

[0134] In the AR pulse generating circuit 330 , the inverter 332 inverts and delays the signal from the delay circuit 343 , and supplies the signal to the NAND gate 331 .

[0135] The NAND gate 331 provides the negative AND of the signal from the inverter 332, the signal from the delay circuit 343, and the control signal AR_SET as the AR enable signal XAR_EN to the AR switch 326. Here, the control signal AR_SET is a signal for forcibly turning off the AR switch 326 regardless of the signal from the AQ pulse generating circuit 340, and is generated by a control circuit (not shown) outside the detection circuit 311. For example, when the on state is forcibly set, a low level is set to the control signal AR_SET.

[0136] With the circuit configuration shown in the figure, the AQ pulse generation circuit 340 turns on the AQ switch 327 for a specific period after the cathode voltage drops due to the incidence of ToF light, and forcibly sets the cathode voltage to 0 volts. This period is called an "active quenching period". In addition, the AR pulse generation circuit 330 turns on the AR switch 326 for a specific period after the active quenching period has passed and provides a recharging current. That is, active recharging starts when the active quenching period has passed.

[0137] Fig.10 4 is a circuit diagram showing a configuration example of the common circuit 400 in the first embodiment of the present technology. The common circuit 400 includes a selection circuit 410 and a gate control circuit 420 .

[0138] The selection circuit 410 generates a selection signal indicating one of the pulse signals PFOUTA and PFOUTB, and supplies the selection signal to each of the detection circuits 311 to 314. The selection circuit 410 includes an OR (logical sum) gate 411 and a latch circuit 412.

[0139] OR gate 411 obtains the decoded signal HDEC from H decoder 231 <0> and HDEC <1> and outputs the logical sum to the latch circuit 412.

[0140] The latch circuit 412 generates selection signals SEL_A and SEL_B based on the signal from the OR gate 411 and the decoded signal OUT_SEL from the V decoder 232. As the latch circuit 412, for example, an SR latch circuit is used.

[0141] The H decoder 231 and the V decoder 232 can decode the HDEC signal <0> 、HDEC <1> The selection signal is set by OUT_SEL and OUT_SEL, and two or one of the pulse signals PFOUTA and PFOUTB are output. In the case of outputting the pulse signal PFOUTA, the high level is set to the selection signal SEL_A by the decoding signal, and the low level is set to the selection signal SEL_B. In the case of outputting the pulse signal PFOUTB, the low level is set to the selection signal SEL_A by the decoding signal, and the high level is set to the selection signal SEL_B. In the case of outputting both the pulse signals PFOUTA and PFOUTB, the high level is set to both the selection signals SEL_A and SEL_B.

[0142] The gate control circuit 420 controls the high level of the gate pulse Gat_HV from the power supply voltage VDDH to the power supply voltage VDDL, and provides the gate pulse to each of the detection circuits 311 to 314. The gate control circuit 420 includes inverters 421 and 422. The inverter 421 is arranged in the high voltage domain, and the inverter 422 and the selection circuit 410 are arranged in the low voltage domain.

[0143] The inverter 421 inverts the gate pulse Gat_HV and supplies the inverted gate pulse Gat_HV to the inverter 422. The inverter 422 inverts the signal from the inverter 422 and supplies the inverted signal as the gate pulse Gat_LV to each of the detection circuits 311 to 314. It should be noted that the inverter 421 is an embodiment of the front-stage inverter described in the claims, and the inverter 422 is an embodiment of the rear-stage inverter described in the claims.

[0144] As described above, the gate control circuit 420 controls the voltage of the gate pulse Gat_HV. Each of the detection circuits 311 to 314 detects the incidence of photons in a period that does not correspond to the detection stop period indicated by the gate pulse, and generates pulse signals PFOUTA and PFOUTB. In addition, the selection circuit 410 also generates selection signals SEL_A and SEL_B. Each of the detection circuits 311 to 314 outputs a pulse signal PFOUTA or PFOUTB according to the selection signal.

[0145] Note that the detection circuit 311 is an example of a first detection circuit described in the claims, and the detection circuit 312 is an example of a second detection circuit described in the claims.

[0146] [Pixel operation example]

[0147] Fig.114 is a timing chart showing an example of the operation of the pixel in the first embodiment of the present technology. The cathode voltages of the four pixels sharing the common circuit 400 are CAT1_HV, CAT2_HV, CAT3_HV, and CAT4_HV, respectively.

[0148] Assume that the light emitting unit 110 emits illumination light at timing T1. At timing T2 immediately thereafter, stray light is generated and incident on each pixel. The waveform of the bold dotted line in the figure represents the waveform of the stray light.

[0149] The timing generation unit 220 generates a gate pulse Gat_HV that becomes a high level in a specific period including the timing T1. By the gate pulse Gat_HV, the cathode voltage of each pixel is controlled to be equal to or lower than the low level of the threshold value of the first-stage inverter 381 during the period from the timing T0 to the timing T3. This period corresponds to a detection stop period during which the incidence of photons cannot be detected.

[0150] Then, the ToF light is incident on each pixel at timings T4, T5, T6, and T7 after the detection stop period has passed. The waveform of the thin dotted line in the figure indicates the irradiation intensity of the ToF light. Because the detection stop period has passed, each pixel detects the incidence of the ToF light, and the cathode voltage drops.

[0151] In a configuration where gating is not performed, each pixel detects the incidence of stray light at timing T2, and cannot detect the incidence of new photons until the dead time has passed. Therefore, for example, the pixel cannot detect the incidence of ToF light at timing T4, and the distance measurement performance at a short distance is degraded. On the other hand, the light detection element 200 can detect the incidence of ToF light at timing T4, etc. as shown in the figure due to the gating, and the distance measurement performance can be improved within a short distance.

[0152] Fig.12 2 is a diagram for describing an example of control of a decoder in the first embodiment of the present technology. Focus on the pixels from the 0th column to the 10th column in a specific row. In the figure, a white circle represents an output terminal of a pulse signal of the A system, and a black circle represents an output terminal of a pulse signal of the B system. In addition, in the multiplexer 240, OR gates 241 and 242 are provided for each row.

[0153] OR gate 241 provides the logical sum of the A-system pulse signals of 3K (K is an integer of 0 or greater) columns, 3K+1 columns, and 3K+2 columns to TDC 250. OR gate 242 provides the logical sum of the B-system pulse signals of 3K, 3K+1, and 3K+2 columns to TDC 250.

[0154] The H decoder 231 and the V decoder 232 can set whether to drive each pixel and set one of the A system and the B system based on the above decoded signal. Therefore, the light detection element 200 can detect ToF light at two points at the same time. For example, it is assumed that the light of the first point is incident from the 0th column to the second column, and the light of the second point is incident from the 7th column to the 9th column.

[0155] In this case, the H decoder 231 and the V decoder 232 are driven by setting the latch signals LAT_HV of the 0th to 2nd columns and the 7th to 9th columns to a high level and setting the latch signals of the other columns to a low level. In addition, the H decoder 231 and the V decoder 232 set the selection signal SEL_A of the 0th to 2nd columns to a high level and set the selection signal SEL_B of the 7th to 9th columns to a high level. Therefore, one of the two points can be detected and output from the 0th to 2nd columns in the A system, and the other of the two points can be detected and output from the 7th to 9th columns in the B system. Then, the subsequent circuit (TDC, etc.) can perform distance measurement on each of the two points at the same time.

[0156] Here, a configuration in which a plurality of pixels do not share the common circuit 400 is assumed as a first comparative example.

[0157] Fig.13 2 is a diagram showing an example of wiring of a signal line for transmitting a gate pulse in the first comparative example. As shown in the figure, in the first comparative example, a signal line 229 for transmitting a gate pulse needs to be wired for each column of the detection circuit.

[0158] Fig.14 1 is a diagram showing an example of wiring of the signal line 229 for transmitting the gate pulse in the first embodiment of the present technology. Since four pixels of 2 rows×2 columns share the common circuit 400, the signal line 229 is wired every two columns.

[0159] Fig.15 : is a diagram showing a wiring example of a signal line for transmitting a gate pulse in a common block in the first embodiment of the present technology. In a common block of 2 rows × 2 columns, a signal line is wired from a gate control circuit 420 in a common circuit 400 to detection circuits 311 to 314. In addition, wiring is performed from the central gate control circuit 420 to each of the four detection circuits so that the wiring length is substantially the same.

[0160] Fig.162 is a diagram showing an embodiment of wiring of signal lines 238 and 239 for transmitting decoded signals in the first comparative example. As shown in the figure, in the first comparative example, for each row, a signal line 238 for transmitting a decoded signal from the H decoder 231 must be wired, and for each column, a signal line 239 for transmitting a decoded signal from the V decoder 232 must be wired. The signal line 238 transmits Fig.10 The decoded signal HDEC is shown in <0> and HDEC <1> , and the signal line 239 transmits the decoded signal OUT_SEL. The signal line 238 physically includes two wirings, but is represented by one line for convenience of description.

[0161] Fig.17 2 is a diagram showing a wiring example of signal lines 238 and 239 for transmitting decoded signals in the first embodiment of the present technology. Since four pixels of 2 rows×2 columns share the common circuit 400, the signal line 238 is wired every two rows, and the signal line 239 is wired every two columns.

[0162] Fig.18 1 is a diagram showing a wiring example of signal lines for transmitting decoded signals in a common block in the first embodiment of the present technology. In a common block of 2 rows×2 columns, a signal line is wired from a selection circuit 410 in a common circuit 400 to each of detection circuits 311 to 314 .

[0163] like Figures 13 to 18 As shown in FIG. 4 , a plurality of pixels share the common circuit 400 , so that the number of wirings of signal lines for transmitting a gating pulse or a decoded signal can be reduced compared to the first comparative example.

[0164] In the above-described photodetection element 200 , four pixels share the common circuit 400 . However, the number of pixels sharing the common circuit 400 is not limited to four, and may be two, sixteen, or the like.

[0165] Fig.19 1 is a diagram showing a wiring example of a signal line for transmitting a gate pulse when the common circuit 400 is shared by 16 pixels in the first embodiment of the present technology. In the drawing, 4 rows×4 columns surrounded by a dotted line represent a common block.

[0166] Fig. 20 4 is a diagram showing a wiring example of a signal line for transmitting a decoded signal when the common circuit 400 is shared by 16 pixels in the first embodiment of the present technology. In the drawing, 4 rows×4 columns surrounded by a dotted line represent a common block.

[0167] like Fig.19 and 20 As shown in , as the number of shared pixels increases, the number of wirings can be further reduced.

[0168] As described above, according to the first embodiment of the present technology, since a plurality of pixels share the common circuit 400 , the circuit area per pixel can be reduced.

[0169] [First Modification]

[0170] In the above-mentioned first embodiment, both the gate control circuit 420 and the selection circuit 410 are shared by four pixels, but one of them may not be shared and may be arranged for each pixel. The light detection element 200 of the first variant of the first embodiment is different from the light detection element 200 of the first embodiment in that the selection circuit 410 is configured for each pixel.

[0171] Fig.21 1 is a circuit diagram showing a configuration example of the detection circuit 311 and the common circuit 400 in the first modification of the first embodiment of the present technology. In the first modification of the first embodiment, the selection circuit 410 is not arranged in the common circuit 400, and the selection circuit 410 is arranged in the detection circuit 311. The selection circuit 410 is also arranged in each of the detection circuits 312, 313, and 314.

[0172] As described above, according to the first modification example of the first embodiment of the present technology, since the selection circuit 410 is arranged in the detection circuit, the number of circuits in the common circuit 400 can be reduced.

[0173] [Second Modification]

[0174] In the first embodiment described above, the gate control circuit 420 including the inverters 421 and 422 is shared by four pixels, but in this configuration, it is difficult to further reduce the circuit area of ​​each pixel. The light detection element 200 of the second variant of the first embodiment is different from the light detection element 200 of the first embodiment in that the logic gate and the trigger are configured in the gate control circuit 420.

[0175] Fig. 22 : is a circuit diagram showing a configuration example of the detection circuit 311 and the common circuit 400 in the second modification of the first embodiment of the present technology. The common circuit 400 of the second modification of the first embodiment is different from the common circuit 400 of the first embodiment in that the OR gate 423 and the flip-flop 371 are arranged in the gate control circuit 420 instead of the inverter 422. In addition, the flip-flop 371 is not arranged in the detection circuit 311.

[0176] The final inverter 382 in the detection circuit 311 outputs the inverted signal as CAT1_LV to the OR gate 423. The final inverter in the detection circuit 312 outputs CAT2_LV to the OR gate 423, and the final inverter in the detection circuit 313 outputs CAT3_LV to the OR gate 423. The final inverter in the detection circuit 314 outputs CAT4_LV to the OR gate 423.

[0177] The OR gate 423 provides the logical sum of CAT1_LV, CAT2_LV, CAT3_LV, and CAT4_LV to the clock terminal of the flip-flop 371 .

[0178] Furthermore, the inverter 421 , the OR gate 423 , and the flip-flop 371 are arranged in the low voltage domain.

[0179] As shown in the figure, by arranging the flip-flop 371 in the common circuit 400 , the flip-flop 371 can be reduced in each of the detection circuits 311 to 314 .

[0180] As described above, according to the second modification example of the first embodiment of the present technology, since the flip-flop 371 is arranged in the common circuit 400 , the number of flip-flops in the detection circuit 311 and the like can be reduced.

[0181] <2. Second Embodiment>

[0182] In the first embodiment described above, the AR pulse generation circuit 330 starts active recharging when the active quenching period has passed, but with this configuration, it is difficult to further shorten the dead time. The light detection element 200 in the second embodiment is different from the light detection element 200 in the first embodiment in that active recharging is started even when the detection stop period has passed.

[0183] Fig.23 3 is a block diagram showing a configuration example of a detection circuit 311 in a second embodiment of the present technology. The detection circuit 311 of the second embodiment is different from the detection circuit 311 in the first embodiment in further including a NOR gate 521 and an AND gate 522 .

[0184] Fig.24 : is a circuit diagram showing a configuration example of the AR pulse generating circuit 330 and the AQ pulse generating circuit 340 in the second embodiment of the present technology.

[0185] The AQ pulse generating circuit 340 of the second embodiment realizes the function of the delay circuit 343 by inverters 344 and 345, a capacitor 346, and a current source 347. Furthermore, the AR pulse generating circuit 330 of the second embodiment includes an inverter 333 and a current source 334 instead of the inverter 332.

[0186] The inverter 345 inverts the signal from the inverter 381 and supplies the inverted signal as the AQ end signal AQ_END to the inverter 344 and the NOR gate 521. The current source 347 is connected to the ground terminal of the inverter 345. The capacitor 346 is connected to the connection node of the inverters 344 and 345. The inverter 344 inverts the AQ end signal AQ_END and supplies the inverted AQ end signal AQ_END to the NOR gate 341.

[0187] The AND gate 522 provides the NOR gate 521 with a logical product of the gate pulse Gat_HV and the latch signal LAT_HV.

[0188] The NOR gate 521 provides the inverted value of the signal from the AND gate 522 and the negative OR of the AQ terminal signal AQ_END as AR_EN to the NAND gate 331 and the inverter 333 .

[0189] The inverter 333 inverts AR_EN from the NOR gate 521 and provides the inverted AR_EN to the NAND gate 331. The current source 334 is connected to the ground terminal of the inverter 333.

[0190] Fig.25 1 is an example of a timing chart showing each of the active recharging control in the second embodiment and the active recharging control in the first embodiment of the present technology. In the drawings, a represents the active recharging control in the second embodiment, and b represents the active recharging control in the first embodiment.

[0191] In a of the drawing, it is assumed that stray light as reflected light in the distance measurement module 100 is generated during the detection stop period from timing T0 to timing T1. In order to prevent the SPAD reaction due to the stray light, the high level gate pulse Gat_HV is provided during this period.

[0192] The AR pulse generation circuit 330 generates a low-level AR enable signal XAR_EN in a period from the timing T1 to the timing T2 at which the gating is ended (ie, the detection stop period has passed). The cathode is quickly charged by active recharging after the gating.

[0193] Then, assuming that ToF light as reflected light reflected by the target is incident at timing T3 after timing T2, the cathode voltage CAT_HV drops, and the SPAD reaction triggers the AQ pulse generation circuit 340 to generate a high-level AQ enable signal in the active quenching period from timing T4 to timing T5.

[0194] In addition, the AR pulse generation circuit 330 generates a low-level AR enable signal XAR_EN in a period from timing T5 to timing T6 after the active quenching period has passed. This active recharging quickly charges the cathode.

[0195] The control in Figure a is through Fig.24 The circuit configuration shown in is implemented.

[0196] On the other hand, Fig.25 As shown in FIG. 1 b, in the first embodiment, the AR enable signal XAR_EN is maintained at a high level in the period from timing T1 to timing T2 after the detection stop period has passed, and active recharging is not performed. Therefore, due to the low-speed charging, the dead time becomes longer. In addition, active recharging after the active quenching period has passed is performed similarly to the second embodiment.

[0197] As described above, in the second embodiment, the AR pulse generation circuit 330 generates a low-level AR enable signal, and performs active recharging when the detection stop period has passed or when the active quenching period has passed. Specifically, by performing active recharging even when the detection stop period has passed, the dead time can be shortened compared to the first embodiment.

[0198] As described above, according to the second embodiment of the present technology, the AR pulse generation circuit 330 generates a low-level AR enable signal when the detection stop period has elapsed or when the active quenching period has elapsed, so that the dead time can be shortened.

[0199] <3. Third Embodiment>

[0200] In the first embodiment described above, the gate control circuit 420 and the selection circuit 410 are shared by a plurality of pixels, but with this configuration, it is difficult to further reduce the circuit area of ​​each pixel. The light detection element 200 in the third embodiment is different from the light detection element 200 in the first embodiment in that a plurality of pixels further share a recharging circuit, an AQ pulse generating circuit 340, etc.

[0201] Fig.26 3 is a circuit diagram showing a configuration example of the detection circuit 311 in the third embodiment of the present technology. In the third embodiment, it is assumed that the common circuit 400 is shared by two pixels.

[0202] The detection circuit 311 includes inverters 381 and 382 and buffers 383 and 384. The circuit configuration of the detection circuit 312 is similar to that of the detection circuit 311.

[0203] In addition, the inverter 381 in the detection circuit 311 provides the inverted signal XCAT1 to the common circuit 400, and the inverter 382 provides the pulse signal CAT1_LV to the common circuit 400. The first-stage inverter (not shown) in the detection circuit 312 provides the inverted signal XCAT2 to the common circuit 400, and the subsequent-stage inverter (not shown) provides the pulse signal CAT2_LV to the common circuit 400.

[0204] Note that the number of shared pixels is not limited to two and may be four or the like.

[0205] Fig. 27 is a block diagram showing a configuration example of the common circuit 400 in the third embodiment of the present technology. In addition to the gate control circuit 420 and the selection circuit 410, the common circuit 400 of the third embodiment includes a PR current source 321, a PR switch 322, a gate switch 323, a PR pulse generation circuit 324, a gate circuit 350, and a latch signal generation circuit 360. In addition, the detection circuit 311 includes an AR current source 325, an AR switch 326, an AQ switch 327, an AR pulse generation circuit 330, and an AQ pulse generation circuit 340. In addition, the detection circuit 311 includes an output control circuit 370, a recharge switching control unit 510, a recharge switching switch 523, and an OR gate 524.

[0206] Furthermore, in the third embodiment, a circuit including the PR current source 321 , the PR switch 322 , the AR current source 325 , and the AR switch 326 is referred to as a recharging circuit 320 .

[0207] The recharge switching switch 523 selects one of the cathode of the photoelectric conversion element 211 or the cathode of the photoelectric conversion element 212 according to the switching signal SPAD_SEL, and is connected to the recharge circuit 320 .

[0208] The recharge switching control unit 510 generates a switching signal SPAD_SEL based on the inversion signal XCAT1 and the AR enable signal XAR_EN, and provides the switching signal SPAD_SEL to the recharge switching switch 523 .

[0209] The OR gate 524 provides the logical sum of the inverted signals XCAT1 and XCAT2 to the AQ pulse generation circuit 340 as OR_OUT.

[0210] Fig.28 : is a diagram showing an example of the operation of the recharge switching control unit 510 in the third embodiment of the present technology.

[0211] In the case where the inversion signal XCAT1 is a logic value of “0” and the AR enable signal XAR_EN is a logic value of “0”, the recharge switching control unit 510 selects the photoelectric conversion element 212 and generates SPAD_SEL of a logic value of “0”.

[0212] In the case where the inversion signal XCAT1 is a logic value of “0” and the AR enable signal XAR_EN is a logic value of “1”, the recharge switching control unit 510 selects the photoelectric conversion element 211 and generates SPAD_SEL of a logic value of “1”.

[0213] In the case where the inversion signal XCAT1 is a logic value of “1”, the recharge switching control unit 510 selects the photoelectric conversion element 211 and generates SPAD_SEL of a logic value of “1”.

[0214] Here, a configuration is assumed in which the recharge circuit 320 is provided for each pixel without being shared, and the PR pulse generation circuit 324 and the AR pulse generation circuit 330 are shared by a plurality of pixels as a second comparative example. Figure 5 The circuit of the second comparative example is described in . The PR pulse generating circuit 324 and the AR pulse generating circuit 330 are arranged in the recharge signal generating circuit in the figure. It should be noted that in the case where active recharging is not performed, the AR pulse generating circuit 330 is not arranged in the charge signal generating circuit.

[0215] Fig.29 is a timing diagram of an embodiment of the operation of the detection circuit in the second comparative example. When a photon is incident on the first pixel corresponding to the cathode voltage CAT1 at timing T0, all four pixels in the common block are charged by active recharging within a specific period starting from timing T1. In addition, it is assumed that a photon is incident on the first pixel at timing T3, and a photon is incident on the second pixel corresponding to the cathode voltage CAT2 at timing T4 immediately thereafter. As described above, in the case where a photon is incident on two pixels almost at the same time, the light detection element 200 cannot detect the incidence of the photon on the second pixel. Then, all four pixels are charged by activating recharging within a specific period starting from timing T5. Thereafter, similarly, whenever a photon is incident on any one of the four pixels, all four pixels are charged.

[0216] As shown in the figure, in the second comparative example, each time a photon is incident on any one of the four pixels, the four pixels are charged simultaneously, so the instantaneous power consumption increases compared to the case where one pixel is charged at a time. In addition, in the case where a photon is incident on two pixels almost at the same time, the light detection element 200 cannot detect the incidence of a photon of one pixel.

[0217] Fig.30 1 is a timing diagram showing an example of the operation of the common circuit 400 in the case where photons are incident on each pixel in sequence in the third embodiment of the present technology. Assume that at time T0, a photon is incident on the first pixel corresponding to the cathode voltage CAT1_HV. The recharge switching control unit 510 connects the photoelectric conversion element 211 to the recharge circuit 320 through the high-level switching signal SPAD_SEL. The AQ pulse generation circuit 340 generates a high-level AQ enable signal AQ_EN for a certain period according to the rise of the output OR_OUT of the OR gate 524. Therefore, active quenching is performed.

[0218] Then, when the AQ enable signal AQ_EN falls at timing T1, the AR pulse generation circuit 330 generates a low-level AR enable signal XAR_EN in a certain period. Because the photoelectric conversion element 211 is connected to the recharging circuit 320, only the first pixel is charged by active recharging. At timing T2 immediately thereafter, the recharging switching control unit 510 connects the photoelectric conversion element 212 to the recharging circuit 320 through the low-level switching signal SPAD_SEL.

[0219] Subsequently, it is assumed that a photon is incident on the second pixel corresponding to the cathode voltage CAT2_HV at timing T3. The AQ pulse generation circuit 340 generates a high-level AQ enable signal AQ_EN in a certain period.

[0220] Then, when the AQ enable signal AQ_EN falls at timing T4, the AR pulse generation circuit 330 generates a low-level AR enable signal XAR_EN in a certain period from timing T5. Since the photoelectric conversion element 212 is connected to the recharge circuit 320, only the second pixel is charged by active recharging.

[0221] As shown in the drawing, since the recharge switching control unit 510 switches the connection destination of the recharge circuit 320, in the case where a photon is incident on one of the two pixels, only the pixel is charged.

[0222] Fig.31 3 is a timing diagram showing an example of the operation of the common circuit 400 in the case where photons are incident on two pixels almost at the same time in the third embodiment of the present technology. It is assumed that a photon is incident on the first pixel at timing T0, and a photon is incident on the second pixel at timing T1 immediately thereafter. The recharge switching control unit 510 connects the photoelectric conversion element 211 to the recharge circuit 320 through the high-level switching signal SPAD_SEL. In addition, the AQ pulse generation circuit 340 generates a high-level AQ enable signal AQ_EN within a certain period.

[0223] Then, when the AQ enable signal AQ_EN falls at timing T2, the AR pulse generation circuit 330 generates a low-level AR enable signal XAR_EN in a certain cycle. Because the photoelectric conversion element 211 is connected to the recharging circuit 320, only the first pixel is charged by active recharging. At the timing T3 immediately thereafter, the recharging switching control unit 510 connects the photoelectric conversion element 212 to the recharging circuit 320 through the low-level switching signal SPAD_SEL. In addition, the AQ pulse generation circuit 340 generates a high-level AQ enable signal AQ_EN in a certain cycle.

[0224] Then, when the AQ enable signal AQ_EN falls at timing T4, the AR pulse generation circuit 330 generates a low-level AR enable signal XAR_EN in a certain period from timing T5. Since the photoelectric conversion element 212 is connected to the recharging circuit 320, only the second pixel is charged by active recharging.

[0225] As shown in the figure, even in the case where photons are incident on two pixels almost simultaneously, the recharge switching control unit 510 switches the connection destination when active recharging of one pixel is completed, so that charging can be performed sequentially pixel by pixel.

[0226] Fig.32 : is a timing chart showing an example of the operation of the common circuit 400 in the case where photons are incident on two pixels almost simultaneously and then the photons are incident on one pixel in the third embodiment of the present technology.

[0227] Assume that a photon is incident on a first pixel at timing T0, and a photon is incident on a second pixel at timing T1 immediately thereafter. The recharge switching control unit 510 connects the photoelectric conversion element 211 to the recharge circuit 320 through a high-level switching signal SPAD_SEL. In addition, the AQ pulse generating circuit 340 generates a high-level AQ enable signal AQ_EN within a certain period.

[0228] Then, when the AQ enable signal AQ_EN falls at timing T2, the AR pulse generation circuit 330 generates a low-level AR enable signal XAR_EN in a certain period. Because the photoelectric conversion element 211 is connected to the recharge circuit 320, only the first pixel is charged by active recharging. At timing T3 immediately thereafter, the recharge switching control unit 510 connects the photoelectric conversion element 212 to the recharge circuit 320 through the low-level switching signal SPAD_SEL.

[0229] Then, it is assumed that a photon is further incident on the first pixel at timing T4. At time T5, the recharge switching control unit 510 connects the photoelectric conversion element 211 to the recharge circuit 320 through the high-level switching signal SPAD_SEL.

[0230] When the AQ enable signal AQ_EN falls at timing T6, the AR pulse generation circuit 330 generates a low-level AR enable signal XAR_EN in a certain period from timing T7. Since the photoelectric conversion element 211 is connected to the recharging circuit 320, only the first pixel is charged by active recharging.

[0231] At the timing T8 when the active recharging is completed, the recharging switching control unit 510 connects the photoelectric conversion element 212 to the recharging circuit 320 through the low-level switching signal SPAD_SEL. In addition, the AQ pulse generating circuit 340 generates a high-level AQ enable signal AQ_EN within a certain period.

[0232] Then, when the AQ enable signal AQ_EN falls at timing T9, the AR pulse generation circuit 330 generates a low-level AR enable signal XAR_EN in a certain period from timing T10. Since the photoelectric conversion element 212 is connected to the recharge circuit 320, only the second pixel is charged by active recharging.

[0233] As shown, even when photons are incident on two pixels almost simultaneously and the photons are incident on one pixel before completing recharging of both pixels, the common circuit 400 can preferentially recharge one cathode and recharge the other cathode after completing recharging.

[0234] like Fig.30 , Fig.31 and Fig.32 As shown, since the recharge switching control unit 510 switches the connection destination of the recharge circuit 320, charging can be performed sequentially pixel by pixel. Therefore, compared with the second comparative example in which four pixels are charged at the same time, instantaneous power consumption can be reduced. In addition, unlike the second comparative example, since the connection destination of active recharging is switched by the recharge switching control unit 510, photons of one pixel can be detected even when another pixel is being recharged.

[0235] Fig.33 is a diagram showing an example of a circuit layout in a detection circuit of a second comparative example. In the second comparative example, a recharge circuit 320 and an AQ pulse generation circuit 340 are arranged in each of the detection circuits 311 and 312. In other words, the recharge circuit 320 and the AQ pulse generation circuit 340 are arranged for each pixel.

[0236] Fig.343 is a diagram showing an example of a circuit layout in a common circuit 400 in a third embodiment of the present technology. In the third embodiment, the recharge circuit 320 and the AQ pulse generation circuit 340 are arranged in the common circuit 400 and are shared by two pixels. As described above, since the recharge circuit 320 and the AQ pulse generation circuit 340 are shared by two pixels, the circuit area can be reduced compared to the second comparative example in which these circuits are configured for each pixel.

[0237] As described above, according to the third embodiment of the present technology, since the recharge circuit 320 and the AQ pulse generation circuit 340 are further shared by a plurality of pixels, the circuit area per pixel can be further reduced.

[0238] [Modifications]

[0239] In the third embodiment described above, in the first embodiment described above, the AR pulse generating circuit 330 starts active recharging when the active quenching period has passed, but the present invention is not limited to this control. The light detecting element 200 in the third embodiment is different from the light detecting element 200 in the third embodiment in that the light detecting element 200 starts active recharging even when the connection destination is switched, except when the active quenching period has passed.

[0240] Fig.35 : is a circuit diagram showing a configuration example of a common circuit 400 in a modification of the third embodiment of the present technology. The common circuit 400 of the modification of the third embodiment is different from the common circuit 400 of the third embodiment in that it further includes an AR start signal generating circuit 530. The circuit configuration of the AR start signal generating circuit 530 will be described later.

[0241] In addition, in a modification of the third embodiment, the recharge switching control unit 510 includes inverters 511, 512, and 513. The inverters 511, 512, and 513 are connected in series. The inverted signal XCAT1 from the detection circuit 311 is input to the input terminal of the inverter 511. The inverters 511, 512, and 513 invert and delay the inverted signal XCAT1 and supply the result as the switching signal SPAD_SEL to the recharge switching switch 523. Therefore, after the inversion signal of the cathode voltage of one of the two pixels exceeds the threshold and becomes a high level, after a certain delay time has passed, the signal SPAD_SEL is switched, and the other pixel is selected.

[0242] Fig.36 : is a circuit diagram showing a configuration example of an AR start signal generation circuit 530 in a modification example of the third embodiment of the present technology. The AR start signal generation circuit 530 includes a NOR gate 531 , an OR gate 532 , and a NOR gate 533 .

[0243] The NOR gate 533 outputs the logical sum of the inverted signal XCAT1 from the detection circuit 311 and the switching signal SPAD_SEL from the recharge switching control unit 510 to the OR gate 532. The OR gate 532 outputs the logical sum of the gate pulse Gat_HV from the timing generation unit 220 and the output signal of the NOR gate 533 to the NOR gate 531. The NOR gate 531 provides the negative OR of the AQ end signal AQ_END from the AQ pulse generation circuit 340 and the output signal of the OR gate 532 to the AR pulse generation circuit 330 as the AR start signal AR_EN.

[0244] The AR pulse generation circuit 330 generates an AR enable signal XAR_EN based on the AR start signal AR_EN.

[0245] With the circuit configuration shown in the drawing, when the active quenching period has elapsed or when the connection destination to the recharging circuit 320 is switched from the photoelectric conversion element 211 to the photoelectric conversion element 212 , a high-level AR start signal AR_EN is generated.

[0246] When the AR start signal AR_EN rises, the AR pulse generation circuit 330 generates a low-level AR enable signal XAR_EN within a pulse period and performs active recharging.

[0247] Fig.37 is a timing diagram showing an example of the operation of the common circuit 400 when one of the two pixels detects a photon in a modification of the third embodiment of the present technology. Assume that a photon is incident on the first pixel corresponding to the photoelectric conversion element 211, and the cathode voltage CAT1_HV drops at time T0. After the active quenching period has passed, the first pixel is charged from timing T1 to timing T2 by active recharging. Then, the switching signal SPAD_SEL returns to a high level at timing T3 after the active recharging, and the second pixel corresponding to the photoelectric conversion element 212 is connected to the recharging circuit 320.

[0248] Fig.38 3 is a timing diagram showing an example of the operation of the common circuit when one of the two pixels detects a photon in a modification of the third embodiment of the present technology. Assume that a photon is incident on the second pixel and the cathode voltage CAT2_HV drops at time T0. The second pixel is charged by active recharging from timing T1 to timing T2 after the active quenching period has passed. The switching signal SPAD_SEL is maintained at a high level, and the connection destination of the recharging circuit 320 is not switched.

[0249] Fig.391 is a timing chart showing an example of the operation of the common circuit when one of two pixels reacts during the active quenching period of the other pixel in the modification of the third embodiment of the present technology.

[0250] It is assumed that the second pixel reacts to the incidence of a photon at timing T0, and the first pixel reacts to the incidence of a photon at timing T1 during the active quenching period. Fig.36 In the circuit configuration shown in , the pulse of the AR enable signal XAR_EN is generated from the logical sum of the inverted signals of the pixels from the OR gate 524. Therefore, the pulse of the AR enable signal XAR_EN is not newly generated, and the active recharging of the first pixel is performed in the period from the timing T2 to the timing T3 after the short active quenching period. At the subsequent timing T4, the active recharging of the second pixel is performed.

[0251] Fig.40 : is a timing chart showing an example of the operation of the common circuit 400 in the case where photons are incident on two pixels almost simultaneously and then the photons are incident on one pixel in the modification of the third embodiment of the present technology.

[0252] Since the two pixels react at the same time at the timing T0, the common circuit 400 performs active recharging of the first pixel from the timing T1. After the active recharging ends, the first pixel reacts at the timing T2 before the active recharging of the second pixel starts. Also in this case, the pulse of the AQ enable signal XAQ_EN is not newly generated, and the active recharging of the first pixel is performed immediately after the timing T2.

[0253] However, when active quenching is not performed, there is a high possibility that latching occurs, which is a problem that the cathode voltage stagnates at a certain value. In addition, the dead time of the second pixel also increases. In order to prevent this, it is necessary to set the delay time in the common circuit 400 to be short so that active recharging of the second pixel is immediately performed at timing T4 after timing T2 when active recharging is completed.

[0254] Fig.41 1 is a timing chart showing an example of the operation of the common circuit 400 when one of the two pixels reacts during the recharging period of the other pixel in the modification of the third embodiment of the present technology.

[0255] Since the second pixel has already reacted at timing T0, the common circuit 400 starts active recharging of the pixel after timing T1. Assume that the first pixel reacts at timing T2 during active recharging. In this case, by switching the connection destination of the recharging circuit 320 at timing T3, active recharging of the first pixel is stopped in the middle, and active recharging of the second pixel is started. At timing T4 thereafter, active recharging of the first pixel stopped in the middle is restarted.

[0256] As described above, according to the modification example of the third embodiment of the present technology, when the active quenching period has elapsed or the connection destination is switched, the advanced AR start signal AR_EN is generated.

[0257] <4. Application examples of mobile objects>

[0258] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented in the form of a device installed on any kind of mobile body (such as, a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot).

[0259] Fig.42 is a block diagram showing an embodiment of a schematic configuration of a vehicle control system, which is an embodiment of a moving body control system to which the technology according to the present disclosure can be applied.

[0260] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.42 In the illustrated embodiment, the vehicle control system 12000 includes a drive system control portion 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output portion 12052, and an in-vehicle network interface (I / F) 12053 are depicted as functional components of the integrated control unit 12050.

[0261] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 is used as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a drive force of the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, and the like.

[0262] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a backup light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave or a signal of various switches transmitted from a mobile device as a substitute for a key may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0263] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the image outside the vehicle and receive the imaged image. In addition, the vehicle exterior information detection unit 12030 may also detect objects such as people, vehicles, obstacles, signs, and text on the road surface based on the received image, or detect the distance thereof.

[0264] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0265] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that images the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0266] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes collision prevention or shock absorption for the vehicle, follow-up driving based on the following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from the lane, etc.

[0267] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby enabling the vehicle to drive automatically without relying on the driver's calculations, etc.

[0268] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the vehicle exterior information acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam based on the position of the front vehicle or the oncoming vehicle detected by the external vehicle information detection unit 12030.

[0269] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Fig.42 In the embodiment of FIG. 1 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0270] Fig.43 This is a diagram of an embodiment of the installation position of the imaging unit 12031.

[0271] exist Fig.43 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0272] The imaging units 12101, 12102, 12103, 12104, 12105 are provided, for example, at locations such as the front nose, side mirrors, rear bumper, rear door, and upper portion of the windshield in the interior of the vehicle 12100. The imaging unit 12101 provided at the front nose in the interior of the vehicle and the imaging unit 12105 provided at the upper portion of the windshield mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 provided to the side mirrors mainly obtain images of the sides of the vehicle 12100. The imaging unit 12104 provided to the rear bumper or rear door mainly obtains images of the rear portion of the vehicle 12100. The imaging unit 12105 provided at the upper portion of the windshield in the interior of the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0273] Please note that Fig.43An embodiment of the shooting range of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 set to the front nose. The imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 set to the side mirrors. The imaging range 12114 represents the imaging range of the imaging unit 12104 set to the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 viewed from above is obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0274] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0275] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting the objects existing on the driving path of the vehicle 12100 and traveling in the same direction as the vehicle 12100 at a prescribed speed (e.g., equal to or greater than 0 km / hour). In addition, the microcomputer 12051 can pre-set the following distance to keep ahead of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. As a result, coordinated control for automatic driving that allows the vehicle to travel automatically without relying on the calculation of the driver, etc., can be performed.

[0276] For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0277] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. This identification of a pedestrian is performed, for example, by a process of extracting feature points in the imaged images of the imaging units 12101 to 12104 as infrared cameras and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer 12051 determines that a pedestrian exists in the imaged images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed as superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0278] The embodiments of the vehicle control system to which the technology according to the present disclosure can be applied have been described above. For example, the technology according to the present disclosure can be applied to the vehicle exterior information detection unit 12030 in the above-mentioned components. Specifically, Figure 1 The distance measurement module 100 can be applied to the vehicle exterior information detection unit 12030. By applying the technology according to the present disclosure to the vehicle exterior information detection unit 12030, the circuit area can be reduced and the cost and power consumption of the unit can be reduced.

[0279] It should be noted that the above-mentioned embodiments show examples for embodying the present technology, and the various contents in the embodiments and the various contents specifying the present invention in the claims have a corresponding relationship. Similarly, the matters specifying the present invention in the claims and the matters with the same names in the embodiments of the present technology have a corresponding relationship, respectively. However, the present technology is not limited to the embodiments, and can be embodied by applying various modifications to the embodiments without departing from the scope of the present technology.

[0280] It should be noted that the effects described in this specification are merely embodiments and are not limiting, and other effects can also be achieved.

[0281] It should be noted that the present technology may also have the following configurations.

[0282] (1) A light detection device comprising:

[0283] a first detection circuit that detects incidence of photons based on a voltage of one of an anode and a cathode of the first photoelectric conversion element in a period that does not correspond to a predetermined detection stop period;

[0284] a second detection circuit that detects incidence of photons based on a voltage of one of an anode and a cathode of the second photoelectric conversion element in a period that does not correspond to the detection stop period; and

[0285] A common circuit controls the voltage of a gate pulse indicating a detection stop period.

[0286] (2) The light detection device according to (1), wherein:

[0287] The first detection circuit and the second detection circuit output at least one of the first pulse signal and the second pulse signal according to the selection signal when the photon incident is detected, and

[0288] Common circuits include:

[0289] The gate control circuit controls the voltage of the gate pulse, and

[0290] A selection circuit generates a selection signal and supplies the selection signal to the first detection circuit and the second detection circuit.

[0291] (3) The light detection device according to (2), wherein:

[0292] The gate control circuit includes:

[0293] a front-stage inverter that inverts the gate pulse and outputs an inverted signal; and

[0294] a subsequent inverter that inverts the inverted signal and supplies the result to the first detection circuit and the second detection circuit,

[0295] The power supply voltages of the front-stage inverter and the rear-stage inverter are different from each other.

[0296] (4) The light detection device according to (2), wherein:

[0297] The gate control circuit includes:

[0298] The inverter inverts the gate pulse and outputs the inverted gate pulse as an enable signal.

[0299] a logic gate that performs a logic operation on the pulse signal from each of the first detection circuit and the second detection circuit and outputs the operation result; and

[0300] The flip-flop supplies a signal of a predetermined level to the first detection circuit and the second detection circuit in synchronization with the operation result when the enable signal has a predetermined value.

[0301] (5) The light detection device according to (1), wherein

[0302] The common circuit also includes:

[0303] a recharging circuit that performs recharging of one of the first photoelectric conversion element and the second photoelectric conversion element,

[0304] an active quenching switch, connecting the recharging circuit and the reference voltage during the active quenching period according to an active quenching enable signal indicating a predetermined active quenching period, and

[0305] The active quenching pulse generating circuit generates an active quenching enabling signal.

[0306] (6) The light detection device according to (5), further comprising:

[0307] A recharging switch selects one of the first photoelectric conversion element and the second photoelectric conversion element and connects the selected one photoelectric conversion element to a recharging circuit, wherein:

[0308] The recharging circuit includes:

[0309] Active recharge current source,

[0310] Passive recharging current source,

[0311] an active recharging switch that opens and closes a path between an active recharging current source and a recharging switch according to an active recharging enable signal; and

[0312] A passive recharging switch opens and closes the path between the passive recharging current source and the recharging switch,

[0313] The common circuit also includes an active recharge pulse generating circuit that generates an active recharge enable signal.

[0314] (7) The light detection device according to (6), wherein:

[0315] The common circuit also includes:

[0316] an active recharge start signal generating circuit that generates an active recharge start signal when the active quenching period has elapsed or when the recharge switching switch is switched, and

[0317] The active recharge pulse generating circuit generates an active recharge enable signal based on the active recharge start signal.

[0318] (8) The light detection device according to (1), wherein:

[0319] The detection circuit includes:

[0320] Active recharge current source,

[0321] an active recharge switch that opens and closes a path between an active recharge current source and a predetermined node according to an active recharge enable signal;

[0322] an active quenching switch connecting a predetermined node and a reference voltage during a predetermined active quenching period, and

[0323] The active recharge pulse generating circuit generates an active recharge enable signal when the detection stop period has elapsed or when the active quenching period has elapsed.

[0324] (9) The light detection device according to any one of (1) to (8), wherein:

[0325] The photoelectric conversion element is a single photon avalanche diode (SPAD).

[0326] (10) A distance measuring device comprising:

[0327] a light emitting unit; and

[0328] A light detection element, comprising: a first detection circuit that detects the incidence of photons based on the voltage of one of the anode and cathode of the first photoelectric conversion element in a period that does not correspond to a predetermined detection stop period; a second detection circuit that detects the incidence of photons based on the voltage of one of the anode and cathode of the second photoelectric conversion element in a period that does not correspond to the detection stop period; a common circuit that controls the voltage of a gate pulse indicating the detection stop period; and a distance measurement unit that performs distance measurement based on the light emission timing of the light emission unit and the incidence timing of photons detected by each of the first detection circuit and the second detection circuit.

[0329] (11) A method for controlling a light detection device, comprising:

[0330] a first detection process in which the first detection circuit detects incidence of photons based on a voltage of one of an anode and a cathode of the first photoelectric conversion element in a period not corresponding to a predetermined detection stop period;

[0331] a second detection process in which the second detection circuit detects incidence of photons based on a voltage of one of an anode and a cathode of the second photoelectric conversion element in a period not corresponding to the detection stop period; and

[0332] A control process in which a common circuit controls the voltage of a gate pulse indicating a detection stop period.

[0333] Reference Symbols List

[0334] 100 Distance measurement module

[0335] 110 Lighting Unit

[0336] 120 Synchronous control unit

[0337] 200 Light detection element

[0338] 201 pixel chip

[0339] 202 Circuit Chip

[0340] 210 Light receiving unit

[0341] 211 to 214 photoelectric conversion element

[0342] 220 Timing Generation Unit

[0343] 231 H Decoder

[0344] 232 V decoder

[0345] 240 Multiplexer

[0346] 241, 242, 411, 423, 524, 532 logic and (OR) gate

[0347] 250 Time to Digital Converter

[0348] 260 Histogram generation unit

[0349] 270 Output interface

[0350] 300 Circuit Blocks

[0351] 311 to 314 detection circuit

[0352] 320 Recharging Circuit

[0353] 321 PR Current Source

[0354] 322 PR switch

[0355] 323 Door switch

[0356] 324 PR pulse generation circuit

[0357] 325 AR Current Source

[0358] 326 AR switch

[0359] 327 AQ Switch

[0360] 330 AR pulse generation circuit

[0361] 331,351NAND gates

[0362] 332, 333, 342, 344, 345, 381, 382, ​​421, 422, 511 to 513 inverters

[0363] 334,347 Current Source

[0364] 340AQ pulse generating circuit

[0365] 341, 352, 521, 531, 533 NOR gate

[0366] 343 Delay Circuit

[0367] 346 Capacitor Components

[0368] 350 Gate Control Circuit

[0369] 360 Latch signal generation circuit

[0370] 361,412 Latch Circuit

[0371] 362 Level Shifter

[0372] 370 Output control circuit

[0373] 371 Trigger

[0374] 372 to 374, 522 logical product (AND) gates

[0375] 383, 384 Buffer

[0376] 400 shared circuit

[0377] 410 Selection Circuit

[0378] 420 Gate Control Circuit

[0379] 510 Recharge switching control unit

[0380] 523 Recharge switch

[0381] 530 AR start signal generating circuit

[0382] 12030 External vehicle information detection unit.

Claims

1. A light detection device, comprising: a first detection circuit that detects incidence of photons based on a voltage of one of an anode and a cathode of the first photoelectric conversion element in a period that does not correspond to a predetermined detection stop period; a second detection circuit that detects incidence of photons based on a voltage of one of an anode and a cathode of a second photoelectric conversion element in a period that does not correspond to the detection stop period; and The common circuit controls the voltage of the gate pulse indicating the detection stop period.

2. The light detection device according to claim 1, wherein: The first detection circuit and the second detection circuit output at least one of a first pulse signal and a second pulse signal according to a selection signal when detecting incident photons, and The shared circuit comprises: a gate control circuit, controlling the voltage of the gate pulse, and A selection circuit generates the selection signal and supplies the selection signal to the first detection circuit and the second detection circuit.

3. The light detection device according to claim 2, wherein: The gate control circuit comprises: a front-stage inverter, inverting the gate pulse and outputting an inverted signal; and a subsequent inverter that inverts the inverted signal and supplies the result to the first detection circuit and the second detection circuit, The power supply voltages of the front-stage inverter and the rear-stage inverter are different from each other.

4. The light detection device according to claim 2, wherein: The gate control circuit comprises: an inverter, inverting the gate pulse and outputting the inverted gate pulse as an enable signal, a logic gate that performs a logic operation on the pulse signal from each of the first detection circuit and the second detection circuit and outputs the operation result; and A flip-flop supplies a signal of a predetermined level to the first detection circuit and the second detection circuit in synchronization with the operation result when the enable signal has a predetermined value.

5. The light detection device according to claim 1, wherein: The shared circuit also includes: a recharging circuit that performs recharging of one of the first photoelectric conversion element and the second photoelectric conversion element, The active quenching switch connects the recharging circuit and the reference voltage and the active quenching pulse generating circuit within the active quenching period according to the active quenching enable signal indicating the predetermined active quenching period, and generates the active quenching enable signal.

6. The light detection device according to claim 5, further comprising: a recharging switch, which selects one of the first photoelectric conversion element and the second photoelectric conversion element and connects the selected one photoelectric conversion element to the recharging circuit, wherein: The recharging circuit comprises: Active recharge current source, Passive recharging current source, an active recharging switch, opening and closing a path between the active recharging current source and the recharging switch according to an active recharging enable signal; and a passive recharging switch, opening and closing a path between the passive recharging current source and the recharging switch, The common circuit also includes an active recharge pulse generating circuit that generates the active recharge enable signal.

7. The light detection device according to claim 6, wherein: The shared circuit also includes: an active recharge start signal generating circuit, which generates an active recharge start signal when the active quenching period has elapsed or when the recharge switch is switched, and The active recharge pulse generation circuit generates the active recharge enable signal based on the active recharge start signal.

8. The light detection device according to claim 1, wherein The detection circuit comprises: Active recharge current source, an active recharging switch, opening and closing a path between the active recharging current source and a predetermined node according to an active recharging enable signal; an active quenching switch, connecting the predetermined node and a reference voltage within a predetermined active quenching period, and The active recharge pulse generating circuit generates the active recharge enable signal when the detection stop period has elapsed or when the active quenching period has elapsed.

9. The light detection device according to claim 1, wherein: The photoelectric conversion element is a single photon avalanche diode (SPAD).

10. A distance measuring device, comprising: Light emitting unit; as well as A light detection element, comprising: a first detection circuit that detects the incidence of photons based on a voltage of one of an anode and a cathode of a first photoelectric conversion element in a period not corresponding to a predetermined detection stop period; a second detection circuit that detects the incidence of photons based on a voltage of one of an anode and a cathode of a second photoelectric conversion element in a period not corresponding to the detection stop period; and a common circuit that controls a voltage of a gate pulse indicating the detection stop period; and a distance measurement unit that performs distance measurement based on the light emission timing of the light emission unit and the incident timing of photons detected by each of the first detection circuit and the second detection circuit.

11. A method for controlling a light detection device, comprising: a first detection process in which the first detection circuit detects incidence of photons based on a voltage of one of an anode and a cathode of the first photoelectric conversion element in a period not corresponding to a predetermined detection stop period; a second detection process in which the second detection circuit detects incidence of photons based on a voltage of one of an anode and a cathode of the second photoelectric conversion element in a period not corresponding to the detection stop period; and A control process in which a common circuit controls the voltage of a gate pulse indicating a detection stop period.

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