Method for removing silicon substrate in chip based on C2W bonding

Abstract

The invention provides a method for removing a silicon substrate in a chip based on C2W bonding, and belongs to the technical field of electro-optical modulators, and the method comprises the steps: forming a waveguide core on a substrate, depositing a first passivation layer, and enabling the first passivation layer to cover the substrate and the waveguide core; metal grooves are formed in the two sides of the waveguide core respectively, and metal electrodes are formed in the metal grooves; depositing a second passivation layer, wherein the second passivation layer covers the metal electrode and the first passivation layer; opening a hole above the metal electrode to form a hole structure; forming a protective layer in an area corresponding to the metal electrode above the second passivation layer, wherein the protective layer covers the metal electrode through the hole structure; bonding an area, corresponding to the waveguide core, above the second passivation layer with the chip; removing the silicon substrate in the chip after bonding; and removing the protective layer. According to the scheme, the device preparation time is shortened, and the cost is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of electro-optic modulators, and in particular to a method for removing a silicon substrate in a chip based on C2W bonding. Background Art

[0002] Compared with traditional silicon photonics, silicon photonics based on silicon nitride (SiN) materials have many individual advantages such as low loss, wide spectrum, and high optical power. Therefore, SiN has gradually become an important platform for ultra-low loss photonic integration with CMOS compatibility. However, due to the lack of electro-optical properties of SiN, it is difficult to realize active devices such as efficient electro-optical modulators.

[0003] Lithium niobate (LN) crystals are known as the "silicon" in the field of photonics due to their excellent electro-optical, nonlinear optical, acousto-optic and photorefractive properties. However, their etching process is complex and incompatible with CMOS technology, so they are very challenging to mass produce.

[0004] Heterogeneous integration of SiN and thin-film lithium niobate (TFLN) can, on the one hand, give full play to the high light transmittance of SiN as an optical waveguide medium, and at the same time, based on the performance advantages of TFLN such as high optoelectronic bandwidth, it can meet the needs of 200Gbps / lane and higher rate applications. Using Chip to wafer (C2W) can avoid etching process and achieve compatibility with CMOS process.

[0005] After C2W bonding, the silicon substrate on the chip needs to be removed by chemical solution corrosion or dry etching to ensure the modulation performance of TFLN.

[0006] The existing technology forms a protective layer after bonding. The electrodes on the wafer need to be protected by the protective layer, while the chip area needs to be exposed for subsequent removal of the silicon substrate. The protective layer can be deposited on the entire surface first, and then the protective layer in the chip area can be removed by photolithography and etching. Alternatively, photoresist can be applied first, and the photoresist in the wafer electrode area can be removed by photolithography, and then the protective layer can be deposited and finally peeled off.

[0007] Whether using post-deposition etching or stripping process, the photolithography process cannot be avoided. However, the chip after bonding is several hundred microns higher than the wafer. If a glue spreader is used, the obstruction of the chip may easily lead to uneven glue layer, bubbles and other undesirable phenomena. If a glue sprayer is used, the utilization rate of the photoresist is low, usually 5% to 15%, and the equipment cost is higher than that of a glue spreader.

[0008] On the other hand, there is a large step between the chip and the wafer, and generally two photolithography processes are required, which is time-consuming and costly. At the same time, the impact of overlay accuracy on the product must also be considered. This can also be accomplished using a double-sided exposure machine, but the cost of this instrument is higher than that of an ordinary photolithography machine. Summary of the invention

[0009] In view of this, an embodiment of the present application provides a method for removing the silicon substrate in a chip based on C2W bonding, which at least partially solves the problem in the prior art that the chip is several hundred microns higher than the wafer after bonding, which easily leads to an uneven protective layer and high cost for preparing the protective layer.

[0010] The embodiment of the present application provides a method for removing a silicon substrate in a chip based on C2W bonding, the method comprising:

[0011] forming a waveguide core on a substrate and depositing a first passivation layer, wherein the first passivation layer covers the substrate and the waveguide core;

[0012] Forming metal grooves on both sides of the waveguide core respectively, and forming metal electrodes in the metal grooves;

[0013] Depositing a second passivation layer, wherein the second passivation layer covers the metal electrode and the first passivation layer;

[0014] Opening a hole above the metal electrode to form a hole structure;

[0015] forming a protective layer in a region above the second passivation layer corresponding to the metal electrode, wherein the protective layer covers the metal electrode through the hole structure;

[0016] Bonding a region above the second passivation layer corresponding to the waveguide core to a chip, wherein a silicon substrate is provided on a side of the chip away from the bonding region;

[0017] removing the silicon substrate in the chip after bonding;

[0018] The protective layer is removed.

[0019] According to a specific implementation of the embodiment of the present application, forming a waveguide core on a substrate includes:

[0020] depositing a waveguide layer on the substrate;

[0021] The waveguide layer is etched to form the waveguide core.

[0022] According to a specific implementation of the embodiment of the present application, the forming of the metal electrode in the metal groove includes:

[0023] Depositing metal, wherein the metal covers the first passivation layer and the metal groove;

[0024] The metal on the first passivation layer is etched, and the metal in the metal groove forms the metal electrode.

[0025] According to a specific implementation of the embodiment of the present application, bonding the area above the second passivation layer corresponding to the waveguide core to the chip includes:

[0026] Sequentially cleaning and plasma activating the area above the second passivation layer corresponding to the waveguide core and the chip;

[0027] Pre-bonding the region above the second passivation layer corresponding to the waveguide core and the chip at room temperature to form a pre-bonded device;

[0028] The pre-bonded device is annealed at 50-120° C. for 6-12 hours to complete the bonding.

[0029] According to a specific implementation of the embodiment of the present application, removing the silicon substrate in the chip includes:

[0030] The silicon substrate in the chip is removed by a wet etching or dry etching process.

[0031] According to a specific implementation of the embodiment of the present application, removing the silicon substrate in the chip includes:

[0032] Grinding the silicon substrate in the chip to reduce the thickness of the silicon substrate to 20-40 μm;

[0033] The ground silicon substrate is removed by wet etching or dry etching.

[0034] According to a specific implementation of the embodiment of the present application, removing the silicon substrate in the chip includes:

[0035] Dry etching the silicon substrate in the chip until the thickness of the silicon substrate is 5-20 μm;

[0036] The remaining silicon substrate is removed by a wet etching process.

[0037] According to a specific implementation of the embodiment of the present application, the thickness of the protective layer is 5-100 μm.

[0038] According to a specific implementation of the embodiment of the present application, removing the protective layer includes:

[0039] The protective layer is removed by soaking in a chemical liquid, wherein the chemical liquid is N-methylpyrrolidone or acetone.

[0040] According to a specific implementation of an embodiment of the present application, the chip also includes an electro-optical material layer and a silicon oxide layer, the electro-optical material layer is bonded to the area above the second passivation layer corresponding to the waveguide core, and the silicon oxide layer is located between the electro-optical material layer and the silicon substrate.

[0041] Beneficial effects:

[0042] The method for removing the silicon substrate in the chip based on C2W bonding in the embodiment of the present application mainly includes forming a protective layer before C2W bonding, and then removing the silicon substrate. In the scheme of the present application, there is no step on the wafer before bonding, and the glue is spread by a glue spreader, so that the glue layer (protective layer) is uniform and no bubbles or other undesirable phenomena will occur; in addition, there is no need to use a glue sprayer, which improves the utilization rate of the photoresist and reduces the cost of device preparation.

[0043] On the other hand, there are no steps on the wafer before bonding, and only one photolithography process is required, which shortens the time and reduces the cost. There is no need to consider the impact of overlay accuracy on the product. In addition, there is no need to use a double-sided exposure machine, which reduces costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 A flowchart of a method for removing a silicon substrate from a chip based on C2W bonding according to an embodiment of the present invention;

[0046] Figure 2 is a schematic diagram of depositing a waveguide layer according to an embodiment of the present invention;

[0047] Figure 3 is a schematic diagram of forming a waveguide core according to an embodiment of the present invention;

[0048] Figure 4 is a schematic diagram of forming a first passivation layer according to an embodiment of the present invention;

[0049] Figure 5 is a schematic diagram of forming a metal groove according to an embodiment of the present invention;

[0050] Figure 6 is a schematic diagram of depositing metal according to an embodiment of the present invention;

[0051] Figure 7is a schematic diagram of forming a metal electrode according to an embodiment of the present invention;

[0052] Figure 8 Schematic diagram of forming a second passivation layer according to an embodiment of the present invention

[0053] Fig. 9 Schematic diagram of forming a hole structure according to an embodiment of the present invention

[0054] Fig.10 A schematic diagram of forming a protective layer according to an embodiment of the present invention;

[0055] Fig.11 is a bonding schematic diagram according to an embodiment of the present invention;

[0056] Fig.12 is a schematic diagram of removing a silicon substrate according to an embodiment of the present invention;

[0057] Fig.13 is a schematic diagram of removing a protective layer according to an embodiment of the present invention;

[0058] Fig.14 is another bonding schematic diagram according to an embodiment of the present invention;

[0059] Fig.15 FIG. 4 is another schematic diagram of removing a silicon substrate according to an embodiment of the present invention.

[0060] In the figure: 1. wafer substrate; 2. waveguide layer; 3. waveguide core; 4. metal groove; 5. metal electrode; 6. hole structure; 7. protective layer; 8. electro-optical material layer; 9. silicon oxide layer; 10. silicon substrate. DETAILED DESCRIPTION

[0061] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0062] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0063] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0064] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0065] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0066] The present application embodiment provides a method for removing silicon substrate from a chip based on C2W bonding. Figures 1 to 13 Describe in detail.

[0067] In one embodiment, the method comprises:

[0068] Step S101, forming a waveguide core 3 on a substrate, and depositing a first passivation layer, wherein the first passivation layer covers the substrate and the waveguide core 3;

[0069] Step S102, forming metal grooves 4 on both sides of the waveguide core 3, and forming metal electrodes 5 in the metal grooves 4;

[0070] Step S103, depositing a second passivation layer, wherein the second passivation layer covers the metal electrode 5 and the first passivation layer;

[0071] Step S104, opening a hole above the metal electrode 5 to form a hole structure 6;

[0072] Step S105, forming a protective layer 7 in a region above the second passivation layer corresponding to the metal electrode 5, wherein the protective layer 7 covers the metal electrode 5 through the hole structure 6;

[0073] Step S106, bonding the region above the second passivation layer corresponding to the waveguide core 3 to the chip, wherein a silicon substrate 10 is provided on a side of the chip away from the bonding region;

[0074] Step S107, removing the silicon substrate 10 in the chip after bonding;

[0075] Step S108, removing the protective layer 7.

[0076] In this embodiment, for the removal of the silicon substrate 10, a method is proposed in which a protective layer 7 is first formed before C2W bonding, and then the silicon substrate 10 is removed. In the method of this embodiment, there is no step on the wafer before bonding, and the glue is evenly spread by a glue spreader, so that the glue layer (protective layer 7) is uniform and there will be no bubbles or other undesirable phenomena; in addition, there is no need to use a glue sprayer, which improves the utilization rate of the photoresist and reduces the cost of device preparation. On the other hand, there is no step on the wafer before bonding, and only one photolithography is required, which shortens the time and reduces the cost, and there is no need to consider the impact of the overlay accuracy on the product; in addition, there is no need to use a double-sided exposure machine, which reduces the cost.

[0077] In a specific implementation, a waveguide core 3 is formed on a substrate, wherein the substrate is set as a wafer substrate 1 .

[0078] In one embodiment, referring to Figure 2 and Figure 3 , the forming of the waveguide core 3 on the substrate comprises:

[0079] depositing a waveguide layer 2 on the substrate;

[0080] The waveguide layer 2 is etched to form the waveguide core 3 .

[0081] In specific implementation, the waveguide layer 2 can be set as a SiN layer. The silicon photonics technology of silicon nitride (SiN) material has many individual advantages such as low loss, wide spectrum, and high optical power. Specifically, SiN has a wide transparent spectrum range from ultraviolet to mid-infrared, which makes it very suitable for optical communication systems of different wavelengths; in the bands commonly used in optical communications (such as 1.3μm and 1.55μm), SiN waveguides can achieve lower propagation losses, which is crucial for maintaining signal strength and reducing noise; SiN materials exhibit higher nonlinear optical effects and can respond more effectively to small changes in electrical signals, thereby improving modulation efficiency and supporting high-speed data transmission; SiN deposition and other processing steps can be well integrated into the existing complementary metal oxide semiconductor (CMOS) microelectronics manufacturing process, facilitating large-scale production and integrated design.

[0082] Furthermore, the thickness of the waveguide layer 2 can be set to 50-800 nm. Etching is performed on the waveguide layer 2 to form a plurality of waveguide cores 3 .

[0083] In a specific implementation, the step of depositing the first passivation layer includes:

[0084] Depositing a first passivation layer to a first preset thickness, and performing chemical mechanical polishing (CMP) on the first passivation layer to reduce the first preset thickness to a second preset thickness. The structure after chemical mechanical polishing is referred to Figure 4 , a first passivation layer is formed on the waveguide core 3.

[0085] Specifically, the first passivation layer may be a silicon oxide layer 9. The second preset thickness may be 50-200 nm, where the thickness refers to the thickness of the passivation layer above the waveguide core 3. The first preset thickness may be adjusted according to specific process requirements.

[0086] Further, see Figure 5 , the metal grooves 4 are respectively formed on both sides of the waveguide core 3, including:

[0087] Metal grooves 4 are formed on both sides of the waveguide core 3 by etching, and the bottom of the metal grooves 4 extends into the interior of the substrate. Preferably, the metal grooves 4 can be set to a square structure, and the width of the metal grooves 4 is set to 20-300 μm.

[0088] In one embodiment, referring to Figure 6 and Figure 7 The step of forming a metal electrode 5 in the metal groove 4 comprises:

[0089] Deposit metal, the metal covers the first passivation layer and the metal groove 4, the structure after metal deposition is as shown in FIG. Figure 6 As shown;

[0090] The metal on the first passivation layer is etched, and the metal in the metal groove 4 forms the metal electrode 5 .

[0091] In the specific implementation, the metal is deposited on the entire surface, so the metal groove 4 and the upper surface of the first passivation layer will be covered with metal. The thickness of the deposited metal can be set to 0.5-1.5μm. The metal on the first passivation layer needs to be removed, and only the metal in the metal groove 4 is retained to form the metal electrode 5. The metal on the first passivation layer can be removed by etching process, and the structure formed is as shown in FIG. Figure 7 shown. Figure 7 The waveguide core 3 and the metal electrode 5 are arranged at intervals, but the arrangement of the waveguide core 3 and the metal electrode 5 is not limited to that shown in the figure.

[0092] Furthermore, the second passivation layer may be a silicon oxide layer 9. The step of depositing the second passivation layer includes:

[0093] The second passivation layer is deposited to a third preset thickness, and the second passivation layer is subjected to chemical mechanical polishing (CMP) to reduce the third preset thickness to a fourth preset thickness. The structure after chemical mechanical polishing is referred to Figure 8 , a passivation layer is formed on the waveguide core 3.

[0094] Specifically, the fourth preset thickness can be set to 50-200 nm, where the thickness refers to the total thickness of the first passivation layer and the second passivation layer above the waveguide core 3. If the thickness is less than 50 nm, the bonding power will decrease; if the thickness is greater than 200 nm, the electro-optical material will not be able to modulate the waveguide core 3.

[0095] In one embodiment, referring to Fig. 9 For the hole structure 6 formed by opening a hole above the metal electrode 5, the hole structure 6 penetrates the passivation layer above the metal electrode 5 to expose the metal electrode 5. The shape of the hole structure 6 can be set to be a square or a rectangle, and the size of the hole structure 6 ranges from 60 to 100 μm, that is, the side length of the square or the square is set to be 60 to 100 μm. When opening the hole, the hole can be opened above part of the metal electrode 5 to facilitate subsequent packaging lead bonding.

[0096] In one embodiment, the protective layer 7 can be set as a photoresist or bonding glue, etc., and a deposition etching or stripping process can be used. Generally, a thicker protective glue is required to ensure that the protective glue is not completely consumed during the etching process to protect the metal electrode 5 that has been opened in the PIC wafer. Therefore, the thickness of the protective glue is related to the thickness of the silicon substrate 10 that needs to be removed, and the thickness is generally set to 5-100μm.

[0097] In a specific implementation, after forming the entire protective layer 7, the area corresponding to the waveguide core 3 needs to be exposed, and an area for bonding is reserved, that is, the area corresponding to the waveguide core 3 is not provided with the protective layer 7, and the entire protective layer 7 can be etched by a photolithography process to remove the protective layer 7 above the area corresponding to the waveguide core 3. Fig.10 The structure shown in the figure can then be directly bonded. Therefore, before bonding, there is no step on the wafer, and only one photolithography is required, which shortens the time and reduces the cost, and there is no need to consider the impact of overlay accuracy on the product. In addition, there is no need to use a double-sided exposure machine, which reduces costs.

[0098] In one embodiment, referring to Fig.11 , bonding the area above the second passivation layer corresponding to the waveguide core 3 to the chip, comprising:

[0099] The area above the second passivation layer corresponding to the waveguide core 3 and the chip are sequentially cleaned and plasma activated;

[0100] Pre-bonding the area above the second passivation layer corresponding to the waveguide core 3 and the chip at room temperature to form a pre-bonded device;

[0101] The pre-bonded device is annealed at 50-120° C. for 6-12 hours to complete the bonding.

[0102] In specific implementation, the size of the chip in C2W bonding is 1mm*1mm-12mm*12mm. Before bonding, both the chip and the wafer need to be cleaned and plasma activated, then pre-bonded at room temperature and annealed at 50-120°C for 6-12h.

[0103] In one embodiment, the chip further includes an electro-optic material layer 8 and a silicon oxide layer 9 , the electro-optic material layer 8 is bonded to a region above the second passivation layer corresponding to the waveguide core 3 , and the silicon oxide layer 9 is located between the electro-optic material layer 8 and the silicon substrate 10 .

[0104] In specific implementation, the electro-optical material can be set to lithium niobate material with a thickness of 300-400 nm, the thickness of silicon oxide can be set to 0.5-2 μm, and the thickness of the silicon substrate 10 is 500-675 μm.

[0105] In one embodiment, referring to Fig.12 , the removing of the silicon substrate 10 in the chip comprises:

[0106] The silicon substrate 10 in the chip is removed by a wet etching or dry etching process.

[0107] In specific implementation, the wet etching may be performed using chemical liquid (such as KOH, TMAH, etc.), and the dry etching may be performed using, for example, xenon fluoride.

[0108] Furthermore, in order to protect the metal electrode 5 during the process of removing the silicon substrate 10 by wet etching or dry etching, the thickness of the protection layer 7 must ensure that the metal electrode 5 is not damaged. Therefore, the thickness of the protection layer 7 is set to 50-100 μm.

[0109] In one embodiment, removing the silicon substrate 10 in the chip includes:

[0110] Grinding the silicon substrate 10 in the chip to reduce the thickness of the silicon substrate 10 to 20-40 μm;

[0111] The ground silicon substrate 10 is removed by wet etching or dry etching.

[0112] In this embodiment, a grinding process is first used to remove a portion of the thickness of the silicon substrate 10, and then wet etching or dry etching is performed, which can reduce the thickness of the protective layer 7, reduce the wet and dry etching time, and reduce the wet and dry material costs. In addition, the probability of a micro-pyramid structure appearing during wet etching due to anisotropic etching, thereby significantly reducing the etching rate, can be reduced.

[0113] Furthermore, the thickness of the protective layer 7 is 5-10 μm. Since a portion of the silicon substrate 10 is removed during the grinding process, the thickness of the silicon substrate 10 to be etched or corroded is reduced, so the thickness of the protective layer 7 can be reduced accordingly.

[0114] In one embodiment, removing the silicon substrate 10 in the chip includes:

[0115] Dry-etching the silicon substrate 10 in the chip until the thickness of the silicon substrate 10 is 5-20 μm;

[0116] The remaining silicon substrate 10 is removed by a wet etching process.

[0117] Regarding the removal of the silicon substrate 10, since only dry etching is used, the surface morphology of the silicon oxide under the silicon is poor, which has an impact on the three layers of the electro-optical material modulation waveguide core; and when only wet etching is used, during the etching process, TMAH and KOH etch silicon anisotropically, and micro-pyramid structures are likely to appear during the etching process, which will greatly reduce the etching rate. Therefore, in this embodiment, a portion of the silicon substrate 10 is first dry-etched, and then wet etching is used to remove the remaining silicon substrate 10. The method of this embodiment can improve the surface morphology of silicon oxide after dry etching alone and reduce the time required for wet etching alone.

[0118] In one embodiment, the thickness of the protective layer 7 is 5-100 μm. The thickness of the protective layer 7 is related to the selected method for removing the silicon substrate 10 , and the thickness of the protective layer 7 can be adjusted according to the specific method for removing the silicon substrate 10 .

[0119] In one embodiment, referring to Fig.13 , the removing of the protective layer 7 comprises:

[0120] The protective layer 7 is removed by soaking in a chemical liquid, wherein the chemical liquid is N-methylpyrrolidone or acetone.

[0121] In one embodiment, since the processing of the protective layer 7 is complicated, and the protective layer 7 is generally made of photoresist or bonding glue, if the wet etching time is too long, TMAH / KOH may penetrate, so a method of first bonding and then opening a hole above the metal electrode 5 can be adopted. Specifically, it includes:

[0122] After depositing the second passivation layer, Figure 8 On the basis of the above, a hole is not opened above part of the metal electrode 5, but the passivation layer (silicon oxide layer 9) above the metal electrode 5 is used as a mask to directly bond the area corresponding to the waveguide core 3 on the second passivation layer to the chip (C2W bonding). The structure after bonding is as shown in FIG. Fig.14 Before bonding, both the chip and wafer are cleaned and plasma activated, then pre-bonded at room temperature and annealed at 50-300°C for 1-12 hours to complete the entire bonding process;

[0123] Since there is no protective layer 7 in this embodiment, the silicon substrate 10 can be directly removed by wet etching using chemical liquid (such as KOH, TMAH, etc.), or by dry etching to remove the silicon substrate 10. The structure after removing the silicon substrate 10 is as follows: Fig.15 As shown;

[0124] Then, a hole is opened above a portion of the metal electrode 5, and the size of the hole is 60-100 μm to facilitate subsequent packaging lead bonding. The structure after the hole is opened is as follows: Fig.13 shown.

[0125] In this embodiment, since no hole is opened above the metal electrode 5 before bonding, the protective layer 7 is not required when removing the silicon substrate 10, thereby reducing the process steps. In addition, the silicon oxide above the metal electrode 5 has a better ability to resist TMAH / KOH.

[0126] The embodiment provided by the present invention can solve the problem of complicated processing of the protective layer 7 through two methods. The first method is to form the protective layer 7 before C2W bonding. There is no step on the wafer before bonding. The glue is evenly spread by a glue spreader, and the glue layer is uniform without bubbles and other undesirable phenomena. In addition, there is no need to use a glue sprayer, which improves the utilization rate of the photoresist and reduces the cost. On the other hand, there is no step on the wafer before bonding, and only one photolithography is required, which shortens the time, reduces the cost, and does not need to consider the impact of the overlay accuracy on the product. In addition, there is no need to use a double-sided exposure machine, which reduces the cost. The second method is to open a hole above the metal electrode 5 after C2W bonding. Through this method, when removing the silicon substrate 10, there is no need to use the protective layer 7, which reduces the process steps; and the silicon oxide above the metal electrode 5 has better resistance to TMAH / KOH.

[0127] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for removing silicon substrate from a chip based on C2W bonding, characterized in that: The method comprises: forming a waveguide core on a substrate and depositing a first passivation layer, wherein the first passivation layer covers the substrate and the waveguide core; Forming metal grooves on both sides of the waveguide core respectively, and forming metal electrodes in the metal grooves; Depositing a second passivation layer, wherein the second passivation layer covers the metal electrode and the first passivation layer; Opening a hole above the metal electrode to form a hole structure; forming a protective layer in a region above the second passivation layer corresponding to the metal electrode, wherein the protective layer covers the metal electrode through the hole structure; Bonding a region above the second passivation layer corresponding to the waveguide core to a chip, wherein a silicon substrate is provided on a side of the chip away from the bonding region; removing the silicon substrate in the chip after bonding; The protective layer is removed.

2. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that: The step of forming a waveguide core on a substrate comprises: depositing a waveguide layer on the substrate; The waveguide layer is etched to form the waveguide core.

3. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that: The forming of the metal electrode in the metal groove comprises: Depositing metal, wherein the metal covers the first passivation layer and the metal groove; The metal on the first passivation layer is etched, and the metal in the metal groove forms the metal electrode.

4. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that: The step of bonding the area above the second passivation layer corresponding to the waveguide core to the chip comprises: Sequentially cleaning and plasma activating the area above the second passivation layer corresponding to the waveguide core and the chip; Pre-bonding the region above the second passivation layer corresponding to the waveguide core and the chip at room temperature to form a pre-bonded device; The pre-bonded device is annealed at 50-120° C. for 6-12 hours to complete the bonding.

5. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that: The removing of the silicon substrate in the chip comprises: The silicon substrate in the chip is removed by a wet etching or dry etching process.

6. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that: The removing of the silicon substrate in the chip comprises: Grinding the silicon substrate in the chip to reduce the thickness of the silicon substrate to 20-40 μm; The ground silicon substrate is removed by wet etching or dry etching.

7. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that: The removing of the silicon substrate in the chip comprises: Dry etching the silicon substrate in the chip until the thickness of the silicon substrate is 5-20 μm; The remaining silicon substrate is removed by a wet etching process.

8. The method for removing silicon substrate from a chip based on C2W bonding according to any one of claims 5 to 7, characterized in that: The thickness of the protective layer is 5-100 μm.

9. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that: The removing of the protective layer comprises: The protective layer is removed by soaking in a chemical liquid, wherein the chemical liquid is N-methylpyrrolidone or acetone.

10. The method for removing silicon substrate from a chip based on C2W bonding according to claim 1, characterized in that: The chip further comprises an electro-optic material layer and a silicon oxide layer. The electro-optic material layer is bonded to a region above the second passivation layer corresponding to the waveguide core, and the silicon oxide layer is located between the electro-optic material layer and the silicon substrate.

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