Power supply network design method and related equipment

Abstract

The invention relates to the technical field of chips, and discloses a power supply network design method and related equipment, and the method comprises the steps: obtaining a design rule and a constraint rule of power supply network design in an integrated circuit; identifying a plurality of voltage domains in the integrated circuit and a plurality of power distribution networks corresponding to the voltage domains, wherein the voltage domains correspond to different voltage values; according to the design rule, generating a metal shape of top-layer metal corresponding to each power distribution network and a metal shape of bottom-layer metal corresponding to each power distribution network; and according to the metal shape of the top-layer metal corresponding to each power distribution network, the metal shape of the bottom-layer metal corresponding to each power distribution network, the design rule and the constraint rule, establishing power connection between the top-layer metal corresponding to each power distribution network and the bottom-layer metal corresponding to each power distribution network. According to the technical scheme provided by the embodiment of the invention, the wiring quality of the power supply network and the performance and stability of a chip can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and more specifically, to a power supply network design method and related equipment. Background Art

[0002] In the Fin-Field-Effect-Transistor (FinFET) process system, the constraints faced by power network design have shown a significant increase compared to traditional processes. Under traditional processes, the design of the power network can be achieved with only a single rule, such as the minimum area of ​​the metal wire. However, the FinFET process has introduced advanced technologies such as multiple masks and FinTrack, making the factors that need to be considered in the power network design extremely complicated.

[0003] If such complex constraints are to be judged one by one, it will inevitably bring a heavy computational burden to the algorithm, causing the amount of calculation to increase exponentially. This will not only consume a lot of computing time, but also occupy a large amount of computing resources, greatly limiting the practical application effectiveness and efficiency improvement of the power network routing algorithm. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, the present application proposes a power network design method, comprising: Obtain design rules and constraints for power network design in integrated circuits; Identify multiple voltage domains in the integrated circuit and multiple power distribution networks corresponding to each of the voltage domains, each of the voltage domains corresponding to a different voltage value; Generate a metal shape of a top metal layer and a metal shape of a bottom metal layer corresponding to each power distribution network according to the design rule; According to the metal shape of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks, the design rules and the constraint rules, a power connection is established between the top metal and the corresponding bottom metal corresponding to each of the power distribution networks to design a power network corresponding to each of the voltage domains.

[0006] In a feasible implementation manner, according to the design rules, the metal shape of the top metal and the metal shape of the corresponding bottom metal corresponding to each of the power distribution networks are generated, including: determining the size and position of the metal shape of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks according to the power network design parameters in the design rules; determining the direction of the metal shape of the top metal corresponding to each of the power distribution networks according to the wiring direction of the layer where the top metal corresponding to each of the power distribution networks is located; determining the direction of the metal shape of the bottom metal corresponding to each of the power distribution networks according to the wiring direction of the layer where the bottom metal corresponding to each of the power distribution networks is located; generating the metal shape of the top metal corresponding to each of the power distribution networks according to the determined size, position and direction of the metal shape of the top metal corresponding to each of the power distribution networks; generating the metal shape of the bottom metal corresponding to each of the power distribution networks according to the determined size, position and direction of the metal shape of the bottom metal corresponding to each of the power distribution networks.

[0007] In a feasible implementation, the method further includes: when the power network design parameters do not include a length parameter, if the wiring direction is a horizontal direction, determining that the lengths of the metal shapes of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks are both the longest lengths in the horizontal direction; if the wiring direction is a vertical direction, determining that the lengths of the metal shapes of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks are both the longest lengths in the vertical direction.

[0008] In a feasible implementation, the method further includes: if the process of the integrated circuit is the first process, then after establishing a power connection between the top metal corresponding to each of the power distribution networks and the corresponding bottom metal, continuing to establish a power connection between the bottom metal and the metal layer where the circuit functional unit is located; if the process of the integrated circuit is the second process, then after establishing a power connection between the top metal corresponding to each of the power distribution networks and the corresponding bottom metal, continuing to establish a power connection between the bottom metal and the bottom metal, so as to realize the power connection through the bottom metal and the metal layer where the circuit functional unit is located.

[0009] In a feasible implementation manner, according to the metal shape of the top metal and the metal shape of the corresponding bottom metal corresponding to each power distribution network, the design rules and the constraint rules, a power connection is established between the top metal and the corresponding bottom metal corresponding to each power distribution network, including: if the top metal and the corresponding bottom metal corresponding to each power distribution network are adjacent metal layers, then according to the metal shape of the top metal and the metal shape of the bottom metal, and the through-hole design parameters in the design rules, a plurality of first through-holes are generated to establish a power connection between the top metal and the bottom metal through the plurality of first through-holes; if the top metal and the corresponding bottom metal corresponding to each power distribution network are non-adjacent metal layers, then according to the metal shape of the top metal and the metal shape of the bottom metal, and the minimum area constraint in the constraint rules, the metal shape of the intermediate layer metal is generated layer by layer between the top metal and the bottom metal; according to the through-hole design parameters, a plurality of second through-holes are generated between the adjacent layers of the top metal, the intermediate layer metal and the bottom metal, to establish a power connection between the top metal and the bottom metal through the metal shape of the intermediate layer metal and the plurality of second through-holes between the adjacent layers.

[0010] In a feasible implementation, based on the metal shape of the top metal and the metal shape of the bottom metal, and the minimum area constraint in the constraint rule, the metal shape of the intermediate metal is generated layer by layer between the top metal and the bottom metal, including: determining the area of ​​the metal shape of the intermediate metal based on the projection of the metal shape of the top metal and the metal shape of the bottom metal on the intermediate metal; if the determined area of ​​the metal shape of the intermediate metal is smaller than the minimum area constraint, filling the metal shape of the intermediate metal to generate a new metal shape of the intermediate metal.

[0011] In a feasible embodiment, the method also includes: performing violation prediction on the surrounding area of ​​the new metal shape of the intermediate layer metal to obtain a prediction result, and the prediction result is used to indicate the probability of a violation; if the prediction result exceeds a preset threshold, the preliminary wiring evaluation index of the logic point corresponding to the surrounding area is updated to obtain a new wiring evaluation index, and the new wiring evaluation index is used to guide the adjustment of the violation.

[0012] In a feasible implementation manner, according to the through-hole design parameters, a plurality of second through-holes are generated between the adjacent layers of the top metal, the middle metal, and the bottom metal, including: determining the border of the through-hole array between the adjacent layers according to the area requirements of the upper metal in the adjacent layers of the top metal, the middle metal, and the bottom metal and the through-hole design parameters; deleting the outermost portion of the border of the through-hole array that exceeds the enclosing range of the lower metal according to the size of the lower metal in the adjacent layers to obtain a new border of the through-hole array; determining the unit spacing of the through-hole array in the longitudinal and transverse directions according to the through-hole design parameters, and generating the through-hole array according to the new border of the through-hole array and the unit spacing of the through-hole array, wherein the through-hole array includes the plurality of second through-holes.

[0013] In a feasible implementation, the method also includes: if the target design parameters in the design rules do not match the target requirement parameters of the process of the integrated circuit, determining the greatest common factor or greatest common multiple of the target design parameters and the target requirement parameters; adjusting the target design parameters according to the greatest common factor or the greatest common multiple to obtain new design parameters.

[0014] In a feasible implementation, the method further includes: calculating the voltage drop of each power distribution network based on the resistance value of each power distribution network corresponding to the target voltage domain and the current value of each power distribution network under the maximum load state; if the voltage drop of the target power distribution network in each power distribution network is less than the voltage value of the target voltage domain, determining that the area corresponding to the target power distribution network is an area with insufficient power supply; if the voltage drop of the target power distribution network is greater than the voltage value of the target voltage domain, determining the target path in the target power distribution network, inserting a power supply filter element in the target path to reduce the voltage drop of the target path, and the voltage drop of the target path is greater than a preset voltage threshold.

[0015] In a feasible implementation, the method further includes: parsing the unified power format file in the constraint rules to obtain a parsed file; determining the position where the power control element needs to be inserted and the position where the power isolation element needs to be inserted according to the positioning information in the parsed file; inserting the power control element at the position where the power control element needs to be inserted, and inserting the power isolation element at the position where the power isolation element needs to be inserted according to the insertion information in the parsed file, the power control element is used to control the on and off of the power supply, and the power isolation element is used to isolate the power supply networks corresponding to each of the voltage domains.

[0016] In a second aspect, the present application proposes a power network design device, comprising: An acquisition unit configured to acquire design rules and constraint rules for power network design in an integrated circuit; an identification unit configured to identify a plurality of voltage domains in the integrated circuit and a plurality of power distribution networks corresponding to each of the voltage domains, each of the voltage domains corresponding to a different voltage value; A generating unit configured to generate a metal shape of a top metal and a metal shape of a corresponding bottom metal of each power distribution network according to the design rule; The connection unit is configured to establish a power connection between the top metal and the corresponding bottom metal corresponding to each power distribution network according to the metal shape of the top metal and the corresponding bottom metal corresponding to each power distribution network, the design rules and the constraint rules, so as to design a power network corresponding to each voltage domain.

[0017] In a third aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to implement the steps of the power supply network design method of any one of the first aspects described above when executing the computer program stored in the memory.

[0018] In a fourth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the power supply network design method of any one of the first aspects is implemented.

[0019] In a fifth aspect, the present application further proposes a chip, wherein the chip at least includes a power supply network designed by any power supply network design method of the first aspect.

[0020] In summary, the power network design method proposed in this application, by acquiring design rules and constraint rules, constructs a systematic design process from identifying voltage domains and power distribution networks to generating top and bottom metal shapes and finally establishing power connections, which can adapt to complex voltage domain situations. The design rules and constraint rules are fully considered throughout the design process, avoiding the limitations of the traditional single rule design method and effectively solving the problem of increasing constraints. By following the rules for precise design at each key step, a large number of invalid calculation attempts caused by blind design are avoided, the quality of power network wiring is effectively improved, and chip performance and stability are enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present specification. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings: Figure 1 A schematic diagram of the structure of a traditional power supply network.

[0022] Figure 2 A schematic flow chart of a power supply network design method provided in an embodiment of the present application.

[0023] Figure 3 A schematic flow chart of a power supply network design method provided in an embodiment of the present application.

[0024] Figure 4 A schematic flow chart of a power supply network design method provided in an embodiment of the present application.

[0025] Figure 5 A schematic flow chart of a power supply network design method provided in an embodiment of the present application.

[0026] Figure 6 A schematic diagram of the structure of a power network design device provided in an embodiment of the present application.

[0027] Figure 7 A schematic diagram of the structure of an electronic device for power network design provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0029] Before further describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0030] 1. FinFET FinFET is an advanced semiconductor process technology. It uses a fin-shaped three-dimensional transistor structure, and current can flow in three directions. Compared with traditional planar transistors, it increases the surface area of ​​the transistor and improves the gate's control over the channel. It can effectively improve the performance of integrated circuits, reduce power consumption and reduce size, and is widely used in high-performance chip manufacturing.

[0031] 2. Plane technology Planar technology is a traditional integrated circuit manufacturing process, in which transistors and other components are built on a two-dimensional plane and have a relatively simple structure. Compared with FinFET technology, planar technology has fewer metal layers and lower transistor integration, but it is still used in some cost-sensitive or low-performance fields.

[0032] 3. Power network The power network is a network system that introduces power from the outside of an integrated circuit and distributes it to various functional modules and components. It consists of power pins, buses, rails, decoupling capacitors and voltage regulators. Its main function is to provide stable and reliable power supply and reduce power supply noise. Factors such as current carrying capacity, noise suppression and electromagnetic compatibility must be considered during design.

[0033] 4. Source / Destination Network In integrated circuits, the source network refers to the network that connects the positive pole of the power supply (usually represented by VDD) to each component and module that needs power; the ground network is the network that connects the negative pole of the power supply (usually represented by VSS) to each component and module. The source / ground network is an important part of the power distribution network. They provide operating voltage for transistors, logic gates and other components in the chip, form a current loop, and ensure the normal operation of the chip. At the same time, the design of the source / ground network is of great significance for reducing power noise and improving the stability and reliability of the chip.

[0034] 5. Metal layer It is an important component of the integrated circuit manufacturing process and is usually made of metal materials (such as aluminum, copper, etc.). The metal layer is used to connect the various components and functional modules in the chip to form electrical interconnections. In chip manufacturing, multiple metal layers are stacked together, and the connection between layers is achieved through structures such as through holes. Different metal layers have different functions in the chip, such as power transmission, signal transmission, etc. The design and layout of the metal layer needs to consider factors such as wiring density, signal integrity, and electromagnetic interference to ensure the high performance and reliability of the chip.

[0035] 6. Through hole In integrated circuit manufacturing, a through-hole is a conductive channel that vertically penetrates multiple metal layers or insulating layers. It is usually made by forming holes in the insulating layer through processes such as photolithography and etching, and then filling them with conductive materials such as metal (such as copper). The main function of a through-hole is to achieve electrical connection between different metal layers, so that signals or power can be transmitted in a multi-layer structure, thereby effectively connecting various components and functional modules inside the chip in three-dimensional space. It is one of the key structures for building a complex integrated circuit interconnection network.

[0036] 7. DRC DRC, or Design Rule Check, is an important part of the integrated circuit design process. It uses specialized software tools to conduct a comprehensive check of the integrated circuit layout based on the design rules specified by the semiconductor manufacturing process. These rules cover multiple aspects such as geometric dimensions, spacing, and the relationship between layers, such as minimum line width, minimum spacing, and metal layer coverage requirements. The purpose of DRC is to ensure that the designed layout can be correctly manufactured under given process conditions, to avoid chip manufacturing failure or performance degradation due to design not meeting process requirements, and is an important means to ensure the manufacturability and reliability of integrated circuit design.

[0037] Based on the above description, please refer to Figure 1 , Figure 1 A schematic diagram of the structure of a traditional power supply network. Figure 1 The power network shown includes: top metal power line ①, top metal ground line ②, middle metal power line ③, middle metal ground line ④, bottom metal ground line ⑤, bottom metal power line ⑥, and metal layer through hole ⑦. The power line and ground line are generally wired alternately.

[0038] The top metal power line ① is responsible for receiving power from an external power source and transmitting it to the entire power network, providing power support for each circuit module in the chip. It is like the "main road" of the power network, carrying a large amount of current. The top metal ground line ② provides a zero potential reference point for the circuit, forming a current loop, which not only stabilizes the circuit potential and reduces signal interference, but also acts as an electrostatic discharge path to protect the chip from electrostatic damage. The middle-layer metal power line ③ and the middle-layer metal ground line ④ are powerful supplements to the top-layer line. The middle-layer metal power line ③ can distribute power to the circuit modules in a specific area more accurately, and is especially suitable for modules with local high power consumption in complex chip layouts, providing more direct power supply. The middle-layer metal ground line ④ assists the top-layer ground line to provide a more stable potential reference for the local circuit, further reduce the ground impedance, and reduce the voltage fluctuation on the ground line. The wiring of the top and middle layers, and the wiring of the middle and bottom layers are all arranged in a cross pattern, which greatly improves the wiring flexibility and can provide connection points for circuit modules from different directions to adapt to complex circuit layouts; at the same time, the cross wiring can make the distance between the power line and the ground line more uniform, which helps to reduce electromagnetic interference, optimize power distribution, and ensure that circuit modules at all levels can obtain a stable power supply. The bottom metal ground wire ⑤ serves as the basic grounding layer of the entire power network, providing a large ground plane, effectively reducing the grounding resistance, and also shielding and isolating external electromagnetic interference, reducing the impact of external interference on the internal circuit of the chip. The bottom metal power line ⑥ assists the middle and top power lines to further optimize power distribution and provide power for the circuit modules at the bottom or specific locations. The metal layer vias⑦ are the key channels that connect the power lines and ground lines of different metal layers, allowing the power to be smoothly transmitted between the top layer, the middle layer and the bottom layer, ensuring that the circuit modules of each layer can establish a reliable electrical connection with the power network. During the current transmission process, the vias can also balance the current distribution, guide the current to be evenly distributed between the layers, and avoid problems such as overheating due to excessive current in certain areas. In addition, the appropriate via layout helps to improve electromagnetic compatibility and reduce the intensity of electromagnetic interference.

[0039] It should be noted that Figure 1 Only three layers of power supply network are shown in FIG. Figure 1 The illustration does not constitute a limitation on the number of power network layers.

[0040] Figure 2 FIG. 1 is a flow chart showing a power supply network design method according to an embodiment of the present application. Figure 2 As shown, the power network design method includes: Step S210, obtaining design rules and constraint rules for power network design in an integrated circuit; Step S220, identifying multiple voltage domains in the integrated circuit and multiple power distribution networks corresponding to each voltage domain, each voltage domain corresponding to a different voltage value; Step S230, generating a metal shape of a top metal and a metal shape of a bottom metal corresponding to each power distribution network according to the design rules; Step S240, according to the metal shape of the top metal and the corresponding bottom metal of each power distribution network, design rules and constraint rules, establish a power connection between the top metal and the corresponding bottom metal of each power distribution network to design a power network corresponding to each voltage domain.

[0041] These steps are described in detail below.

[0042] In step S210, design rules and constraint rules for power network design in an integrated circuit are obtained.

[0043] In integrated circuit design, the design rules and constraints of power network design are the core basis for ensuring the reliability and functionality of the power supply system. These rules guide the physical implementation and electrical performance optimization of the power network through multi-dimensional definitions and constraints.

[0044] Design rules are mainly defined by users through parameter settings, covering the basic physical properties of the power network. Design rules include geometric parameters such as the width (Width), pitch (Pitch), and displacement (Offset) of the power network, voltage domain names, voltage values, voltage switches, source / ground network names, and metal layer connection rules for standard cell pins, which also fall within the scope of design rules. These rules can be entered through the user interface or configuration file during the layout planning stage.

[0045] Constraint rules are mainly obtained from the TechDatabase and Unified PowerFormat (UPF) files. These rules together reflect the limitations of manufacturing processes and electrical performance. TechDatabase contains process parameters for Design Rule Check (DRC), such as Via Generation Rules, Metal Enclosure Rules, etc. These rules ensure the manufacturing feasibility of metal lines and vias. For example, the minimum area of ​​metal lines in the FinFET process must meet both planar and 3D constraints (such as edge length, continuous edge length), and the top metal enclosure and bottom metal enclosure sizes of the via must meet cross-layer DRC requirements to prevent short circuits or open circuits during the manufacturing process. In addition, TechDatabase also contains resistance and capacitance data for metal layers and via layers, which are critical to electrical performance simulation. Low-power voltage constraint rules can be obtained from UPF files.

[0046] In step S220 , multiple voltage domains in the integrated circuit and multiple power distribution networks corresponding to each voltage domain are identified, each voltage domain corresponding to a different voltage value.

[0047] In integrated circuit design, voltage domain refers to independent areas with the same power supply voltage in the chip. Since different functional modules in the chip (such as digital circuits, analog circuits, input and output interfaces, etc.) have different voltage requirements (for example, core logic usually uses low voltage to reduce power consumption, while I / O interfaces require higher voltage to ensure signal integrity), it is necessary to divide multiple voltage domains, each of which corresponds to a different voltage value, and each voltage domain corresponds to an independent power supply network. Its core goal is to provide stable voltage for circuits in specific areas and meet the current transmission requirements of different modules through differentiated design.

[0048] Identifying multiple voltage domains in an integrated circuit can be done by parsing design rules and constraint rules. As mentioned earlier, the design rules clearly include key information such as voltage domain name, voltage value, voltage switch, etc., while the UPF file in the constraint rules further defines the boundaries and interaction methods of each voltage domain through low power constraints. For example, when the design includes dynamic voltage frequency adjustment function, the voltage domains corresponding to different working modes will be clearly marked.

[0049] Each voltage domain contains multiple power distribution networks, namely source / ground networks, which work together to form a complete current transmission path. During the design and manufacturing process, integrated circuit design rules must be strictly followed, such as the design rule check (DRC) requirements for metal line width, spacing, and via layout to avoid problems such as short circuits and open circuits. In addition, the source / ground networks of different voltage domains need to be designed according to the characteristics of the voltage domain. For example, a high voltage domain may use a thicker metal layer due to its large current demand; a low voltage domain may use a denser via layout to reduce resistance.

[0050] In step S230, a metal shape of a top metal layer and a metal shape of a bottom metal layer corresponding to each power distribution network are generated according to the design rules.

[0051] In integrated circuit design, in order to build a stable and efficient power network, the metal shape of the top metal and the metal shape of the bottom metal corresponding to the source / ground network can be accurately generated. The chip is divided into multiple different voltage domains, each of which has its own unique power supply requirements and working characteristics.

[0052] In each voltage domain, there are many source / ground networks. The source network is responsible for providing positive voltage to the circuit module, while the ground network serves as a return path for the reference potential. Together, the two form a power distribution network. To ensure that these networks can transmit current normally and efficiently, corresponding metal shapes need to be generated for them.

[0053] For the top metal, it plays an important role in carrying large currents in current transmission. The metal shape of the top metal can be determined according to the design rules. For example, if a source network needs to transmit a large current, the top metal line will be designed to be relatively wide in order to reduce resistance. At the same time, in order to achieve uniform distribution of current, the top metal can be designed into a grid or a structure similar to a tree trunk branch. The main line is responsible for transmitting the main current, and the branch line accurately guides the current to each power module to ensure that the circuit modules in the entire voltage domain can obtain stable power supply.

[0054] The bottom metal is also critical. It usually focuses on powering low current areas and serves as an important path for signal return. The metal shape of the bottom metal can be a checkerboard or parallel line shape. On the one hand, this structure can make full use of the space, and on the other hand, it is orthogonal to the top metal, which can effectively reduce electromagnetic interference and ensure the stability of signal transmission.

[0055] In step S240, based on the metal shape of the top metal and the corresponding bottom metal of each power distribution network, design rules and constraint rules, a power connection is established between the top metal and the corresponding bottom metal of each power distribution network to design a power network corresponding to each voltage domain.

[0056] Establishing power connections between the top metal and the bottom metal is a key step in designing a power network. This process needs to be carried out under the premise of meeting the design rules and constraint rules. Design rules play an extremely critical guiding role in this process. It is mainly defined directly by users through parameter settings based on actual needs. Constraint rules are mainly obtained from TechDatabase and UPF files.

[0057] After generating the metal shape of the top metal and the bottom metal corresponding to each source / ground network, you can then establish a power connection between the top metal and the bottom metal corresponding to each power distribution network according to the metal shape, design rules and constraint rules, that is, establish a power connection between the top metal and the bottom metal corresponding to each source network, and establish a power connection between the top metal and the bottom metal corresponding to each ground network. When establishing the connection, the location and method of the connection must be determined strictly according to the design rules, while meeting the requirements of the constraint rules for manufacturing process and electrical performance. For example, according to the through-hole generation rules, through-holes that meet the size requirements are set at appropriate locations to achieve reliable connection between the top and bottom metals. In this way, the various power distribution networks are organically combined, and finally a power network that can meet the electrical performance requirements of each voltage domain is successfully designed to ensure that the chip can operate stably and efficiently under different working conditions.

[0058] The power network design method proposed in this application obtains design rules and constraint rules to build a systematic design process from identifying voltage domains and power distribution networks to generating top and bottom metal shapes and finally establishing power connections, which can adapt to complex voltage domain situations. The design rules and constraint rules are fully considered throughout the design process, avoiding the limitations of traditional single rule design methods and effectively solving the problem of increasing constraints. By following the rules for precise design at each key step, a large number of invalid calculation attempts caused by blind design are avoided, effectively improving the quality of power network wiring and enhancing chip performance and stability.

[0059] In some embodiments of the present application, generating the metal shape of the top metal and the metal shape of the corresponding bottom metal corresponding to each power distribution network according to the design rules may specifically include the following steps: first, determining the size and position of the metal shape of the top metal and the corresponding bottom metal corresponding to each power distribution network according to the power network design parameters in the design rules; then, determining the direction of the metal shape of the top metal corresponding to each power distribution network according to the wiring direction of the layer where the top metal corresponding to each power distribution network is located; determining the direction of the metal shape of the bottom metal corresponding to each power distribution network according to the wiring direction of the layer where the bottom metal corresponding to each power distribution network is located; finally, generating the metal shape of the top metal corresponding to each power distribution network according to the determined size, position and direction of the metal shape of the top metal corresponding to each power distribution network; generating the metal shape of the bottom metal corresponding to each power distribution network according to the determined size, position and direction of the metal shape of the bottom metal corresponding to each power distribution network.

[0060] Specifically, in the process of generating the metal shapes of the top metal and the bottom metal, the size and position of the metal shape of the top metal corresponding to each power distribution network and the size and position of the metal shape of the bottom metal corresponding to each power distribution network can be first determined according to the power network design parameters in the design rules.

[0061] It needs to be explained that the top metal is usually composed of multiple metal lines. The main function of each metal line is to serve as a conductive channel to transmit electrical signals. The number of metal lines depends on the complexity of the circuit and the design requirements. The size of the metal shape of the top metal refers to the geometric characteristics of the metal line width, length and spacing between them. These characteristics directly affect the performance, power consumption and reliability of the circuit. The width of the metal line determines the current that the metal line can carry. Wider metal lines can withstand larger currents, but also occupy more chip area. Therefore, choosing the right width is a trade-off process, which requires both ensuring sufficient current capacity and minimizing the space occupied by other components. The length of the metal line affects the distance that the signal propagates. Too long metal lines will increase signal delays, thereby reducing the operating speed of the circuit. Therefore, it is usually hoped that the metal lines are as short as possible to shorten the signal path and reduce delays. The spacing between metal lines ensures that there will be no short circuit or crosstalk between different metal lines. Appropriate spacing can also improve signal integrity and avoid problems such as electromagnetic interference. The position of the metal shape of the top metal refers to the layout and arrangement of the metal lines on the chip.

[0062] The bottom metal is usually composed of multiple metal lines. The size of the metal shape of the bottom metal refers to the geometric features such as the width, length and spacing between the metal lines. These features also directly affect the performance, power consumption and reliability of the circuit. The width of the metal line determines the current that the bottom metal can carry. Wider metal lines can withstand larger currents, but may also increase the parasitic capacitance and parasitic resistance of the chip, thereby affecting signal integrity. Therefore, choosing the right width requires balancing the relationship between current capacity and signal integrity. The length of the metal line affects the distance that the signal propagates. Longer lines of the bottom metal may increase signal delay, thereby reducing the operating speed of the circuit. In addition, longer metal lines may also increase power consumption and noise, so it is usually hoped that the metal lines of the bottom metal are as short as possible to shorten the signal path and reduce delay. The spacing between the metal lines ensures that there will be no short circuit or crosstalk between different metal lines. Appropriate spacing can also improve signal integrity and avoid electromagnetic interference and other problems. Especially in the power supply network, the spacing of the bottom metal also needs to meet the current density requirements to ensure uniform current distribution and avoid local overheating. The location of the metal shape of the bottom metal refers to the layout and arrangement of the metal lines on the chip.

[0063] The power network design parameters can be geometric parameters such as the length, width, spacing, and displacement of the power network. These parameters provide the core basis for determining the size and position of the metal shape. Taking the determination of the size and position of the metal shape of the top metal according to the power network design parameters as an example, the length, width, and spacing of the metal lines of the top metal and the spacing between adjacent metal lines can be determined according to the length, width, and spacing of the power network. At the same time, the position of the metal lines of the top metal on the chip can be determined according to the displacement parameters of the power network. The method of determining the size and position of the metal shape of the bottom metal is similar and will not be repeated here.

[0064] Next, the wiring direction is also an important factor in determining the direction of the metal shape. For the top metal, the wiring direction of the layer where it is located has a specific plan. In chip design, the top metal may be designed with a specific wiring direction, such as horizontal or vertical, according to the overall layout requirements. This wiring direction directly determines the direction of the top metal shape. For example, if the wiring direction of the layer where the top metal is located is planned to be horizontal, then the corresponding top metal shape will also be mainly horizontal. In the same way, the wiring direction of the layer where the bottom metal is located determines the direction of the bottom metal shape. The bottom metal usually focuses on high-density wiring, and its wiring direction setting cooperates with the top metal to reduce electromagnetic interference. If the wiring direction of the layer where the bottom metal is located is vertical, then the bottom metal shape will be mainly vertical, forming an orthogonal arrangement with the horizontal direction of the top metal, effectively reducing the signal interference between different source / ground networks and ensuring the stable operation of the power supply network.

[0065] Finally, based on the size, position and direction of the top metal shape corresponding to each power distribution network determined earlier, the metal shape of the top metal can be generated. Similarly, for the bottom metal, based on the determined size, position and direction, a metal shape of the bottom metal that meets the requirements can be generated. This process ensures that the generation of the metal shape of the top metal and the metal shape of the bottom metal in the power network not only meets the various parameter requirements in the design rules, but also can adapt to the overall electrical performance and layout requirements of the chip, laying a solid foundation for the subsequent establishment of a stable and efficient power connection between the top metal and the bottom metal, thereby ensuring that the entire power network can provide stable and reliable power support for each component in the integrated circuit.

[0066] As mentioned above, when the power network design parameters include length parameters, the length of the metal line of the top metal and the length of the metal line of the corresponding bottom metal of each power distribution network can be directly determined based on the length parameters. However, the power network design parameters do not necessarily include length parameters. When the power network design parameters do not include length parameters, the length of the metal line can be determined based on the wiring direction.

[0067] In some embodiments of the present application, when the length parameter is not included in the power network design parameters, if the wiring direction is horizontal, the lengths of the metal shapes of the top metal and the corresponding bottom metal corresponding to each power distribution network are determined to be the longest length in the horizontal direction; if the wiring direction is vertical, the lengths of the metal shapes of the top metal and the corresponding bottom metal corresponding to each power distribution network are determined to be the longest length in the vertical direction.

[0068] In this embodiment, when the wiring direction is horizontal, the length of the metal shape of the top metal and the bottom metal corresponding to each power distribution network can be set to the longest length in the horizontal direction. This means that in the horizontal direction, the metal line needs to be extended as far as possible to cover the longest range required for the entire current path. This is done to ensure that the current can flow smoothly from the power supply end to the load end, avoiding the current bottleneck or increased voltage drop caused by too short metal lines.

[0069] When the wiring direction is vertical, the length of the metal shape of the top metal and bottom metal corresponding to each power distribution network can be set to the longest length in the vertical direction. This means that in the vertical direction, the metal line needs to be extended as far as possible to cover the longest range required for the entire current path. Similarly, this is done to ensure that the current can flow smoothly from the power supply end to the load end, avoiding the current bottleneck or increased voltage drop caused by too short metal lines.

[0070] In some embodiments of the present application, the power connection method is different according to the process of the integrated circuit. Specifically, if the process of the integrated circuit is the first process, after the power connection is established between the top metal corresponding to each power distribution network and the corresponding bottom metal, the power connection is continued to be established between the bottom metal and the metal layer where the circuit functional unit is located; if the process of the integrated circuit is the second process, after the power connection is established between the top metal corresponding to each power distribution network and the corresponding bottom metal, the power connection is continued to be established between the bottom metal and the bottom metal, so as to realize the power connection through the bottom metal and the metal layer where the circuit functional unit is located.

[0071] Among them, the first process can be a FinFET process, the second process can be a planar process, and the circuit function module can be a standard cell and a macro cell. In an integrated circuit using the FinFET process, after establishing a power connection between the top metal and the bottom metal corresponding to each power distribution network, due to the characteristics of the FinFET process, in order to ensure that the circuit function unit can obtain a stable and accurate power supply, it is necessary to continue to establish a power connection between the bottom metal and the metal layer where the circuit function unit is located. The FinFET process has a three-dimensional structure, a high degree of device integration, and extremely strict requirements on the accuracy and efficiency of power distribution. By directly connecting the bottom metal to the metal layer where the standard cell and the macro cell are located, the loss and interference in the power transmission process can be minimized to the greatest extent, meeting the stringent requirements of the process in terms of high performance and low power consumption, thereby ensuring the stable operation and high performance of the entire integrated circuit.

[0072] For integrated circuits using planar technology, after establishing power connections between the top metal and the bottom metal of each power distribution network, the bottom metal can be further connected to the bottom metal. The bottom metal here is the smallest wiring layer of the planar technology. It has good conductivity and low resistance and can be used as a global power distribution layer.

[0073] The reason for this is that the planar process is a two-dimensional structure with relatively few metal layers, unlike the FinFET process, which has more metal layers to achieve direct connection between the bottom metal and the metal layer where the circuit functional unit is located. By connecting the bottom metal to the minimum wiring layer, the power supply can be distributed across the entire chip with the help of the minimum wiring layer, thereby providing power to circuit functional units such as standard units and macro units. This method conforms to the characteristics of the planar process, and effectively reduces the process complexity and cost while meeting the basic functions of the circuit.

[0074] In some embodiments of the present application, Figure 3 As shown, establishing a power connection between the top metal and the bottom metal can be achieved through a through hole. Specifically, step S240 can specifically include steps S310 to S330, which are described in detail as follows: Step S310: If the top metal and the corresponding bottom metal corresponding to each power distribution network are adjacent metal layers, a plurality of first through holes are generated according to the metal shape of the top metal and the metal shape of the bottom metal, and the through hole design parameters in the design rules, so as to establish a power connection between the top metal and the bottom metal through the plurality of first through holes.

[0075] When establishing a power connection between the top metal and the bottom metal, on the one hand, if the top metal corresponding to each power distribution network and the corresponding bottom metal are adjacent metal layers, multiple first through holes can be generated according to the metal shape of the top metal and the metal shape of the bottom metal, and the through hole design parameters in the design rules to establish a power connection between the top metal and the bottom metal through the multiple first through holes.

[0076] In integrated circuit design, adjacent metal layers mean that the two layers of metal are physically adjacent, with only an insulating layer in between. The top metal and bottom metal each have their own specific metal shapes, which determine the path and range of current transmission. The via design parameters in the design rules specify the size, spacing, location and other requirements of the via.

[0077] Based on this information, multiple first vias can be generated at appropriate locations. These vias are like bridges, passing through the middle insulating layer to connect the top metal and the bottom metal, thereby realizing the transmission of power between the two metal layers. For example, the design rules may stipulate that the minimum diameter of the via is 0.1 micron and the spacing between adjacent vias is at least 0.2 micron. Based on the metal shapes of the top metal and the bottom metal, multiple vias can be placed at locations that meet these parameter requirements to ensure the stability and reliability of the power connection.

[0078] Step S320: If the top metal and the corresponding bottom metal corresponding to each power distribution network are non-adjacent metal layers, the metal shape of the intermediate layer metal is generated layer by layer between the top metal and the bottom metal according to the metal shape of the top metal and the metal shape of the bottom metal, and the minimum area constraint in the constraint rule.

[0079] On the other hand, if the top metal and the corresponding bottom metal corresponding to each power distribution network are non-adjacent metal layers, the metal shape of the intermediate layer metal can be generated layer by layer between the top metal and the bottom metal according to the metal shape of the top metal and the metal shape of the bottom metal and the minimum area constraint in the constraint rules.

[0080] When the top metal and the bottom metal are not adjacent metal layers, they cannot be directly connected through vias, and the middle metal is needed to achieve power transmission. The minimum area constraint in the constraint rule means that the metal shape of the middle metal needs to meet certain area requirements. This is to ensure that the middle metal can carry enough current and avoid overheating due to excessive current density caused by too small an area.

[0081] When generating the metal shape of the middle layer metal, you can start from the top metal and generate the metal shape of the middle layer metal layer by layer according to certain algorithms and rules. These shapes must match the shapes of the top metal and the bottom metal and meet the minimum area constraint. For example, when generating the middle layer metal shape, you need to consider how to effectively guide the current of the top metal to the middle layer and then transmit it to the bottom metal through the middle layer. At the same time, ensure that the area of ​​the middle layer metal is large enough to meet the needs of current transmission.

[0082] Step S330: Generate multiple second vias between the top metal layer, the middle metal layer and the adjacent layers of the bottom metal layer according to the via design parameters, so as to establish a power connection between the top metal layer and the bottom metal layer through the metal shape of the middle metal layer and the multiple second vias between the adjacent layers.

[0083] After generating the metal shape of the middle layer metal of the top layer metal and the bottom layer metal, multiple second through holes can be generated between the adjacent layers of the top layer metal, the middle layer metal and the bottom layer metal according to the through hole design parameters to establish a power connection between the top layer metal and the bottom layer metal through the metal shape of the middle layer metal and the multiple second through holes between the adjacent layers.

[0084] After the metal shape of the intermediate layer metal is generated, connections can be established between adjacent layers. Similarly, according to the via design parameters in the design rules, multiple second vias are generated between the top metal and the adjacent intermediate layer metal, between each intermediate layer metal, and between the last intermediate layer metal and the bottom metal. These second vias connect the metals of adjacent layers to form a complete power transmission path. Through the metal shape of the intermediate layer metal and the multiple second vias between these adjacent layers, the power can be transmitted from the top metal through the intermediate layer metal in sequence and finally to the bottom metal, thereby realizing the power connection between non-adjacent metal layers. For example, multiple vias are generated between the top metal and the first intermediate layer metal to introduce the current of the top metal into the first intermediate layer metal; then multiple vias are generated between the first intermediate layer metal and the second intermediate layer metal to continue to transmit the current until it reaches the bottom metal.

[0085] This method of establishing power connections improves the flexibility and reliability of connections by adopting different strategies for adjacent and non-adjacent metal layers, and can better adapt to complex chip layout and routing; at the same time, it strictly follows design rules and constraints to ensure electrical performance and meet the stability requirements of the chip under different working conditions; in addition, it can also optimize the performance of the power distribution network, make power distribution more balanced, reduce electromagnetic interference, and improve the overall working stability and electromagnetic compatibility of the chip.

[0086] In some embodiments of the present application, Figure 4As shown, step S320 may specifically include steps S410 to S420, which are specifically described as follows: In step S410, the area of ​​the metal shape of the middle metal layer is determined according to the metal shape of the top metal layer and the projection of the metal shape of the bottom metal layer on the middle metal layer.

[0087] In integrated circuit design, the top metal and bottom metal are at different levels in space, and the middle metal is located between them. By projecting the shapes of the top metal and the bottom metal onto the plane where the middle metal is located, the projection area of ​​the two metal layers in the middle layer can be obtained. These projection areas reflect the corresponding relationship between the top metal and the bottom metal and the middle metal in space.

[0088] For example, the top metal may be a rectangular shape, and the bottom metal may be a circular shape. After projecting them onto the plane of the middle metal, the corresponding rectangular and circular projections will be obtained. Then, by calculating the total area covered by these projected areas, the preliminary area of ​​the metal shape of the middle metal can be determined. This area calculation provides basic data for subsequent judgment of whether the minimum area constraint is met.

[0089] In step S420 , if the determined area of ​​the metal shape of the intermediate metal layer is smaller than the minimum area constraint, the metal shape of the intermediate metal layer is filled to generate a new metal shape of the intermediate metal layer.

[0090] The minimum area constraint in the constraint rules is to ensure that the intermediate layer metal has sufficient conductive area to carry current, to avoid excessive current density due to too small an area, which in turn causes problems such as heat and electromigration, affecting the performance and reliability of the chip.

[0091] When the calculated area of ​​the middle metal shape is less than the minimum area constraint, it can be filled. The filling method can be based on the existing shape of the middle metal, expanding it to the surrounding or adding metal areas inside. For example, if the middle metal shape is a small rectangle that does not meet the minimum area requirement, you can evenly add metal strips of a certain width around the rectangle, or add some metal blocks inside the rectangle to increase its area so that it meets the minimum area constraint and generates a new metal shape that meets the requirements.

[0092] In some embodiments of the present application, after generating a new metal shape of the intermediate layer metal, a violation prediction can be performed on the surrounding area of ​​the new metal shape of the intermediate layer metal to obtain a prediction result, which is used to indicate the probability of a violation occurring; if the prediction result exceeds a preset threshold, the preliminary wiring evaluation index of the logic point corresponding to the surrounding area is updated to obtain a new wiring evaluation index, which is used to guide the adjustment of the violation.

[0093] Specifically, after generating a new metal shape for the middle layer metal, the surrounding area of ​​the new metal shape can be predicted for violations. Violations refer to violations of wiring rules. Wiring rules are a series of strict standards set during the integrated circuit manufacturing process to ensure chip performance and manufacturability, including metal line width, spacing, overlap and many other requirements. The final inspection result is a specific numerical value or probability value, which intuitively reflects the probability of violations in the surrounding area. The preset threshold is a standard set in advance. When the prediction result exceeds this preset threshold, it means that the surrounding area of ​​the new shape of the middle layer metal is very likely to have violations.

[0094] In integrated circuit design, the 3D wiring database stores the wiring information of each level of the chip, including the location, direction, connection relationship of the metal wires, etc. This information is recorded in the form of logical coordinate points to form a three-dimensional wiring map. The preliminary wiring evaluation index, also called the EVA value, is a numerical value used to evaluate the importance, risk or other related indicators of the logic coordinate point in the design. It comprehensively considers multiple factors such as wiring density, wiring length, and the number of vias, and can reflect the pros and cons of the current wiring design. When the prediction results show that there is a high risk of violation, it means that there is a high risk of DRC violation in the surrounding area. At this time, the EVA value of the logic coordinate point corresponding to the surrounding area needs to be updated to reflect this change. For example, the original EVA value of the logic coordinate point indicates a low risk, but because the DRC prediction shows a high risk of violation, the EVA value needs to be updated to a value indicating a high risk. In this way, in the subsequent design optimization process, designers can make targeted adjustments to these high-risk areas based on the updated EVA value to reduce the possibility of DRC violation and improve the quality and manufacturability of integrated circuit design.

[0095] In some embodiments of the present application, Figure 5 As shown, according to the through-hole design parameters, generating a plurality of second through-holes between adjacent layers of the top metal layer, the middle metal layer, and the bottom metal layer may specifically include steps S510 to S530, and these steps are described below: Step S510: Determine the border of the through hole array between adjacent layers according to the area requirements of the top metal layer, the middle metal layer and the upper metal layer in the adjacent layers of the bottom metal layer and the through hole design parameters.

[0096] In integrated circuit design, different metal layers need to be electrically connected through vias. In order to generate multiple second vias in the adjacent layers of the top metal, the middle metal, and the bottom metal, in this embodiment, the frame of the via array between adjacent layers can be determined based on the area requirements of the upper metal in the adjacent layers of the top metal, the middle metal, and the bottom metal and the via design parameters. Among them, the area size of the upper metal determines the range in which the vias can be arranged. At the same time, it is also necessary to combine the via design parameters, which include information such as the size and number of the vias.

[0097] By comprehensively considering the area requirements of the upper metal layer and the via design parameters, the area that the via array between adjacent layers should occupy, that is, the border of the via array, can be determined. For example, if the upper metal area is small, then the border of the via array will also be small accordingly, and the shape and size of this border should be reasonably planned according to the via design parameters to ensure that the vias generated subsequently can meet the requirements of electrical performance and manufacturing process.

[0098] Step S520: according to the size of the lower metal layer in the adjacent layer, delete the outermost part of the frame of the through hole array that exceeds the surrounding range of the lower metal layer to obtain a new frame of the through hole array.

[0099] After determining the preliminary border of the via array, the size of the underlying metal in the adjacent layer needs to be considered. The size of the underlying metal limits the actual range of the via array, because the via must be surrounded by the underlying metal to ensure effective current transmission.

[0100] Specifically, the outermost part of the frame of the through-hole array can be checked. If it exceeds the surrounding range of the lower metal layer, this part will be deleted. After such processing, a new frame of the through-hole array that meets the size requirements of the lower metal layer is obtained. This new frame ensures that the layout of the through-hole array matches the layout of the lower metal layer, avoiding electrical connection problems caused by the through-hole exceeding the range of the lower metal layer.

[0101] Step S530, determining the unit spacing of the through hole array in the longitudinal and transverse directions according to the through hole design parameters, and generating a through hole array according to the new border of the through hole array and the unit spacing of the through hole array, wherein the through hole array includes a plurality of second through holes.

[0102] After obtaining the new frame of the through-hole array, the unit spacing of the through-hole array in the vertical and horizontal directions must be determined based on the through-hole design parameters. The setting of the unit spacing is very important, as it ensures that there is enough space between the through-holes to avoid electrical short circuits or interference caused by too small spacing, and also ensures that the layout of the entire through-hole array meets the design requirements and manufacturing process standards.

[0103] Then, a specific through-hole array can be generated by combining the new border of the through-hole array and the determined unit spacing. This through-hole array includes multiple second through-holes, which will establish effective electrical connections between the adjacent layers of the top metal, the middle metal and the bottom metal, so that the current can be smoothly transmitted between different metal layers, thereby realizing various functions of the integrated circuit.

[0104] In some embodiments of the present application, the second through hole may be a large-sized through hole by default. In an integrated circuit, current needs to be transmitted between different metal layers through the second through hole. The large-sized second through hole has a larger cross-sectional area, which can reduce resistance and reduce energy loss during current transmission, thereby improving the current passing capacity. Therefore, in the absence of special requirements, a large-sized second through hole is selected by default to construct a through hole array to ensure that the current can flow stably and efficiently between the upper and lower metal layers to meet the electrical performance requirements of the circuit.

[0105] As mentioned earlier, the design rules are mainly set by the user. However, due to the particularity of the FinFET process, these parameters set by the user may not match the FinTrack requirements of the FinFET process. FinTrack requirements are a series of strict specifications for fin-related design and manufacturing in the FinFET process, covering fin size (such as width, height, length, etc., precise requirements at the nanometer level), fin spacing (needs to be precisely controlled to achieve high-density integration and avoid interference), patterning accuracy (using complex processes to ensure that the shape, size and position of the fins meet the design, and the process accuracy requirements such as lithography and etching are extremely high), material selection and quality (the characteristics of the substrate and related deposition materials must meet specific conditions) and process control (various parameters in multiple complex steps must be precisely controlled) to ensure the realization of high-performance and high-reliability FinFET devices.

[0106] In some embodiments of the present application, if the target design parameters in the design rules do not match the target requirement parameters of the integrated circuit process, the greatest common factor or greatest common multiple of the target design parameters and the target requirement parameters can be determined, and the target design parameters can be adjusted according to the greatest common factor or the greatest common multiple to obtain new design parameters.

[0107] For example, if the design rule set by the user stipulates that the width of a metal line is 10 microns, and the specific process requires the width of the metal line to be 12 microns, there is a mismatch. To solve this mismatch, find the greatest common factor or greatest common multiple of the two mismatched parameters. In the example just now, the greatest common factor of 10 and 12 is 2, and the least common multiple is 60. The purpose of calculating the greatest common factor or greatest common multiple is to find a value that can coordinate between the two. Adjust the target design parameters based on the calculated greatest common factor or greatest common multiple. If the adjustment is based on the greatest common factor, the design parameters can be adjusted according to the multiples of the greatest common factor. For example, the metal line width can be adjusted to a multiple of 2, such as 8 microns, 12 microns, etc., to make it closer to the process requirements. If the lowest common multiple is used as the basis, multiple design parameters can be adjusted uniformly so that they can meet the process requirements while also conforming to the overall framework of the design rules as much as possible, so as to achieve a balance between the design rules and process requirements, and obtain new design parameters so that the integrated circuit design can not only meet the feasibility of process manufacturing, but also achieve the performance and functions expected by the design rules as much as possible.

[0108] In some embodiments of the present application, in order to timely discover problems in the designed power supply network, avoid design rework caused by discovering problems after chip manufacturing is completed, thereby saving design time and cost and reducing project risks. In this embodiment, the voltage drop of the power supply network under maximum load can be calculated to ensure the stability and reliability of the integrated circuit power supply network. Specifically, the voltage drop of each power distribution network can be calculated according to the resistance value of each power distribution network corresponding to the target voltage domain and the current value of each power distribution network under maximum load; if the voltage drop of the target power distribution network in each power distribution network is less than the voltage value of the target voltage domain, the area corresponding to the target power distribution network is determined to be an insufficiently powered area; if the voltage drop of the target power distribution network is greater than the voltage value of the target voltage domain, the target path in the target power distribution network is determined, and a power filter element is inserted in the target path to reduce the voltage drop of the target path, and the voltage drop of the target path is greater than the preset voltage threshold.

[0109] In this embodiment, the target voltage domain refers to a specific voltage range, which corresponds to a part of the power network, including multiple power distribution networks. Each power distribution network has its own resistance value and a corresponding current value under the maximum load state. According to Ohm's law (voltage drop = current × resistance), the voltage drop of each power distribution network can be calculated by the resistance value of each power distribution network and their current value under the maximum load state.

[0110] After calculating the voltage drop of each power distribution network, the voltage drop of each power distribution network (i.e., the target power distribution network) can be compared with the voltage value of the target voltage domain. If the voltage drop of a target power distribution network is less than the voltage value of the target voltage domain, this means that when the power distribution network reaches its corresponding area during the power transmission process, the voltage has been reduced to a level that is insufficient to meet the normal operation requirements of the area. Therefore, it can be determined that the area corresponding to the target power distribution network is an insufficiently powered area. For example, the target voltage domain requires a voltage of 1.2V, but the voltage drop of a power distribution network makes the voltage reaching the corresponding area only 1.0V, then this area may not be able to work properly and is an insufficiently powered area.

[0111] If the voltage drop of a target power distribution network is greater than the voltage value of the target voltage domain, it means that there is a problem with the power distribution network, which may be caused by excessive resistance or excessive current. At this time, it is necessary to further determine the target path in the target power distribution network. The target path refers to those paths whose voltage drop is greater than the preset voltage threshold. The preset voltage threshold is a pre-set standard used to determine whether the voltage drop is too large. When it is found that the voltage drop of the target path exceeds this threshold, measures need to be taken to reduce the voltage drop. Inserting power filter elements (such as decoupling capacitors, etc.) in the target path is a common solution. Power filter elements can provide local charge storage and release functions. When the current changes, they can quickly replenish or absorb charges, thereby reducing voltage fluctuations and reducing voltage drops, ensuring the stability of the power supply, and enabling the target path to meet normal power supply requirements.

[0112] In some embodiments of the present application, in order to meet the low power design goal of UPF in the constraint rules, in this embodiment, the UPF file can be read and processed. Specifically, first, the unified power format file in the constraint rules can be parsed to obtain a parsed file; then, according to the positioning information in the parsed file, the position where the power control element needs to be inserted and the position where the power isolation element needs to be inserted are determined; finally, according to the insertion information in the parsed file, the power control element is inserted at the position where the power control element needs to be inserted, and the power isolation element is inserted at the position where the power isolation element needs to be inserted. The power control element is used to control the on and off of the power supply, and the power isolation element is used to isolate the power supply networks corresponding to each voltage domain.

[0113] As mentioned above, the constraint rules obtained in this application include a unified power format (UPF) file. The UPF file records various information and constraints related to power management. First, the UPF file can be parsed. Through a specific parsing tool or algorithm, the content in the UPF file is converted into a clearer and easier to process form to obtain a parsed file.

[0114] In some embodiments, a lexical analyzer may be used to analyze the read UPF command. Its working principle is similar to splitting a sentence into individual words and determining the part of speech and meaning of each word. Here, the lexical analyzer decomposes the UPF command into <operation, parameter> tuples.

[0115] For example, a UPF command may have an instruction "set the power switch on time to 10 microseconds". The lexical analyzer will recognize "set" as an operation and "power switch on time to 10 microseconds" as a parameter, and combine them into a tuple. The purpose of this is to convert complex UPF commands into a more concise and easy-to-process form, so that subsequent algorithms can further process and apply these constraint information.

[0116] After obtaining the parsed file, the corresponding power distribution network can be found in the entire power network according to the positioning information in the parsed file. For example, the constraint may specify a specific power network or ground network. That is, according to the positioning information, the specific location where the power control component and the power isolation component need to be inserted can be determined. The positioning information describes in detail where these components need to be inserted in the entire power network. The function of the power control component is to control the on and off of the power supply. For example, when some circuit modules do not need to work, the power supply can be cut off through the power control component, thereby achieving the purpose of energy saving; and the power isolation component is used to isolate the power networks corresponding to each voltage domain, prevent electrical interference and current leakage between different voltage domains, and ensure that each voltage domain can work stably.

[0117] Finally, according to the insertion information in the parsed file, the corresponding components are inserted at the previously determined positions. Through such operations, the power supply network can be effectively managed, so that the power supply can be stably supplied to each circuit module according to the design requirements, while avoiding mutual interference between different voltage domains, and ensuring the normal operation of the entire integrated circuit system.

[0118] In some embodiments of the present application, connectivity check is an important link to ensure the correct implementation of circuit functions, and its main purpose is to ensure that the connection between all standard cells, macro modules and power supply networks is accurate. During or after the design of the power supply network, a connectivity check can be performed to prevent isolated nodes that are not connected to any standard cells or macro modules from appearing in the power supply network. If there are suspended nodes, the power lines or ground lines connected to these nodes cannot provide power to the components in the circuit, which will not only cause the related components to fail to work, but may also cause electrical performance problems, such as increased power supply noise, decreased circuit stability, etc. Through connectivity checks, these connection errors can be discovered and corrected in a timely manner to ensure that the power supply of the chip is normal and improve the reliability and performance of the chip.

[0119] In a second aspect, the present application also proposes a power network design device, such as Figure 6 As shown, the power network design device includes: an acquisition unit 601 , an identification unit 602 , a generation unit 603 and a connection unit 604 .

[0120] Among them, the acquisition unit 601 is configured to acquire design rules and constraint rules for power network design in an integrated circuit; the identification unit 602 is configured to identify multiple voltage domains in the integrated circuit, and multiple power distribution networks corresponding to each of the voltage domains, each of the voltage domains corresponding to a different voltage value; the generation unit 603 is configured to generate the metal shape of the top metal and the metal shape of the corresponding bottom metal corresponding to each of the power distribution networks according to the design rules; the connection unit 604 is configured to establish a power connection between the top metal and the corresponding bottom metal corresponding to each of the power distribution networks according to the metal shape of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks, the design rules and the constraint rules, so as to design a power network corresponding to each of the voltage domains.

[0121] In some embodiments of the present application, the generation unit 603 is further configured to determine the size and position of the metal shapes of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks according to the power network design parameters in the design rules; determine the direction of the metal shape of the top metal corresponding to each of the power distribution networks according to the wiring direction of the layer where the top metal corresponding to each of the power distribution networks is located; determine the direction of the metal shape of the bottom metal corresponding to each of the power distribution networks according to the wiring direction of the layer where the bottom metal corresponding to each of the power distribution networks is located; generate the metal shape of the top metal corresponding to each of the power distribution networks according to the determined size, position and direction of the metal shape of the top metal corresponding to each of the power distribution networks; generate the metal shape of the bottom metal corresponding to each of the power distribution networks according to the determined size, position and direction of the metal shape of the bottom metal corresponding to each of the power distribution networks.

[0122] In some embodiments of the present application, the device also includes a determination unit, which is configured to, when the power network design parameters do not include a length parameter, if the wiring direction is a horizontal direction, determine that the lengths of the metal shapes of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks are the longest lengths in the horizontal direction; if the wiring direction is a vertical direction, determine that the lengths of the metal shapes of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks are the longest lengths in the vertical direction.

[0123] In some embodiments of the present application, the connection unit 604 is also configured to, if the process of the integrated circuit is the first process, then after establishing a power connection between the top metal corresponding to each power distribution network and the corresponding bottom metal, continue to establish a power connection between the bottom metal and the metal layer where the circuit functional unit is located; if the process of the integrated circuit is the second process, then after establishing a power connection between the top metal corresponding to each power distribution network and the corresponding bottom metal, continue to establish a power connection between the bottom metal and the bottom metal, so as to realize the power connection through the bottom metal and the metal layer where the circuit functional unit is located.

[0124] In some embodiments of the present application, the connection unit 604 is further configured to generate a plurality of first through holes according to the metal shape of the top metal and the metal shape of the bottom metal, and the through hole design parameters in the design rules, if the top metal corresponding to each of the power distribution networks and the corresponding bottom metal are adjacent metal layers, so as to establish a power connection between the top metal and the bottom metal through the plurality of first through holes; if the top metal corresponding to each of the power distribution networks and the corresponding bottom metal are non-adjacent metal layers, then generate the metal shape of the intermediate layer metal layer by layer between the top metal and the bottom metal according to the metal shape of the top metal and the metal shape of the bottom metal, and the minimum area constraint in the constraint rules; and generate a plurality of second through holes between the adjacent layers of the top metal, the intermediate layer metal and the bottom metal according to the through hole design parameters, so as to establish a power connection between the top metal and the bottom metal through the metal shape of the intermediate layer metal and the plurality of second through holes between the adjacent layers.

[0125] In some embodiments of the present application, the generation unit 603 is also configured to determine the area of ​​the metal shape of the intermediate layer metal based on the metal shape of the top layer metal and the projection of the metal shape of the bottom layer metal on the intermediate layer metal; if the determined area of ​​the metal shape of the intermediate layer metal is smaller than the minimum area constraint, the metal shape of the intermediate layer metal is filled to generate a new metal shape of the intermediate layer metal.

[0126] In some embodiments of the present application, the device also includes a prediction unit, which is configured to perform violation prediction on the peripheral area of ​​the new metal shape of the intermediate layer metal to obtain a prediction result, and the prediction result is used to indicate the probability of a violation occurring; if the prediction result exceeds a preset threshold, the preliminary wiring evaluation index of the logic point corresponding to the peripheral area is updated to obtain a new wiring evaluation index, and the new wiring evaluation index is used to guide the adjustment of the violation.

[0127] In some embodiments of the present application, the generation unit 603 is also configured to determine the border of the through-hole array between the adjacent layers according to the area requirements of the top-layer metal, the middle-layer metal and the upper-layer metal in the adjacent layers of the bottom-layer metal and the through-hole design parameters; delete the outermost part of the border of the through-hole array that exceeds the enclosing range of the lower-layer metal according to the size of the lower-layer metal in the adjacent layers to obtain a new border of the through-hole array; determine the unit spacing of the through-hole array in the longitudinal and transverse directions according to the through-hole design parameters, and generate the through-hole array according to the new border of the through-hole array and the unit spacing of the through-hole array, wherein the through-hole array includes the multiple second through holes.

[0128] In some embodiments of the present application, the determination unit is further configured to determine the greatest common factor or greatest common multiple of the target design parameters and the target requirement parameters if the target design parameters in the design rules do not match the target requirement parameters of the process of the integrated circuit; and adjust the target design parameters according to the greatest common factor or the greatest common multiple to obtain new design parameters.

[0129] In some embodiments of the present application, the device also includes a calculation unit, which is configured to calculate the voltage drop of each power distribution network based on the resistance value of each power distribution network corresponding to the target voltage domain and the current value of each power distribution network under the maximum load state; if the voltage drop of the target power distribution network in each power distribution network is less than the voltage value of the target voltage domain, the area corresponding to the target power distribution network is determined to be an area with insufficient power supply; if the voltage drop of the target power distribution network is greater than the voltage value of the target voltage domain, the target path in the target power distribution network is determined, and a power supply filter element is inserted into the target path to reduce the voltage drop of the target path, and the voltage drop of the target path is greater than a preset voltage threshold.

[0130] In some embodiments of the present application, the device also includes a parsing unit, which is configured to parse the unified power format file in the constraint rules to obtain a parsed file; determine the position where the power control element needs to be inserted and the position where the power isolation element needs to be inserted according to the positioning information in the parsed file; insert the power control element at the position where the power control element needs to be inserted, and insert the power isolation element at the position where the power isolation element needs to be inserted according to the insertion information in the parsed file, the power control element is used to control the on and off of the power supply, and the power isolation element is used to isolate the power supply networks corresponding to each of the voltage domains.

[0131] Based on the same concept, a power supply network designed by the power supply network design method described in any of the above embodiments should also be within the protection scope of this application. Similarly, a chip that at least includes a power supply network designed by the power supply network design method described in any of the above embodiments should also be within the protection scope of this application.

[0132] like Figure 7 As shown, an embodiment of the present application also provides an electronic device 700, including a memory 710, a processor 720, and a computer program 711 stored in the memory 710 and executable on the processor, and when the processor 720 executes the computer program 711, the steps of any of the above-mentioned power supply network design methods are implemented.

[0133] Since the electronic device introduced in this embodiment is a device used to implement a power network design device in the embodiment of the present application, based on the method introduced in the embodiment of the present application, the technical personnel in this field can understand the specific implementation mode of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application is not introduced in detail here. As long as the equipment used by the technical personnel in this field to implement the method in the embodiment of the present application is within the scope of protection of this application.

[0134] In a specific implementation process, when the computer program 711 is executed by the processor 720, any implementation method in the corresponding embodiment can be implemented.

[0135] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0136] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to memory, disk, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0137] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0138] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0139] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0140] An embodiment of the present application further provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes the processing flow of the power supply network design in the corresponding embodiment.

[0141] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0142] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0143] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0144] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0145] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0146] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0147] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A power network design method, characterized in that: include: Obtain design rules and constraints for power network design in integrated circuits; Identify multiple voltage domains in the integrated circuit and multiple power distribution networks corresponding to each of the voltage domains, each of the voltage domains corresponding to a different voltage value; Generate a metal shape of a top metal layer and a metal shape of a bottom metal layer corresponding to each power distribution network according to the design rule; According to the metal shape of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks, the design rules and the constraint rules, a power connection is established between the top metal and the corresponding bottom metal corresponding to each of the power distribution networks to design a power network corresponding to each of the voltage domains.

2. The method according to claim 1, characterized in that Generating a metal shape of a top metal layer and a metal shape of a bottom metal layer corresponding to each power distribution network according to the design rule, including: Determine the size and position of the metal shape of the top metal and the bottom metal corresponding to each of the power distribution networks according to the power network design parameters in the design rules; Determine the direction of the metal shape of the top metal layer corresponding to each power distribution network according to the wiring direction of the layer where the top metal layer corresponding to each power distribution network is located; Determine the direction of the metal shape of the bottom metal corresponding to each power distribution network according to the wiring direction of the layer where the bottom metal corresponding to each power distribution network is located; Generate a metal shape of the top metal corresponding to each power distribution network according to the determined size, position and direction of the metal shape of the top metal corresponding to each power distribution network; The metal shape of the underlying metal corresponding to each of the power distribution networks is generated according to the determined size, position and direction of the metal shape of the underlying metal corresponding to each of the power distribution networks.

3. The method according to claim 2, characterized in that The method further comprises: When the power network design parameters do not include a length parameter, if the wiring direction is a horizontal direction, then the lengths of the metal shapes of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks are determined to be the longest length in the horizontal direction; if the wiring direction is a vertical direction, then the lengths of the metal shapes of the top metal and the corresponding bottom metal corresponding to each of the power distribution networks are determined to be the longest length in the vertical direction.

4. The method according to claim 1, characterized in that: The method further comprises: If the process of the integrated circuit is the first process, after establishing a power connection between the top metal layer corresponding to each of the power distribution networks and the corresponding bottom metal layer, continue to establish a power connection between the bottom metal layer and the metal layer where the circuit functional unit is located; If the process of the integrated circuit is the second process, after establishing a power connection between the top metal and the corresponding bottom metal corresponding to each of the power distribution networks, continue to establish a power connection between the bottom metal and the bottom metal to achieve a power connection through the bottom metal and the metal layer where the circuit functional unit is located.

5. The method according to claim 1, characterized in that According to the metal shape of the top metal and the corresponding bottom metal of each power distribution network, the design rule and the constraint rule, a power connection is established between the top metal and the corresponding bottom metal of each power distribution network, including: If the top metal and the bottom metal corresponding to each of the power distribution networks are adjacent metal layers, a plurality of first through holes are generated according to the metal shape of the top metal and the metal shape of the bottom metal, and the through hole design parameters in the design rule, so as to establish a power connection between the top metal and the bottom metal through the plurality of first through holes; If the top metal and the bottom metal corresponding to each of the power distribution networks are non-adjacent metal layers, then according to the metal shape of the top metal and the metal shape of the bottom metal, and the minimum area constraint in the constraint rule, the metal shape of the intermediate metal is generated layer by layer between the top metal and the bottom metal; According to the via design parameters, a plurality of second vias are generated between the top metal layer, the middle metal layer and the adjacent layers of the bottom metal layer to establish a power connection between the top metal layer and the bottom metal layer through the metal shape of the middle metal layer and the plurality of second vias between the adjacent layers.

6. The method according to claim 5, characterized in that According to the metal shape of the top metal layer and the metal shape of the bottom metal layer, and the minimum area constraint in the constraint rule, the metal shape of the intermediate metal layer is generated layer by layer between the top metal layer and the bottom metal layer, including: Determine the area of ​​the metal shape of the middle metal layer according to the metal shape of the top metal layer and the projection of the metal shape of the bottom metal layer on the middle metal layer; If the determined area of ​​the metal shape of the intermediate metal layer is smaller than the minimum area constraint, the metal shape of the intermediate metal layer is filled to generate a new metal shape of the intermediate metal layer.

7. The method according to claim 6, characterized in that The method further comprises: Performing violation prediction on the surrounding area of ​​the new metal shape of the intermediate layer metal to obtain a prediction result, wherein the prediction result is used to indicate the probability of a violation occurring; If the prediction result exceeds a preset threshold, the preliminary wiring evaluation index of the logic point corresponding to the surrounding area is updated to obtain a new wiring evaluation index, and the new wiring evaluation index is used to guide the adjustment of the violation.

8. The method according to claim 5, characterized in that Generating a plurality of second through holes between adjacent layers of the top metal layer, the middle metal layer, and the bottom metal layer according to the through hole design parameters, including: Determine the border of the through hole array between the adjacent layers according to the area requirements of the top metal layer, the middle metal layer and the upper metal layer in the adjacent layers of the bottom metal layer and the through hole design parameters; According to the size of the lower metal layer in the adjacent layer, the outermost portion of the frame of the through hole array that exceeds the surrounding range of the lower metal layer is deleted to obtain a new frame of the through hole array; According to the through hole design parameters, the unit spacing of the through hole array in the longitudinal and transverse directions is determined, and according to the new border of the through hole array and the unit spacing of the through hole array, the through hole array is generated, and the through hole array includes the plurality of second through holes.

9. The method according to claim 1, characterized in that: The method further comprises: If the target design parameter in the design rule does not match the target requirement parameter of the process of the integrated circuit, determining the greatest common factor or greatest common multiple of the target design parameter and the target requirement parameter; According to the greatest common factor or the greatest common multiple, the target design parameters are adjusted to obtain new design parameters.

10. The method according to claim 1, characterized in that The method further comprises: Calculating the voltage drop of each power distribution network according to the resistance value of each power distribution network corresponding to the target voltage domain and the current value of each power distribution network under the maximum load state; If the voltage drop of the target power distribution network among the power distribution networks is less than the voltage value of the target voltage domain, determining that the area corresponding to the target power distribution network is an insufficiently powered area; If the voltage drop of the target power distribution network is greater than the voltage value of the target voltage domain, a target path in the target power distribution network is determined, and a power filter element is inserted into the target path to reduce the voltage drop of the target path, and the voltage drop of the target path is greater than a preset voltage threshold.

11. The method according to claim 1, characterized in that: The method further comprises: Parsing the unified power supply format file in the constraint rules to obtain a parsed file; Determine, according to the positioning information in the parsed file, a position where a power control component needs to be inserted and a position where a power isolation component needs to be inserted; According to the insertion information in the parsed file, the power control element is inserted at the position where the power control element is needed, and the power isolation element is inserted at the position where the power isolation element is needed. The power control element is used to control the on and off of the power supply, and the power isolation element is used to isolate the power supply networks corresponding to each of the voltage domains.

12. A power network design device, characterized in that: include: An acquisition unit configured to acquire design rules and constraint rules for power network design in an integrated circuit; an identification unit configured to identify a plurality of voltage domains in the integrated circuit and a plurality of power distribution networks corresponding to each of the voltage domains, each of the voltage domains corresponding to a different voltage value; A generating unit configured to generate a metal shape of a top metal and a metal shape of a corresponding bottom metal of each power distribution network according to the design rule; The connection unit is configured to establish a power connection between the top metal and the corresponding bottom metal corresponding to each power distribution network according to the metal shape of the top metal and the corresponding bottom metal corresponding to each power distribution network, the design rules and the constraint rules, so as to design a power network corresponding to each voltage domain.

13. An electronic device comprising: A memory and a processor, wherein the processor is used to implement the steps of the power supply network design method according to any one of claims 1 to 11 when executing a computer program stored in the memory.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the power supply network design method according to any one of claims 1 to 11 are implemented.

15. A chip, characterized in that: The chip at least includes a power supply network designed by the power supply network design method according to any one of claims 1-11.

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