Verification Method, Electronic Device and Medium of Data Extraction Module

Abstract

The present invention relates to the field of chip technology, and in particular to a verification method, electronic device and medium for a data extraction module. The method comprises step S1, reading the chip data to be tested output by the data extraction module from a memory, and generating first chip text data according to a preset data structure; step S2, obtaining the standard chip data output by a checker corresponding to the read data extraction module, and generating second chip text data according to a preset data structure; step S3, executing EA i m Comparison of different domains in LA m Different EAs in i m Comparison and Different LA m If all the comparisons are passed, step S4 is executed; otherwise, it is determined that the verification fails and the process ends; step S4, comparing the first chip text data and the second chip text data, if the comparison is passed, it is determined that the verification passes; otherwise, it is determined that the verification fails and the process ends. The present invention can realize an accurate verification data extraction module.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular, to a verification method, an electronic device, and a medium for a data extraction module. Background Art

[0002] Existing post-silicon performance test analysis usually obtains chip data by reading chip registers, which has the disadvantages of long reading time and few types of acquired information. Therefore, a data extraction module capable of real-time extracting performance parameters during chip operation can be set and written into memory in a preset format. The preset format is set as a key (token) for example. Software can directly read the memory to simply and efficiently read out a large amount of chip performance data, greatly improving the post-silicon performance test efficiency. Setting a data extraction module also requires verifying the data extraction module.

[0003] However, the existing verification method directly compares the result of the design under test (DUT) with the expected result of the checker (model). The data output by the data extraction module is in a preset format, and the timing of the checker cannot strictly correspond to the timing of the data extraction module. Therefore, it is impossible to perform a bit-by-bit comparison between the data output by the data extraction module and the data output by the checker. It can be seen that the existing verification method cannot check the correctness of the data output by the data extraction module, and thus cannot verify the data extraction module. It can be seen that how to provide a technology capable of accurately verifying the data extraction module has become an urgent technical problem to be solved. Summary of the Invention

[0004] The purpose of the present invention is to provide a verification method, an electronic device, and a medium for a data extraction module, which can accurately verify the data extraction module.

[0005] According to the first aspect of the present invention, a verification method for a data extraction module is provided, including:

[0006] Step S1: Read the data of the chip under test output by the data extraction module from the memory, and generate first chip text data {LA 1 ,LA 2 ,...,LA m ,...,LA M} according to a preset data structure. LA m is the list of the m-th type of chip data under test, the value range of m is from 1 to M, M is the total number of types of chip data under test, and LA m ={EA 1 m ,EA 2 m ,...,EA i m ,...,EA f(m)m}, EA i m is the i-th text data to be measured in LA, EA m in, EA 1 m , EA 2 m ,..., EA i m ,..., EA f(m) m Arranged in the order of generation, the value range of i is from 1 to f(m), and f(m) is the total number of text data to be measured in LA m in, EA i m = {HA 1 im , HA 2 im ,...., HA j im ,..., HA g(m) im}, HA j im is EA i m the j-th field segment in, and the value range of j is from 1 to g(m), and g(m) is the total number of field segments divided by the text data to be measured in LA m in;

[0007] Step S2, Obtain the standard chip data output by the checker corresponding to the read data extraction module, and generate the second chip text data {LB 1 , LB 2 ,..., LB n ,..., LB N}, LB n is the list of the n-th type of standard chip data, and the value range of n is from 1 to N, and N is the total number of standard chip data types, LB n = {EB 1 n , EB 2 n ,..., EB k n ,..., EB p(n) n}, EB k n is LB n the k-th standard text data in, and the value range of k is from 1 to p(n), and p(n) is the total number of standard text data in LB m in, EB 1 n , EB2 n ,..., EB k n ,..., EB p(n) n Arrange in the order of generation, EB k n = {HB 1 kn , HB 2 kn ,...., HB r kn ,..., HB q(n) kn}, HB r kn is the r-th field segment in EB k n , where the value range of r is from 1 to q(n), and q(n) is the total number of field segments divided by the standard text data in LB m The lengths of the text data to be measured and the standard text data are the same;

[0008] Step S3, perform one or more of the following comparisons on {LA 1 , LA 2 ,..., LA m ,..., LA M}: comparison of different field segments in EA i m , comparison of different EA in LA m , and comparison of different LA i m . If all comparisons pass, execute step S4; otherwise, determine that the verification of the data extraction module fails and end the process; m

[0009] Step S4, compare {LA 1 , LA,..., LA 2 ,..., LA m ,..., LA M} and {LB 1 , LB 2 ,..., LB n ,..., LB N}. If the comparison passes, determine that the verification of the data extraction module passes; otherwise, determine that the verification of the data extraction module fails and end the process.

[0010] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method according to the first aspect of the present invention.

[0011] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions for executing the method according to the first aspect of the present invention.

[0012] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solutions, a verification method, an electronic device and a medium of a data extraction module provided by the present invention can achieve considerable technical progress and practicality, and have wide industrial utilization value. It has at least the following beneficial effects:

[0013] The present invention first stores the data of the chip under test output by the data extraction module in the memory, then generates the first chip text data according to a preset data structure, and generates the second chip text data with the same data structure. Then, the first chip text data is compared with different domain segments in the same text data under test, different text data under test, different lists of chip data under test, and the overall comparison between the first chip text data and the second chip text data, realizing the bit-by-bit comparison of the data output by the data extraction module and the data output by the checker, thus realizing the accurate verification of the data extraction module. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0015] Figure 1 It is a flowchart of a verification method for a data extraction module provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0017] An embodiment of the present invention provides a verification method for a data extraction module, as Figure 1 shown, including:

[0018] Step S1: Read the data of the chip under test output by the data extraction module from the memory, and generate the first chip text data {LA 1 ,LA 2 ,...,LA m ,...,LA M} according to a preset data structure, where LA m is the list of the m-th type of data of the chip under test, the value range of m is from 1 to M, and M is the total number of types of data of the chip under test, and LA m ={EA 1 m ,EA 2 m ,...,EA i m ,...,EA f(m) m}, where EA i m is the i-th text data under test in LA m , and EA 1 m ,EA 2 m ,...,EA i m ,...,EA f(m) m are arranged in the order of generation, the value range of i is from 1 to f(m), and f(m) is the total number of text data under test in LA m , and EA i m ={HA 1 im ,HA 2 im ,....,HA j im ,...,HA g(m) im}, where HA j im is the j-th field segment in EA i m , and the value range of j is from 1 to g(m), and g(m) is the total number of field segments divided by the text data under test in LA m .

[0019] Among them, the data extraction module is used to extract the data of the chip under test in the chip. As an example, the chip can specifically be a GPU chip, and the data of the chip under test can specifically be the performance parameters during the operation of the chip. The preset data structure divides the data of the chip under test into different hierarchical structures for storage.

[0020] Step S2, obtain the standard chip data output by the checker corresponding to the read data extraction module, and generate the second chip text data according to the preset data structure {LB 1 ,LB 2 ,...,LB n ,...,LB N},LB n is the list of the nth type of standard chip data, where the value range of n is from 1 to N, and N is the total number of standard chip data types, LB n ={EB 1 n ,EB 2 n ,...,EB k n ,...,EB p(n) n},EB k n is the kth standard text data in LB n , where the value range of k is from 1 to p(n), and p(n) is the total number of standard text data in LB m ,EB 1 n ,EB 2 n ,...,EB k n ,...,EB p(n) n arranged in the order of generation, EB k n ={HB 1 kn ,HB 2 kn ,....,HB r kn ,...,HB q(n) kn},HB r kn is the rth field segment in EB k n , where the value range of r is from 1 to q(n), and q(n) is the total number of field segments divided by the standard text data in LB m . The lengths of the text data to be measured and the standard text data are the same.

[0021] It should be noted that the checker can be specifically set as a model generated based on a high-level language, and the data output by the checker is standard chip data. The standard chip data is also stored according to the same preset data structure as the chip data to be measured, and different hierarchical structures are also divided to facilitate subsequent comparison.

[0022] Step S3, for {LA1 , LA 2 ,..., LA m ,..., LA M} Execute EA i m Compare different field segments in, LA m Different EAs in i m Compare and different LAs m One or more of the comparisons. If all comparisons pass, execute step S4. Otherwise, determine that the verification of the data extraction module fails and end the process.

[0023] It should be noted that based on different hierarchical structures, by executing EA i m Compare different field segments in, LA m Different EAs in i m Compare and different LAs m One or more of the comparisons can achieve bit-by-bit comparison and realize the verification of the data extraction module.

[0024] Step S4, compare {LA 1 , LA 2 ,..., LA m ,..., LA M} and {LB 1 , LB 2 ,..., LB n ,..., LB N}. If the comparison passes, determine that the verification of the data extraction module passes. Otherwise, determine that the verification of the data extraction module fails and end the process.

[0025] As an embodiment, step S1 includes:

[0026] Step S11: Obtain the data of the chip under test through the data extraction module and store it in the memory.

[0027] Step S12: Read the data of the chip under test from the starting address of the data of the chip under test in the memory and store it in the form of an X-bit array.

[0028] Step S13: Combine Y arrays to generate EA i m , and store it in the corresponding LA m in the order of generation, and finally generate {LA 1 , LA 2 ,..., LA m ,..., LA M}.

[0029] Among them, X can specifically be set to 32 bits, and Y can be set to 2. Then EA i m has a corresponding length of 64 bits. However, it can be understood that the specific data of X and Y can be adjusted according to application requirements.

[0030] As an embodiment, in step S3, for {LA 1 , LA 2 ,..., LA m ,..., LA M}, perform comparison of different domain segments in EA i m , including at least one of step S31 and step S32:

[0031] Step S31: Determine whether the specified bits corresponding to HA i m in EA e im and the specified bits corresponding to HA d im meet the consistency matching condition. The value range of e is from 1 to g(m), and the value range of d is from 1 to g(m), e ≠ g.

[0032] It should be noted that the consistency matching condition can specifically be set as: when the specified bit corresponding to HA e im is 1, the specified bit corresponding to HA d im is also 1, or it can be set as: when the specified bit corresponding to HA e im is 0, the specified bit corresponding to HA d im is also 0.

[0033] Step S32: Determine whether the specified bits corresponding to HA i m in EA s im and the specified bits corresponding to HA v im meet the exclusivity matching condition. The value range of s is from 1 to g(m), and the value range of v is from 1 to g(m), s ≠ v.

[0034] It should be noted that the exclusivity matching condition can specifically be set as: when the specified bit corresponding to HA e im is 1, the specified bit corresponding to HA d im is 0, or it can be set as: when the specified bit corresponding to HA e imWhen the corresponding designated bit is 0, HA d im The corresponding designated bit is also 1.

[0035] Among them, HA e im The corresponding designated bit can be one or more bits, HA d im The corresponding designated bit can be one or more bits, HA e im The corresponding designated bit and HA d im The number of corresponding designated bits can be the same or different, and can be flexibly set according to application requirements. e im and HA d im Can be used for EA i m The adjacent domain segment can also be EA i m Non-adjacent domain segments.

[0036] As an embodiment, in step S3, {LA 1 ,LA 2 ,...,LA m ,...,LA M}Execute LA m Different EAs in i m Comparisons include:

[0037] Step S33: Determine EA 1 m ,EA 2 m ,...,EA i m ,...,EA f(m) m Each EA in i m Is the axth field segment in accordance with EA 1 m ,EA 2 m ,...,EA i m ,...,EA f(m) m The order of increasing, decreasing, remaining consistent, or wrapping back is as follows, and ax is a value between 1 and g(m).

[0038] It should be noted that one or more LAs can be mExecute step S33, which is set according to specific application requirements. Winding back refers to winding back when increasing to a certain value or decreasing to a certain value.

[0039] As an embodiment, in step S3, for {LA 1 ,LA 2 ,...,LA m ,...,LA M}, different LA m comparisons are performed, including:

[0040] Step S34, determine whether there is data with a preset mapping relationship and the same number in LA u and LA z .

[0041] It should be noted that the preset mapping relationship and the corresponding data are set according to specific application requirements.

[0042] As an embodiment, step S4 includes:

[0043] Step S41, determine whether the total number of text data to be tested in {LA 1 ,LA 2 ,...,LA m ,...,LA M} is the same as the total number of standard text data in {LB 1 ,LB 2 ,...,LB n ,...,LB N}. If they are the same, execute step S42; otherwise, determine that the verification of the data extraction module fails and end the process.

[0044] It should be noted that since {LA 1 ,LA 2 ,...,LA m ,...,LA M} and {LB 1 ,LB 2 ,...,LB n ,...,LB N} are generated based on the same preset data structure, therefore, the total number of text data to be tested in {LA 1 ,LA 2 ,...,LA m ,...,LA M} should be the same as the total number of standard text data in {LB 1 ,LB 2 ,...,LB n ,...,LB N} is consistent with the total number of standard text data. In some application scenarios, the generation order of the text data to be tested needs to be strictly consistent with the generation order of the standard text data. In some application scenarios, it is not necessary for the generation order of the text data to be tested to be strictly consistent with the generation order of the standard text data. Therefore, it is necessary to further judge by cases through step S42.

[0045] Step S42: If the verification requirement of the data extraction module is order consistency, then execute step S43. If the verification requirement of the data extraction module is disordered consistency, then execute step S44.

[0046] Step S43: Judge whether the sorting of the text data to be tested in {LA 1 ,LA 2 ,...,LA m ,...,LA M} is consistent with the sorting of the text data to be tested in {LB 1 ,LB 2 ,...,LB n ,...,LB N}. If they are consistent, it is determined that the data extraction module passes the verification. Otherwise, it is determined that the data extraction module fails the verification, and the process ends.

[0047] It should be noted that step S43 can specifically determine whether the sorting of the text data to be tested in {LA k n and each EB k n corresponding information is consistent to determine whether the sorting of the text data to be tested in {LA 1 ,LA 2 ,...,LA m ,...,LA M} is consistent with the sorting of the text data to be tested in {LB 1 ,LB 2 ,...,LB n ,...,LB N}.

[0048] Step S44: Determine whether each EB 1 ,LB 2 ,...,LB n ,...,LB N corresponding to each EA i m in the judgment exists in {LB k n}. If all exist, it is determined that the data extraction module passes the verification. Otherwise, it is determined that the data extraction module fails the verification, and the process ends.

[0049] It should be noted that step S44 can specifically judge each EA in turni m In the {LB 1 ,LB 2 ,...,LB n ,...,LB N}, is there a corresponding EB k n . If it exists, it is okay, and there is no need to ensure the same order.

[0050] During the information comparison process, there is information in some fields that does not need to be compared. In order to improve the comparison efficiency and reduce the error situation during the comparison, the corresponding bits can be masked before the comparison. As an embodiment, between step S2 and step S3, the following is further included:

[0051] Step S10: Set a mask on the preset mask bits of EA i m , and set a mask on the preset mask bits of the corresponding EB i m of EA k n . The bits where the mask is set are set to 0 during the comparison process of step S3 and step S4.

[0052] It should be noted that some fields are used to represent timestamps. However, when comparing with the checker, due to the limitation of the checker's timing, it is impossible to compare based on timing. Therefore, the bits corresponding to the timestamp can be directly masked. Thus, the preset mask bits can be set to the bits corresponding to the timestamp. In addition, some identifiers are randomly generated, and there will be inconsistent situations during the comparison, but this is not an abnormal situation. Therefore, such identifiers can be set as preset identifiers, and then the bits corresponding to the preset identifier information can be set as mask bits.

[0053] It should be noted that in order to realize the reuse of the comparison strategy, relevant bits can also be masked through step S10 to realize the reuse of the comparison strategy. The comparison strategy is the comparison process determined based on step S3 and step S4.

[0054] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operations are completed, but it can also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0055] An embodiment of the present invention further provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method of the embodiment of the present invention.

[0056] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions for executing the method of the embodiment of the present invention.

[0057] In the embodiment of the present invention, the data of the chip to be tested output by the data extraction module is first stored in the memory, then the first chip text data is generated according to a preset data structure, and the second chip text data with the same data structure is generated. Then, the comparison of different domain segments in the same text data to be tested, the comparison of different text data to be tested, the comparison of different lists of chip data to be tested, and the overall comparison of the first chip text data and the second chip text data are performed on the first chip text data, realizing the bit-by-bit comparison of the data output by the data extraction module and the data output by the checker, thereby realizing the accurate verification of the data extraction module.

[0058] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to be equivalent embodiments within the scope of the technical solution of the present invention. However, as long as the content does not depart from the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A verification method for a data extraction module, characterized in that: include: Step S1, read the chip data to be tested output by the data extraction module from the memory, and generate the first chip text data {LA1, LA2, ..., LA m ,...,LA M }, L.A. m is the data list of the mth type of chip to be tested, the value range of m is 1 to M, M is the total number of chip data types to be tested, LA m ={EA1 m ,EA2 m ,...,EA i m ,...,EA f(m) m },EA i m For LA m The i-th text data to be tested in EA1 m ,EA2 m ,...,EA i m ,...,EA f(m) m Arranged in the order of generation, the value range of i is 1 to f(m), f(m) is LA m The total number of text data to be tested in EA i m ={HA1 im ,HA2 im ,....,HA j im ,...,HA g(m) im }, HA j im For EA i m The jth domain in the , j ranges from 1 to g(m), g(m) is LA m The total number of domain segments into which the text data to be tested is divided; Step S2, obtain the standard chip data output by the checker corresponding to the read data extraction module, and generate the second chip text data {LB1, LB2, ..., LB n ,...,LB N }, LB n is the data list of the nth type of standard chip, the value range of n is 1 to N, N is the total number of standard chip data types, LB n ={EB1 n ,EB2 n ,...,EB k n ,...,EB p(n) n }, EB k n For LB n The kth standard text data in the , k ranges from 1 to p(n), p(n) is LB m Total number of standard text data in EB1 n ,EB2 n ,...,EB k n ,...,EB p(n) n Arranged in the order of generation, EB k n ={HB1 kn ,HB2 kn ,....,HB r kn ,...,HB q(n) kn }, HB r kn EB k n The rth domain in the , r ranges from 1 to q(n), q(n) is LB m The total number of domain segments divided by the standard text data in the test data and the standard text data have the same length; Step S3: {LA1, LA2, ..., LA m ,...,LA M }Execute EA i m Comparison of different domains in LA m Different EAs in i m Comparison and Different LA m If all the comparisons are passed, step S4 is executed; otherwise, it is determined that the data extraction module verification fails and the process ends; Step S4: Compare {LA1, LA2, ..., LA m ,...,LA M } and {LB1,LB2,...,LB n ,...,LB N }, if the comparison passes, it is determined that the data extraction module verification has passed, otherwise, it is determined that the data extraction module verification has failed and the process ends.

2. The method according to claim 1, characterized in that The step S1 comprises: Step S11, obtaining the chip data to be tested through the data extraction module and storing it in the memory; Step S12, reading the chip data to be tested from the starting address of the chip data to be tested in the memory, and storing it in the form of an X-bit array; Step S13: Combine Y arrays to generate EA i m , and store them in the corresponding LA in the order of generation m In the final generation, {LA1,LA2,...,LA m ,...,LA M }.

3. The method according to claim 1, characterized in that In step S3, {LA1, LA2, ..., LA m ,...,LA M }Execute EA i m The method comprises comparing different domain segments in the embodiment of the present invention, comprising at least one of step S31 and step S32: Step S31, determine EA i m HA e im The corresponding designated bit and HA d im Whether the corresponding designated bit meets the consistency matching condition, the value range of e is 1 to g(m), the value range of d is 1 to g(m), e≠d; Step S32: Determine EA i m HA s im The corresponding designated bit and HA v im Whether the corresponding specified bit meets the mutually exclusive matching condition. The value range of s is 1 to g(m), the value range of v is 1 to g(m), s≠v.

4. The method according to claim 1, characterized in that In step S3, {LA1, LA2, ..., LA m ,...,LA M }Execute LA m Different EAs in i m Comparisons include: Step S33, determine EA1 m ,EA2 m ,...,EA i m ,...,EA f(m) m Each EA in i m Is the axth field segment in accordance with EA1 m ,EA2 m ,...,EA i m ,...,EA f(m) m The order of increasing, decreasing, remaining consistent, or wrapping back is as follows, and ax is a value between 1 and g(m).

5. The method according to claim 1, characterized in that: In step S3, {LA1, LA2, ..., LA m ,...,LA M }Execute different LA m Comparisons include: Step S34: Determine LA u and LA z Whether there is data with a preset mapping relationship and the same number.

6. The method according to claim 1, characterized in that The step S4 comprises: Step S41: Determine {LA1, LA2, ..., LA m ,...,LA M } and the total number of text data to be tested in {LB1,LB2,...,LB n ,...,LB N } is consistent, if it is consistent, then execute step S42, otherwise, determine that the data extraction module verification fails, and end the process; Step S42: If the verification requirement of the data extraction module is sequential consistency, then execute step S43; if the verification requirement of the data extraction module is random consistency, then execute step S44; Step S43: Determine {LA1, LA2, ..., LA m ,...,LA M } and the order of the text data to be tested in {LB1,LB2,...,LB n ,...,LB N } whether the order of the text data to be tested is consistent, if it is consistent, it is determined that the data extraction module verification has passed, otherwise, it is determined that the data extraction module verification has not passed, and the process ends; Step S44, {LB1, LB2, ..., LB n ,...,LB N } whether each EA in the judgment exists i m Corresponding EB k n If both exist, it is determined that the data extraction module verification has passed, otherwise, it is determined that the data extraction module verification has failed and the process ends.

7. The method according to claim 1, characterized in that The steps S2 and S3 also include: Step S10: In EA i m Set the mask on the preset mask position of EA i m Corresponding EB k n A mask is set on the preset mask bit, and the bit of the mask is set to 0 during the comparison process of step S3 and step S4.

8. The method according to claim 7, characterized in that The preset masking bit is a bit corresponding to the timestamp or a bit corresponding to the preset identification information.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions to be executed by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method of any one of the preceding claims 1-8.

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