Method for forming diffusion barrier layer in interconnection structure and diffusion barrier layer
By forming a graphene layer with a helical structure in the interconnect structure as a diffusion barrier layer, the problems of void nucleation and electromigration failure at the bottom of the through hole are solved, and the effect of reducing resistivity and improving electromigration life is achieved.
Patent Information
- Application Number
- CN202510071008.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-16
- Publication Date
- 2025-05-13
AI Technical Summary
In the existing interconnect structure, the bottom of the through holes is prone to void nucleation and growth, resulting in electromigration failure. As the technology node advances, existing diffusion barrier materials cannot meet the resistivity and electromigration life requirements of the interconnect structure.
A low dielectric constant dielectric layer is formed in the interconnect structure and a first barrier layer is covered thereon, and a helical graphene layer is then grown on the first barrier layer, instead of the metal adhesion layer, reducing the thickness of the diffusion barrier layer.
By reducing the thickness of the diffusion barrier layer, reducing the resistivity of the interconnect structure, improving the electron scattering behavior of copper metal interconnect materials, inhibiting the migration or diffusion of copper, improving the electromigration life, and improving the reliability of the interconnect structure.
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Figure CN119993907A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing; in particular, to a diffusion barrier layer and a method for forming the same. Background Art
[0002] With the expansion of integrated circuit (IC) scale and the advancement of technology nodes, the back end of line (BEOL) is becoming more and more important in the entire manufacturing process. The interconnect structure manufactured by the back end process includes multi-layer metal wires and inter-layer metal vias, which are used to connect various integrated circuit components and devices manufactured by the front end process (FEOL).
[0003] In copper interconnect structures, the bottom of the through-hole is the main area where electromigration failure occurs. Figure 1 Shown is a schematic diagram of a copper interconnect structure. Figure 1 As shown, the copper interconnect structure includes a lower metal interconnect layer 110 and an interlayer metal via embedded in an intermetallic dielectric layer 130. The interlayer metal via includes a diffusion barrier layer 134 and a metallization layer 136 formed in sequence on the inner surface of the via. The stress and stress gradient between the diffusion barrier layer and the copper surface reach a maximum near the bottom of the via, which is conducive to the nucleation of voids. In addition, the interface bonding force between copper and the diffusion barrier layer is weak, and it is easy to peel off at this place under the driving of high current density, resulting in the growth of voids and the generation of voids 140 ( Figure 1 ), resulting in electromigration failure.
[0004] In addition, in conventional metal interconnect structures, before the opening in the interlayer dielectric (ILD) layer is filled with copper material, a diffusion barrier layer such as tantalum nitride (TaN) is formed as a liner on the exposed sidewall surface and bottom surface of the opening to prevent copper from diffusing into the dielectric material of the interlayer dielectric layer and damaging the BEOL structure. However, as the technology node advances below 55nm, the copper interconnect structure is scaled down, and the thickness of the diffusion barrier layer is reduced accordingly, which directly affects the reliability of the device; on the contrary, if the thickness of the above-mentioned diffusion barrier layer remains relatively constant, the volume of the metal filler composed of copper in the copper interconnect structure will be reduced, thereby affecting the resistivity, and a metal liner layer is usually required between the diffusion barrier layer and the electroplated copper to enhance the interface bonding force, which will affect the metal filling capability.
[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention
[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for forming a diffusion barrier layer in an interconnect structure and a diffusion barrier layer to solve the problem that in the existing interconnect structure, the bottom of the through hole is prone to nucleation and growth of voids, and even causes electromigration failure. With the advancement of technology nodes, the existing diffusion barrier materials can no longer meet the resistivity and electromigration life requirements of the interconnect structure.
[0007] To achieve the above object and other related objects, the present invention provides a method for forming a diffusion barrier layer in an interconnect structure, comprising the following steps:
[0008] forming a low dielectric constant dielectric layer, wherein the low dielectric constant dielectric layer comprises a top surface and a recess extending inward from the top surface, wherein the recess has a side wall and a bottom;
[0009] Covering the low dielectric constant dielectric layer to form a first barrier layer;
[0010] A graphene layer with a spiral structure is grown on the first barrier layer.
[0011] Optionally, the step of forming the graphene layer is performed after forming the first barrier layer, which includes: directly growing nanocrystalline graphene on the first barrier layer by a radio frequency plasma enhanced chemical vapor deposition process.
[0012] Optionally, before the step of forming the graphene layer, the step includes: pre-treating the first barrier layer with hydrogen plasma.
[0013] Optionally, the plasma enhanced chemical vapor deposition process is performed in an inductively coupled plasma chemical vapor deposition device, including: pre-introducing an inert gas and raising the temperature to 350°C to 400°C; then, introducing a gas mixture including a carbon-containing precursor, the gas mixture is excited by plasma to produce carbon free radicals, and spiral nanocrystalline graphene is grown on the surface of the first barrier layer, the spiral nanocrystalline graphene is merged to form a graphene layer with a spiral structure; wherein the gas mixture also includes an inert gas, and the carbon-containing precursor includes one of methane, ethylene, and acetylene.
[0014] Optionally, the first barrier layer is formed by a reactive sputtering process or a chemical vapor deposition process, and the material of the first barrier layer includes one or a combination of tantalum nitride and carbide.
[0015] Optionally, before the step of forming the first barrier layer, the step includes: forming a through hole or a groove on the low dielectric constant medium layer; wherein the first barrier layer and the graphene layer are sequentially conformally deposited on the sidewall and bottom of the through hole or the groove.
[0016] The present invention also provides a diffusion barrier layer for an interconnect structure, comprising: a substrate and a low dielectric constant dielectric layer located on the substrate, a through hole formed in the low dielectric constant dielectric layer, a diffusion barrier layer is arranged on the sidewall and bottom of the through hole, and the diffusion barrier layer comprises a first barrier layer and a graphene layer with a spiral structure.
[0017] Optionally, the thickness of the graphene layer ranges from 1 nm to 2 nm, and the number of layers of the graphene layer is one or two.
[0018] Optionally, the graphene layer includes spiral nanocrystalline graphene to form a spiral current conduction path from a bottom layer to a top layer of the graphene layer.
[0019] The present invention provides an interconnect structure, comprising a substrate, a device layer, a low dielectric constant dielectric layer stacked in sequence from bottom to top, a through hole penetrating the low dielectric constant dielectric layer, the inner surface of the through hole being sequentially formed with the above-mentioned diffusion barrier layer and a metallization layer.
[0020] As described above, the present invention provides a method for forming a diffusion barrier layer in an interconnect structure and a diffusion barrier layer, which have the following beneficial effects:
[0021] The method for forming a diffusion barrier layer in an interconnect structure provided by the present invention directly grows a graphene layer with a spiral structure on the first barrier layer after forming the first barrier layer to replace the metal adhesion layer, thereby reducing the overall thickness of the diffusion barrier layer and facilitating reducing the resistivity of the interconnect structure; in addition, the graphene is directly grown on the first barrier layer through a plasma chemical vapor deposition process without the need to additionally introduce a catalytic substrate, and nanocrystalline graphene is grown at a low temperature, while the deposition rate can be increased, and the method has broad application prospects.
[0022] The diffusion barrier layer provided by the present invention comprises nanocrystalline graphene with a spiral structure having a low resistivity, which meets the requirements for the interconnection structure of the back-end process when the technology node is advanced to below 55nm, and can improve the electron scattering behavior on the surface of metal interconnection materials such as copper, thereby further reducing the overall resistivity of the interconnection structure.
[0023] By applying the diffusion barrier layer provided by the present invention, the diffusion barrier layer includes a graphene layer with a spiral structure, which effectively inhibits the migration or diffusion of metal interconnect materials such as copper. At the same time, the good interface bonding between the graphene layer and the metallization layer is utilized to effectively prevent the diffusion of copper vacancies, thereby improving the electromigration life and achieving the purpose of improving the reliability of the interconnect structure. In addition, the graphene layer can improve the adhesion to the metal interconnect material such as copper. Compared with the original metal adhesion layer, the thickness of the diffusion barrier layer including the graphene layer is significantly reduced, thereby reducing the overall resistivity of the interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 Shown is a schematic diagram of a copper interconnect structure.
[0025] Figure 2 Shown is a schematic diagram of a diffusion barrier layer for a copper interconnect structure.
[0026] Figure 3 It is a schematic diagram showing a structure obtained after step S11 of a method for forming a diffusion barrier layer in an interconnect structure according to an embodiment of the present invention.
[0027] Figure 4 It is a partial enlarged view of the structure obtained after step S12 of the method for forming a diffusion barrier layer in an interconnect structure in an embodiment of the present invention.
[0028] Figure 5 It is a partial enlarged view of the structure obtained after step S13 of the method for forming a diffusion barrier layer in an interconnect structure in an embodiment of the present invention.
[0029] Figure 6 It is a schematic diagram showing the structure obtained after step S22 of the method for manufacturing the interconnect structure in an embodiment of the present invention.
[0030] Figure 7 It is a schematic diagram showing the structure obtained after step S23 of the method for manufacturing the interconnect structure in an embodiment of the present invention.
[0031] Component number description
[0032] 110 Lower metal interconnect layer
[0033] 130 Intermetallic dielectric layer
[0034] 132 Through Holes
[0035] 134 Diffusion Barrier
[0036] 1341 First barrier layer
[0037] 1342 Metal lining
[0038] 136 Metallization layer
[0039] 140 Hollow
[0040] 210 Substrate
[0041] 220 Low dielectric constant dielectric layer
[0042] 232 Depression
[0043] 234 First barrier layer
[0044] 236 Graphene Layer
[0045] 238 Metallization layer
[0046] 332 Through Hole
[0047] Steps S11~S13, S21~S23 DETAILED DESCRIPTION
[0048] Hereinafter, the embodiments of the present invention are described by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. For the purpose of clarity, parts and steps familiar to those skilled in the art are omitted to avoid unnecessary confusion of the elements of the present invention.
[0049] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
[0050] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0051] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0052] Figure 2 A schematic diagram of a diffusion barrier layer for a copper interconnect structure is shown. A diffusion barrier layer is formed on the sidewalls and bottom of a via hole or trench embedded in a dielectric layer, taking a via hole embedded in an intermetallic dielectric layer as an example. Figure 2As shown, a diffusion barrier layer is formed on the sidewall and bottom of the through hole 132 to prevent copper from diffusing into the dielectric layer. The diffusion barrier layer includes a first barrier layer 1341 and a metal liner layer 1342. Usually, the first barrier layer 1341 is selected as a TaN layer, and the metal liner layer 1342 is selected as a Ta layer. The above diffusion barrier layer can effectively inhibit the migration or diffusion of copper. However, as the size of CMOS devices continues to shrink, the thickness of the TaN layer and / or the Ta layer is also reduced accordingly; at this time, the role of the above diffusion barrier layer in reducing the through hole resistance, the adhesion with copper, and ensuring the electronic migration performance of copper is greatly reduced, and it cannot meet the requirements of the device.
[0053] In order to meet the barrier performance requirements of CMOS devices in proportion to the reduction, the present invention provides a new diffusion barrier layer for an interconnect structure, and a method for forming a diffusion barrier layer in an interconnect structure. Compared with the above-mentioned diffusion barrier layer, the present invention reduces the overall thickness of the diffusion barrier layer by directly growing a spirally structured graphene layer on the first barrier layer after forming the first barrier layer, replacing the metal adhesion layer, which is beneficial to reducing the resistivity of the interconnect structure.
[0054] Hereinafter, the method for forming the diffusion barrier layer of the present invention will be described in detail with reference to the accompanying drawings.
[0055] Embodiment 1
[0056] See also Figure 2 , this embodiment provides a method for forming a diffusion barrier layer in an interconnect structure.
[0057] S11: forming a low dielectric constant dielectric layer, and patterning the low dielectric constant dielectric layer;
[0058] S12: covering the patterned low dielectric constant dielectric layer to form a first barrier layer;
[0059] S13: growing a graphene layer with a spiral structure on the first barrier layer.
[0060] First, step S11 is performed to form a low dielectric constant dielectric layer and pattern the low dielectric constant dielectric layer.
[0061] Specifically, at step S11, a substrate 210 is provided, and a low dielectric constant dielectric layer 220 is formed on the substrate 210; the substrate 210 can be selected as a semiconductor material or an insulating material as needed, including but not limited to: for example, a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate; the low dielectric constant dielectric layer can refer to an interlayer dielectric layer or an intermetallic dielectric layer, and the material of the low dielectric constant dielectric layer 220 can be a material with a dielectric constant less than 3.5, for example, one or more of SiOH, SiOCH, tetraethyl orthosilicate (TEOS), fluorine-doped silicate glass (FSG), borosilicate glass (BSG), phosphosilicate glass (PSG), boron-doped phosphosilicate glass (BPSG), hydrogen silicon siloxane (HSQ) or methyl siloxane (MSQ).
[0062] Figure 3 Schematic diagram of the structure obtained after the step of forming the recess. Figure 3 As shown, the step of patterning the low-k dielectric layer 220 includes: forming a recess 232 from the top surface of the low-k dielectric layer to the inside, the recess 232 having sidewalls and a bottom. In some examples, the recess from the top surface of the low-k dielectric layer to the inside is formed as a through hole, a groove, or a combination of the two.
[0063] In a specific example, an etch stop layer may be formed between the substrate and the low dielectric constant dielectric layer.
[0064] Furthermore, step S11 also includes: baking the patterned low dielectric constant dielectric layer to remove moisture so as to enhance the adhesion of its surface to subsequent film layers.
[0065] Next, step S12 is performed to form a first barrier layer covering the patterned low-k dielectric layer.
[0066] Specifically, a first barrier layer is formed by covering the patterned low-k dielectric layer, wherein the patterned low-k dielectric layer includes a top surface and a recess extending from the top surface to the inside. The "first barrier layer" mentioned herein may be a diffusion barrier material commonly used in the art to inhibit the migration or diffusion of copper, including but not limited to nitrides or carbides of refractory metals, such as Ti, Ta, and W. Ideally, the material of the diffusion barrier layer is selected to have a sufficiently low resistivity while ensuring good interface performance between the dielectric layer and the metal interconnect material, which is beneficial to improving circuit performance.
[0067] Figure 4 This is a partial enlarged view of the structure obtained after the step of forming the first barrier layer. Figure 4As shown, the step of forming the first barrier layer 234 includes forming the first barrier layer by conformally depositing a barrier material on the patterned low dielectric constant dielectric layer, that is, on the sidewalls and bottom of the recess 232, and on the top surface of the low dielectric constant dielectric layer; wherein the first barrier layer is formed by, for example, a reactive sputtering process or a chemical vapor deposition process, and the material of the first barrier layer includes one or a combination of tantalum nitride and carbide.
[0068] Next, step S13 is performed to grow a graphene layer with a spiral structure on the first barrier layer.
[0069] Specifically, in step S13 , after forming the first barrier layer, the graphene layer 236 is formed. Figure 5 FIG. 1 is a partial enlarged view of the structure obtained after the step of forming the graphene layer. Figure 5 As shown, the graphene layer 236 conformally covers the first barrier layer 234. In this embodiment, nanocrystalline graphene is directly grown on the first barrier layer 234 by radio frequency plasma enhanced chemical vapor deposition (RF-PECVD) process, and the nanocrystalline graphene grows based on the aggregation of screw dislocations to obtain a graphene layer with a spiral structure; wherein the RF-PECVD process includes one of an inductively coupled plasma chemical vapor deposition (ICP-CVD) process and a capacitively coupled plasma chemical vapor deposition (CCP-CVD) process.
[0070] Based on the above technical solution, after forming the first barrier layer, there is no need to form a metal catalyst layer, and nanocrystalline graphene is directly grown on the first barrier layer. Compared with the conventional CVD process in which single-crystalline graphene is grown on a catalyst layer or a catalyst substrate composed of Cu, Ni, Co or similar transition metals with high carbon solubility, during the PECVD process, the plasma enhancement effect promotes the decomposition of carbon-containing precursors and reduces the activation energy of graphene growth. Therefore, nanocrystalline graphene can be grown at a low temperature, for example, at a temperature not higher than 550°C, and nanocrystalline graphene can be grown at a rate ten times that of growing graphene on a catalyst layer or a catalyst substrate through a high-temperature chemical vapor deposition process.
[0071] In some examples, the plasma enhanced chemical vapor deposition process is performed in an inductively coupled plasma chemical vapor deposition (ICP-CVD) device to grow spiral nanocrystalline graphene on the first barrier layer, and the spiral nanocrystalline graphene is combined to form a spiral graphene layer. Covalent bonds are formed between adjacent spiral nanocrystalline graphenes. Through this covalent bond combination, a spiral-driven current conduction path from the bottom layer to the top layer of the graphene is provided, so that the spiral graphene layer has enhanced out-of-plane conductivity. A thinner graphene layer is used to replace the original metal adhesion layer, such as a Ta layer. In the back-end process where the technology node is advanced to below 55nm, the thickness of the Ta layer is generally 4nm to 10nm. The purpose can be achieved by using a graphene layer of only 1nm in the above scheme.
[0072] At step S13, the plasma enhanced chemical vapor deposition process is performed in an inductively coupled plasma chemical vapor deposition (ICP-CVD) device, and the specific steps are as follows: a gas mixture including a carbon-containing precursor is introduced, and the gas mixture is excited by a plasma source to generate carbon fragments or carbon atoms, and spiral nanocrystalline graphene is grown on the surface of the first barrier layer, and the spiral nanocrystalline graphene is merged to form a graphene layer with a spiral structure; wherein the carbon-containing precursor includes one of methane, ethylene, and acetylene; the gas mixture also includes an inert gas, and the inert gas includes at least one of argon (Ar), neon (Ne), nitrogen (N2), helium (He), krypton (Kr), and xenon (Xe), and the gas mixture is excited by plasma to generate carbon free radicals, hydrogen free radicals, hydrogen free atoms and similar active groups; preferably, the inert gas is argon (Ar). In some examples, the gas mixture also includes a reducing gas, and the reducing gas includes hydrogen (H2). The growth mechanism of the graphene layer with a spiral structure is attributed to the introduction of screw dislocations. These dislocations provide continuous carbon-containing precursors during the growth process. During the ICP-CVD process, acetylene (C2H2) as a carbon-containing precursor is introduced and decomposed in the plasma to produce carbon atoms. These carbon atoms diffuse on the growth substrate (i.e., the first barrier layer) and gather at the screw dislocations to form a continuous carbon atom chain. As the growth proceeds, these chains are connected and grown into nanocrystalline graphene, thereby forming a graphene layer with a spiral structure. In this embodiment, a nitride or carbide of a refractory metal can be used to form the first barrier layer, and graphene is directly grown thereon. Since the first barrier layer (e.g., a TaN layer) has good chemical stability and thermal stability, the performance of the first barrier layer will not be affected.
[0073] In a preferred example, the step of forming the graphene layer 236 includes: before introducing the gas mixture, first, pre-treating the depression with hydrogen plasma to remove surface water vapor, thereby improving adhesion, and at the same time removing the surface oxide layer or impurities as a reducing agent, which is conducive to the subsequent formation of a high-quality graphene layer; then, placing the substrate with the depression in a reaction chamber, and introducing an inert gas into the reaction chamber to adjust the reaction chamber to the required temperature and chamber pressure; wherein, the method of generating the hydrogen plasma includes: introducing H2, exciting H2 to generate hydrogen ions, electrons, and neutral particles such as hydrogen radicals, thereby forming a plasma state of dynamic equilibrium. Preferably, the substrate temperature is raised to 350°C to 400°C by the heated gas flow of the inert gas, and the chamber pressure has a limit pressure of 5.0×10 -7 Torr.
[0074] Furthermore, the step of forming the graphene layer is as follows: introducing a gas mixture, the gas mixture comprising acetylene (C2H2), hydrogen (H2) and argon (Ar), maintaining the chamber pressure at a pressure condition of 20mTorr-30mTorr to generate plasma of the gas mixture, directly growing nanocrystalline graphene on the first barrier layer, and the reaction duration is 5min-10min to form a helical graphene with a thickness of nearly 1nm. Since the helical graphene layer can be formed by merging the helical nanocrystalline graphene, the helical graphene layer has bonding continuity, so that electrons can be more effectively transmitted between layers.
[0075] This embodiment also provides a diffusion barrier layer for an interconnect structure, comprising: a substrate and a low dielectric constant dielectric layer located on the substrate, a through hole formed in the low dielectric constant dielectric layer, a diffusion barrier layer is arranged on the sidewall and bottom of the through hole, and the diffusion barrier layer comprises a first barrier layer and a graphene layer with a spiral structure.
[0076] In some examples, the graphene layer includes nanocrystalline graphene; preferably, spiral nanocrystalline graphene is obtained based on the aggregation growth of screw dislocations, covalent bonds are formed between adjacent spiral nanocrystalline graphene, and the resulting spiral structure graphene layer has bonding continuity, thus forming a spiral current conduction path from the bottom layer to the top layer of the graphene layer, realizing interlayer electron transfer, thereby enhancing the out-of-plane conductivity of the graphene layer.
[0077] In this embodiment, the thickness of the graphene layer ranges from 1 nm to 2 nm, and the number of layers of the graphene layer is one or more layers; for example, when the graphene layer is provided with two or more layers, covalent bonds are formed between the spiral nanocrystalline graphene between adjacent layers to achieve interlayer electron transfer, thereby providing better vertical conductivity.
[0078] Embodiment 2
[0079] This embodiment provides a method for manufacturing an interconnect structure, comprising the following steps:
[0080] S21: forming a low dielectric constant dielectric layer and a through hole or a groove in the low dielectric constant dielectric layer;
[0081] S22: forming a diffusion barrier layer at least on the inner surface of the through hole or the trench;
[0082] S23: Filling the through hole or the trench and covering the low dielectric constant dielectric layer to form a metallization layer.
[0083] In this embodiment, the method for manufacturing the interconnect structure includes the method for forming a diffusion barrier layer in the interconnect structure as described above. Specifically, the interconnect structure may be a copper interconnect structure.
[0084] In step S21 , the low dielectric constant dielectric layer is patterned to form openings including through holes or trenches, and the low dielectric constant dielectric layer is used as an interlayer dielectric layer or an intermetallic dielectric layer.
[0085] Specifically, a device layer (not shown) is formed on the substrate 210, and one or more metal interconnection layers are formed on the device layer, and adjacent metal interconnection layers are connected by interlayer metal vias embedded in the metal interlayer dielectric layer; wherein the device layer includes various doping regions, etc., for forming necessary parts or structures of semiconductor devices, and the doping regions are, for example, lightly doped source and drain regions (LDD). The above parts or structures can be determined according to the actual semiconductor device manufacturing process, and are well known to those skilled in the art, and will not be described in detail here. Here, for the sake of simplicity, the specific structure of the substrate and the device layer thereon is not shown in the figure.
[0086] Figure 6 The opening of a through hole or trench in a low dielectric constant dielectric layer is shown using a Damascus process, and metal interconnect structures, such as metal lines (wiring) and metal vias (vertical interconnects), are formed separately at the openings of the through holes or trenches. In other embodiments, a dual-Damascus process known in the art can be used to etch openings in dual dielectric layers and fill them with metal materials, wherein the trench openings and through hole openings are patterned in the same dielectric layer and filled with metal materials simultaneously. The dual-Damacus process includes a "through hole first" process, a "trench first" process, and a "buried through hole" process, wherein each process sequence includes a patterned dielectric layer for forming openings of through holes and trenches, and a different process sequence for filling the openings of the through holes and trenches with metal materials.
[0087] In some examples, at step S22, as Figure 6As shown, the first barrier layer 23 is conformally deposited on the sidewall and bottom of the through hole 332. The material and / or manufacturing process of the first barrier layer can adopt the similar method described in the previous embodiment, which will not be repeated here.
[0088] Furthermore, after the step of forming the first barrier layer 234, a graphene layer with a spiral structure is grown by an inductively coupled plasma chemical vapor deposition (ICP-CVD) process, and the graphene layer includes spiral nanocrystalline graphene. Compared with the metal adhesion layer, the thickness of the diffusion barrier layer including the graphene layer is significantly reduced, thereby reducing the resistivity of the entire interconnection structure; compared with conventional two-dimensional layered graphene, the spiral nanocrystalline graphene has bonding continuity, and the graphene layer with such a spiral structure has enhanced out-of-plane conductivity.
[0089] In step S23, a metallization layer is formed to cover the graphene layer, the metallization layer fills the through hole or the groove, and the top surface of the metallization layer is substantially flush or level with the top surface of the low dielectric constant dielectric layer. Figure 7 Schematic diagram of the structure obtained after the step of forming the metallization layer. Figure 7 As shown, the step of forming the metallization layer 238 includes: plating the metal filling material by, for example, electroplating or electrochemical plating; then, flattening the metal filling material, removing a portion of the metal filling material so that the top surface of the metal filling material retained in the through hole or the groove is flush with the top surface of the low dielectric constant dielectric layer, to form a metallization layer; wherein the metal filling material is selected from any one of W, Co, Cu, Ru and Al. In some examples, before the step of forming the metal filler, a metal seed layer is formed on the graphene layer to enhance the metal filling capability and avoid the formation of holes, seams or similar defects in the subsequent filling process; for example, when the material of the metallization layer is copper, the material of the metal seed layer may include Cu, CuAl alloy or CuMn alloy.
[0090] This embodiment also provides an interconnect structure, including a substrate, a device layer, a low dielectric constant dielectric layer stacked in sequence from bottom to top, a through hole penetrating the low dielectric constant dielectric layer, the inner surface of the through hole is sequentially formed with the diffusion barrier layer as described above, and a metallization layer.
[0091] Since a metallization layer is formed on the graphene layer of the spiral structure, the electron scattering behavior of the metal surface can be improved. In particular, when the technology node enters below 55nm and the wire size in the copper interconnect structure is close to the electron free path of copper, the electron scattering problem begins to become prominent. By arranging a graphene layer between the first barrier layer and the metal interconnect material and utilizing the good interface bonding force between the graphene layer and the metallization layer, the nucleation and growth of voids are effectively suppressed, and the electromigration characteristics are thereby improved. At the same time, the electron scattering at the interface is reduced, and the resistivity of the interconnect structure is further reduced.
[0092] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for forming a diffusion barrier layer in an interconnect structure, characterized in that: The following steps are involved: forming a low dielectric constant dielectric layer, and patterning the low dielectric constant dielectric layer; Covering the patterned low dielectric constant dielectric layer to form a first barrier layer; A graphene layer with a spiral structure is grown on the first barrier layer.
2. The method for forming a diffusion barrier layer in an interconnect structure according to claim 1, characterized in that: The step of forming the graphene layer is performed after forming the first barrier layer, and includes: directly growing nanocrystalline graphene on the first barrier layer by a radio frequency plasma enhanced chemical vapor deposition process.
3. The method for forming a diffusion barrier layer in an interconnect structure according to claim 2, characterized in that: Before the step of forming the graphene layer, the step includes: pre-treating the first barrier layer with hydrogen plasma.
4. The method for forming a diffusion barrier layer in an interconnect structure according to claim 2, characterized in that: The plasma enhanced chemical vapor deposition process is performed in an inductively coupled plasma chemical vapor deposition device, including: pre-introducing an inert gas and heating it to 350°C to 400°C; then, introducing a gas mixture including a carbon-containing precursor, wherein the gas mixture is excited by plasma to generate carbon free radicals, and spiral nanocrystalline graphene grows on the surface of the first barrier layer, wherein the spiral nanocrystalline graphene merges to form a graphene layer with a spiral structure; wherein the gas mixture also includes an inert gas, and the carbon-containing precursor includes one of methane, ethylene, and acetylene.
5. The method for forming a diffusion barrier layer in an interconnect structure according to claim 1, characterized in that: The first barrier layer is formed by a reactive sputtering process or a chemical vapor deposition process, and the material of the first barrier layer includes one or a combination of tantalum nitride and carbide.
6. The method for forming a diffusion barrier layer in an interconnect structure according to claim 1, characterized in that: After the step of forming the low dielectric constant dielectric layer, it includes: forming a recess from the top surface of the low dielectric constant dielectric layer to the inside, the recess having side walls and a bottom; forming the first barrier layer by conformally depositing a barrier material on the side walls and bottom of the recess and the surface of the low dielectric constant dielectric layer.
7. A diffusion barrier layer for an interconnect structure, characterized in that: include: A substrate and a low dielectric constant dielectric layer located on the substrate, wherein a through hole is formed in the low dielectric constant dielectric layer, and a diffusion barrier layer is arranged on the sidewall and bottom of the through hole, and the diffusion barrier layer includes a first barrier layer and a graphene layer with a spiral structure.
8. The diffusion barrier layer according to claim 7, characterized in that: The thickness of the graphene layer ranges from 1 nm to 2 nm, and the number of layers of the graphene layer is one or two.
9. The diffusion barrier layer according to claim 7, characterized in that: The graphene layer includes spiral nanocrystalline graphene to form a spiral current conduction path from a bottom layer to a top layer of the graphene layer.
10. An interconnection structure, characterized in that: It comprises a substrate, a device layer, a low dielectric constant dielectric layer stacked in sequence from bottom to top, a through hole penetrating the low dielectric constant dielectric layer, the inner surface of the through hole is sequentially formed with a diffusion barrier layer according to any one of claims 7 to 9, and a metallization layer.