Semiconductor device capable of preventing internal corrosion and preparation method thereof

Abstract

The invention discloses a semiconductor device capable of preventing the interior from being corroded and a preparation method of the semiconductor device, and relates to a power semiconductor device.The semiconductor device is provided with an inner-ring inorganic passivation layer surrounding and adjoining a chemical plating metal layer and at least one outer-ring inorganic passivation layer located on the periphery of the inner-ring inorganic passivation layer; and a gap D2 filled with the organic passivation layer is arranged between the inner ring inorganic passivation layer and the outer ring inorganic passivation layer, so that the problem of adhesion between the passivation layer and the metal layer caused by corrosion in the chemical plating process can be avoided, and the yield of device production and the reliability in the use process are improved.

Description

Technical Field

[0001] The present invention relates to power semiconductor devices, in particular to a structure capable of preventing the internal parts of devices such as shielded gate field effect transistors and insulated gate bipolar transistors from being corroded and a preparation method thereof. Background Art

[0002] Top view of the wafer surface of a power semiconductor device Figure 1 As shown, a quadrilateral device is included, which at least includes: a cell region 202 for current conduction, and a terminal region 201 for maintaining the breakdown voltage of peripheral devices and surrounding the cell region. The terminal region 201 is completely covered with a passivation layer for protection; the cell region has a gate opening region 101 and a source opening region 102 as regions for chemical metal deposition, and the positions outside the gate opening region 101 and the source opening region 102 are covered by the passivation layer.

[0003] Figure 2 Shown Figure 1 The cross-sectional schematic diagram of the device after metallization is shown at the cut line A. A metallized metal layer 209 is deposited above the opening position of the surface metal layer 206, which is close to the edge of the organic passivation layer 208. The device includes a metal layer 203 at the bottom, a semiconductor layer 204 above the bottom metal layer, an oxide isolation layer 205 located on the upper surface of the semiconductor, a surface metal layer 206 located above the oxide isolation layer, an inorganic passivation layer 207 located above the surface metal layer, and an organic passivation layer 208 located above the inorganic passivation layer and wrapping both ends thereof. The area covered by the passivation layer is the terminal area 201 of the device, and the opening position of the surface metal layer 206 belongs to the cell area 202.

[0004] Before chemical plating, the wafer surface is pre-treated to remove dirt and oxides on the wafer surface, and then the wafer surface is roughened with a chemical etching solution to ensure the density and enhanced bonding strength of the catalyst deposited on the surface metal layer. However, the chemical etching solution can easily corrode the metal surface and also the surface metal layer 206 under the inorganic passivation layer 207, resulting in poor adhesion between the passivation layer and the surface metal layer 206, causing delamination or detachment problems, and causing irreversible damage to the device structure during the chemical plating process.

[0005] After micro-roughening, the metal surface will be activated, and the wafer will be immersed in the prepared chemical plating solution to form chemical plating layers of different elements on the metal surface. However, during the activation process, the catalyst will be deposited on the surface metal layer 206 under the inorganic passivation layer 207 along the gap, resulting in the appearance of chemically plated metal in the opening area, and the metal surface under the passivation layer will also grow a dislocated chemically plated metal area 210, and the edge of the organic passivation layer 208 will be aggravated by the infiltration of chemically plated metal, which will affect the inside of the device.

[0006] In order to improve the problem of poor adhesion between the inorganic passivation layer 207 and the surface metal layer 206 caused by the chemical plating process, the following method can also be used: Figure 3 The method shown reduces the end of the organic passivation layer from the contact surface with the surface metal layer 206 to the surface of the inorganic passivation layer 207 to solve the adhesion problem. However, during the molding process, the molding resin layer 301 will harden on the inorganic passivation layer 207 not covered by the organic passivation layer 208 to generate stress, causing cracks to appear at this position. When the device works for a long time, the cracks will extend to the terminal area 201 of the device. Ultimately, external impurity ions and water vapor enter the terminal area 201 through the cracks, causing surface leakage and device failure. Summary of the invention

[0007] The following conclusions can be drawn from the previous examples. First, the organic passivation layer has insufficient adhesion to the surface metal layer, which causes the organic passivation layer to fall off. The infiltrated chemically plated metal will also aggravate the peeling problem of the organic passivation layer, affecting the leakage of the device. Second, the molding resin hardens on the inorganic passivation layer in the absence of the buffer of the organic passivation layer, generating stress and causing the inorganic passivation layer to crack. External impurity ions and moisture enter the terminal area through the cracks, causing surface leakage and device failure.

[0008] A semiconductor device for preventing internal corrosion, the semiconductor device comprising a cell region and a terminal region surrounding the cell region, the cell region being provided with a gate opening region and a source opening region; a chemically plated metal layer is deposited on the gate opening region and the source opening region, the region outside the gate opening region and the source opening region is covered with a passivation layer, the passivation layer comprising an inorganic passivation layer and an organic passivation layer located above the inorganic passivation layer, the inorganic passivation layer comprising an inner ring inorganic passivation layer surrounding the adjacent chemically plated metal layer and at least one outer ring inorganic passivation layer located outside the inner ring inorganic passivation layer, a gap D2 is provided between the inner ring inorganic passivation layer and the outer ring inorganic passivation layer, the organic passivation layer fills the gap D2 downwards.

[0009] Furthermore, the gap D2 is in the shape of a straight bar, a curve, or a combination of the above shapes.

[0010] Furthermore, the outer ring inorganic passivation layer includes a first outer ring inorganic passivation layer and a second outer ring inorganic passivation layer located outside the first outer ring inorganic passivation layer, and a gap D4 is provided between the first outer ring inorganic passivation layer and the second outer ring inorganic passivation layer, and the organic passivation layer fills the gap D4 downward.

[0011] Furthermore, the gap D4 is in the shape of a straight bar, a curve, or a combination of the above shapes.

[0012] Furthermore, the first outer ring inorganic passivation layer is composed of a plurality of isolated inorganic passivation regions, a gap D5 is provided between each of the inorganic passivation regions, and the organic passivation layer fills the gap D5 downwards.

[0013] Furthermore, the first outer ring inorganic passivation layer is H-shaped.

[0014] The semiconductor device may be a laterally diffused metal oxide semiconductor, a vertically diffused metal oxide semiconductor, an insulated gate bipolar transistor or a diode.

[0015] The present invention also provides a method for preparing a semiconductor device that prevents internal corrosion, the method comprising the following steps: First, an inorganic passivation layer is formed on the surface metal layer and the oxide isolation layer, and the thickness of the inorganic passivation layer is 2-10µm; Second, a photoresist is formed on the inorganic passivation layer, and the required portion of the inorganic passivation layer is obtained through exposure on the photomask, thereby exposing the area to be etched; Third, the inorganic passivation layer is subjected to a vertical etching process from the surface downward until the opening position of the surface metal layer and the surface opening position of the oxide isolation layer are respectively etched, and then the photoresist is removed; Fourth, an organic passivation layer is coated on the upper surface of the device, and the gap D2 of the inorganic passivation layer is also fully filled by the organic passivation layer, and the thickness of the organic passivation layer is 5-10µm; Fifth, a photoresist is formed on the organic passivation layer, and the required portion of the organic passivation layer is obtained through exposure on the photomask, thereby exposing the area to be etched; Sixth, after the etching and degumming process, an organic passivation layer is formed and deposited on the inorganic passivation layer, and the organic passivation layer does not cover a portion of the top surface and side surfaces of the inner circle inorganic passivation layer; Seventh, the wafer is subjected to chemical etching to roughen the exposed metal surface above the cell area, deposit catalyst and activate, and finally immersed in chemical plating solution to form chemically plated metal.

[0016] The device provided by the present invention can avoid the adhesion problem between the passivation layer and the metal layer caused by corrosion during the chemical plating process, thereby increasing the yield rate of device production and the reliability during use. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A top view of the surface of a power semiconductor device wafer; Figure 2 Shown Figure 1 A schematic cross-sectional view of the device at the cut line A after metallization plating; Figure 3 for Figure 1 A schematic cross-sectional view of a device at a cutting line A after the mold encapsulation is completed; Figure 4 A cross-sectional schematic diagram of a passivation layer layout of the present invention; Figure 5 for Figure 4 A top view of the surface structure of a semiconductor device; Figure 6 A structural top view of another embodiment of the gap; Figure 7-13 A cross-sectional schematic diagram of a key step of an embodiment of a passivation layer layout of the present invention; Fig.14 is a cross-sectional schematic diagram of another passivation layer layout of the present invention; Fig.15 for Fig.14 A top view of the surface structure above the semiconductor device; Fig.16 A top view of the structure of yet another embodiment of the gap. DETAILED DESCRIPTION

[0018] For the convenience of each component, region, layer, step or part in the figure, the process of description will inevitably refer to a certain component, region, layer, step or part as being oriented above or below other components. These spatial description terms also include orientations in other dimensions such as left or right to clearly explain the structure of the device.

[0019] The corresponding position words described in this document, such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", and "vertical", are relative positions corresponding to the reference figures. The specific implementation is not limited to a fixed direction. It should be noted that the devices in the drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and trenches in the drawings, and the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0020] The drawings shown in the present invention include top views and cross-sectional views of the device for describing the embodiments. In order to explain the device more clearly under the premise of explaining the present invention and not contradicting each other, the size, relative dimensions and overlapping area between each component, layer, or part may be exaggerated compared with the actual ones, but all components, layers, or parts in the drawings are consistent with those indicated in the drawings. The shape shown in the cross-sectional view and the actual shape of the device do not limit the scope of the present application, and it is expected that the embodiments may be subject to different shape changes due to the process or technical level, such as the passivation layer etching process resulting in a terminal bevel structure with a positive or negative angle. Therefore, the drawings are used to illustrate the structure of the cross-section of the device, and the embodiments should not be limited to a specific shape.

[0021] Since the device structures of the inorganic passivation layer and the surface metal layer can be commonly used in different semiconductor devices such as laterally diffused metal oxide semiconductor (LDMOS), vertically diffused metal oxide semiconductor (VDMOS), insulated gate bipolar transistor (IGBT) and diode (Diode), for the convenience of explanation, the following will be explained with metal oxide semiconductor, but the present invention is not limited to this.

[0022] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments.

[0023] Figure 4 A cross-sectional view of a semiconductor device of the first embodiment of the present invention is shown. The inorganic passivation layer 207 is divided into two parts, an inner inorganic passivation layer 2071 surrounding the electroless metal layer 209 and an outer inorganic passivation layer 2072 located at other positions, wherein a gap D2 is provided between the inner inorganic passivation layer and the outer inorganic passivation layer, and the organic passivation layer 208 fills the gap D2, so that the contact area between the organic passivation layer 208 and the inorganic passivation layer 207 can be increased, and the adhesion between the organic passivation layer 208 and the inorganic passivation layer 207 can be improved, thereby reducing the impact of device leakage caused by peeling of the outer side of the organic passivation layer 208. The inner inorganic passivation layer 2071 can also serve as a barrier layer to prevent cracks from extending to the terminal area 201 of the device, thereby protecting the inside of the device.

[0024] Figure 5 Show Figure 4 The top view of the surface structure above the semiconductor device, the right picture is the layout of the surface structure of the semiconductor device before covering the organic passivation layer 208, while the left picture is not covered. The gap D2 of the inorganic passivation layer 207 is a straight strip extending in a direction parallel to the edge of the device, so that the organic passivation layer 208 fully fills the gap between the inorganic passivation layers 207.

[0025] As Figure 5 Further improvements to the technical solution shown, such as Figure 6 As shown, by changing the pattern of etching the inorganic passivation layer 207 on the photoresist, the gap D2' of the inorganic passivation layer 207 extends to the left and right sides in the parallel direction of the device edge without affecting the cell region 202, or the path length of the gap D2' can be increased to fill the organic passivation layer 208. Figure 5 The contact area between the organic passivation layer 208 and the inorganic passivation layer 207 is further increased on the basis of the design invention, and the gap D2' can be a curve, or a plurality of straight gaps connected (such as Figure 6 ).

[0026] The present invention provides a method for manufacturing a device as follows Figure 7-13 shown.

[0027] The semiconductor body 204 may be made of materials such as silicon (Si), silicon carbide (SiC), and gallium nitride (GaN), and the surface metal layer 206 may be made of a single element such as aluminum, copper, or an alloy such as aluminum-copper.

[0028] First, as Figure 7 As shown, an inorganic passivation layer 207 such as silicon nitride is formed on the surface metal layer 206 and the oxide isolation layer 205 by chemical vapor deposition. The thickness of the inorganic passivation layer 207 is at least 2µm (micrometer) to 10µm (micrometer) and covers the vertical top of the oxide isolation layer 205 and the surface metal layer 206 and the sidewalls of the surface metal layer 206.

[0029] Second, if Figure 8 As shown, a photoresist 211 is formed on the inorganic passivation layer 207, and a required portion of the inorganic passivation layer 207 is obtained by exposure through the photomask, thereby exposing the etching area.

[0030] Third, if Fig. 9 As shown, the inorganic passivation layer 207 is etched vertically downward from the surface until the opening position of the surface metal layer 206 and the opening position of the oxidation isolation layer 205 appear at the etching position, and then the photoresist 211 is removed.

[0031] D1 is the width of the opening of the oxide isolation layer 205, which is the horizontal distance from the edge section of the inorganic passivation layer 207 to the outer edge of the semiconductor layer 204 in the horizontal direction and has no vertical overlap with the inorganic passivation layer 207 and the oxide isolation layer 205. Usually, the length of D1 is at least 20µm (micrometers).

[0032] D2 is the width of the opening of the surface metal layer 206 and the gap width of the inorganic passivation layer 207. Usually, the length of D2 is at least 5 μm (micrometer).

[0033] However, in another embodiment, when the photoresist 211 is formed on the inorganic passivation layer 207, it will cover the oxidation isolation layer 205 vertically above. Therefore, after the exposure and de-germing process, the inorganic passivation layer 207 vertically above the oxidation isolation layer 205 is retained and completely covers the surface metal layer 206 to the edge of the semiconductor layer 204 and the oxidation isolation layer 205.

[0034] Fourth, if Fig.10As shown, an organic passivation layer is applied on the inorganic passivation layer 207, the surface metal layer 206 and the oxide isolation layer 205 by spin coating. The organic passivation layer is composed of a low hardness material, and its constituent material may be an organic polymer, such as styrene cyclobutene (BCB), polyimide, epoxy resin, etc., which has excellent mechanical properties and thermal stability and can be used as an important material for protecting semiconductor devices. The gap D2 of the inorganic passivation layer 207 is also fully filled by the organic passivation layer 208. The thickness of the organic passivation layer 208 is at least 5µm (micrometer) to 10µm (micrometer).

[0035] Fifth, if Fig.11 As shown, a photoresist is formed on the organic passivation layer, and the required portion of the organic passivation layer is obtained through exposure through the photoresist, thereby exposing the etching area.

[0036] Sixth, if Fig.12 As shown, after the etching and degumming process, an organic passivation layer 208 is formed and deposited on the inorganic passivation layer 207. The inner edge of the organic passivation layer 208 along the surface metal layer 206 does not completely cover the underlying inorganic passivation layer 207 and the surface metal layer 206, that is, part of the top surface and side surfaces of the inner inorganic passivation layer are not covered by the organic passivation layer 208, thereby preventing the organic passivation layer 208 from peeling off on the surface metal layer 206 due to insufficient adhesion; in addition, the side surfaces of the inorganic passivation layer 207 above the terminal region 201 of the organic passivation layer 208 are also covered with the organic passivation layer 208, so that the width of the exposed position of the oxidation isolation layer 205 changes from D1 to D3, where D3 is the width of the exposed position of the oxidation isolation layer 205. In another embodiment, the width of the position D3 can be completely covered by the organic passivation layer 208, but it also depends on the requirements of the subsequent wafer processing process for the cutting path and the terminal region structure not shown in this example.

[0037] Seventh, such as Fig.13 As shown, the wafer is subjected to chemical etching to roughen the exposed metal surface above the cell region 202, deposit catalysts and activate, and finally immersed in chemical plating solutions of different formulations to form chemically plated metal 209.

[0038] By arranging the inorganic passivation layer 207 and the organic passivation layer 208 of the present embodiment, a gap D2 is set. Even if the device undergoes a molding curing process to harden the molding resin 301 and generate stress, horizontal cracks will appear due to the lack of buffering effect of the organic passivation layer 208. However, since the gap D2 is filled with the organic passivation layer 208, it can prevent external impurity ions and water vapor from entering the surface metal layer 206 from the crack position. Therefore, the gap of the inorganic passivation layer 207 is filled with the organic passivation layer 208 with a distance length of D2, which can effectively prevent the cracks of the inorganic passivation layer 207 from extending to the terminal area 201 of the device, and prevent external impurity ions and water vapor from entering the device along with the cracks, thereby increasing the reliability of the device.

[0039] A variation of the present invention is as follows Fig.14 As shown, Fig.15 for Fig.14 The top view of the surface structure above the semiconductor device is different from the above embodiment in that: the outer inorganic passivation layer is divided into two sections, namely the first outer inorganic passivation layer 2073 and the second outer inorganic passivation layer 2074, wherein a first gap D2' is provided between the inner inorganic passivation layer 2071 and the first outer inorganic passivation layer 2073, and a second gap D4 is provided between the first outer inorganic passivation layer 2073 and the second outer inorganic passivation layer 2074, that is, a gap is added. This change is used to strengthen the above-mentioned role: as a barrier layer, it prevents the cracks of the inorganic passivation layer 207 from extending to the terminal area 201 of the device, thereby protecting the inside of the device.

[0040] Fig.16 Further improvement is made, the difference is that the pattern on the inorganic passivation layer 207 is changed, the first outer ring inorganic passivation layer 2073 is composed of multiple separated inorganic passivation areas, and a gap D5 is provided between each inorganic passivation area, so that the gap can be further expanded to obtain a longer gap path. Fig.16 The shape of each inorganic passivation area is H-shaped. Of course, it can also be other shapes that can increase the gap area, so that more organic passivation layer 208 can be filled, the contact area between the organic passivation layer 208 and the inorganic passivation layer 207 can be increased, and the chance of the organic passivation layer 208 being peeled off can be reduced.

[0041] Those skilled in the art should know that the above manufacturing steps only list key steps and do not show the complete steps of forming a device. Specific detailed manufacturing steps can be obtained based on common manufacturing process steps and common sense knowledge in the field and can be appropriately increased, decreased or changed.

[0042] In addition, those skilled in the art should know that the structural features and process steps mentioned in the above-mentioned embodiments of the present invention can be combined with each other to form more embodiment device structures and manufacturing processes.

Claims

1. A semiconductor device for preventing internal corrosion, the semiconductor device comprising a cell region and a terminal region surrounding the cell region, wherein a gate opening region and a source opening region are provided in the cell region; a chemically plated metal layer is deposited on the gate opening region and the source opening region, and a passivation layer is covered on the region outside the gate opening region and the source opening region, characterized in that: The passivation layer includes an inorganic passivation layer and an organic passivation layer located above the inorganic passivation layer, the inorganic passivation layer includes an inner circle inorganic passivation layer surrounding the adjacent chemically plated metal layer and at least one outer circle inorganic passivation layer located outside the inner circle inorganic passivation layer, a gap D2 is provided between the inner circle inorganic passivation layer and the outer circle inorganic passivation layer, and the organic passivation layer fills the gap D2 downward.

2. The semiconductor device for preventing internal corrosion according to claim 1, characterized in that: The gap D2 is in the shape of a straight bar, a curve, or a combination of the above shapes.

3. The semiconductor device for preventing internal corrosion according to claim 1, characterized in that: The outer ring inorganic passivation layer includes a first outer ring inorganic passivation layer and a second outer ring inorganic passivation layer located outside the first outer ring inorganic passivation layer. A gap D4 is provided between the first outer ring inorganic passivation layer and the second outer ring inorganic passivation layer, and the organic passivation layer fills the gap D4 downward.

4. The semiconductor device for preventing internal corrosion according to claim 3, characterized in that: The gap D4 is in the shape of a straight bar, a curve, or a combination of the above shapes.

5. The semiconductor device for preventing internal corrosion according to claim 3, characterized in that: The first outer ring inorganic passivation layer is composed of a plurality of isolated inorganic passivation regions, a gap D5 is provided between each of the inorganic passivation regions, and the organic passivation layer fills the gap D5 downward.

6. The semiconductor device for preventing internal corrosion according to claim 5, characterized in that: The first outer ring inorganic passivation layer is H-shaped.

7. The semiconductor device for preventing internal corrosion according to claim 1, characterized in that: The semiconductor device is a laterally diffused metal oxide semiconductor, a vertically diffused metal oxide semiconductor, an insulated gate bipolar transistor or a diode.

8. A method for preparing a semiconductor device to prevent internal corrosion, characterized in that: The preparation method comprises the following steps: First, an inorganic passivation layer is formed on the surface metal layer and the oxide isolation layer, and the thickness of the inorganic passivation layer is 2-10µm; Second, a photoresist is formed on the inorganic passivation layer, and the required portion of the inorganic passivation layer is obtained through exposure on the photomask, thereby exposing the area to be etched; Third, the inorganic passivation layer is subjected to a vertical etching process from the surface downward until the opening position of the surface metal layer and the surface opening position of the oxide isolation layer are respectively etched, and then the photoresist is removed; Fourth, an organic passivation layer is coated on the upper surface of the device, and the gap D2 of the inorganic passivation layer is also fully filled by the organic passivation layer, and the thickness of the organic passivation layer is 5-10µm; Fifth, a photoresist is formed on the organic passivation layer, and the required portion of the organic passivation layer is obtained through exposure on the photomask, thereby exposing the area to be etched; Sixth, after the etching and degumming process, an organic passivation layer is formed and deposited on the inorganic passivation layer, and the organic passivation layer does not cover a portion of the top surface and side surfaces of the inner circle inorganic passivation layer; Seventh, the wafer is subjected to chemical etching to roughen the exposed metal surface above the cell area, deposit catalyst and activate, and finally immersed in chemical plating solution to form chemically plated metal.

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