Lead frame package with enhanced wiring capability

Abstract

A semiconductor chip package includes a semiconductor chip having a first side and a second side opposite the first side. The first side includes a chip pad. The semiconductor chip package includes a first lead frame structured to form a footprint of the semiconductor chip package. The semiconductor chip package further includes a structured metal plate disposed between the first lead frame and the semiconductor chip, wherein the first side of the semiconductor chip faces the structured metal plate. A pattern of bonding material is disposed between the first lead frame and the structured metal plate. The pattern of bonding material is configured to electrically and mechanically connect the structure of the first lead frame to the structure of the structured metal plate. The semiconductor chip package includes a molding compound embedded in the first lead frame, the structured metal plate, and the semiconductor chip.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor packaging technology, and in particular to lead frame packaging. Background Art

[0002] Packaging technology can have a significant impact on device performance. A packaging concept can aim to provide high routing capability, high variability in footprint design, good board-level reliability (e.g., high thermal cycle on board (TCoB) performance), and good heat dissipation within the board, as well as low assembly cost. In addition, especially for power applications, the packaging concept should provide low package inductance and low spreading resistance in the board routing, which is disadvantageous for customers because they may not be able to enjoy the low R of, for example, a power transistor device. DS(on) .

[0003] To overcome some of the above disadvantages, packaging solutions based on laminates are used. In this way, the footprint design of the device is no longer limited by the pad layout of the chip. However, the use of laminates in packaging leads to higher packaging costs and limitations in the soldering materials that can be used. In addition, due to the relatively low metal thickness of the redistribution layer in the laminate, it is difficult to obtain low package resistance. Summary of the invention

[0004] According to one aspect of the present disclosure, a semiconductor chip package includes a semiconductor chip having a first side and a second side opposite to the first side, wherein the first side includes a chip pad. The semiconductor chip package includes a first lead frame, which is structured to form a footprint of the semiconductor chip package. The semiconductor chip package also includes a structured metal plate disposed between the first lead frame and the semiconductor chip, wherein the first side of the semiconductor chip faces the structured metal plate. A pattern of a bonding material is disposed between the first lead frame and the structured metal plate, wherein the pattern of the bonding material is configured to electrically and mechanically connect the structure of the first lead frame to the structure of the structured metal plate. The semiconductor chip package also includes a molding compound embedded in the first lead frame, the structured metal plate, and the semiconductor chip.

[0005] According to another aspect of the present disclosure, a method for manufacturing a semiconductor chip package includes bonding a first lead frame structured to form a footprint of the semiconductor chip package to a second lead frame structured to align with a chip pad of the semiconductor chip. A semiconductor chip having a first side and a second side opposite the first side is attached to the second lead frame with a chip pad, wherein the first side includes the chip pad. The first lead frame, the second lead frame, and the semiconductor chip are embedded in a molding compound.

[0006] According to another aspect of the present disclosure, a method for manufacturing a semiconductor chip package includes attaching a semiconductor chip having a first side and a second side opposite the first side to a second lead frame with a chip pad, wherein the first side includes the chip pad. The second lead frame and the semiconductor chip are embedded in a molding compound. The first lead frame structured to form a footprint of the semiconductor chip package is bonded to the second lead frame.

[0007] According to another aspect of the present disclosure, a method for manufacturing a semiconductor chip package includes bonding a first lead frame structured to form a footprint of the semiconductor chip package to a metal plate. The first lead frame is embedded in a pre-molding compound. The metal plate is structured to provide a structured metal plate. A semiconductor chip having a first side and a second side opposite the first side is attached to the structured metal plate with a chip pad, wherein the first side includes the chip pad. The first lead frame, the structured metal plate, and the semiconductor chip are embedded in a molding compound. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the accompanying drawings, the same reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they are mutually exclusive, and / or may be selectively omitted if not necessarily required for description. The embodiments are depicted in the accompanying drawings and are exemplarily described in detail in the following description.

[0009] Figure 1 is a perspective exploded view of an example of a semiconductor chip package without a molding compound.

[0010] Figure 2 is a plan view of a first side of an example of a semiconductor chip, illustrating an exemplary layout of source, drain, and gate pads.

[0011] Figure 3 is a perspective view of a footprint side of an example of a semiconductor chip package.

[0012] Figure 4 is a perspective exploded view of an example of a semiconductor chip package without a molding compound, the chip package including a plurality of semiconductor chips.

[0013] Figure 5 is a perspective view of a footprint side of an example of a semiconductor chip package including a plurality of semiconductor chips.

[0014] Figure 6 A method of manufacturing a semiconductor chip package is illustrated using exemplary stages of forming a stack including a plurality of lead frames and molding.

[0015] Figure 7 An exemplary stage of a method of manufacturing a semiconductor chip package using pre-molding including a stack of a plurality of lead frames is illustrated.

[0016] Figure 8 Exemplary stages of a method of manufacturing a semiconductor chip package using molding including a lead frame and a stack of semiconductor chips are illustrated.

[0017] Fig. 9 Exemplary stages of a method of manufacturing a semiconductor chip package using forming a stack comprising a lead frame and a metal plate and structuring the metal plate are illustrated. DETAILED DESCRIPTION

[0018] As used in this specification, the term "electrically connected" or "electrically coupled" or similar terms are not meant to mean that elements are directly in contact together; intermediate elements may be provided between the "electrically connected" or "electrically coupled" elements, respectively. However, according to the present disclosure, the above-mentioned and similar terms may also optionally have a specific meaning that the elements are directly in contact together, that is, no intermediate elements are provided between the "electrically connected" or "electrically coupled" elements, respectively.

[0019] In addition, the words "above" or "below" with respect to a component, element or material layer formed or located or arranged "above" or "below" a surface may be used herein to mean that the component, element or material layer is located (e.g., placed, formed, arranged, deposited, etc.) "directly on the implied surface" or "directly below the implied surface", such as in direct contact with it. However, the words "above" or "below" used with respect to a component, element or material layer formed or located or arranged "above" or "below" a surface may alternatively be used herein to mean that the component, element or material layer is located (e.g., placed, formed, arranged, deposited, etc.) "indirectly on the implied surface" or "indirectly below the implied surface", with one or more additional components, elements or layers arranged between the implied surface and the component, element or material layer.

[0020] refer to Figures 1 to 3 , the semiconductor chip package 100 includes a semiconductor chip 120. The semiconductor chip 120 has a first side 120A (see Figure 2 ) and a second side 120B opposite to the first side 120A.

[0021] The semiconductor chip package 100 further includes a first lead frame 140. The first lead frame 140 is structured to form a footprint of the semiconductor chip package 100.

[0022] The semiconductor chip package 100 further includes a structured metal plate 160 disposed between the first lead frame 140 and the semiconductor chip 120 . The first side 120A of the semiconductor chip 120 faces the structured metal plate 160 .

[0023] For example, the structured metal sheet 160 may be Figure 1However, in other examples (e.g., see Fig. 9 ), the structured metal plate 160 is not a lead frame.

[0024] A pattern of bonding material 170 is disposed between the first lead frame 140 and the structured metal plate 160. The pattern of bonding material 170 is configured to electrically and mechanically connect structures of the first lead frame 140 to structures of the structured metal plate 160.

[0025] like Figure 3 As shown, the first lead frame 140 , the structured metal plate 160 and the semiconductor chip 120 are embedded in a molding compound 180 .

[0026] In the following, without loss of generality, the structured metal plate 160 is sometimes referred to as a second lead frame 160 , keeping in mind that non-lead frame type structured metal plates 160 may also be used.

[0027] For example, all chip pads of the semiconductor chip may be disposed on the first side 120A of the semiconductor chip 120 . Figure 2 An exemplary layout of chip pads 122_1 , 122_2 , 122_3 on a first side 120A of an exemplary semiconductor chip 120 is shown. For example, the semiconductor chip 120 may be a transistor chip, such as a power transistor chip. For example, the semiconductor chip 120 may be a horizontal device.

[0028] The layout of the chip pads 122_1, 122_2, 122_3 may include a plurality of source pads (S) 122_2 and a plurality of drain pads (D) 122_1. In addition, a gate pad (G) 122_3 may be provided. In the following, the chip pad layout is described by taking a power transistor chip 120, such as a GaN device, as an example. However, the following description is also applicable to other semiconductor chips 120 that are not transistor chips and / or are not power devices and / or are not horizontal devices but vertical devices. For example, the present disclosure may also include an IC (integrated circuit) chip that also provides a plurality of chip pads on the first side 120A of the semiconductor chip 120.

[0029] Back to Figure 2 , the plurality of source pads (S) 122_2 may be arranged, for example, in a plurality of (horizontal) rows parallel to the longitudinal sides of the semiconductor chip 120. Similarly, the plurality of drain pads (D) 122_1 may be arranged in a plurality of (horizontal) rows parallel to the rows of the source pads (S) 122_2. Figure 2In the example shown, the rows of source pads (S) 122_2 and the rows of drain pads (D) 122_1 are, for example, interlaced and / or alternating. In other examples, multiple rows (e.g., 2 rows) of source pads (S) 122_2 and multiple rows (e.g., 2 rows) of drain pads (D) 122_1 can be, for example, interlaced and / or alternating.

[0030] In addition, the source pad (S) 122_2 and the drain pad (D) 122_1 may be offset from each other, for example, in the longitudinal (horizontal) direction. In other examples, the source pad (S) 122_2 and the drain pad (D) 122_1 may be aligned with each other, for example, in the longitudinal (horizontal) direction. The gate pad (G) 122_3 may be arranged at a corner of the semiconductor chip 120 and may be formed, for example, by a single gate pad (G).

[0031] The (exemplary) layout of the chip pads S, D, G obviously needs to be re-routed through the package internal interconnects in order to provide, for example Figure 3 The layout of the package terminal pads 140_1 , 140_2 , and 140_3 is shown. The rewiring is performed by the second lead frame 160 .

[0032] For example, the second leadframe 160 (or more generally, the structured metal plate) may include one or more first structures 160_1, one or more second structures 160_2, and one or more third structures 160_3. In the example shown, the plurality of first structures 160_1 are configured to be connected to the source pad 122_2 of the semiconductor chip 120, and thus reroute the source load current in the semiconductor chip package 100. In the example shown, the plurality of second structures 160_2 are configured to be connected to the drain pad 122_1 of the semiconductor chip 120, and thus reroute the drain load current in the semiconductor chip package 100. In addition, the third structure 160_3 may be connected to the gate pad 122_3 of the semiconductor chip 120, and may, for example, be configured to reroute the gate signal in the semiconductor chip package 100.

[0033] For example, a pattern of the bonding material 170 disposed between the first lead frame 140 and the second lead frame 160 electrically connects, for example, the first structure 160_1 to the first package terminal pad (S) 140_1, the second structure 160_2 to the second package terminal pad (D) 140_2, and the third structure 160_3 to the third package terminal pad (G) 140_3.

[0034] The bonding material 170 may include or be a solder material, a conductive adhesive, a metal paste or a diffusion solder material. In particular, a solder having a relatively high reflow temperature, such as, for example, a lead-based solder, may be used.

[0035] The higher the reflow temperature of the solder used in the semiconductor chip package 100, the easier the package assembly at the customer's board is. On the other hand, conventional laminate packages require the use of lead-free solders, such as, for example, SAC solder (tin-silver-copper alloy). The reflow temperature of SAC solder is relatively low, and therefore may remelt during customer board assembly, resulting in quality problems (package delamination) in conventional laminate-based packages.

[0036] like Figure 1 As shown, the first lead frame 140 can be structured to form a plurality of separated longitudinal segments (e.g., package terminal pads (S) 140_1 and package terminal pads (D) 140_2) extending in a first lateral direction, and the second lead frame (structured metal plate) 160 can be structured to form a plurality of separated longitudinal segments (e.g., first structures 160_1 and second structures 160_2) extending in a second lateral direction. The first lateral direction and the second lateral direction can be different from each other. The first lateral direction and the second lateral direction can be, for example, perpendicular to each other. Reference Figure 1 The first lateral direction may, for example, be a longitudinal direction of the semiconductor chip package 100 , and the second lateral direction may, for example, be a transverse lateral direction of the semiconductor chip package 100 .

[0037] In the example shown, the second lead frame 160 is exposed at the side wall of the package 100. In other examples, the second lead frame 160 may not be exposed at the side wall of the package 100. Specifically, the second lead frame 160 may be, for example, completely embedded in (covered by) the mold compound 180. This may help meet creepage distance requirements and can make installation at the customer's site easier.

[0038] refer to Figure 4 and Figure 5 , an example of a semiconductor chip package 400 may include a plurality of semiconductor chips 120_1, 120_2. The first lead frame 440 may be structured to include a first package terminal pad (Vin) 440_1, a second package terminal pad (GND) 440_2, a third package terminal pad (SW) 440_3, a fourth package terminal pad (G1) 440_4, and a fifth package terminal pad (G2) 440_5. In the example shown, the third package terminal pad (SW) 440_3 is a structure of the first lead frame 440, which is connected to the chip pads of at least two semiconductor chips 120_1, 120_2 via the structure of the second lead frame (structured metal plate) 160.

[0039] The semiconductor chip package 400 may, for example, implement a half-bridge circuit. In the half-bridge circuit, the first package terminal pad 440_1 may be connected to an input voltage Vin, the second package terminal pad 440_2 may be connected to ground (GND), and the third package terminal pad 440_3 may be a switch (SW) node of the circuit. The fourth package terminal pad 440_4 may be a gate terminal (G1) connected to the gate pad 122_3 of the first semiconductor chip 120_1 via the structure of the second lead frame 160, and the fifth package terminal pad 440_5 may be a second gate terminal (G2) connected to the gate pad 122_3 of the second semiconductor chip 120_2 via the structure of the second lead frame 160.

[0040] In all examples disclosed herein, the transistor chip(s) 120, 120_1, 120_2 may, for example, be capable of switching high current and / or medium or high voltage (e.g., a blocking voltage greater than 50 V or 100 V or 200 V or 300 V or 400 V or 500 V). In particular, the exemplary transistor packages as disclosed herein may operate in the medium voltage (MV) range, with a blocking voltage equal to or greater than or less than 200 V or 150 V or 100 V or 50 V.

[0041] The (power) transistor chips 120 may be of different types. For example, the examples described herein particularly relate to HEMT (high electron mobility transistor) devices. The (one or more) semiconductor transistor chips 120, 120_1, 120_2 disclosed herein may, for example, be III-V compound semiconductor chips having, for example, a high band gap. The power transistor chips 120, 120_1, 120_2 may, for example, be GaN chips. In this case, the GaN chips 120, 120_1, 120_2 may, for example, be lateral GaN devices on substrates, such as GaN devices on Si or GaN devices on SiC or GaN devices on sapphire.

[0042] In all examples disclosed herein, the second lead frame (or structured metal plate) 160 may have a thickness equal to or greater than 150 μm or 200 μm or 250 μm or 500 μm or 900 μm or 1.27 mm or 2.0 mm.

[0043] Figures 6 to 9 Various exemplary methods of manufacturing semiconductor chip packages 100, 400 are illustrated. Figure 6 , a first lead frame 140 and a second lead frame 160 are provided.

[0044] At S1_1a, a bonding material 170 is applied to the second lead frame 160. For example, the bonding material 170 applied at S1_1a may be a solder material, a conductive adhesive, or a metal paste.

[0045] Alternatively, at S1_1b, a bonding material 170 suitable for forming a diffusion solder connection may be applied to the second lead frame 160. The bonding material applied at S1_1b is a diffusion solder material such as, for example, NiSn or AuSn.

[0046] As from Figure 6 As can be clearly seen in FIG. 1 , the bonding material 170 can be applied to each of the separate structures 160_1, 160_2, 160_3 (see FIG. 1 ). Figure 1 ).

[0047] In other examples, the bonding material 170 may be applied to the first lead frame 140 instead of the second lead frame 160 .

[0048] At S1_2a, the first lead frame 140 is attached to the second lead frame 160 by a suitable attachment process, depending on the type of bonding material 170 used. For example, a reflow process (soldering material) or a curing process (conductive adhesive) may be used.

[0049] At S1_2b, the first lead frame 140 is welded to the second lead frame 160 by diffusion welding.

[0050] As a result of S1_2a or S1_2b, a stack of two interconnected leadframes 140, 160 is produced. The stack of leadframes 140, 160 may include partial or full package internal rewiring from chip pads 122_1, 122_2, 122_3 to package terminal pads 140_1, 140_2, 140_3 or 440_1, 440_2, 440_3, 440_4, 440_5.

[0051] At S1_3 , the stack of lead frames 140 , 160 may be flipped. After S1_3 , the second lead frame 160 is the top lead frame of the lead frame stack 140 , 160 .

[0052] At S1_4, one or more semiconductor chips 120 are attached to the stack of lead frames 140, 160. In the example shown, for example, four semiconductor chips 120 are attached. However, depending on the size and cost of the stack of lead frames 140, 160, any number of semiconductor chips 120 may be attached to the stack of lead frames 140, 160.

[0053] At S1_5 , the first lead frame 140 , the second lead frame 160 , and the semiconductor chip 120 are embedded in the mold compound 180 .

[0054] Furthermore, S1_5 may include (optional) electroplating of package terminal pads 140_1 - 3 , 440_1 - 5 and semiconductor chip package singulation.

[0055] The separation of the semiconductor chip package 100 may include separating (eg, sawing) the molded body into desired semiconductor chip packages 100 , 400 .

[0056] Figure 7 An example of another method of manufacturing a semiconductor chip package 100, 400 is illustrated. The method may start with the same process as described above, ie S2_1a, S2_1b, S2_2a and S2_2b may correspond to S1_1a, S1_1b, S1_2a and S1_2b respectively. Reference is made to the above description to avoid repetition.

[0057] At S2_3 , after the first lead frame 140 is bonded to the second lead frame 160 , the first lead frame 140 and the second lead frame 160 are embedded in a pre-mold compound 780 .

[0058] S2_4 and S2_5 correspond to processes S1_4 and S1_5 described above, and reference is made to the above description to avoid repetition. More specifically, at S2_4, the semiconductor chip 120 is attached to the pre-molded stack of lead frames 140, 160. S2_5 may include molding the pre-molded stack of lead frames 140, 160 to apply the final molding compound 180, optional electroplating, and semiconductor chip package singulation, as described in conjunction with S1_5.

[0059] Figure 8 An example of another method of manufacturing a semiconductor chip package 100, 400 is illustrated. A second lead frame 160 and one or more semiconductor chips 120 are provided. At S3_1, the one or more semiconductor chips 120 are attached to the second lead frame 160. Again, the semiconductor chips 120 are flip-chip attached to the second lead frame 160, i.e., attached to the second lead frame 160 with their first side 120A (on which the chip pads 122_1, 122_2, 122_3 are located).

[0060] At S3_2 , the second lead frame 160 and the semiconductor chip 120 are embedded in the mold compound 180 . Figure 8 A view of the side of the mold compound 180 facing the footprint of the subsequent semiconductor chip package 100 , 400 is illustrated.

[0061] At S3_3, a pattern of bonding material 170 can be applied to the structures of the second lead frame 160 exposed at the mold compound 180. As described above, the bonding material 170 can be, for example, a conventional die attach material (e.g., a solder material, a conductive adhesive, a metal paste) or a tin-based material, such as, for example, a diffusion solder material, such as NiSn or AuSn. For example, applying the pattern of bonding material at S3_3 can include an electroplating process. For example, all structures of the second lead frame 160 exposed at the mold compound 180 are fully electroplated.

[0062] At S3_4 , the first lead frame 140 is bonded to the second lead frame 160 .

[0063] At S3_5, an (optional) process of applying an underfill material to the footprint side of the semiconductor chip package 100, 400 may be performed. The underfill material may be used to further protect (cover) the bonding material area at the footprint side of the semiconductor chip package 100, 400. For example, an underfill material (not shown) may be applied along the grooves in the first lead frame 140 by a dispenser, and these grooves may be filled with an insulating polymer material by capillary force (i.e., without the need for a second molding process).

[0064] S3_5 may further include electroplating and semiconductor chip package singulation processes, as described above in combination with S1_5 and S2_5.

[0065] Fig. 9 An example of a method of manufacturing a semiconductor chip package 100, 400 is illustrated. A first lead frame 140 and a metal plate 960 may be provided. For example, the metal plate 960 may be an unstructured continuous metal plate.

[0066] At S4_1, a pattern of bonding material 170 may be applied between the first lead frame 140 structured to form the footprint of the semiconductor chip package 100, 400 and the metal plate 960. In the example shown, for example, the bonding material 170 is applied to the first lead frame 140. The bonding material 170 as described above may be used.

[0067] At S4_2, the first lead frame 140 is bonded to the metal plate 960. Any of the above-described processes may be used.

[0068] At S4_3, the first lead frame 140 is embedded in the pre-mold compound 980. In addition, a mask layer is applied to the side of the metal plate 960 opposite to the side to which the first lead frame 140 has been attached. Fig. 9 As shown, a mask layer (eg, a photoresist layer) is structured to provide a structured mask layer 990. The structuring of the mask layer may be performed by a photolithography process.

[0069] After patterning the metal plate 960 corresponding to the structured mask layer 990, the metal plate 960 is etched at S4_4. As a result, a structured metal plate 160 (corresponding to the second lead frame 160) is generated. In addition, still at S4_4, the structured mask layer (e.g., photoresist) can be removed. In this way, the structured metal plate 160 is exposed and ready for semiconductor chip attachment.

[0070] Optionally, as previously described, an underfill material may be applied between the grooves of the structured metal sheet 160 .

[0071] At S4_5 , one or more semiconductor chips 120 are attached to the structured metal plate 160 with their chip pads in a flip-chip configuration.

[0072] At S4_6, the first lead frame 140, the structured metal plate 160 and the semiconductor chip(s) 120 are embedded in the mold compound 180. Furthermore, semiconductor chip package singulation may be performed as described above in conjunction with S1_5, S2_5, S3_5.

[0073] For examples in which a semiconductor transistor chip 120 is used, the face-down orientation of the transistor chip 120 in combination with a first lead frame to structured metal plate (or second lead frame) stack, which first lead frame to structured metal plate (or second lead frame) stack can be used as a routable substrate for the semiconductor chip package 100, 400, allowing the semiconductor chip package footprint to be aligned with the footprint of a conventional MOSFET (metal oxide semiconductor field effect transistor) package, however, the conventional MOSFET package cannot meet the high current transfer and / or fast switching requirements of the semiconductor chip packages 100, 400 described herein.

[0074] Example

[0075] The following examples relate to further aspects of the present disclosure:

[0076] Example 1 is a semiconductor chip package. The semiconductor chip package includes a semiconductor chip having a first side and a second side opposite to the first side. The first side includes a chip pad. The semiconductor chip package includes a first lead frame, which is structured to form a footprint of the semiconductor chip package. The semiconductor chip package also includes a structured metal plate disposed between the first lead frame and the semiconductor chip, wherein the first side of the semiconductor chip faces the structured metal plate. A pattern of bonding material is disposed between the first lead frame and the structured metal plate. The pattern of bonding material is configured to electrically and mechanically connect the structure of the first lead frame to the structure of the structured metal plate. The semiconductor chip package includes a molding compound embedded in the first lead frame, the structured metal plate, and the semiconductor chip.

[0077] In Example 2, the subject matter of Example 1 can optionally include, wherein all chip pads of the semiconductor chip are disposed on the first side of the semiconductor chip.

[0078] In Example 3, the subject matter of Example 1 or 2 may optionally include, wherein the semiconductor chip is a power chip, in particular a power transistor chip, more particularly a GaN transistor chip.

[0079] In Example 4, the subject matter of any of the preceding examples can optionally include wherein the structured metal plate is a second lead frame.

[0080] In Example 5, the subject matter of any of the preceding examples can optionally include wherein the pattern of bonding material is formed of at least one of the group consisting of a solder material, a conductive adhesive, a metal paste, or a diffusion solder material.

[0081] In Example 6, the subject matter of any of the preceding examples may optionally include wherein the first lead frame is structured to form a plurality of separate longitudinal segments extending in a first lateral direction, and the structured metal plate is structured to form a plurality of separate longitudinal segments extending in a second lateral direction, the first lateral direction and the second lateral direction being different from each other.

[0082] In Example 7, the subject matter of any preceding example can optionally include wherein the chip package includes a plurality of semiconductor chips, and the structure of the first lead frame is connected to chip pads of at least two of the semiconductor chips via the structure of the structured metal plate.

[0083] Example 8 is a method for manufacturing a semiconductor chip package. The method includes joining a first lead frame structured to form a footprint of the semiconductor chip package to a second lead frame structured to align with a chip pad of the semiconductor chip. A semiconductor chip having a first side and a second side opposite the first side is attached to the second lead frame with a chip pad, wherein the first side includes the chip pad. The first lead frame, the second lead frame, and the semiconductor chip are embedded in a molding compound.

[0084] In Example 9, the subject matter of Example 8 can optionally further include applying a pattern of bonding material between the first lead frame and the second lead frame, wherein the pattern of bonding material is configured to electrically and mechanically connect structures of the first lead frame to structures of the second lead frame.

[0085] In Example 10, the subject matter of Example 8 or 9 can optionally further include, after bonding the first lead frame to the second lead frame and before attaching the semiconductor chip to the second lead frame, embedding the first lead frame and the second lead frame in a pre-mold compound.

[0086] In Example 11, a method of manufacturing a semiconductor chip package. The method includes attaching a semiconductor chip having a first side and a second side opposite the first side to a second lead frame with a die pad, wherein the first side includes the die pad. The second lead frame and the semiconductor chip are embedded in a molding compound. The first lead frame structured to form a footprint of the semiconductor chip package is bonded to the second lead frame.

[0087] In Example 12, the subject matter of Example 11 may optionally further include applying a pattern of bonding material between the first lead frame and the second lead frame after embedding the second lead frame and the semiconductor chip in the molding compound and before bonding the first lead frame to the second lead frame, wherein the pattern of bonding material is configured to electrically and mechanically connect the structure of the first lead frame to the structure of the second lead frame.

[0088] Example 13 is a method for manufacturing a semiconductor chip package. The method includes bonding a first lead frame structured to form a footprint of the semiconductor chip package to a metal plate. The first lead frame is embedded in a pre-molding compound. The metal plate is structured to provide a structured metal plate. A semiconductor chip having a first side and a second side opposite the first side is attached to the structured metal plate with a chip pad, wherein the first side includes the chip pad. The first lead frame, the structured metal plate, and the semiconductor chip are embedded in a molding compound.

[0089] In Example 14, the subject matter of Example 13 can optionally further include applying a pattern of bonding material between the first lead frame and the metal plate, wherein the pattern of bonding material is configured to electrically and mechanically connect the structure of the first lead frame to an area of ​​the metal plate corresponding to the structure of the structured metal plate.

[0090] In Example 15, the subject matter of any one of Examples 8 to 14 can optionally include wherein the second lead frame or the metal plate has a thickness equal to or greater than 150 μm or 200 μm or 250 μm or 500 μm or 900 μm or 1.27 mm or 2.0 mm.

[0091] In Example 16, the subject matter of any one of Examples 8 to 15 may optionally include, wherein the first lead frame is structured to form a plurality of separate longitudinal segments extending in a first lateral direction, and the second lead frame or structured metal plate is structured to form a plurality of separate longitudinal segments extending in a second lateral direction, the first lateral direction and the second lateral direction being different from each other.

[0092] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor chip package, comprising: a semiconductor chip having a first side and a second side opposite the first side, wherein the first side includes a chip pad; a first leadframe structured to form a footprint of a semiconductor chip package; a structured metal plate disposed between the first lead frame and the semiconductor chip, wherein a first side of the semiconductor chip faces the structured metal plate; a pattern of bonding material disposed between the first lead frame and the structured metal plate, wherein the pattern of bonding material is configured to electrically and mechanically connect structures of the first lead frame to structures of the structured metal plate; and A molding compound embeds the first lead frame, the structured metal plate and the semiconductor chip.

2. The semiconductor chip package according to claim 1, wherein: All chip pads of the semiconductor chip are arranged on a first side of the semiconductor chip.

3. The semiconductor chip package according to claim 1 or 2, wherein: The semiconductor chip is a power chip, in particular a power transistor chip, and more particularly a GaN transistor chip.

4. The semiconductor chip package according to any one of the preceding claims, wherein: The structured metal plate is a second lead frame.

5. The semiconductor chip package according to any one of the preceding claims, wherein: The pattern of the bonding material is formed of at least one of the group consisting of a solder material, a conductive adhesive, a metal paste, or a diffusion solder material.

6. The semiconductor chip package according to any one of the preceding claims, wherein: The first lead frame is structured to form a plurality of separate longitudinal segments extending in a first lateral direction, and the structured metal sheet is structured to form a plurality of separate longitudinal segments extending in a second lateral direction, the first lateral direction and the second lateral direction being different from each other.

7. The semiconductor chip package according to any one of the preceding claims, wherein: The chip package includes a plurality of semiconductor chips, and the structure of the first lead frame is connected to chip pads of at least two semiconductor chips via the structure of the structured metal plate.

8. A method for manufacturing a semiconductor chip package, comprising: bonding a first lead frame structured to form a footprint of a semiconductor chip package to a second lead frame structured to align with a chip pad of the semiconductor chip; attaching a semiconductor chip having a first side and a second side opposite the first side to the second lead frame with a die pad, wherein the first side includes the die pad; and The first lead frame, the second lead frame and the semiconductor chip are embedded in a molding compound.

9. The method according to claim 8, further comprising: A pattern of bonding material is applied between the first lead frame and the second lead frame, wherein the pattern of bonding material is configured to electrically and mechanically connect structures of the first lead frame to structures of the second lead frame.

10. The method according to claim 8 or 9, further comprising: After bonding the first lead frame to the second lead frame and before attaching the semiconductor chip to the second lead frame, the first lead frame and the second lead frame are embedded in a pre-mold compound.

11. A method for manufacturing a semiconductor chip package, comprising: attaching a semiconductor chip having a first side and a second side opposite the first side to the second lead frame with a die pad, wherein the first side includes the die pad; embedding the second lead frame and the semiconductor chip in a molding compound; and The first lead frame structured to form a footprint of the semiconductor chip package is bonded to a second lead frame.

12. The method according to claim 11, further comprising: After embedding the second lead frame and the semiconductor chip in the molding compound and before bonding the first lead frame to the second lead frame, a pattern of bonding material is applied between the first lead frame and the second lead frame, wherein the pattern of bonding material is configured to electrically and mechanically connect the structure of the first lead frame to the structure of the second lead frame.

13. A method for manufacturing a semiconductor chip package, comprising: bonding a first lead frame structured to form a footprint of a semiconductor chip package to a metal plate; embedding the first lead frame in a pre-mold compound; structuring the metal sheet to provide a structured metal sheet; attaching a semiconductor chip having a first side and a second side opposite the first side to the structured metal plate with a chip pad, wherein the first side includes the chip pad; and The first lead frame, the structured metal plate and the semiconductor chip are embedded in a molding compound.

14. The method according to claim 13, further comprising: A pattern of bonding material is applied between the first lead frame and the metal plate, wherein the pattern of bonding material is configured to electrically and mechanically connect structures of the first lead frame to areas of the metal plate corresponding to structures of the structured metal plate. 15 . The method according to claim 8 , wherein the second lead frame or the metal plate has a thickness equal to or greater than 150 μm, 200 μm, 250 μm, 500 μm, 900 μm, 1.27 mm, or 2.0 mm.

16. The method according to any one of claims 8 to 15, wherein: The first lead frame is structured to form a plurality of separate longitudinal segments extending in a first lateral direction, and the second lead frame or the structured metal plate is structured to form a plurality of separate longitudinal segments extending in a second lateral direction, the first lateral direction and the second lateral direction being different from each other.

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