A driving circuit for suppressing crosstalk in GaN HEMT bridge arms

Abstract

This invention discloses a driving circuit for suppressing crosstalk in GaN HEMT bridge arms. The invention incorporates upper and lower bridge arm crosstalk suppression circuits within the high and low-side driving circuits, respectively. The upper bridge arm crosstalk suppression circuit absorbs positive voltage spike crosstalk in the high-side driving circuit when the power transistor is on, and absorbs negative voltage spike crosstalk in the high-side driving circuit when the power transistor is off. Similarly, the lower bridge arm crosstalk suppression circuit absorbs positive voltage spike crosstalk in the low-side driving circuit when the power transistor is on, and absorbs negative voltage spike crosstalk in the low-side driving circuit when the power transistor is off. This invention effectively suppresses upper and lower bridge arm crosstalk, protects the gate of the GaN HEMT power device, and improves the reliability of the GaN HEMT half-bridge driving circuit.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, and particularly relates to a drive circuit for suppressing crosstalk in GaN HEMT bridge arms. Background Technology

[0002] With the rapid development of semiconductor technology, third-generation wide-bandgap power semiconductor devices, represented by GaN (gallium nitride) HEMT (high electron mobility transistor), have demonstrated excellent performance in high-speed switching applications due to their significant advantages of low on-resistance and low parasitic capacitance. They have significantly reduced the switching and conduction losses of power devices, opening up broad application prospects for the field of high power density converters.

[0003] In a half-bridge driver circuit composed of GaN HEMTs, this device serves as the core switching unit. While its rapid turn-on characteristic improves system efficiency, it also presents potential problems. Specifically, the tiny parasitic capacitance of GaN HEMTs accelerates the conduction process, but it also causes a sharp rise in the drain-source voltage of the GaN HEMT on the opposite side when one side of the GaN HEMT rapidly hard-turns on. This rapidly rising voltage is coupled to the drive turn-off circuit through the transfer capacitor. Due to the impedance in the circuit, this leads to an unexpected increase in the gate voltage. When the voltage rise exceeds the threshold voltage, it will cause the GaN HEMT, which should be in the turn-off state, to conduct due to crosstalk, significantly increasing conduction losses and even causing shoot-through under high voltage conditions, jeopardizing device reliability and system stability.

[0004] On the other hand, when one GaN HEMT in the half-bridge circuit performs a hard turn-off operation, the other GaN HEMT enters a reverse freewheeling state, accompanied by a rapid drop in drain-source voltage. During this process, a reverse current is generated in the turn-off circuit through the current extraction effect of the transfer capacitor. This current, also affected by the circuit impedance, forms a negative voltage at the gate. If the negative voltage exceeds the HEMT gate withstand limit, it will trigger reverse overvoltage breakdown, posing a direct threat to device safety.

[0005] Traditional strategies, such as slowing down the switching speed of devices, can suppress crosstalk conduction to some extent, but at the expense of switching efficiency; directly reducing the impedance of the turn-off circuit is effective, but it is easy to cause turn-off overvoltage and EMI (electromagnetic interference) noise problems; while using negative voltage turn-off technology may exacerbate the risk of reverse overvoltage breakdown. Summary of the Invention

[0006] The purpose of this invention is to provide a driving circuit for suppressing crosstalk in GaN HEMT bridge arms without affecting the switching speed of GaN power transistors, increasing switching losses, or adding extra control signals. This circuit can effectively suppress crosstalk caused by the gate-source voltage of GaN power transistors in half-bridge circuits, thereby keeping the positive and negative crosstalk voltages within safe thresholds, thus solving the technical problems mentioned in the background art.

[0007] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0008] A driving circuit for suppressing crosstalk in GaN HEMT bridge arms is provided. The driving circuit is connected in the GaN HEMT bridge arm, which includes an upper bridge arm circuit and a lower bridge arm circuit. The upper bridge arm circuit and the lower bridge arm circuit have the same structure.

[0009] The drive circuit includes two crosstalk suppression circuits: the crosstalk suppression circuit in the upper bridge arm is used to suppress crosstalk spike voltage in the high-side drive circuit; the crosstalk suppression circuit in the lower bridge arm is used to suppress crosstalk spike voltage in the low-side drive circuit.

[0010] The high-side drive circuit and the crosstalk suppression circuit in the lower bridge arm share a dual-channel isolation chip 1;

[0011] The low-side drive circuit and the crosstalk suppression circuit in the upper bridge arm share a dual-channel isolation chip 2;

[0012] The first signal output HOUT1 of the dual-channel isolation chip 1 is connected to one end of resistor R1, and the other end of resistor R1 is connected to the gate of power transistor M1.

[0013] The second signal output LOUT2 of the dual-channel isolation chip 2 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the gate of power transistor M2.

[0014] Furthermore, the upper bridge arm circuit includes a gate circuit for a power transistor M1, which includes a dual-channel isolation chip 1, a power transistor M1, and a resistor R1.

[0015] The first signal output HOUT1 of the dual-channel isolation chip 1 is connected to one end of resistor R1, and the other end of resistor R1 is connected to the gate of power transistor M1.

[0016] The lower bridge arm circuit includes a gate circuit for power transistor M2, which includes a dual-channel isolation chip 2, power transistor M2, and resistor R5.

[0017] The second signal output LOUT2 of the dual-channel isolation chip 2 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the gate of power transistor M2.

[0018] Furthermore, the crosstalk suppression circuit set in the upper bridge arm is a first crosstalk suppression circuit, which includes a dual-channel isolation chip 2, an auxiliary transistor Q1, a diode D1, a resistor R2, a resistor R3, and a capacitor C1.

[0019] The first signal output LOUT1 of the dual-channel isolation chip 2 is connected to one end of resistors R2 and R3. The other end of resistor R3 is connected to the anode of diode D1. The cathode of diode D1 and the other end of resistor R2 are connected to the gate of auxiliary transistor Q1.

[0020] The drain of the auxiliary transistor Q1 is connected to capacitor C1, and the other end of capacitor C1 is connected to the gate of the power transistor M1.

[0021] The source of auxiliary transistor Q1 is connected to the source of power transistor M1;

[0022] One end of resistor R4 is connected to the gate of power transistor M1, and the other end is connected to the source of power transistor M1.

[0023] The crosstalk suppression circuit set in the lower bridge arm is the second crosstalk suppression circuit, which includes a dual-channel isolation chip 1, an auxiliary transistor Q2, a diode D2, a resistor R6, a resistor R7, and a capacitor C2.

[0024] The second signal output HOUT2 of the dual-channel isolation chip 2 is connected to one end of resistors R6 and R7. The other end of resistor R7 is connected to the anode of diode D2. The cathode of diode D2 and the other end of resistor R6 are connected to the gate of auxiliary transistor Q2.

[0025] The drain of the auxiliary transistor Q2 is connected to capacitor C2, and the other end of capacitor C2 is connected to the gate of the power transistor M2.

[0026] The source of auxiliary transistor Q2 is connected to the source of power transistor M2;

[0027] One end of resistor R8 is connected to the gate of power transistor M2, and the other end is connected to the source of power transistor M2.

[0028] Furthermore, the logic inputs of the dual-channel isolation chip 1 include signal input terminals IN1-A and IN1-B, and the input terminals IN1-A and IN1-B are connected to the first control signal PWM1.

[0029] The logic inputs of the dual-channel isolation chip 2 include signal input terminals IN2-A and IN2-B, which are connected to the second control signal PWM2.

[0030] The first output ground VEEH1 of dual-channel isolation chip 1 and the first output ground VEEL1 of dual-channel isolation chip 2 are both connected to the high-side reference ground GNDH.

[0031] The second output ground VEEH2 of dual-channel isolation chip 1 and the second output ground VEEL2 of dual-channel isolation chip 2 are both connected to the low-side reference ground GNDL.

[0032] Furthermore, the dual-channel isolation chip 1 and dual-channel isolation chip 2 used are both isolated dual-channel gate driver chips. On the one hand, the chip logic input and output are isolated, and on the other hand, the two output channels are isolated from each other.

[0033] Since diode D1 is connected in series with resistor R3, the gate resistance of auxiliary transistor Q1 is the parallel connection of resistors R2 and R3 when it is turned on, and the gate resistance is R2 when it is turned off.

[0034] Since diode D2 is connected in series with resistor R7, the gate resistance of auxiliary transistor Q2 when it is turned on is the parallel connection of resistors R6 and R7, and the gate resistance of auxiliary transistor Q1 when it is turned off is R6.

[0035] The gate resistance of power transistor M1 when it is turned on and off is R1; the gate resistance of power transistor M2 when it is turned on and off is R5.

[0036] By selecting the resistance values ​​of resistors R1, R2, R3, R5, R6, and R7, the switching speed of the auxiliary transistors and the power transistors of the upper and lower bridge arms in the circuit can be controlled.

[0037] The auxiliary transistor Q1 turns on faster than the power transistor M2 turns off, and turns off slower than the power transistor M2 turns on.

[0038] The auxiliary transistor Q2 turns on faster than the power transistor M1 turns off, and turns off slower than the power transistor M1 turns on.

[0039] Furthermore, both auxiliary transistors Q1 and Q2 are low-voltage gallium nitride switches, and the switching speed of the auxiliary transistors should be faster than that of the power transistors.

[0040] Furthermore, the resistance values ​​of resistors R1, R2, R3, R5, R6, and R7 should satisfy the following formula:

[0041]

[0042] Furthermore, the operating cycle of the drive circuit for suppressing GaN HEMT bridge arm crosstalk is divided into four stages:

[0043] In the first stage, the first control signal PWM1 remains low, and the second control signal PWM2 sends a turn-off signal; power transistor M1 is in the off state, power transistor M2 is off, auxiliary transistor Q1 is off, and auxiliary transistor Q2 is in the off state; the auxiliary transistor Q1 turns off slowly, and when power transistor M2 turns off, the auxiliary transistor Q1 is still in the on state, so that the gate of power transistor M1 and the high-side reference ground GNDH are formed, suppressing the crosstalk caused by the instant of power transistor M2 turning off;

[0044] In the second stage, the first control signal PWM1 sends an enable signal, and the second control signal PWM2 remains at a low level; power transistor M1 is turned on, power transistor M2 is turned off, auxiliary transistor Q1 is turned off, and auxiliary transistor Q2 is turned on; the auxiliary transistor Q2 turns on quickly, and when power transistor M1 turns on, auxiliary transistor Q2 has already turned on, so that a second crosstalk suppression path is formed between the gate of power transistor M2 and the low-side reference ground GNDL, suppressing the crosstalk caused by the instant power transistor M1 turns on;

[0045] In the third stage, the first control signal PWM1 sends a turn-off signal, and the second control signal PWM2 remains at a low level; power transistor M1 is turned off, power transistor M2 is in the off state, auxiliary transistor Q1 is in the off state, and auxiliary transistor Q2 is turned off; the auxiliary transistor Q2 turns off slowly, and when power transistor M1 is turned off, the auxiliary transistor Q2 is still in the on state, so that the gate of power transistor M2 and the low-side reference ground GNDL are formed, suppressing the crosstalk caused by the moment power transistor M1 is turned off;

[0046] In the fourth stage, the first control signal PWM1 remains low, and the second control signal PWM2 sends an enable signal; power transistor M1 is off, power transistor M2 is on, auxiliary transistor Q1 is on, and auxiliary transistor Q2 is off; the auxiliary transistor Q1 turns on quickly, and when power transistor M2 turns on, auxiliary transistor Q1 is already on, forming a second crosstalk suppression path between the gate of power transistor M1 and the high-side reference ground GNDH, suppressing the crosstalk caused by the instant power transistor M2 turns on.

[0047] The driving circuit for suppressing crosstalk in GaN HEMT bridge arms according to the present invention has the following advantages:

[0048] Before crosstalk occurs in the upper or lower bridge arm, this invention alternately turns on either the lower or upper bridge arm crosstalk suppression circuit. The capacitors in the circuit absorb the crosstalk caused by the instantaneous on / off state of the upper and lower bridge arms. This achieves efficient and reliable active suppression of crosstalk between the upper and lower bridge arms without affecting the switching speed or switching losses of the upper and lower bridge arm switching devices or adding extra control signals, thus improving the reliability of the switching devices. From the overall circuit structure, only the crosstalk suppression circuit needs to be designed to achieve the above-mentioned objectives, making it easy to implement and low in cost. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of the driving circuit for suppressing crosstalk in a GaN HEMT half-bridge according to an embodiment of the present invention.

[0050] Figure 2 This is a timing diagram of the driving circuit for suppressing crosstalk in a GaN HEMT half-bridge according to an embodiment of the present invention.

[0051] Figure 3 This is a simulation circuit structure diagram in an embodiment of the present invention;

[0052] Figure 4 The waveform of the gate-source voltage Vgs of the high-side power transistor without crosstalk suppression circuitry is shown.

[0053] Figure 5 The waveform of the gate-source voltage Vgs of the high-side power transistor with the crosstalk suppression circuit added. Detailed Implementation

[0054] To better understand the purpose, structure, and function of this invention, the following detailed description of a driving circuit for suppressing GaN HEMT bridge arm crosstalk is provided in conjunction with the accompanying drawings.

[0055] like Figure 1 As shown, this embodiment provides a driving circuit for suppressing GaN HEMT bridge arm crosstalk. The driving circuit is connected in the GaN HEMT bridge arm, and the GaN HEMT bridge arm includes an upper bridge arm circuit and a lower bridge arm circuit. The upper bridge arm circuit and the lower bridge arm circuit have the same structure.

[0056] The drive circuit includes two crosstalk suppression circuits: the crosstalk suppression circuit in the upper bridge arm is used to suppress crosstalk spike voltage in the high-side drive circuit; the crosstalk suppression circuit in the lower bridge arm is used to suppress crosstalk spike voltage in the low-side drive circuit.

[0057] The high-side drive circuit and the crosstalk suppression circuit in the lower bridge arm share a dual-channel isolation chip 1;

[0058] The low-side drive circuit and the crosstalk suppression circuit in the upper bridge arm share a dual-channel isolation chip 2;

[0059] The upper bridge arm circuit includes a gate circuit for power transistor M1, and the gate circuit for power transistor M1 includes a dual-channel isolation chip 1, power transistor M1, and resistor R1.

[0060] The first signal output HOUT1 of the dual-channel isolation chip 1 is connected to one end of resistor R1, and the other end of resistor R1 is connected to the gate of power transistor M1.

[0061] The lower bridge arm circuit includes a gate circuit for power transistor M2, which includes a dual-channel isolation chip 2, power transistor M2, and resistor R5.

[0062] The second signal output LOUT2 of the dual-channel isolation chip 2 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the gate of power transistor M2.

[0063] The crosstalk suppression circuit set in the upper bridge arm is the first crosstalk suppression circuit, which includes a dual-channel isolation chip 2, an auxiliary transistor Q1, a diode D1, a resistor R2, a resistor R3, and a capacitor C1.

[0064] The first signal output LOUT1 of the dual-channel isolation chip 2 is connected to one end of resistors R2 and R3. The other end of resistor R3 is connected to the anode of diode D1. The cathode of diode D1 and the other end of resistor R2 are connected to the gate of auxiliary transistor Q1.

[0065] The drain of the auxiliary transistor Q1 is connected to capacitor C1, and the other end of capacitor C1 is connected to the gate of the power transistor M1.

[0066] The source of auxiliary transistor Q1 is connected to the source of power transistor M1;

[0067] One end of resistor R4 is connected to the gate of power transistor M1, and the other end is connected to the source of power transistor M1.

[0068] The crosstalk suppression circuit set in the lower bridge arm is the second crosstalk suppression circuit, which includes a dual-channel isolation chip 1, an auxiliary transistor Q2, a diode D2, a resistor R6, a resistor R7, and a capacitor C2.

[0069] The second signal output HOUT2 of the dual-channel isolation chip 2 is connected to one end of resistors R6 and R7. The other end of resistor R7 is connected to the anode of diode D2. The cathode of diode D2 and the other end of resistor R6 are connected to the gate of auxiliary transistor Q2.

[0070] The drain of the auxiliary transistor Q2 is connected to capacitor C2, and the other end of capacitor C2 is connected to the gate of the power transistor M2.

[0071] The source of auxiliary transistor Q2 is connected to the source of power transistor M2;

[0072] One end of resistor R8 is connected to the gate of power transistor M2, and the other end is connected to the source of power transistor M2.

[0073] The logic inputs of the dual-channel isolation chip 1 include signal input terminals IN1-A and IN1-B, and the input terminals IN1-A and IN1-B are connected to the first control signal PWM1.

[0074] The logic inputs of the dual-channel isolation chip 2 include signal input terminals IN2-A and IN2-B, which are connected to the second control signal PWM2.

[0075] The first output ground VEEH1 of dual-channel isolation chip 1 and the first output ground VEEL1 of dual-channel isolation chip 2 are both connected to the high-side reference ground GNDH.

[0076] The second output ground VEEH2 of dual-channel isolation chip 1 and the second output ground VEEL2 of dual-channel isolation chip 2 are both connected to the low-side reference ground GNDL.

[0077] The dual-channel isolation chip 1 and dual-channel isolation chip 2 used are both isolated dual-channel gate driver chips. On the one hand, the chip logic input and output are isolated, and on the other hand, the two output channels are isolated from each other.

[0078] By selecting the resistance values ​​of resistors R1, R2, R3, R5, R6, and R7, the switching speed of the auxiliary transistor and high-power transistor in the circuit can be controlled.

[0079] Since diode D1 is connected in series with resistor R3, the gate resistance of auxiliary transistor Q1 is the parallel connection of resistors R2 and R3 when it is turned on, and the gate resistance is R2 when it is turned off.

[0080] Since diode D2 is connected in series with resistor R7, the gate resistance of auxiliary transistor Q2 when it is turned on is the parallel connection of resistors R6 and R7, and the gate resistance of auxiliary transistor Q1 when it is turned off is R6.

[0081] The gate resistance of power transistor M1 when it is turned on and off is R1; the gate resistance of power transistor M2 when it is turned on and off is R5.

[0082] The auxiliary transistor Q1 turns on faster than the power transistor M2 turns off, and turns off slower than the power transistor M2 turns on.

[0083] The auxiliary transistor Q2 turns on faster than the power transistor M1 turns off, and turns off slower than the power transistor M1 turns on.

[0084] Both auxiliary transistors Q1 and Q2 are low-voltage gallium nitride switches, and the switching speed of the auxiliary transistors should be faster than that of the power transistors.

[0085] The resistance values ​​of resistors R1, R2, R3, R5, R6, and R7 should satisfy the following formula:

[0086]

[0087] Figure 2 This is the timing diagram of the drive circuit for suppressing crosstalk in the GaN HEMT half-bridge in this embodiment. The following is in conjunction with... Figure 2 Explanation of the working principle of this embodiment:

[0088] Before time t0, power transistor M1 is in the off state, power transistor M2 is in the on state, auxiliary transistor Q1 is in the off state, and auxiliary transistor Q2 is in the on state.

[0089] At time t0, the second control signal PWM2 sends a turn-off signal, which controls the power transistor M2 and the auxiliary transistor Q1 simultaneously through the dual-channel isolation chip 2;

[0090] During the t0-t1 period, power transistor M1 is in the off state, power transistor M2 is off, auxiliary transistor Q1 is on, and auxiliary transistor Q2 is on. When auxiliary transistor Q1 is off, its gate resistance is R2. By matching a gate resistance R2 with a larger resistance value to auxiliary transistor Q1, its turn-off speed is controlled so that the turn-off speed of auxiliary transistor Q1 is slower than that of power transistor M2. When power transistor M2 is off, auxiliary transistor Q1 is still on. A first crosstalk suppression path is formed between the gate of power transistor M1 and the high-side reference ground GNDH.

[0091] When power transistor M2 turns off, a sudden change in the drain-source voltage of power transistor M1 causes a negative dV / dt change. This dV / dt change acts on the Miller capacitance of power transistor M1, generating a negative displacement current. Without a crosstalk suppression circuit, this displacement current would generate an additional gate-source negative crosstalk voltage spike through the lower drive circuit. This spike might exceed the maximum gate-source breakdown voltage of the GaN transistor, causing it to break down. With the introduction of the crosstalk suppression circuit, auxiliary transistor Q1 conducts, providing a low-impedance path. Capacitor C1 absorbs the energy of the negative crosstalk voltage spike, suppressing the crosstalk caused by the instant power transistor M2 turns off.

[0092] During the t1-t2 period, auxiliary transistor Q1 is turned off;

[0093] During the t2-t3 period, both the high-side transistor and the power transistor are in the off state, and the auxiliary transistors Q1 and Q2 are also in the off state.

[0094] At time t3, the first control signal PWM1 sends an enable signal, which controls the power transistor M1 and the auxiliary transistor Q2 simultaneously through the dual-channel isolation chip 1.

[0095] During the t3-t4 period, power transistor M1 is turned on, power transistor M2 is turned off, auxiliary transistor Q1 is turned off, and auxiliary transistor Q2 is turned on. When auxiliary transistor Q2 is turned on, its gate resistor is the parallel connection of resistors R6 and R7. By matching the smaller resistor R7, its turn-on speed is controlled, so that the turn-on speed of auxiliary transistor Q2 is faster than that of power transistor M1. Before power transistor M1 is turned on, auxiliary transistor Q2 is already in the turn-on state. A second crosstalk suppression path is formed between the gate of power transistor M2 and the low-side reference ground GNDL.

[0096] During the t4-t5 period, power transistor M1 begins to conduct, and the drain-source voltage of power transistor M2 undergoes a sudden change, causing a positive dV / dt change. This dV / dt change acts on the Miller capacitance of power transistor M2, generating a positive displacement current. Without a crosstalk suppression circuit, this displacement current would generate an additional gate-source positive crosstalk voltage spike through the upper drive circuit. This gate-source positive crosstalk voltage spike might exceed its threshold voltage VTH, causing false turn-on. Due to the introduction of the crosstalk suppression circuit, auxiliary transistor Q2 conducts, providing a low-impedance path. Capacitor C2 absorbs the energy of the positive crosstalk voltage spike, suppressing the crosstalk caused by the instant power transistor M1 turns on.

[0097] During the t5-t6 period, power transistor M1 is in the on state, power transistor M2 is in the off state, auxiliary transistor Q1 is in the off state, and auxiliary transistor Q2 is in the on state.

[0098] At time t6, the first control signal PWM1 sends a turn-off signal, and the turn-on signal simultaneously controls the power transistor M1 and the auxiliary transistor Q2 through the dual-channel isolation chip 1.

[0099] During the t6-t7 period, power transistor M1 is turned off, power transistor M2 is turned off, auxiliary transistor Q1 is turned off, and auxiliary transistor Q2 is turned off. When auxiliary transistor Q2 is turned off, its gate resistance is R6. By matching a gate resistance R6 with a larger value to auxiliary transistor Q2, its turn-off speed is controlled, so that the turn-off speed of auxiliary transistor Q2 is slower than that of power transistor M1. When power transistor M1 is turned off, auxiliary transistor Q2 is still in the on state, and a second crosstalk suppression path is formed between the gate of power transistor M2 and the low-side reference ground GNDL.

[0100] When power transistor M1 turns off, the drain-source voltage of power transistor M2 changes abruptly, causing a negative dV / dt change. This dV / dt change acts on the Miller capacitance of power transistor M2, generating a negative displacement current. Without a crosstalk suppression circuit, this displacement current would generate an additional gate-source negative crosstalk voltage spike through the lower drive circuit. This spike might exceed the maximum gate-source breakdown voltage of the GaN transistor, causing it to break down. With the introduction of the crosstalk suppression circuit, auxiliary transistor Q2 conducts, providing a low-impedance path. Capacitor C2 absorbs the energy of the positive crosstalk voltage spike, suppressing the crosstalk caused by the instant power transistor M1 turns off.

[0101] During the t7-t8 period, auxiliary transistor Q2 is turned off;

[0102] During the t8-t9 period, both the high-side transistor and the power transistor are in the off state, and the auxiliary transistors Q1 and Q2 are also in the off state.

[0103] At time t9, the second control signal PWM2 sends an enable signal, which controls the power transistor M2 and the auxiliary transistor Q1 simultaneously through the dual-channel isolation chip 2.

[0104] During the t9-t10 period, power transistor M1 is off, power transistor M2 is on, auxiliary transistor Q1 is on, and auxiliary transistor Q2 is off. When auxiliary transistor Q1 is on, its gate resistance is the parallel connection of resistors R2 and R3. By matching the smaller resistance value of resistor R3, its conduction speed is controlled, so that the conduction speed of auxiliary transistor Q1 is faster than that of power transistor M2. Before power transistor M2 is on, auxiliary transistor Q1 is already on. The first crosstalk suppression path is formed between the gate of power transistor M1 and the high-side reference ground GNDH.

[0105] During the t10-t11 period, power transistor M2 begins to conduct. A sudden change in the drain-source voltage of power transistor M1 causes a positive dV / dt change. This dV / dt change acts on the Miller capacitance of power transistor M1, generating a positive displacement current. Without a crosstalk suppression circuit, this displacement current would generate an additional gate-source positive crosstalk voltage spike through the upper drive circuit. This spike might exceed its threshold voltage VTH, causing false turn-on. Due to the introduction of the crosstalk suppression circuit, auxiliary transistor Q1 conducts, providing a low-impedance path. Capacitor C1 absorbs the energy of the positive crosstalk voltage spike, suppressing the crosstalk caused by the instant power transistor M2 turns on.

[0106] After time t11, power transistor M2 turns on and power transistor M1 turns off, and the half-bridge circuit begins the next cycle.

[0107] To compare the crosstalk suppression effect of this invention in a half-bridge circuit, this embodiment uses LTspice software to build a simulation circuit model, and the simulation circuit structure diagram is shown below. Figure 3 As shown in the figure. The power transistors M1 and M2 are modeled using the TP65H150G4LSG from Transform, the Schottky diodes D1 and D2 in the crosstalk suppression circuit are 1N5817, the auxiliary transistors Q1 and Q2 are GS61008P, and the capacitors C1 and C2 are 5uF. Compared with a traditional circuit without crosstalk suppression, the simulation circuit model in this embodiment has a load inductance L0 of 500uH, a load resistance R0 of 20Ω, a filter capacitor C0 of 5uF, and a DC input voltage VDC of 400V. The drive resistors R1 and R2 are 5Ω, the absorption capacitors C1 and C2 in the crosstalk suppression circuit are 5uF, the resistors R2 and R5 are 15Ω, the resistors R3 and R7 are 15Ω, and the resistors R4 and R8 are 10kΩ. The comparison results are as follows. Figure 4 and Figure 5 As shown in the waveform, it can be seen that when the traditional half-bridge drive circuit does not have a crosstalk suppression circuit, the positive crosstalk voltage peak value of the gate-source voltage Vgs of the power transistor M2 can reach 4V and the negative crosstalk voltage peak value can reach -8V due to crosstalk. Moreover, there are large oscillations at the moment when the power transistor M1 is turned on and off. When the bridge arm crosstalk suppression circuit of the present invention is added, the positive and negative crosstalk voltages of the gate-source voltage Vgs of the power transistor Q2 almost completely disappear.

[0108] This invention focuses on optimizing the performance of GaN HEMT half-bridge circuits. In particular, through innovative circuit design and control strategies, it effectively suppresses crosstalk turn-on and gate reverse overshoot phenomena without sacrificing the normal turn-off speed of the devices or adding extra control signals. This provides an innovative solution for improving the overall efficiency and reliability of GaN HEMT half-bridge circuits.

[0109] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A drive circuit for suppressing GaN HEMT bridge leg cross-talk, characterized by, The driving circuit is connected in a GaN HEMT bridge arm, the GaN HEMT bridge arm includes an upper bridge arm circuit and a lower bridge arm circuit, the upper bridge arm circuit and the lower bridge arm circuit are structurally identical; The driving circuit includes two crosstalk suppression circuits, which are a crosstalk suppression circuit in the upper bridge arm and a crosstalk suppression circuit in the lower bridge arm; the crosstalk suppression circuit in the upper bridge arm is used for suppressing the crosstalk spike voltage in the high-side driving circuit; the crosstalk suppression circuit in the lower bridge arm is used for suppressing the crosstalk spike voltage in the low-side driving circuit; The high-side driving circuit and the lower bridge arm crosstalk suppression circuit share a double-channel isolation chip 1; The low-side driving circuit and the upper bridge arm crosstalk suppression circuit share a double-channel isolation chip 2; The upper bridge arm circuit includes a power tube M1 gate circuit, and the power tube M1 gate circuit includes the double-channel isolation chip 1, a power tube M1, and a resistor R1; One end of the resistor R1 is connected to the first signal output HOUT1 of the double-channel isolation chip 1, and the other end of the resistor R1 is connected to the gate of the power tube M1; The lower bridge arm circuit includes a power tube M2 gate circuit, and the power tube M2 gate circuit includes the double-channel isolation chip 2, a power tube M2, and a resistor R5; One end of the resistor R5 is connected to the second signal output LOUT2 of the double-channel isolation chip 2, and the other end of the resistor R5 is connected to the gate of the power tube M2; The crosstalk suppression circuit arranged in the upper bridge arm is a first crosstalk suppression circuit, and the first crosstalk suppression circuit includes the double-channel isolation chip 2, an auxiliary transistor Q1, a diode D1, a resistor R2, a resistor R3, and a capacitor C1; One end of the resistor R3 is connected to the first signal output LOUT1 of the double-channel isolation chip 2, and the other end of the resistor R3 is connected to the anode of the diode D1; the cathode of the diode D1 and the other end of the resistor R2 are commonly connected to the gate of the auxiliary transistor Q1; The drain of the auxiliary transistor Q1 is connected to the capacitor C1, and the other end of the capacitor C1 is connected to the gate of the power tube M1; The source of the auxiliary transistor Q1 is connected to the source of the power tube M1; One end of the resistor R4 is connected to the gate of the power tube M1, and the other end of the resistor R4 is connected to the source of the power tube M1; The crosstalk suppression circuit arranged in the lower bridge arm is a second crosstalk suppression circuit, and the second crosstalk suppression circuit includes the double-channel isolation chip 1, an auxiliary transistor Q2, a diode D2, a resistor R6, a resistor R7, and a capacitor C2; One end of the resistor R7 is connected to the second signal output HOUT2 of the double-channel isolation chip 1, and the other end of the resistor R7 is connected to the anode of the diode D2; the cathode of the diode D2 and the other end of the resistor R6 are commonly connected to the gate of the auxiliary transistor Q2; The drain of the auxiliary transistor Q2 is connected to the capacitor C2, and the other end of the capacitor C2 is connected to the gate of the power tube M2; The source of the auxiliary transistor Q2 is connected to the source of the power tube M2; One end of the resistor R8 is connected to the gate of the power tube M2, and the other end of the resistor R8 is connected to the source of the power tube M2.

2. The drive circuit to suppress GaN HEMT bridge leg cross-talk according to claim 1, characterized in that, The logic input of the double-channel isolation chip 1 includes signal input ends IN1-A and IN1-B, and the input ends IN1-A and IN1-B are commonly connected to a first control signal PWM1; The logic input of the dual-channel isolation chip 2 includes signal input ends IN2-A and IN2-B, and the input ends IN2-A and IN2-B are commonly connected to a second control signal PWM2; The first output ground VEEH1 of the dual-channel isolation chip 1 and the first output ground VEEL1 of the dual-channel isolation chip 2 are commonly connected to a high-side reference ground GNDH; The second output ground VEEH2 of the dual-channel isolation chip 1 and the second output ground VEEL2 of the dual-channel isolation chip 2 are commonly connected to a low-side reference ground GNDL; The dual-channel isolation chip 1 and the dual-channel isolation chip 2 are both isolation dual-channel gate drive chips, and on the one hand, the logic input and output of the chip are isolated, and on the other hand, the two output channels are isolated from each other.

3. The drive circuit to suppress GaN HEMT bridge leg cross-talk according to claim 1, wherein, By selecting the resistance values of the resistors R1, R2, R3, R5, R6 and R7, the switching speed of the auxiliary transistor in the control circuit and the power tubes of the upper bridge arm and the lower bridge arm is controlled; The turn-on speed of the auxiliary transistor Q1 is faster than the turn-off speed of the power tube M2, and the turn-off speed of the auxiliary transistor Q1 is slower than the turn-on speed of the power tube M2; The turn-on speed of the auxiliary transistor Q2 is faster than the turn-off speed of the power tube M1, and the turn-off speed of the auxiliary transistor Q2 is slower than the turn-on speed of the power tube M1; The auxiliary transistors Q1 and Q2 are both low-voltage gallium nitride switching tubes, and the switching speed of the auxiliary transistors should be faster than that of the power tubes; The resistance values of the resistors R1, R2, R3, R5, R6 and R7 should satisfy the following formula: R1≤ R6, R5≤ R2.

4. The drive circuit to suppress GaN HEMT bridge leg cross-talk according to claim 3, characterized in that, The working cycle of the circuit is divided into four stages, which are: In the first stage, the first control signal PWM1 keeps low level, and the second control signal PWM2 sends off signal; the power tube M1 is in the off state, the power tube M2 is off, the auxiliary transistor Q1 is off, and the auxiliary transistor Q2 is in the off state; the auxiliary transistor Q1 is slow in the off state, and when the power tube M2 is off, the auxiliary transistor Q1 is still in the on state, so that the first crosstalk suppression path is formed between the gate of the power tube M1 and the high-side reference ground GNDH, thereby suppressing the crosstalk caused by the power tube M2 in the off state; In the second stage, the first control signal PWM1 sends on signal, and the second control signal PWM2 keeps low level; the power tube M1 is on, the power tube M2 is in the off state, the auxiliary transistor Q1 is in the off state, and the auxiliary transistor Q2 is on; the auxiliary transistor Q2 is fast in the on state, and when the power tube M1 is on, the auxiliary transistor Q2 has been on, so that the second crosstalk suppression path is formed between the gate of the power tube M2 and the low-side reference ground GNDL, thereby suppressing the crosstalk caused by the power tube M1 in the on state; In the third stage, the first control signal PWM1 sends off signal, and the second control signal PWM2 keeps low level; the power tube M1 is off, the power tube M2 is in the off state, the auxiliary transistor Q1 is in the off state, and the auxiliary transistor Q2 is off; the auxiliary transistor Q2 is slow in the off state, and when the power tube M1 is off, the auxiliary transistor Q2 is still in the on state, so that the first crosstalk suppression path is formed between the gate of the power tube M2 and the low-side reference ground GNDL, thereby suppressing the crosstalk caused by the power tube M1 in the off state; In the fourth stage, the first control signal PWM1 keeps low level, and the second control signal PWM2 sends an opening signal; the power transistor M1 is in the off state, the power transistor M2 is in the on state, the auxiliary transistor Q1 is in the on state, and the auxiliary transistor Q2 is in the off state; the auxiliary transistor Q1 has a fast on speed, and when the power transistor M2 is in the on state, the auxiliary transistor Q1 has been in the on state, so that a second crosstalk suppression path is formed between the gate of the power transistor M1 and the high-side reference ground GNDH, thereby suppressing the crosstalk caused by the power transistor M2 in the on state.

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