Level shifter for high voltage driver

Abstract

The invention relates to a level shifter for a high voltage driver. Described embodiments include a voltage level shifter (600) having a first driver (402) having an input to receive a first signal (X, 206), an output, a positive power supply terminal coupled to a first supply terminal (202, HB), and a negative power supply terminal coupled to a second supply terminal (215, HS). The transistor (404) has first and second current terminals and a first control terminal. The first current terminal is coupled to the first driver output, and the first control terminal is adapted to be coupled to a low-side drive transistor control terminal. A second driver (410) has an input coupled to the second current terminal, an output, a positive power supply terminal coupled to a third supply terminal (VCC, 238), and a negative power supply terminal coupled to ground. The second driver provides a second signal (Y, 234) at the second driver output. The voltage at the third supply terminal is less than 10% of the voltage at the first supply terminal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Indian Patent Application No. 202341076596 filed on November 9, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a level shifter for a high voltage driver. Background Art

[0004] The present specification relates to signal level shifters, such as circuits that convert a signal from a first voltage domain to a second voltage domain. The first voltage domain may be a higher voltage domain, and the second voltage domain may be a lower voltage domain. Conversely, the first voltage domain may be a lower voltage domain, and the second voltage domain may be a higher voltage domain.

[0005] Many power modules require bidirectional signal transfer between a high voltage domain and a low voltage domain. The signals transferred between the voltage domains may be, for example, signals for voltage regulation or protection features such as an over-voltage indicator, an over-current indicator, or an over-temperature indicator. Typically, a monolithic half-bridge power driver stage contains a monolithic downward level shifter to transfer logic signals from a higher voltage domain to a lower voltage domain, since the controller is powered by a low voltage supply.

[0006] In many cases, conventional monolithic downward level shifters use drain extended p-channel metal oxide semiconductor (DEPMOS) transistors. However, DEPMOS semiconductor processes generally do not support higher voltages (e.g., >120V). Therefore, monolithic bidirectional level shifters for higher voltage signals may require a multi-die multi-chip module (MCM) solution to meet the voltage specifications, thus significantly increasing their cost. Summary of the invention

[0007] In a first example, a circuit for voltage level shifting includes a first driver having a first driver input, a first driver output, a first driver positive power supply terminal, and a first driver negative power supply terminal. The first driver input is configured to receive a first signal. The first driver positive power supply terminal is coupled to a first voltage supply terminal, and the first driver negative power supply terminal is coupled to a second voltage supply terminal.

[0008] The transistor has a first current terminal, a second current terminal and a first control terminal. The first current terminal is coupled to the first driver output, and the first control terminal is suitable for coupling to the low-side driver transistor control terminal. The second driver has a second driver input, a second driver output, a second driver positive power supply terminal and a second driver negative power supply terminal. The second driver input is coupled to the second current terminal. The second driver positive power supply terminal is coupled to the third voltage supply terminal, and the second driver negative power supply terminal is coupled to the ground terminal.

[0009] The second driver is configured to provide a second signal at the second driver output. A voltage at the third voltage supply terminal is less than 10% of a voltage at the first voltage supply terminal. A resistor is coupled between the third voltage supply terminal and the second driver input.

[0010] In a second example, the level shifting circuit includes a diode module having a diode module input, a diode module output, and a diode module control terminal. The diode module input is coupled to a first voltage supply terminal. The first driver has a first driver input, a first driver output, a first driver positive power supply terminal, and a first driver negative power supply terminal. The first driver positive power supply terminal is coupled to the second voltage supply terminal, and the first driver negative power supply terminal is coupled to the third voltage supply terminal.

[0011] The overvoltage detection circuit has a first overvoltage input and a second overvoltage input and an overvoltage output. The first overvoltage input is coupled to the second voltage supply terminal, and the second overvoltage input is coupled to the third voltage supply terminal. The overvoltage output is coupled to the first driver input, and the overvoltage detection circuit is configured to provide a first signal at the overvoltage output. The transistor has a first current terminal and a second current terminal and a first control terminal. The first current terminal is coupled to the first driver output, and the first control terminal is coupled to the first voltage supply terminal.

[0012] The second driver has a second driver input, a second driver output, a second driver positive power supply terminal, and a second driver negative power supply terminal. The second driver input is coupled to the second current terminal. The second driver positive power supply terminal is coupled to the first voltage supply terminal, and the second driver negative power supply terminal is coupled to the ground terminal. The second driver output is coupled to the diode module control terminal, and the second driver is configured to provide a second signal at the second driver output. A resistor is coupled between the first voltage supply terminal and the second driver input. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A block diagram of an exemplary signal level shifter for providing bidirectional signal transfer between a lower voltage domain and a higher voltage domain is shown.

[0014] Figure 2 A schematic diagram for an exemplary monolithic signal level shifter is shown.

[0015] Figure 3 A block diagram of an exemplary monolithic power driver stage with a bidirectional level shifter operating across two voltage domains is shown.

[0016] Figure 4 A simplified schematic diagram showing an exemplary monolithic level shifter.

[0017] Figure 5 An exemplary timing diagram showing a monolithic level shifter.

[0018] Figure 6 A schematic diagram showing an exemplary monolithic signal level shifter in a startup regulation circuit.

[0019] Figure 7 An exemplary timing diagram showing a monolithic signal level shifter in a startup regulation circuit. DETAILED DESCRIPTION

[0020] In this specification, the same reference numerals depict the same or similar (in function and / or structure) features. The drawings are not necessarily drawn to scale.

[0021] A voltage level shifter, also known as a voltage level translator, is a circuit that converts specific signals from one voltage domain to another in applications that utilize multiple voltage domains. Bidirectional signaling between high and low voltage domains is a requirement in many power supplies and voltage regulator modules (VRMs). Examples of signals passed between voltage domains include voltage regulation signals and fault warning signals, such as over-voltage indicators, over-current indicators, or over-temperature indicators.

[0022] The controller is powered by a low voltage supply, so the half-bridge power driver stage usually requires a down level shifter to pass the logic signal from the higher voltage power driver stage to the lower voltage controller. Without a down level shifter, the signal from the higher voltage domain may damage or destroy the controller. Traditional monolithic down level shifters can use drain extended p-channel metal oxide semiconductor (DEPMOS) transistors.

[0023] DEPMOS has a source, a gate, a drain and a drift region between the gate and the drain. The extra layer (drift region) increases the drift resistance. In DEPMOS, there is a field plate that increases the source-to-drain voltage rating. However, the DEPMOS process does not generally support higher voltages (e.g., >120V). Therefore, a bidirectional level shifter for higher voltage signals may require a multi-die multi-chip module (MCM) solution, thus significantly increasing the cost of the signal level shifter.

[0024] Figure 1 A block diagram of an exemplary signal level shifter 100 for providing bidirectional signal transfer between a lower voltage domain and a higher voltage domain is shown. The signal level shifter 100 includes a low voltage circuit 110, an isolation circuit 120, and a high voltage circuit 140. The low voltage circuit 110 typically operates in the range of 3V to 5V and may include a controller. The low voltage circuit has an output 112 and an input 114 for transmitting and receiving lower voltage signals, respectively. The high voltage circuit 140 typically operates in the range of 120V to 220V and may include a power driver and a field effect transistor (FET). The high voltage circuit 140 has an output 142 and an input 144 for receiving and transmitting higher voltage signals, respectively.

[0025] The isolation circuit 120 includes a low voltage transmit driver 122, a high voltage receive driver 124, a high voltage transmit driver 126, a low voltage receive driver 128, and an isolator 130. The low voltage transmit driver 122 receives a lower voltage signal 112 from the low voltage circuit 110 and provides the signal to the isolator 130. The isolator 130 converts the signal from the lower voltage to a higher voltage and provides the converted signal to the input of the high voltage receive driver 124. The output of the high voltage receive driver 124 provides a higher voltage signal 142 to the high voltage circuit 140.

[0026] The high voltage transmit driver 126 receives the higher voltage signal 144 from the high voltage circuit 140 and provides the signal to the isolator 130. The isolator 130 converts the signal from the higher voltage to a lower voltage and provides the converted signal to the input of the low voltage receive driver 128. The output of the low voltage receive driver 128 provides the lower voltage signal 114 to the low voltage circuit 110.

[0027] In at least one case, the isolation circuit 120 provides capacitive isolation between the low voltage circuit 110 and the high voltage circuit 140, which performs substantially the same function as a level shifter. A disadvantage of the signal level shifter 100 is that it is a three-die solution. The low voltage circuit 110 is located on a first die, the isolation circuit 120 is located on a second die, and the high voltage circuit 140 is located on a third die. The three-die solution of the signal level shifter requires an MCM, which is significantly more expensive than a monolithic circuit.

[0028] Figure 2 A schematic diagram for an exemplary monolithic signal level shifter 200 is shown. The monolithic signal level shifter 200 includes a lower voltage circuit 250 and a higher voltage circuit 240. The higher voltage circuit is powered by a voltage source HB 202 and includes a current source 204, transistors 210, 212, 214, 216, 220, and 222, and diodes 218 and 224. The lower voltage circuit is powered by V CC238 is powered and includes transistors 226, 228, 230, and 232. The higher voltage differential signal is X 206 and 208, and the converted lower voltage signal is Y 234.

[0029] The monolithic signal level shifter 200 has two power domains: HB-HS for higher voltage circuits and V CC - ground. Signals must be transmitted and received in both directions to allow the power stage to communicate with the controller. In many cases, the control signals for the power drivers in the driver stage come from the controller in the lower voltage domain. Therefore, the control signals are provided to a signal level shifter which shifts the signals from V CC -domain to the HB-HS domain. Similarly, controller monitoring can occur on the higher voltage side, such as detecting if the difference between HB and HS exceeds 5V undervoltage lockout (UVLO) and overvoltage lockout (OVLO). Signals such as UVLO and OVLO are provided to a signal level shifter that passes the signal from the HB-HS domain to the V CC Another example of a signal that may require level translation is a zero voltage detection (ZVD) signal, which is detected in a higher voltage domain and then translated to a lower voltage domain before being provided to the controller.

[0030] The signals passed in the monolithic signal level shifter 200 are X 206 in the higher voltage circuit 240 and 208, and Y 234 in the lower voltage circuit 250. This signal X 206 is provided to the gate of transistor 210, and the signal 208 is provided to the gate of transistor 212. Transistors 210 and 212 are powered by HB 202 through current source 204. The gate of transistor 214 and the gate of transistor 216 are coupled together and coupled to HS 215. In some cases, HS 215 is connected to the switch terminal of the switching voltage regulator. Cross-coupled transistors 220 and 222 are coupled to the drains of transistors 214 and 216. The sources of transistors 220 and 222 are each coupled to ground. Diode 218 is coupled between the source and drain of transistor 220. Diode 224 is coupled across transistor 222 from source to drain. Transistors 214 and 216 block current and prevent high voltages between HB 202 and ground, which in some cases may be 200V.

[0031] Transistors 226 and 228 are configured to form a current mirror. The sources of transistors 226 and 228 are coupled to V CC 238. Transistor 230 is coupled between the drain of transistor 226 and ground and has a gate coupled to the drain of transistor 222. Transistor 232 is coupled between the drain of transistor 228 and ground and has a gate coupled to the drain of transistor 220. Signal Y 234 is provided at the drains of transistors 228 and 232 coupled together.

[0032] Figure 3 A block diagram of an exemplary monolithic power driver stage 300 having a bidirectional monolithic signal level shifter 200 operating across two voltage domains is shown. A controller (not shown) operates in a manner controlled by V CC 238 and ground. HB 202 and HS 215 define a higher voltage domain, which is a floating power domain in at least some cases. A boot capacitor (usually external) between HB 202 and HS 215 acts as a floating power supply. The voltage difference between HB 202 and HS 215 can be adjusted to 5V to operate the high-side GaN FET 302 efficiently and reliably.

[0033] When the low-side GaN FET 304 is turned on, the startup capacitor C boot From V CC 238 is charged. During the third quadrant conduction period of the switching converter, it is possible to charge the start capacitor C boot For this reason, a regulation feedback loop is added to the circuit to prevent the startup capacitor C boot This feedback requires a level shifter to convert the signal from the higher voltage domain to the lower voltage domain. The zero voltage detection signal (ZVD) is passed to a controller (not shown) to optimize the dead time during the third quadrant conduction period over multiple cycles, thereby improving efficiency. The ZVD signal must also be converted from the higher voltage domain to the lower voltage domain.

[0034] Depending on whether the high-side GaN FET 302 or the low-side GaN FET 304 is turned on, the voltage at HS 215 will be at V IN However, the gate-to-source voltage of both the high-side GaN FET 302 and the low-side GaN FET 304 should not exceed 5V to avoid overstressing the device. CC The voltage between HB 202 and ground is 5V, and the voltage between HB 202 and HS 215 is 5V. The voltage difference between HB 202 and HS 215 is set to 5V by the startup diode, which in at least one case is a transistor and a diode. When the low-side GaN FET 304 is turned on, the capacitor C boot From V CC238 charging.

[0035] To pass a signal from a lower voltage circuit to a higher voltage circuit, a 200V transistor fabricated in an NMOS, LDMOS, or drain extended NMOS (DENMOS) process is traditionally required. The gate-to-source voltage (V GS ) is typically 5V. However, when the transistor is off, the transistor must be able to withstand 200V between its drain and its source without damage. This is within the capabilities of a DENMOS or LDMOS component, so this component can be used for lower voltage circuit to higher voltage circuit signal level shifters.

[0036] However, a complementary DEPMOS device is needed to implement a higher voltage circuit to lower voltage circuit signal level shifter. In a DEPMOS device, V GS is also at 5V. So if the source is at 200V, the voltage at the drain can drop to 0V, but the voltage at the gate can only reach 195V because if V GS If the voltage exceeds 5V, the transistor will be destroyed. However, the conventional 200V DEPMOS process does not provide sufficient transistor performance characteristics for level shifter applications. Therefore, a method is needed that can pass signals from a higher voltage (HB-HS) domain to a lower voltage (V CC -ground) domain level shifter.

[0037] Figure 4 A simplified schematic diagram of an exemplary monolithic level shifter 400 is shown. X 206 is a higher voltage domain signal to be converted to a lower voltage domain. In this case, X 206 is a single-ended signal, but in other cases, X can be a differential signal. The higher signal X from the higher voltage domain is provided to the input of driver 402. Driver 402 is powered by HB 202 on the positive rail and HS 215 on the negative rail. The output of driver 402 is coupled to the drain of transistor 404.

[0038] Transistor 404 provides isolation between the higher voltage domain and the lower voltage domain. The source of transistor 404 is coupled to the input of driver 410. Gate drive signal LI is provided to the gate of transistor 404. Driver 410 is driven by V CC 238 is powered, and the negative rail of driver 410 is coupled to ground. In at least one case, the voltage at HB 202 is greater than V CC Ten times the voltage at 238.

[0039] The output of driver 410 provides signal Y 234, which is signal X converted from a higher voltage domain to a lower voltage domain. Resistor 408 is coupled between V CC238 and the source of transistor 404. Resistor 408 helps to ensure that when transistor 404 is off, the voltage at the input of driver 410 does not remain floating, which could cause the voltage at the output of driver 410 to be unpredictable.

[0040] Unlike transistors 214 and 216 of monolithic signal level shifter 200, which are DEPMOS transistors, transistor 404 is a laterally-diffused metal oxide semiconductor (LDMOS) transistor. In at least one case, transistor 404 is a 200V LDMOS transistor, but the voltage rating of transistor 404 may be selected to meet the maximum voltage specification of a particular application. The performance of conventional 200V LDMOS transistors is able to meet the performance requirements of the monolithic high voltage level shifter, compared to the unsatisfactory performance of conventional 200V DEPMOS transistors.

[0041] Figure 5 An exemplary timing diagram 500 of the monolithic level shifter 400 is shown. Graph 510 shows a timing diagram of signal LI 406, which is a control signal provided to the gate of transistor 404 and the gate of a low-side drive FET (not shown). Graph 520 shows a timing diagram of the high-side drive FET control signal HI, which is generated in a lower voltage domain and converted to a higher voltage domain. Graph 530 shows a timing diagram of signal HS 215. Graph 540 shows a timing diagram of signal Y 234.

[0042] HS signal 530 varies between ground and 200V. A data signal is superimposed on top of HS signal 530. The data signal carries information to be transferred between a higher voltage domain and a lower voltage domain. HS signal 530 is periodic, where the signal is high during a portion of the cycle and low during a portion of the cycle. When HS signal 530 is low, transistor 404 is turned on, and the data signal superimposed on HS 530 can be transferred from a higher voltage domain to a lower voltage domain. However, when HS signal 530 is high, transistor 404 is turned off, and no current flows through transistor 404.

[0043] Only when the HS signal 530 is in the low voltage portion of its cycle does the transistor 404 act as a pass gate for the data signal superimposed on the HS signal 530. When the HS signal 530 is high (e.g., 200V), the transistor 404 will block all current, isolating the higher voltage domain from the lower voltage domain during that time. When the HS signal 530 is low, the signal passes from the higher voltage domain to the lower voltage domain.

[0044] The monolithic level shifter 400 does not act as a continuous time level shifter, but rather a sampling level shifter. The signal superimposed on the HS 530 is sampled during the high cycle of HS 215. The signal is held or temporarily stored and then transferred from the higher voltage domain to the lower voltage domain during the next low cycle of the HS signal 530. An important consideration is that the signal can be blocked by transistor 404 without overstressing or damaging transistor 404, which is a 200V LDMOS transistor. The voltage at HB 202 will always be 5V higher than the voltage at HS 215. Therefore, when the voltage at HS 215 varies between ground and 200V, the voltage at HB 202 will vary in phase with the voltage at HS 215 over a range of 5V to 205V.

[0045] Signal X 206 can be any signal of interest in the higher voltage domain, and Y 234 is the same signal of interest converted to the lower voltage domain. In many cases, HS 215 is also connected to the switch terminal of the converter power stage. Resistor 408 acts as a pull-up resistor for the input of driver 410. Connected at V CC Resistor 408 between 238 and the input of driver 410 helps prevent the voltage at the source terminal of transistor 404 from simply floating when transistor 404 is turned off. When transistor 404 is turned off, the signal is blocked and the data signal is not available for use during that half of the HS cycle during that time. However, if the input of driver 410 is left floating, current can flow from V CC 238 flows to ground. To avoid this, the input of driver 410 is initialized to V CC 238. Therefore, when transistor 404 is off, HS signal 530 is high and the signal is not passed.

[0046] Transistor 404 can be coupled to a low-side drive FET in the driver stage by providing signal LI 406 to each of its gates. When signal LI 406 is high, the voltage difference between HB 202 and HS 215 is equal to V CC The voltage difference between 238 and ground. When the low-side driver FET is turned on, the signal is passed from the higher voltage domain to the lower voltage domain. When the high-side driver FET is turned off, the signal is blanked. The output Y 234 of the level shifter is pulled high during the blanking period.

[0047] Startup regulation is another application that may require passing a signal from a higher voltage domain to a lower voltage domain. The switch controls the charging of the startup capacitor. The overvoltage detection circuit provides a feedback mechanism for the startup regulation control loop. If the voltage difference between HB 202 and HS215 exceeds 5V, the overvoltage detection circuit detects this and provides an output signal as a control signal to stop charging the startup capacitor.

[0048] Figure 6 A schematic diagram showing an exemplary monolithic signal level shifter in a startup regulation circuit. Startup diode 650 is coupled to V CC 238 and HB 202. Startup diode 650 is a switch and a diode in series. The switch of startup diode 650 can be a transistor. Startup capacitor 642 is coupled between HB 202 and HS215. Startup capacitor 642 can have a capacitance in the range of several microfarads. Boot capacitor 642 can be located on the same monolithic substrate as other circuit systems, or can be located outside the device. Startup capacitor 642 stores the charge received from the switch of startup diode 650. During the period when the low-side drive FET (not shown) is turned on, startup capacitor 642 draws charge from V CC 238 charging.

[0049] Overvoltage detection circuit 646 has a first input coupled to HB 202 and a second input coupled to HS 215. Overvoltage detection circuit 646 includes circuitry to compare the voltage of HB 202 to the voltage of HS 215 and provide a signal at its output indicating whether the difference between those voltages exceeds 5 V. The output of overvoltage detection circuit 646 is X206, which is a signal to convert from a lower voltage domain to a higher voltage domain.

[0050] Driver 402 is powered by HB 202 on the positive rail and HS 215 on the negative rail. The input of driver 402 is coupled to the output of overvoltage detection circuit 646 and receives signal X 206. The output of driver 402 is coupled to the drain of transistor 404, which in at least one case is a p-channel LDMOS FET. The gate of transistor 404 is coupled to V CC 238, so the voltage at the gate of transistor 404 is maintained at a constant value. The switching on and off of transistor 404 is controlled by the output of driver 402, which is controlled by the voltage swing of HS215.

[0051] Transistor 404 provides isolation between the higher voltage domain and the lower voltage domain. The source of transistor 404 is coupled to the input of driver 410. Driver 410 is powered by V CC 238 is powered, and the negative rail of driver 410 is coupled to ground. The output of driver 410 provides signal Y 234, which is the overvoltage output signal X converted from the higher voltage domain to the lower voltage domain. Resistor 408 is coupled between V CC 238 and the source of transistor 404.

[0052] If the overvoltage output signal X is high (or true), the signal is passed to the lower voltage (V CC) domain, then returns to the startup diode 650, and disconnects the startup diode 650 to stop charging the startup capacitor 642. Charging of the startup capacitor 642 occurs only when the voltage at HS215 is at or below ground. If the voltage at HS215 is higher than V CC , then the startup diode 650 blocks the charging of the startup capacitor 642. Current can flow through the startup diode 650 only when the voltage at HS215 is at or below ground.

[0053] Figure 7 A timing diagram 700 of an exemplary monolithic signal level shifter in the startup regulation circuit 600 is shown. Graph 710 shows a timing diagram of signal LI, which is a signal that controls a low-side drive FET (not shown). Graph 720 shows a timing diagram of signal HI, which is a signal that controls a high-side drive FET (not shown). HI is generated in a lower voltage domain and then converted to a higher voltage domain to provide to the gate of the high-side drive FET. Graph 730 shows a timing diagram of signal HS 215. Graph 740 shows a timing diagram of signal HB 202. Graph 750 shows a timing diagram of signal X, which is the output of the overvoltage detection circuit 646.

[0054] When LI 710 is high, the low side FET (not shown) turns on, causing HS 730 to be pulled down to ground. When HS 730 is pulled down to ground, if the difference between the voltage at HB 202 and HS 215 is less than 5V, HB 740 becomes less than 5V. In response, the start diode 650 turns on, allowing current to flow from V CC 238 flows to the startup capacitor 642, thereby storing the charge in the startup capacitor 642. The voltage at HB 740 will increase and rise to 4.2 to 4.3V, which in some cases is higher than V CC 238 is 0.7 to 0.8V lower.

[0055] The voltage difference between HB 740 and HS 730 will accumulate even higher than 5V, and then the overvoltage detection circuit 646 will detect this and stop charging the startup capacitor 642 by disconnecting the startup diode 650. Therefore, there is a closed loop regulation that ensures that the voltage difference between HB 740 and HS 730 does not exceed 5V, and if the difference is less than 5V, it will help to increase the voltage difference. This occurs when the low-side drive transistor is turned on. Once the low-side drive transistor is disconnected and the high-side drive transistor is turned on, HS 730 will reach 200V and HB 740 will reach 105V. In this case, the startup diode 650 blocks the current because the startup diode is reverse biased and no current flows through the reverse biased diode.

[0056] In this specification, "terminal", "node", "interconnection", "lead" and "pin" are used interchangeably. Unless specifically stated to the contrary, these terms generally mean the interconnection between device elements, circuit elements, integrated circuits, devices or other electronic or semiconductor components or their ends.

[0057] In this specification, "ground" includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification.

[0058] In this specification, the term "coupled" may cover connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in the first instance, device A is coupled to device B through a direct connection; or (b) in the second instance, if the intermediate component C does not change the functional relationship between device A and device B, device A is coupled to device B through the intermediate component C, so that device B is controlled by device A via the control signal generated by device A.

[0059] In this specification, even if operations are described in a particular order, some operations may be optional, and the operations need not be performed in the particular order to achieve a specified result. In some instances, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the embodiments described above does not necessarily require such separation in all embodiments.

[0060] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. A circuit for voltage level shifting, comprising: a first driver having a first driver input, a first driver output, a first driver positive power supply terminal, and a first driver negative power supply terminal, wherein the first driver input is configured to receive a first signal, the a first driver positive power supply terminal coupled to a first voltage supply terminal and said first driver negative power supply terminal coupled to a second voltage supply terminal; a transistor having a first current terminal and a second current terminal and a first control terminal, wherein the first current terminal is coupled to the first driver output and the first control terminal is adapted to be coupled to a low-side driver transistor control terminal; a second driver having a second driver input, a second driver output, a second driver positive power supply terminal, and a second driver negative power supply terminal, wherein the second driver input is coupled to the second current terminal, the second driver positive power supply terminal is coupled to a third voltage supply terminal, the second driver negative power supply terminal is coupled to a ground terminal, the second driver is configured to provide a second signal at the second driver output, and a voltage at the third voltage supply terminal is less than 10% of a voltage at the first voltage supply terminal; and A resistor is coupled between the third voltage supply terminal and the second driver input.

2. The circuit of claim 1, wherein the transistor is a Laterally Diffused Metal Oxide Semiconductor (DEPMOS) transistor. 3 . The circuit of claim 2 , wherein the second voltage supply terminal is coupled to a switch terminal of a switching voltage regulator. 4 . The circuit of claim 1 , wherein the first signal is in a first voltage domain and the second signal is in a second voltage domain. 5 . The circuit of claim 4 , wherein the first voltage domain is a higher voltage domain and the second voltage domain is a lower voltage domain. The circuit according to claim 1 , wherein the first signal is superimposed on a voltage at the second voltage supply terminal. 7 . The circuit according to claim 6 , wherein the voltage at the second voltage supply terminal cyclically varies between a high level and a low level.

8. The circuit of claim 7, wherein the second signal is valid only when the voltage at the second voltage supply terminal is at the low level.

9. The circuit of claim 1, wherein the first signal provides information regarding one of: an overvoltage condition, an overcurrent condition, and an overtemperature condition.

10. The circuit of claim 1, wherein the second signal is provided to a controller.

11. A level shift circuit, comprising: a diode module having a diode module input, a diode module output, and a diode module control terminal, wherein the diode module input is coupled to the first voltage supply terminal; a first driver having a first driver input, a first driver output, a first driver positive power supply terminal, and a first driver negative power supply terminal, wherein the first driver positive power supply terminal is coupled to a second voltage supply terminal and the first driver negative power supply terminal is coupled to a third voltage supply terminal; an overvoltage detection circuit having a first overvoltage input and a second overvoltage input and an overvoltage output, wherein the first overvoltage input is coupled to the second voltage supply terminal, the second overvoltage input is coupled to the third voltage supply terminal, the overvoltage output is coupled to the first driver input, and the overvoltage detection circuit is configured to provide a first signal at the overvoltage output; a transistor having a first current terminal and a second current terminal and a first control terminal, wherein the first current terminal is coupled to the first driver output and the first control terminal is coupled to the first voltage supply terminal; a second driver having a second driver input, a second driver output, a second driver positive power supply terminal, and a second driver negative power supply terminal, wherein the second driver input is coupled to the second current terminal, the second driver positive power supply terminal is coupled to the first voltage supply terminal, the second driver negative power supply terminal is coupled to a ground terminal, the second driver output is coupled to the diode module control terminal, and the second driver is configured to provide a second signal at the second driver output; and A resistor is coupled between the first voltage supply terminal and the second driver input. 12 . The level shifting circuit of claim 11 , further comprising a capacitor coupled between the second voltage supply terminal and the third voltage supply terminal. 13 . The level shift circuit according to claim 11 , wherein a voltage at the first voltage supply terminal is less than 10% of a voltage at the second voltage supply terminal.

14. The level shifting circuit of claim 11, wherein the diode module comprises a switch connected in series with a diode.

15. The level shift circuit according to claim 11, wherein the transistor is a Laterally Diffused Metal Oxide Semiconductor (DEPMOS) transistor. 16 . The level shifting circuit of claim 11 , wherein the third voltage supply terminal is coupled to a switch terminal of a switching voltage regulator.

17. The level shifting circuit of claim 11, wherein the first signal is in a first voltage domain and the second signal is in a second voltage domain.

18. The level shift circuit of claim 17, wherein the first voltage domain is a higher voltage domain, and the second voltage domain is a lower voltage domain.

19. The level shift circuit according to claim 11, wherein the first signal is superimposed on a voltage at the third voltage supply terminal. 20 . The level shift circuit according to claim 19 , wherein the voltage at the third voltage supply terminal cyclically changes between a high level and a low level. 21 . The level shift circuit according to claim 20 , wherein the second signal is valid only when the voltage at the third voltage supply terminal is at the low level.

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