An event-driven analog-to-digital converter

Abstract

The application discloses an event-driven analog-digital converter, comprising a signal folding module, a first comparison control circuit, a multi-level comparison module, a second logic control circuit and a folding logic control circuit. The signal folding module is used for folding an input signal and outputting a folded signal. The first comparison control circuit is used for comparing the folded signal with a threshold common-mode voltage, generating a first comparison result and generating a signal direction conversion event pulse according to the first comparison result. The multi-level comparison module is connected with the signal folding module and the first comparison control circuit and is used for comparing the folded signal with an upper threshold voltage or a lower threshold voltage according to the first comparison result, generating a second comparison result. The second logic control circuit is used for generating a sampling mark event pulse according to the second comparison result. The folding logic control circuit is connected with the first comparison control circuit and the second logic control circuit and is used for generating a sampling event pulse and feeding back the sampling event pulse to the signal folding module. The up-down counter module is connected with the first comparison control circuit and the second logic control circuit and is used for generating an amplitude code.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more particularly to an event-driven analog-to-digital converter. Background Technology

[0002] In recent years, MEMS gas sensors have been widely used in industrial production, environmental monitoring, and healthcare. To convert the electrical data from gas sensors into digital signals that are easily processed by digital signal processing systems, analog-to-digital converters (ADCs) are applied to gas sensor systems. When a gas sensor detects an abnormal gas, its output voltage changes, outputting a small analog signal. This change is acquired by the ADC and converted into a digital signal with sufficient speed and accuracy. Finally, the signal is sent to the back-end processing section of the sensing system for odor identification and corresponding concentration prediction.

[0003] In existing technologies, two traditional Nyquist sampling analog-to-digital converters (ADCs)—successive approximation ADCs and Σ-Δ (Sigma-Delta) ADCs—are commonly used to sample analog signals at a fixed sampling frequency before performing analog-to-digital conversion. However, unlike the continuously changing output signals of other sensors, the output information of gas sensors is relatively sparse, remaining constant for most of the time. For example, over 95% of the time during the entire detection period, the output signal of a gas sensor remains essentially unchanged in amplitude. Only within very short time windows does the sensor output high-frequency, large-amplitude signals. This signal characteristic leads to a significant waste of power in ADCs using uniform sampling methods on voltage nodes with no effective information, resulting in low converter efficiency. Furthermore, signals that change within a very short time may not be effectively monitored. Summary of the Invention

[0004] This invention provides an event-driven analog-to-digital converter (ADC) to solve the technical problem that existing ADCs waste a lot of power on voltage nodes with no effective information during sampling, resulting in low energy efficiency of the converter and the inability to effectively monitor signals that change in a very short time.

[0005] To address the aforementioned technical problems, this invention provides an event-driven analog-to-digital converter, comprising:

[0006] The signal folding module includes a switched capacitor circuit for folding the input signal and outputting a folded signal;

[0007] A first comparison control circuit is connected to the output terminal of the signal folding module, and is used to compare the folded signal with the threshold common-mode voltage, generate a first comparison result, and generate a signal direction conversion event pulse based on the first comparison result;

[0008] A multi-level comparison module is connected to the output of the signal folding module and the first comparison control circuit, and is used to select an upper threshold voltage or a lower threshold voltage to compare with the folded signal according to the first comparison result, and generate a second comparison result.

[0009] The second logic control circuit is connected to the output of the multi-level comparison module and is used to generate a sampling marker event pulse based on the second comparison result.

[0010] A folding logic control circuit, connected to the first comparison control circuit and the second logic control circuit, is used to generate a sampling event pulse based on the signal direction conversion event pulse and the sampling marker event pulse, and to feed the sampling event pulse back to the signal folding module.

[0011] The rise-fall counter module is connected to the first comparison control circuit and is also connected to the first comparison control circuit and the second logic control circuit through an OR gate, and is used to generate an amplitude code based on the signal direction conversion event pulse and the sampling mark event pulse;

[0012] Wherein, the threshold common-mode voltage is the average of the upper threshold voltage and the lower threshold voltage.

[0013] Compared with the prior art, the event-driven analog-to-digital converter of the present invention utilizes a signal folding module to fold the input signal. A first comparison control circuit compares the folded signal with a threshold common-mode voltage to generate a first comparison result and generates a signal direction conversion event pulse based on the first comparison result. A multi-level comparison module then selects either an upper or lower threshold voltage to compare with the folded signal based on the first comparison result, generating a second comparison result. A second logic control circuit then generates a sampling marker event pulse based on the second comparison result. Finally, a folding logic control circuit generates a sampling event pulse based on the signal direction conversion event pulse and the sampling marker event pulse, and feeds the sampling event pulse back to... The signal folding module folds the signal according to the sampling event pulse, and the rise / fall counter module generates an amplitude code based on the sampling marker event pulse and the signal direction conversion event pulse. It can be seen that the event-driven analog-to-digital converter of this invention only samples when the amplitude of the input signal changes significantly, greatly reducing the energy loss of the overall system due to useless sampling points. Furthermore, when the input signal changes rapidly, the sampling rate of the event-driven analog-to-digital converter of this invention will adaptively increase, and when the input signal does not change, the sampling rate will adaptively decrease. This means that the sampling rate can be automatically adjusted according to the rate of change of the input signal, thereby significantly improving the energy efficiency ratio of the analog-to-digital converter. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic circuit block diagram of an event-driven analog-to-digital converter according to an embodiment of the present invention.

[0016] Figure 2 yes Figure 1 The diagram shows the specific circuit diagrams of the first and second logic control circuits in the event-driven analog-to-digital converter.

[0017] Figure 3 yes Figure 1 The diagram shows a detailed circuit diagram of the multiplexer in an event-driven analog-to-digital converter.

[0018] Figure 4 yes Figure 1 The diagram shows a detailed circuit diagram of the folding logic control circuit in the event-driven analog-to-digital converter.

[0019] Figure 5 yes Figure 1 The diagram shows a specific circuit diagram of the switched capacitor circuit in the event-driven analog-to-digital converter.

[0020] Figure 6 yes Figure 1 The diagram shows a schematic of the rise / fall counter module in the event-driven analog-to-digital converter.

[0021] Figure 7 yes Figure 6 The diagram shows the specific circuit diagram of the riser counter in the riser counter module.

[0022] Figure 8 This is a schematic diagram of the pulse generator in the event-driven analog-to-digital converter of the present invention.

[0023] Figure 9 This is a waveform diagram of the event-driven analog-to-digital converter of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Reference Figures 1 to 8 , Figures 1 to 8 A specific embodiment of the event-driven analog-to-digital converter of the present invention is illustrated. In the embodiment shown in the figures, the event-driven analog-to-digital converter includes a signal folding module 10, a first comparison control circuit 20, a multi-level comparison module 30, a second logic control circuit 40, a folding logic control circuit 50, and a rise / fall counter module 60. The signal folding module 10 includes a switched capacitor circuit for folding the input signal VIN and outputting a folded signal VON. The first comparison control circuit 20 is connected to the output of the signal folding module 10 and is used to compare the folded signal VON with a threshold common-mode voltage VM to generate a first comparison result and generate a signal direction conversion event pulse based on the first comparison result. The multi-level comparison module 30 is connected to the output of the signal folding module 10 and the first comparison control circuit 20 and is used to select an upper threshold voltage VH or a lower threshold voltage VL based on the first comparison result and compare it with the folded signal. The second comparison result is generated by comparing VON; the second logic control circuit 40 is connected to the output of the multi-level comparison module 30 and is used to generate a sampling marker event pulse CC according to the second comparison result; the folding logic control circuit 50 is connected to the first comparison control circuit 20 and the second logic control circuit 40 and is used to generate a sampling event pulse according to the signal direction conversion event pulse and the sampling marker event pulse CC, and feed the sampling event pulse back to the signal folding module 10; the rise-fall counter module 60 is connected to the first comparison control circuit 20 and is also connected to the first comparison control circuit 20 and the second logic control circuit 40 through an OR gate OR1 and is used to generate an amplitude code according to the sampling marker event pulse CC and the signal direction conversion event pulse; wherein, the threshold common-mode voltage VM is the average of the upper threshold voltage VH and the lower threshold voltage VL.

[0026] Based on the above design, the first comparison control circuit 20, the multi-level comparison module 30, and the second logic control circuit 40 of this invention are used to monitor the changes in the input signal VIN and determine whether a sampling event has occurred. The rise-fall counter module 60 of this invention can generate an amplitude code based on the sampling marker event pulse CC and the signal direction conversion event pulse to quantize the amplitude of the sampling point. The signal folding module 10 can fold the signal based on the sampling event pulse, and sampling is only performed when the amplitude of the input signal VIN changes significantly, which greatly reduces the energy loss of the overall system due to useless sampling points. Moreover, when the input signal VIN changes rapidly, the sampling rate of the event-driven analog-to-digital converter of this invention will adaptively increase, and when the input signal VIN does not change, the sampling rate will adaptively decrease. That is, the sampling rate can be automatically adjusted according to the rate of change of the input signal VIN, thereby significantly improving the energy efficiency ratio of the analog-to-digital converter.

[0027] Continue to refer to Figure 1 and Figure 2 In some embodiments, the first comparison control circuit 20 includes a first comparison module and a first logic control circuit 22. The first comparison module includes a first comparator U21, the non-inverting input of which is connected to the output of the signal folding module 10. The inverting input of the first comparator U21 receives the threshold common-mode voltage VM and is used to compare the folded signal VON with the threshold common-mode voltage VM to generate a first comparison result. The first logic control circuit 22 is connected to the output of the first comparator U21 and includes a first NOT gate NOT1 and a second NOT gate NOT2. The input of the first NOT gate NOT1 is connected to the output of the first comparator U21, and the output of the first NOT gate NOT1 is transmitted via a pulse. The generator is connected to one input of the OR gate OR1, i.e., outputs the UDP signal to the OR gate OR1. The OR gate OR1 receives the UDP and CC signals and outputs the CHANGE signal. The input of the second NOT gate NOT2 is connected to the output of the first NOT gate NOT1. The outputs of the second NOT gate NOT2 and the first NOT gate NOT1 are connected to the multi-level comparison module 30 through a buffer, respectively, and output the UD signal (used to indicate whether the folded signal VON output by the signal folding module 10 is above or below the threshold common-mode voltage VM) and the UDB signal to the multi-level comparison module 30. The output of the second NOT gate NOT2 is also connected to the rise-fall counter module 60, i.e., outputs the UD signal to the rise-fall counter module 60. Understandably, in this embodiment, the sampling marker event pulse includes the UD signal, the UDB signal, and the UDP signal, and the three signals are independent of each other.

[0028] Combination Figure 3 In some embodiments, the multi-level comparison module 30 includes a multiplexer MUX and a second comparator U32. The enable control terminal of the multiplexer MUX is connected to the output terminal of the first comparison control circuit 20. The output terminal of the signal folding module 10, the upper threshold voltage VH, or the lower threshold voltage VL are respectively connected to an input terminal of the multiplexer MUX. The two output terminals of the multiplexer MUX are respectively connected to the non-inverting input terminal and the inverting input terminal of the second comparator U32. The output terminal of the second comparator U32 serves as the output terminal of the multi-level comparison module 30, outputting the second comparison result. Specifically, as shown... Figure 3As shown, the multiplexer MUX includes switches S7, S8, S9, and S10. The control terminals of switches S7 and S9 are connected to the output terminal of the first NOT gate NOT1, and the control terminals of switches S8 and S10 are connected to the output terminal of the second NOT gate NOT2. The input terminals of switches S8 and S9 are connected to the output terminal of the signal folding module 10. The input terminals of switches S7 and S10 are respectively connected to the lower threshold voltage VL and the upper threshold voltage VH. The output terminals of switches S7 and S9 are connected to the inverting input terminal of the second comparator U32, and the output terminals of switches S8 and S10 are connected to the non-inverting input terminal of the second comparator U32. Based on the above design, the multiplexer MUX sends the required signal to both ends of the second comparator U32. When the output signal (RCO signal) of the first comparator U21 is high, it indicates that the signal VON is higher than VM. At this time, the multiplexer MUX sends VH to the non-inverting input of the second comparator U32 and VON to the inverting input of the second comparator U32. When the RCO signal is low, it indicates that the signal VON is lower than VM. At this time, the multiplexer MUX sends VON to the non-inverting input of the second comparator U32 and VL to the inverting input of the second comparator U32. Overall, since VON is between VH and VL most of the time, the second comparator U32 outputs logic 1 most of the time, and only briefly outputs logic 0 when VON crosses VH or VL.

[0029] Continue to refer to Figure 2 In some embodiments, the second logic control circuit 40 includes a CMOS transmission gate TG1, an NMOS transistor S0, a T flip-flop TFF1, a pulse generator, and a first flip-flop. The input of the CMOS transmission gate TG1 is connected to the output of the multi-level comparison module 30. The output of the CMOS transmission gate TG1 and the drain of the NMOS transistor S0 are connected to the clock input pin of the T flip-flop TFF1 through a NOT gate. The source of the NMOS transistor S0 is grounded. The inverted output pin of the T flip-flop TFF1 is connected to the pulse generator. The output of the pulse generator serves as the second logic control circuit 40. The output terminal outputs the sampling marker event pulse CC and connects to the input pin of the first flip-flop. The inverted output pin of the first flip-flop is connected to the lower control terminal of the CMOS transmission gate TG1, and the non-inverted output pin of the first flip-flop is connected to the upper control terminal of the CMOS transmission gate TG1 and the gate of the NMOS transistor S0. This allows the NMOS transistor S0 to be turned off and the CMOS transmission gate TG1 to be turned on when the sampling marker event pulse CC is low, and the NMOS transistor S0 to be turned on and the CMOS transmission gate TG1 to be turned off when the sampling marker event pulse CC is high, thereby latching the T flip-flop TFF1.

[0030] Specifically, in this embodiment, the first comparator U21 and the second comparator U32 are preferably hysteresis comparators, the first flip-flop is preferably an SR flip-flop SR1, and the second logic control circuit 40 further includes a NAND gate NAND0. The output of the OR gate OR1 is connected to one input of the NAND gate NAND0 after passing through a delay unit and a seventh NOT gate NOT7 in sequence. The other input of the NAND gate NAND0 receives a reset signal, and its output is connected to the R input pin of the SR flip-flop SR1. The S input pin of the SR flip-flop SR1 is connected to the output of the pulse generator. Figure 8 As shown, the pulse generators used in this embodiment are all composed of XOR gates and delay units.

[0031] Continue to refer to Figure 1 and Figure 4 In some embodiments, the folded logic control circuit 50 includes a D flip-flop D1, a first NAND gate NAND1, a second NAND gate NAND2, a third NOT gate NOT3, a fourth NOT gate NOT4, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, and a fourth AND gate AND4. The clock input pin of the D flip-flop D1 is connected to the output of the second logic control circuit 40. Its D input pin and QB output pin are connected to an input pin of the first NAND gate NAND1. The Q output pin of the D flip-flop D1 is connected to an input pin of the second NAND gate NAND2. The other input pins of the second NAND gate NAND2 and the first NAND gate NAND1 are connected to the outputs of the first NAND gate NAND1 and the second NAND gate NAND2 respectively via a delay unit, and are also connected to the third NOT gate NOT3 and the fourth NOT gate NOT4 respectively. The input terminals of the first AND gate (NOT3) are connected to the input terminals of the second AND gate (AND1) and the second AND gate (AND2), respectively. The output terminal of the fourth NOT gate (NOT4) is connected to the input terminals of the third AND gate (AND3) and the fourth AND gate (AND4), respectively. The other input terminals of the first AND gate (AND1) and the third AND gate (AND3) are connected to the output terminal of the second NOT gate (NOT2), and the other input terminals of the second AND gate (AND2) and the fourth AND gate (AND4) are connected to the output terminal of the first NOT gate (NOT1). The output terminals of the first AND gate (AND1), the second AND gate (AND2), the third AND gate (AND3), and the fourth AND gate (AND4) are respectively connected to the control terminal of a switching transistor of the switched capacitor circuit, so that the switched capacitor circuit folds the input signal VIN according to the sampling event pulses from the first AND gate (AND1), the second AND gate (AND2), the third AND gate (AND3), and the fourth AND gate (AND4).

[0032] Combination Figure 5In some embodiments, the switched capacitor circuit includes a first capacitor string C1, a second capacitor string C2, a third capacitor string C3, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, and a sixth switch S6. The control terminals of the first switch S1, second switch S2, third switch S3, and fourth switch S4 are respectively connected to the output terminals of the second AND gate AND2, the first AND gate AND1, the fourth AND gate AND4, and the third AND gate AND3. The input terminals of the first switch S1 and the third switch S3 both receive the upper threshold voltage VH, and the input terminals of the second switch S2 and the fourth switch S4 both receive the upper threshold voltage VH. The threshold voltage VL is described below, and the output terminals of the first switch S1 and the second switch S2 are both connected to the midpoint of the third capacitor string C3. The output terminals of the third switch S3 and the fourth switch S4 are both connected to the midpoint of the first capacitor string C1. The midpoint of the second capacitor string C2 is connected to the midpoints of the first capacitor string C1 and the third capacitor string C3 through the fifth switch S5 and the sixth switch S6, respectively. The control terminals of the fifth switch S5 and the sixth switch S6 are respectively connected to the output terminals of the third NOT gate NOT3 and the fourth NOT gate NOT4. The two ends of the first capacitor string C1, the second capacitor string C2, and the third capacitor string C3 are all connected between the input signal VIN and ground. In this embodiment, the second capacitor string C2 is responsible for tracking the input signal VIN. The adjacent first capacitor string C1 and third capacitor string C3 are responsible for shifting the voltage of the input signal VIN by 1 LSB, that is, shifting the voltage of the second capacitor string C2 by 1 LSB. When the VIN signal is between VM and VH, the voltage of the upper plate of the lower capacitor in the capacitor string used for the shift operation will be pre-charged by VL. When the VIN signal is between VM and VL, the voltage of the upper plate of the lower capacitor in the adjacent capacitor string used for the shift operation will be pre-charged by VH.

[0033] Based on the above design, when the input signal VIN crosses VH or VL, the second comparator U32 will be triggered, causing the second logic control circuit 40 to generate a CC pulse. When the input signal VIN is higher than VM, the first comparator U21 will output a logic level of 1; when the input signal VIN is lower than VM, the first comparator U21 will output a logic level of 0. Specifically, when the second logic control circuit 40 generates a CC pulse, if UD is 1, it indicates that the input signal VIN has crossed VH upwards, and the signal folding module 10 will adjust the voltage of the input signal VIN downwards by 1 LSB. If UD is 0, it indicates that the input signal VIN has crossed VL downwards, and the signal folding module 10 will adjust the voltage of the input signal VIN upwards by 1 LSB. The signal folding module 10 will fold the input signal VIN into a window with a width of 2 LSB.

[0034] Reference Figure 9 , Figure 9 This is a waveform diagram of the event-driven analog-to-digital converter of the present invention. When the folded logic control circuit 50 initially operates, RESET resets the D flip-flop D1, Q = 0, QB = 1. At this time, P1 = 1, P2 = 0, P2H = 0, P2L = 0; when UD = 1, P1H = 0, P1L = 1 (the third capacitor string C3 is pre-charged by VL), and when UD = 0, P1H = 1, P1L = 0 (the third capacitor string C3 is pre-charged by VH).

[0035] When UD = 1 and a CC pulse arrives, the D flip-flop D1 is connected with Q(n+1) = QB(n), so the new Q = 1 and QB = 0, causing P1 to change to 0 first and P2 to change to 1. At this time, P1H = 0, P1L = 0, P2H = 0 and P2L = 1. When UD = 1 and a CC pulse arrives, it indicates that VON has crossed VH and needs to be shifted down. Previously, the third capacitor string C3 was precharged by VL, so P1, P1H, and P1L are opened, and P2 is closed, causing the input signal VIN to move down 1 LSB. At the same time, since UD is still 1 and VON is still in the upper LSB, P2L needs to be 1 to precharge the first capacitor string C1 with VL in preparation for the next shift down. It should be noted that P1H and P1L are controlled by P1. When P1 becomes 0 first, it will inevitably cause P1H and P1L to become 0. This operation must be faster than the closing of P2 (by adding a delay unit), otherwise VL will be directly connected to VON.

[0036] When UD = 1 and the next CC pulse arrives, the D flip-flop D1, due to its connection Q(n+1) = QB(n), has a new Q = 0 and QB = 1. This causes P2 to change to 0 first, and then P1 to change to 1. At this time, P1H = 0, P1L = 1, P2H = 0, and P2L = 0. That is, when UD = 1 and the next CC pulse arrives, it indicates that VON has crossed VH and needs to shift down. At this time, the first capacitor string C1 has been precharged by VL, so P2, P2H, and P2L are opened, and P1 is closed, causing the input signal VIN to move down 1 LSB. At the same time, since UD is still 1 and VON is still within the upper LSB, P1L needs to be 1. VL is used to precharge the third capacitor string C3 in preparation for the next shift down. It is important to note here that the delay of the delay unit should be designed reasonably so that P2H = 0 and P2L = 0 are fully set before P1 = 1.

[0037] When no CC pulse is generated, meaning no VON crossover event occurs with VH and VL, but UD transitions from 1 to 0, since the previous D flip-flop D1 state is not updated by CC, P1=1, P2=0, resulting in P1H=1, P1L=0, P2H=0, and P2L=0. (At this point, UD changes from 1 to 0, meaning VON is moving forward, so the third capacitor string C3, which was precharged with VL, needs to be switched to be precharged with VH).

[0038] When UD = 0 and a CC pulse arrives, it indicates that VON has encountered VL. Since the D flip-flop D1 is connected with Q(n+1) = QB(n), the new Q = 1 and QB = 0, causing P1 to change to 0 first, and then P2 to change to 1. At this time, P1H = 0, P1L = 0, P2H = 1, and P2L = 0. That is, when UD = 0 and a CC pulse arrives, it indicates that VON has crossed VL and needs to be shifted up. Previously, the third capacitor was precharged by VH, so P1, P1H, and P1L are opened, and P2 is closed, causing the input signal VIN to move up 1 LSB. At the same time, because UD is still 0 at this time, and VON is in the lower LSB, P2H needs to be 1, using VH to precharge the first capacitor in series C1 to prepare for the next shiftup.

[0039] When UD = 0 and the next CC pulse arrives, it indicates that VON has encountered VL. Since the D flip-flop D1 is connected with Q(n+1) = QB(n), the new Q = 0 and QB = 1, causing P2 to change to 0 first, and then P1 to change to 1. At this time, P1H = 1, P1L = 0, P2H = 0, and P2L = 0. That is, when UD = 0 and a CC pulse arrives, it indicates that VON has crossed VL and needs to shift up. Previously, the first capacitor series C1 was precharged by VH, so P2, P2H, and P2L are opened, and P1 is closed, causing the input signal VIN to move up 1 LSB. At the same time, since UD is still 0 at this time and VON is in the lower LSB, P1H needs to be 1 to precharge the right branch with VH to prepare for the next shift up.

[0040] Combination Figure 6In some embodiments, the ramp counter module 60 includes a ramp counter (COUNTER) and logic gate circuits. The logic gate circuits include a fifth NOT gate (NOT5), a sixth NOT gate (NOT6), a multi-input NOR gate (NOR1), a multi-input AND gate (AND0), a third NAND gate (NAND3), a fourth NAND gate (NAND4), a fifth NAND gate (NAND5), and a first NOR gate (NOR2). The inputs of the fifth NOT gate (NOT5) and the sixth NOT gate (NOT6) are respectively connected to the outputs of the second NOT gate (NOT2) and the OR gate (OR1). The two inputs of the third NAND gate (NAND3) are respectively connected to the outputs of the second NOT gate (NOT2) and the multi-input AND gate (AND0). The two inputs of the fourth NAND gate (NAND4) are respectively connected to the fifth NOT gate (NOT5). The outputs of the NOR1 and NAND3 and NAND4 are respectively connected to the two inputs of the NAND5. The outputs of the NAND5 and NOT6 are respectively connected to the two inputs of the NOR2. The outputs of the NOR2 and NOT2 are respectively connected to the CHANGE pin and UD signal input pin of the COUNTER. The output pin of the COUNTER serves as the output of the COUNTER module 60, used to output amplitude codes, and is connected to the inputs of the NOR1 and AND0.

[0041] In this embodiment, the up-down counter COUNTER is a 6-bit up-down counter, the multi-input NOR gate NOR1 is a 6-bit NOR gate, the multi-input AND gate AND0 is a 6-bit AND gate, and the register is a 6-bit DFF register. Preferably, as follows... Figure 7 As shown, the 6-bit up / down counter (COUNTER) includes 6 TFFs, 5 2-to-1 multiplexers (C), and logic gates. The outputs of the 6 TFFs constitute the 6-bit data of the 6-bit up / down counter (COUNTER). The T signal of the first-stage TFF is set to 1, and the T signal of the subsequent five TFFs depends on the state of the outputs of the previous stages.

[0042] Understandably, the six-bit input NOR gate NOR1 and the six-bit input AND gate AND0 can monitor over- and under-overflow. Therefore, when the up-down counter COUNTER is full, i.e., all 6 bits of the output are 1, O_F = 1; when the up-down counter COUNTER is empty, i.e., all 6 bits of the output are 0, U_F = 1; when O_F = 1 and UD = 1 (indicating that the input signal VIN is still rising), the CHANGE pin of the 6-bit up-down counter COUNTER constructed by TFF is set to 0 and no longer changes (i.e., no longer counts up); when U_F = 1 and UD_B = 1 (UD = 0, indicating that the input signal VIN is still falling), the CHANGE pin of the 6-bit up-down counter COUNTER constructed by TFF is set to 0 and no longer changes (i.e., no longer counts down).

[0043] When the up-down counter (COUNTER) starts working, it is first reset, that is, the RST input of all 6 TFFs is set to 0. At this time, the Q output of each TFF is 0 and the QB output is 1. Table 1 shows the output of each TFF in the 6-bit up-down counter COUNTER under 14 consecutive CHANGE signals. The UD signal is 1 on the rising edge of the first 7 CHANGE signals and 0 on the rising edge of the last 7 CHANGE signals. Since there are only 7 rising edges of CHANGE signals in a specific signal direction, this example only observes the first 3 bits of the up-down counter COUNTER. Understandably, the toggling of the TFF depends on the T generated by the previous rising edge of the CHANGE signal, not the T generated by the current rising edge of the CHANGE signal.

[0044]

[0045]

[0046] Table 1

[0047] As shown in the table above, when the up / down counter (COUNTER) is reset, the output of each bit is set to 0. During the first 7 rising edges of the CHANGE signal when UD = 1, the first three bits gradually change from 000 to 111. During the last 7 rising edges of the CHANGE signal when UD = 0, the first three bits gradually change from 111 to 000. That is, when a rising edge of the CHANGE signal arrives, the up / down counter (COUNTER) will count up or down sequentially according to the indication of UD. In other words, the up / down counter (COUNTER) is changed by the direction of the UD signal.

[0048] Furthermore, in order to output the 6-bit data uniformly only after the output signal of the rise-fall counter (COUNTER) is completely stable, the rise-fall counter module 60 also includes a 6-bit register DFF1. The input pin of the register DFF1 is connected to the output pin of the rise-fall counter (COUNTER), and the output pin of the register DFF1 serves as the output terminal of the rise-fall counter module 60 for outputting the amplitude code. The enable pin of the register DFF1 is connected to the output terminal of the OR gate (OR1) through a delay unit. The CHANGE signal is output to the enable pin of the register DFF1 after the delay unit, serving as the clock trigger signal EN of the 6-bit DFF register DFF1, to ensure that the output of the 6-bit TFF can be completely stable within the delay time. After the CHANGE signal passes through the delay unit, it is also connected to the NAND gate (NAND0) in the second logic control circuit 40 after passing through the seventh NOT gate (NOT7). Thus, the ACK signal is output for new bit sampling monitoring only after the local data processing of the second logic control circuit 40 is completed.

[0049] Understandably, the specific working process of the first logic control circuit 22 and the second logic control circuit 40 of the present invention is as follows: RESET is set to 0, T flip-flop TFF1 outputs: Q=0, QB=1. If there is enough time, CC3 becomes 0. Since RESET=0, rdy=1. In summary, S=0 and R=1 of SR flip-flop SR1, so hld=0 and hldb=1, causing NMOS transistor S0 (high level conduction) to turn off, CMOS transmission gate TG1 to turn on, and CCO signal (output signal of the second comparator U32) can be transmitted. At the same time, the T terminal of TFF1 is set to 1, indicating that when CLK changes on the rising edge, the output of TFF1 will be flipped. When VON is between VH and VL, CCO outputs 1. When VON crosses VH or VL, CCO output becomes 0.

[0050] After the reset is complete, RESET is set to 1. If ACK = 1 (ACK can be represented as a flag indicating that the current data output by the up / down counter COUNTER has been completely stabilized), rdy = 0. For TFF1, the circuit reset is complete and it can start working normally. For SR1, rdy becomes 0, which will not affect its output result, and therefore will not affect the working state of TG1 and S0 transistors.

[0051] When the CCO signal flips from 1 to 0, the output of TG1 flips from 1 to 0. After passing through the NOT gate, the clock input pin of TFF1 flips from 0 to 1. Therefore, the output Q of TFF1 flips from 0 to 1, and QB flips from 1 to 0. After the flip signal of QB output passes through the pulse generator, CC3 will briefly go high. This high level is used as the CC signal through the buffer output, and the brief high level of CC3 will cause the S output of SR1 to briefly become 1, resulting in the output Q of SR1 becoming 1 and QB becoming 0, that is, hld = 1 and hldb = 0 (and this state...). After CC3 becomes 0, the output of SSR1 will not change, causing TG1 to turn off. The output CCO of the second comparator U32 cannot affect the subsequent circuit of TG1. At the same time, the input of NOT0 gate is pulled to 0. At this time, the clock input pin of TFF1 is essentially locked until R of SR1 is set to 1 again (for example, the RESET signal of the NAND0 input pin of NAND gate is set to 0, or the ACK signal is received (indicating that the previous state of the entire ADC has been completely processed and is ready to accept new input)). Only then will the clock input pin of TFF1 accept the new toggle signal.

[0052] In summary, the event-driven analog-to-digital converter of this invention utilizes a signal folding module to fold the input signal. A first comparison control circuit compares the folded signal with a threshold common-mode voltage to generate a first comparison result and, based on the first comparison result, generates a signal direction conversion event pulse. A multi-level comparison module then selects either an upper or lower threshold voltage to compare with the folded signal based on the first comparison result, generating a second comparison result. A second logic control circuit then generates a sampling marker event pulse based on the second comparison result. Finally, a folding logic control circuit generates a sampling event pulse based on the signal direction conversion event pulse and the sampling marker event pulse, and feeds the sampling event pulse back to the signal control module. The signal folding module folds the signal according to the sampling event pulse, and the rise and fall counter module generates an amplitude code based on the sampling mark event pulse and the signal direction conversion event pulse. It can be seen that the event-driven analog-to-digital converter of the present invention only samples when the amplitude of the input signal changes significantly, which greatly reduces the energy loss of the overall system due to useless sampling points. Moreover, when the input signal changes rapidly, the sampling rate of the event-driven analog-to-digital converter of the present invention will adaptively increase, and when the input signal does not change, the sampling rate will adaptively decrease. That is, the sampling rate is automatically adjusted according to the rate of change of the input signal, thereby significantly improving the energy efficiency ratio of the analog-to-digital converter.

[0053] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. An event-driven analog-to-digital converter, characterized by The application relates to a signal folding module, comprising: a signal folding module comprising a switched capacitor circuit, which is used for folding an input signal and outputting a folded signal; a first comparison control circuit connected with the output end of the signal folding module, which is used for comparing the folded signal with a threshold common-mode voltage, generating a first comparison result, and generating a signal direction conversion event pulse according to the first comparison result; a multi-level comparison module connected with the output end of the signal folding module and the first comparison control circuit, which is used for selecting an upper threshold voltage or a lower threshold voltage to compare with the folded signal according to the first comparison result, and generating a second comparison result; a second logic control circuit connected with the output end of the multi-level comparison module, which is used for generating a sampling mark event pulse according to the second comparison result; a folding logic control circuit connected with the first comparison control circuit and the second logic control circuit, which is used for generating a sampling event pulse according to the signal direction conversion event pulse and the sampling mark event pulse, and feeding back the sampling event pulse to the signal folding module; and a up-down counter module connected with the first comparison control circuit and further connected with the first comparison control circuit and the second logic control circuit through an OR gate, which is used for generating an amplitude code. The threshold common-mode voltage is the average of the upper threshold voltage and the lower threshold voltage. The multi-level comparison module comprises a multiplexer and a second comparator, wherein the enable control end of the multiplexer is connected with the output end of the first comparison control circuit, the output end of the signal folding module, the upper threshold voltage or the lower threshold voltage is connected with an input end of the multiplexer respectively, two output ends of the multiplexer are connected with the non-inverting input end and the inverting input end of the second comparator respectively, the output end of the second comparator is used as the output end of the multi-level comparison module, and the second comparison result is outputted. The second logic control circuit comprises a CMOS transmission gate, an NMOS tube, a T flip-flop, a pulse generator and a first flip-flop, the input end of the CMOS transmission gate is connected with the output end of the multi-level comparison module, the output end of the CMOS transmission gate and the drain of the NMOS tube are connected with the clock input pin of the T flip-flop through a NOT gate, the source of the NMOS tube is grounded, the inverting output pin of the T flip-flop is connected with the pulse generator, the output end of the pulse generator is used as the output end of the second logic control circuit, the sampling mark event pulse is outputted, and the input pin of the first flip-flop is connected with the pulse generator, the inverting output pin of the first flip-flop is connected with the lower control end of the CMOS transmission gate, the non-inverting output pin of the first flip-flop is connected with the upper control end of the CMOS transmission gate and the gate of the NMOS tube, so that the NMOS tube is closed and the CMOS transmission gate is opened when the sampling mark event pulse is low, the NMOS tube is opened and the CMOS transmission gate is closed when the sampling mark event pulse is high, and the T flip-flop is latched. ​ ​ ​ ​ 2. The event-driven analog-to-digital converter of claim 1, wherein, ​ 3. An event-driven analog-to-digital converter as claimed in claim 1 or 2, characterized in that, ​ 4. An event-driven analog-to-digital converter as claimed in claim 3, characterized in that, The first trigger is an SR trigger, and the second logic control circuit further comprises an NAND gate, an output of the OR gate is connected to an input of the NAND gate through a delay unit and a seventh NAND gate in sequence, another input of the NAND gate receives a reset signal, and an output of the NAND gate is connected to an R input pin of the SR trigger, and an S input pin of the SR trigger is connected to an output of the pulse generator.

5. The event-driven analog-to-digital converter of claim 1, wherein, The first comparison control circuit comprises: A first comparison module connected to an output of the signal folding module, for comparing the folded signal with a threshold common-mode voltage to generate a first comparison result; A first logic control circuit connected to an output of the first comparison module, comprising a first NAND gate and a second NAND gate, an input of the first NAND gate is connected to the output of the first comparison module, an output of the first NAND gate is connected to an input of the OR gate through a pulse generator, and an input of the second NAND gate is connected to an output of the first NAND gate, an output of the second NAND gate and the output of the first NAND gate are respectively connected to the multi-level comparison module through a buffer, and the output of the second NAND gate is also connected to the up-down counter module.

6. An event-driven analog-to-digital converter as claimed in claim 5, characterized in that, The folding logic control circuit comprises a D trigger, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate, wherein a clock input pin of the D trigger is connected to an output of the second logic control circuit, a D input pin and a QB output pin are connected to an input pin of the first NAND gate, a Q output pin of the D trigger is connected to an input pin of the second NAND gate, another input pins of the second NAND gate and the first NAND gate are respectively connected to outputs of the first NAND gate and the second NAND gate through a delay unit, and are respectively connected to input pins of the third NAND gate and the fourth NAND gate, an output of the third NAND gate is connected to an input pin of the first AND gate and the second AND gate, an output of the fourth NAND gate is connected to an input pin of the third AND gate and the fourth AND gate, another input pins of the first AND gate and the third AND gate are connected to the output of the second NAND gate, another input pins of the second AND gate and the fourth AND gate are connected to the output of the first NAND gate, and outputs of the first AND gate, the second AND gate, the third AND gate, and the fourth AND gate are respectively connected to control ends of switch tubes of the switched capacitor circuit, so that the switched capacitor circuit folds an input signal according to sampling event pulses from the first AND gate, the second AND gate, the third AND gate, and the fourth AND gate.

7. An event-driven analog-to-digital converter as claimed in claim 6, characterized in that, The switch capacitor circuit comprises a first capacitor string, a second capacitor string, a third capacitor string, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube and a sixth switch tube, wherein control ends of the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are connected to output ends of the second AND gate, the first AND gate, the fourth AND gate and the third AND gate respectively, input ends of the first switch tube and the third switch tube receive the upper threshold voltage, input ends of the second switch tube and the fourth switch tube receive the lower threshold voltage, output ends of the first switch tube and the second switch tube are connected to a midpoint of the third capacitor string, output ends of the third switch tube and the fourth switch tube are connected to a midpoint of the first capacitor string, a midpoint of the second capacitor string is connected to midpoints of the first capacitor string and the third capacitor string through the fifth switch tube and the sixth switch tube respectively, and control ends of the fifth switch tube and the sixth switch tube are connected to output ends of the third NOT gate and the fourth NOT gate respectively, and the first capacitor string, the second capacitor string and the third capacitor string are connected between the input signal and the ground.

8. The event-driven analog-to-digital converter of claim 5, wherein, The up-down counter module comprises an up-down counter and a logic gate circuit, the logic gate circuit comprises a fifth NOT gate, a sixth NOT gate, a multi-input OR gate, a multi-input AND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate and a first NOR gate, input ends of the fifth NOT gate and the sixth NOT gate are connected to output ends of the second NOT gate and the OR gate respectively, two input ends of the third NAND gate are connected to output ends of the second NOT gate and the multi-input AND gate respectively, two input ends of the fourth NAND gate are connected to output ends of the fifth NOT gate and the multi-input OR gate respectively, an output end of the fifth NAND gate and an output end of the sixth NOT gate are connected to two input ends of the first NOR gate respectively, an output end of the first NOR gate and an output end of the second NOT gate are connected to a counting pin and a signal input pin of the up-down counter respectively, an output pin of the up-down counter is used as an output end of the up-down counter module and is used for outputting an amplitude code, and input ends of the multi-input OR gate and the multi-input AND gate are connected.

9. An event-driven analog-to-digital converter as claimed in claim 8, characterized in that, The up-down counter module further comprises a register, an input pin of the register is connected to the output pin of the up-down counter, an output pin of the register is used as an output end of the up-down counter module and is used for outputting an amplitude code, and an enable pin of the register is connected to the output end of the OR gate through a delay unit.

10. The event-driven analog-to-digital converter of claim 9, wherein, The up-down counter is a 6-bit up-down counter, the multi-input OR gate is a six-bit input OR gate, the multi-input AND gate is a six-bit input AND gate, and the register is a 6-bit DFF register.

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