Printed circuit board, memory module including same, and method of manufacturing printed circuit board

Abstract

A printed circuit board, a memory module including the same, and a method of manufacturing the printed circuit board are provided. The printed circuit board (PCB) may include: a body having an edge and a first surface on which a semiconductor chip is disposed; a first pin including a first tab extending in a first direction perpendicular to an edge of the body and configured to receive a first signal corresponding to communication between the outside and the semiconductor chip, and a first tie bar protruding from an end of the first tab toward the edge of the body, the first tie bar having a first length; and a second pin including a second tab extending in the first direction and configured to receive a ground voltage of the ground and a second tie bar protruding from an end of the second tab toward an edge of the body, the second tie bar having a second length greater than the first length.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0174936 filed on December 5, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0155647 filed on November 10, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] The disclosed example embodiments relate to an electronic device and a method of manufacturing the electronic device, and more particularly, to a printed circuit board (PCB), a memory module including the printed circuit board (PCB), and a method of manufacturing the PCB. Background Art

[0003] Generally, a central processing unit (CPU) such as a microcomputer and an expansion board for peripheral devices may be mounted on a mainboard of a personal computer. The CPU may generally be mounted on the mainboard in a socket manner or a slot manner. In addition, the expansion board may be mounted on the mainboard by being inserted into an expansion slot such as a peripheral component interconnect (PCI) express slot.

[0004] Semiconductor memories are widely used to store data in various electronic devices such as computers and wireless communication devices. As a type of semiconductor memory, dynamic random access memory (DRAM) operates in a manner of writing and reading data through charges stored in cell capacitors of memory cells. Semiconductor memories may be mounted on a PCB, and the PCB, at least one semiconductor memory, etc. may be configured as a memory module.

[0005] Connecting pins or contact tabs may be formed on a PCB for a memory module, and the PCB may be inserted into a socket provided in a main board, etc. The memory module may be a single in-line memory module (SIMM) structure in which tabs are formed on one surface and a dual in-line memory module (DIMM) structure in which tabs are formed on both surfaces.

[0006] The information disclosed in this background technology section is already known or derived by the inventors before or during the process of implementing one or more embodiments of the present application, or is technical information acquired in the process of implementing one or more embodiments. Therefore, the information disclosed in this background technology section may contain information that does not form prior art known to the public. Summary of the invention

[0007] One or more example embodiments provide a printed circuit board (PCB), a memory module including the PCB, and a method of manufacturing the PCB, which can reduce damage to relatively weak signal pins when the PCB is installed in a socket and can improve resistance and robustness to electrostatic discharge (ESD) of the memory module.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0009] According to one aspect of an example embodiment, a PCB may include: a main body having an edge and a first surface, a semiconductor chip being arranged on the first surface; a first pin including a first protrusion and a first tie rod, the first protrusion extending in a first direction perpendicular to the edge of the main body and configured to receive a first signal corresponding to communication between an external part and the semiconductor chip, the first tie rod protruding from an end of the first protrusion toward the edge of the main body, the first tie rod having a first length; and a second pin, the second pin including a second protrusion and a second tie rod, the second protrusion extending in the first direction and configured to receive a ground voltage of a ground, the second tie rod protruding from an end of the second protrusion toward the edge of the main body, the second tie rod having a second length greater than the first length.

[0010] According to one aspect of an example embodiment, a memory module may include a semiconductor chip and a PCB, the PCB including: a body on which the semiconductor chip is disposed; a first pin spaced apart from an edge of the body by a first distance, the first pin including an end terminal to which a first signal is applied; and a second pin spaced apart from the edge of the body by a second distance smaller than the first distance, the second pin including an end terminal to which a second power supply voltage is applied, the second power supply voltage having a level lower than a level of a first power supply voltage corresponding to power supply to the semiconductor chip.

[0011] According to one aspect of an example embodiment, a method for manufacturing a PCB may include: forming an internal wiring layer on a board layer; disposing an insulating layer on the board layer and the internal wiring layer; forming a contact hole penetrating the insulating layer; forming an external wiring layer on the insulating layer; forming a first pin, the first pin including a first protrusion to which a signal is applied and a first tie bar having a first length; forming a second pin, the second pin including a second protrusion to which a ground voltage is applied and a second tie bar having a second length greater than the first length; and separating the resulting product into a printed circuit board having a first edge portion along a cutting line, the first pin and the second pin being disposed on the first edge portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of certain example embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0013] Figure 1 is a plan view of a printed circuit board (PCB) according to one or more example embodiments.

[0014] Figure 2 is a diagram showing a method according to one or more example embodiments Figure 1 A stereogram of portion A of FIG.

[0015] Figure 3 is a diagram showing a method according to one or more example embodiments Figure 1 A stereogram of part B of FIG.

[0016] Figure 4 is a plan view illustrating a first pin and a second pin according to one or more example embodiments.

[0017] Figure 5 is a plan view illustrating a first pin and a second pin according to one or more example embodiments.

[0018] Figure 6 is a plan view illustrating an arrangement of a plurality of pins according to one or more example embodiments.

[0019] Figure 7 is a plan view illustrating an arrangement of a plurality of pins according to one or more example embodiments.

[0020] Figure 8 is a plan view illustrating a plurality of pins according to one or more example embodiments.

[0021] Fig. 9 is a plan view of a PCB according to one or more example embodiments.

[0022] Fig.10 is a plan view of a PCB according to one or more example embodiments.

[0023] Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig.11E and Fig.11F is a cross-sectional view illustrating a method of manufacturing a PCB according to one or more example embodiments.

[0024] Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E and Fig.12F is a cross-sectional view illustrating a method of processing a surface of a pin according to one or more example embodiments.

[0025] Fig.13 is a perspective view illustrating an example of a substrate according to one or more example embodiments. DETAILED DESCRIPTION

[0026] Hereinafter, the disclosed example embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the accompanying drawings, and their redundant descriptions will be omitted. One or more embodiments described herein are example embodiments, and therefore, the disclosure is not limited thereto and may be implemented in various other forms.

[0027] As used herein, expressions such as "at least one of..." when following a list of elements modify the entire list of elements rather than the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0028] It will be understood that when an element or layer is referred to as being “on”, “over”, “on”, “under”, “below”, “under”, “connected to” or “coupled to” another element or layer, the element or layer can be directly on, over, above, below, under, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on”, “directly over”, “directly on”, “directly below”, “directly under”, “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers.

[0029] Figure 1 is a plan view of a printed circuit board (PCB) according to an embodiment.

[0030] Reference Figure 1 PCB 100 may be a substrate on which one or more semiconductor chips 10 are mounted. Figure 2 The plurality of pins 120 shown in FIG. 1 may be formed near or at one edge (or one edge portion) of the PCB 100. The plurality of pins 120 may constitute a portion of an external wiring layer exposed to the outside of the body 110. Since the edge in which the plurality of pins 120 are formed is inserted into a slot mounted on the main board, the PCB 100 may be mounted on the main board.

[0031] The PCB 100 may be made by coating a conductive foil such as copper (Cu), silver (Ag), or gold (Au) on a flat plate formed by compressing phenol, epoxy glass resin, etc. to a predetermined thickness. Circuit interconnection lines are formed by patterning the copper foil (Cu foil), and electronic components such as semiconductor chips, etc. may be mounted on the PCB 100 by bumps.

[0032] The PCB 100 may be a single-layer PCB and a double-layer PCB. The single-layer PCB may be a substrate in which wiring is formed only on one surface (or the first surface) of the body 110. The double-layer PCB may be a substrate in which wiring is formed on both surfaces (or the first surface and the second surface) of the body 110. In addition, more than three copper foil layers may be formed in three or more layers by using an insulator (such as a prepreg), and three or more interconnection layers (or referred to as wiring layers) may be formed on the PCB 100 according to the number of copper foil layers. In addition, the wiring (also referred to as interconnection line) exposed to the outside may be electrically connected to the plurality of pins 120 through contacts and internal wiring. The wiring exposed to the outside and the plurality of pins 120 may constitute an external wiring layer of the PCB 100.

[0033] The wiring constituting the external wiring layer may be densely formed in a predetermined pattern in and around the mounting area where the semiconductor chip 10 is mounted. The mounting area in which the semiconductor chip 10 is mounted may be set in a specific area on one surface or both surfaces of the main body 110. In the mounting area, the semiconductor chip 10 may be mounted in a flip chip manner so that the semiconductor chip 10 and the wiring may be electrically connected to each other. The semiconductor chip 10 mounted on the main body 110 may be a memory chip or a logic chip. When the semiconductor chip 10 is a memory chip, the semiconductor chip 10 may include a dynamic (random access memory (RAM)) (DRAM), a static RAM (SRAM), a synchronous DRAM (SDRAM), a double data rate (DDR) SDRAM (DDR SDRAM), a low power DDR (LPDDR), a graphic DDR (GDDR) SDRAM, a rambus DRAM (RDRAM), a flash memory, an electrically erasable programmable ROM (EEPROM), etc. The PCB 100 on which such a memory chip is mounted may constitute a memory module. That is, the memory module may include a semiconductor chip 10 implemented as a memory chip, a PCB 100, etc. In this case, the semiconductor chip 10 may be a DDR5-based memory chip, and the memory module may be a DDR5-based memory module.

[0034] In addition, the semiconductor chip 10 may be mounted on only one surface of the body 110 or on both surfaces of the body 110. In one or more embodiments, as Figure 1, the number of semiconductor chips 10 mounted on only one surface of the body 110 may be eight, but the number of semiconductor chips 10 mounted on one surface of the body 110 is not limited to eight. That is, less than or more than eight semiconductor chips 10 may be mounted on both surfaces of the body 110, respectively. For example, 16 semiconductor chips may be mounted on each of the two surfaces of the PCB 100. Although the semiconductor chip 10 is simply shown in a quadrilateral shape, the semiconductor chip 10 may be mounted on the PCB 100 in the form of a package sealed by a sealing material, rather than being mounted on the PCB 100 in the form of a bare chip.

[0035] A plurality of pins 120 may be formed on one surface or both surfaces of the body 110. When a plurality of pins 120 are formed only on one surface of the body 110, a memory module including the semiconductor chip 10 and the PCB 100 may be referred to as a single in-line memory module (SIMM). When a plurality of pins 120 are formed on both surfaces of the body 110, the memory module may be referred to as a dual in-line memory module (DIMM). The structure or device into which the PCB 100 is inserted may be referred to as a socket or a slot. When the memory module is a SIMM, the number of pins 120 may be 144. However, the embodiment is not limited thereto. When the memory module is a DIMM, the number of pins 120 may be 288, and 144 pins may be arranged on both surfaces of the body 110, respectively. However, the embodiment is not limited thereto.

[0036] The body 110 may include a first surface on which at least one semiconductor chip 10 is mounted. In addition, the body 110 may further include a second surface. When the memory module is a SIMM, the semiconductor chip 10 may not be mounted on the second surface. When the memory module is a DIMM, the semiconductor chip 10 may be mounted on the second surface. When only a memory chip is mounted in the mounting area of ​​the body 110, the memory module may be referred to as an unbuffered DIMM (UDIMM).

[0037] The PCB 100 may further include a notch 130 formed at a predetermined position at one edge of the body 110. A first edge region 141 and a second edge region 142 separated by the notch 130 may be provided at one edge of the body 110. Some of the plurality of pins 120 may be arranged and aligned in the first edge region 141, and the remaining pins of the plurality of pins 120 may be arranged and aligned in the second edge region 142.

[0038] Figure 2 is a diagram showing a method according to one or more example embodiments Figure 1 A stereogram of portion A of FIG. Figure 3 is a diagram showing a method according to one or more example embodiments Figure 1 A stereogram of part B of FIG.

[0039] Reference Figure 1 , Figure 2 and Figure 3 , the PCB 100 may include a body 110 and pins 120 formed on the body 110. The pins 120 may constitute a portion of an external wiring layer exposed to the outside of the body 110. The body 110 may include a plurality of edges and a plurality of surfaces. The pins 120 may be arranged on a first surface 110S of the body 110 and may be spaced apart from one edge 110E by a predetermined distance.

[0040] In one or more embodiments, the plurality of pins 120 may include a signal pin and a ground pin. The signal pin may be a metal component through which a signal generated by communication between the outside and the semiconductor chip 10 passes. The outside may represent, for example, a processor (such as a central processing unit (CPU), a graphics processing unit (GPU), or a neural processing unit (NPU)), but the embodiment is not limited thereto. The signal generated by communication between the outside and the semiconductor chip 10 may correspond to a data signal including data, a command signal including a command, an address signal including an address, and the like. The signal passing through the signal pin may include a signal sent from the outside to the semiconductor chip 10, or a signal sent from the semiconductor chip 10 to the outside. For example, a command signal and / or an address signal may be generated externally and sent to the semiconductor chip 10 through a signal pin. For example, a data signal may be generated by the semiconductor chip 10 implemented as a memory chip and sent to the outside through a signal pin, or may be generated externally and sent to the semiconductor chip 10 through a signal pin. The ground pin may be a metal component to which ground (or ground voltage) is applied.

[0041] Reference Figure 2 and Figure 3 In one or more embodiments, the plurality of pins 120 may include a first pin 121, a second pin 122, a third pin 123, and a fourth pin 124. The first pin 121 and the third pin 123 may be spaced apart from the edge 110E of the body 110 by a first distance, and may have an end (or end terminal) to which a signal is applied. The end of the pin coupled to the slot may be referred to as a coupling end. The second pin 122 and the fourth pin 124 may be spaced apart from the edge 110E by a second distance smaller than the first distance, and may have an end (or, a coupling end or end terminal) to which a second power supply voltage having a level lower than that of the first power supply voltage is applied. The first power supply voltage may correspond to a power supply to a memory chip and a core defined in a specification of the Joint Electron Device Engineering Council (JEDEC), and the second power supply voltage may correspond to a power supply return or ground defined in the JEDEC specification.

[0042] Reference Figure 1 and Figure 2 For example, the plurality of pins 120 may include a first pin 121, a second pin 122, and the like. The first pin 121 may correspond to a signal pin. The first pin 121 may include a first tab 121TAB and a first tie-bar 121TB. The first tab 121TAB may extend in a first direction D1 parallel to the first surface 110S (e.g., toward an edge 110E of the body 110). In one or more embodiments, the first direction D1 may be any direction on the first surface 110S. In one or more embodiments, the second direction D2 may be parallel to the first surface 110S. In one or more embodiments, the edge 110E of the body 110 extends in the second direction D2. For example, the first direction D1 may be perpendicular to the second direction D2 along which the edge 110E of the body 110 extends. For example, the first direction D1 may not be perpendicular to the second direction D2, and an angle between 0 degrees and 90 degrees relative to the first direction D1 and the second direction D2 may be formed. When the PCB 100 is installed (or combined) in the socket, the first signal generated by the communication between the outside and the semiconductor chip 10 may pass through the first protrusion 121TAB. The first signal may correspond to a data signal or a control signal including, for example, a command and an address. The first tie bar 121TB may protrude (or extend) from the end of the first protrusion 121TAB toward the edge 110E, and may have a first length along the first direction D1. The second pin 122 may correspond to the ground pin. The second pin 122 may include a second protrusion 122TAB and a second tie bar 122TB. The second protrusion 122TAB may be arranged parallel to the first pin 121 relative to the edge 110E, and may extend in the first direction D1 (for example, toward the edge 110E of the body 110). For example, the first pin 121 and the second pin 122 may be arranged adjacent to each other in the second direction D2. When the PCB 100 is installed (or combined) in the socket, a ground voltage having a ground voltage level may be applied to the second protrusion 122TAB. The second tie bar 122TB may protrude (or extend) from an end of the second tab 122TAB toward the edge 110E and may have a second length along the first direction D1 greater than the first length of the first tie bar 121TB. The plurality of first pins 121 and the plurality of second pins 122 may be repeatedly arranged in the second direction D2 on the first surface 100S.

[0043] Reference Figure 1 and Figure 3For example, the plurality of pins 120 may include a third pin 123, a fourth pin 124, etc. The third pin 123 may correspond to a signal pin and may include a third tab 123TAB and a third tie bar 123TB. The fourth pin 124 may correspond to a ground pin and may include a fourth tab 124TAB and a fourth tie bar 124TB. Since the description of the third pin 123 and the fourth pin 124 is similar to that of the reference Figure 2 The description of the first pin 121 and the second pin 122 are similar, so redundant descriptions thereof are omitted.

[0044] In one or more embodiments, in the case where the pins are included in the same edge region, the positions and directions in which the tie bars are arranged at the ends of the pins may be the same. Figure 1 and Figure 2 For example, the tie bar of the pin 120 included in the first edge region 141 may be located on a first side at the end of the tab (eg, the left end of the tab). Figure 1 and Figure 3 For example, the tie bars of the pins 120 included in the second edge region 142 may be located on the second side at the end of the tab (eg, the right end of the tab). However, the embodiment is not limited thereto.

[0045] In one or more embodiments, the pins included in the first edge region 141 may be formed to be symmetrical with the pins included in the second edge region 142 about an axis extending along the first direction D1. That is, the shape of the pins included in the first edge region 141 may be symmetrical with the shape of the pins included in the second edge region 142. Figure 1 , Figure 2 and Figure 3 For example, in the case where the first pin 121 and the second pin 122 are included in the first edge region 141, the first tie bar 121TB and the second tie bar 122TB may be located at the left end portions of the first tab 121TAB and the second tab 122TAB, respectively. In addition, for the third pin 123 and the fourth pin 124 included in the second edge region 142, the third tie bar 123TB and the fourth tie bar 124TB may be located at the right end portions of the third tab 123TAB and the fourth tab 124TAB, respectively. However, the embodiment is not limited thereto.

[0046] According to one or more embodiments, when a user or a device inserts the PCB 100 into a socket, a ground pin having a relatively close distance from an edge to an end first contacts the socket, and thus, charges accumulated in the memory module by static electricity are released through the ground pin. Therefore, damage to relatively weak signal pins can be reduced, and resistance and robustness of the memory module to electrostatic discharge (ESD) can be improved.

[0047] The grooves (e.g., notches 130) may be formed by removing a portion of the upper and lower surfaces of the body 110. Such grooves may be formed in a form in which the thickness of the body 110 is reduced, and by forming a plurality of grooves in the edge 110E, when the PCB 100 is inserted into the slot, the insertion force may be significantly reduced, and thus, there is an effect of solving problems such as defects of the PCB 100, defects of the slot, and contact failure between the PCB 100 and the slot.

[0048] Figure 4 is a plan view illustrating a first pin and a second pin according to one or more example embodiments.

[0049] Reference Figure 4 , the first pin 410 and the second pin 420 may extend in the first direction D1 on the first surface 110S of the body 110 , and may be adjacently arranged in the second direction D2 .

[0050] The first pin 410 may include a first tab 410TAB and a first tie bar 410TB. The end of the first pin 410 may include an end 410TAB_T of the first tab 410TAB and an end of the first tie bar 410TB. The end 410TAB_T of the first tab 410TAB may correspond to a portion excluding the end of the first tie bar 410TB from the end of the first pin 410.

[0051] The second pin 420 may include a second tab 420TAB and a second tie bar 420TB. The end of the second pin 420 may include an end 420TAB_T of the second tab 420TAB and an end of the second tie bar 420TB. The end 420TAB_T of the second tab 420TAB may correspond to a portion excluding the end of the second tie bar 420TB from the end of the second pin 420.

[0052] In one or more embodiments, the distance between the edge 110E and the component of each pin can be referred to as a sub-spacing. The end of the tie bar and the end of the tab can be referred to as a joining end. Figure 4 , the sub-interval d1 may correspond to the distance between the end of the tie bar 420TB of the second pin 420 and the edge 110E of the body 110, the sub-interval d2 may correspond to the distance between the end of the tie bar 410TB of the first pin 410 and the edge 110E of the body 110, and the sub-interval d3 may correspond to the distance between the end 410TAB_T of the tab 410TAB of the first pin 410 and the edge 110E of the body 110. The sub-interval d3 may also correspond to the distance between the end 420TAB_T of the tab 420TAB of the second pin 420 and the edge 110E of the body 110.

[0053] In one or more embodiments, the end of the first pin 410 may include a first coupling end facing the edge 110E and spaced apart from the edge 110E by a sub-interval d2 (i.e., an end of the tie bar 410TB) and a second coupling end facing the edge 110E and spaced apart from the edge 110E by a sub-interval d3 larger than the sub-interval d2 (i.e., an end 410TAB_T of the tab 410TAB). The end of the second pin 420 may include a third coupling end facing the edge 110E and spaced apart from the edge 110E by a sub-interval d1 smaller than the sub-interval d2 (i.e., an end of the tie bar 420TB) and a fourth coupling end facing the edge 110E and spaced apart from the edge 110E by a sub-interval d3 larger than the sub-interval d1 (i.e., an end 420TAB_T of the tab 420TAB). The sub-interval d3 may correspond to the distance between the end 420TAB_T of the tab 420TAB and the edge 110E and the distance between the end 410TAB_T of the tab 410TAB and the edge 110E so that the sub-interval is the same or substantially the same for both the first pin 410 and the second pin 420 .

[0054] According to the JEDEC specification, the distance between the edge 110E and the end of the tie bar may have a predetermined range. Therefore, in one or more embodiments, the maximum value of the sub-interval d2 may be about 700 micrometers (μm). In addition, the minimum value of the sub-interval d1 may be about 100 μm. The length of each of the first tie bar 410TB and the second tie bar 420TB may be designed and formed in various ways within a range in which the difference between the sub-interval d2 and the sub-interval d1 is included within about 600 μm. In one or more embodiments, the difference between the sub-interval d2 and the sub-interval d1 may be about 200 μm, but the embodiment is not limited thereto.

[0055] When the user inserts the PCB 100 into the slot, the user may apply a relatively large force to the PCB 100, twist the PCB 100 to the left or right, or immediately concentrate the force only on one side of the PCB 100. When the user inserts the PCB 100 into the slot as in one or more embodiments described herein, the tie bar may first contact the slot. In addition, charges may be accumulated in the memory module including the PCB 100 by static electricity. If the tie bar provided on the signal pin contacts the slot before the ground pin when the memory module charged by static electricity is inserted into the slot, the charges accumulated by static electricity are released through the signal pin, which may damage the signal pin having relatively weak resistance.

[0056] According to one or more embodiments, when a user inserts PCB 100 into a slot, a tie bar provided in the pin may first contact the socket. In this case, a ground pin having a relatively long tie bar first contacts the socket, and the charge accumulated in the memory module by static electricity may be released through the ground pin. Therefore, damage to relatively weak signal pins may be reduced, and the resistance and robustness of the memory module to ESD may be improved. That is, when an ESD evaluation is performed on the memory module of the inventive concept, the charge level when a defect occurs is further increased compared to the prior art.

[0057] Figure 5 is a plan view illustrating a first pin and a second pin according to one or more embodiments.

[0058] Reference Figure 5 The first pin 510 and the second pin 520 can be as described above. Figure 4 The first pin 510 may be arranged in parallel as described above, and each may have a lug and a tie bar (e.g., extending toward the edge 100E of the body 110). The end of the first pin 510 may include an end 510TAB_T of the first lug 510TAB and an end of the first tie bar 510TB. The end 510TAB_T of the first lug 510TAB may be referred to as a first combined end. The end of the second pin 520 may include an end 520TAB_T of the second lug 520TAB and an end of the second tie bar 520TB. The end 520TAB_T of the second lug 520TAB may be referred to as a second combined end.

[0059] Reference Figure 5 , the sub-interval d1 may correspond to the distance between the end of the tie bar 520TB of the second pin 520 and the edge 110E of the body 110, and the sub-interval d2 may correspond to the distance between the end of the tie bar 510TB of the first pin 510 and the edge 110E of the body 110. The sub-interval d3 may correspond to the distance between the end 520TAB_T of the tab 520TAB of the second pin 520 and the edge 110E of the body 110. The sub-interval d4 may correspond to the distance between the end 510TAB_T of the tab 510TAB of the first pin 510 and the edge 110E of the body 110. The size of the sub-interval d2 may be larger than the size of the sub-interval d1. The maximum value of the sub-interval d2 may be about 700 μm. In addition, the minimum value of the sub-interval d1 may be about 100 μm. Furthermore, the sub-interval d3 may be smaller than the sub-interval d4 so that the end 510TAB_T of the tab 510TAB of the first pin 510 is spaced apart from the edge 110E by a greater distance than the end 520TAB_T of the tab 520TAB of the second pin 520 is spaced apart from the edge 110E.

[0060] According to one or more embodiments described herein, when a user inserts the PCB 100 into the socket by twisting the PCB 100, the ground pin having a relatively long tie bar first contacts the socket, and the charge accumulated in the memory module by static electricity can be discharged through the ground pin. Therefore, damage to relatively weak signal pins can be reduced, and the resistance and robustness of the memory module to ESD can be improved.

[0061] The PCB 100 may be inserted into the slot by the device. In this case, the PCB 100 may be accurately inserted into the slot without twisting, etc., and the end of the protrusion (or the combined end) may first contact the slot. However, if the end of the signal pin contacts the slot before the ground pin when the memory module charged by static electricity is inserted into the slot, the charge accumulated by static electricity is discharged through the signal pin, which may damage the signal pin.

[0062] According to one or more embodiments, when the device precisely inserts the PCB 100 into the socket, the ground pin having a relatively close distance from the edge 110E to the end of the protrusion first contacts the socket, and thus, the charge accumulated in the memory module by static electricity is discharged through the ground pin. Therefore, damage to relatively weak signal pins can be reduced, and the resistance and robustness of the memory module to ESD can be improved.

[0063] Figure 6 is a plan view showing an arrangement of a plurality of pins according to one or more embodiments.

[0064] Reference Figure 6 PCB 100 may include a first pin 610, a second pin 620, a third pin 630, and a fourth pin 640. The first pin 610 and the third pin 630 may correspond to signal pins, and the second pin 620 and the fourth pin 640 may correspond to ground pins. The first pin 610 and the second pin 620 may correspond to the above reference pins. Figures 2 to 5 The first pin 610, the second pin 620, the third pin 630, and the fourth pin 640 may be included in Figure 1 The first edge region 141 or Figure 1 in the second edge region 142 .

[0065] The third pin 630 may have an end spaced a first distance from one edge (e.g., edge 600E) and applied with a third signal, which is different from the first signal applied to the first pin 610. The first distance may be a distance between one edge and the end of the first pin 610. In one or more embodiments, the first signal and the third signal may be signals of the same type but have different values. For example, the first signal and the third signal may be data signals. In one or more embodiments, the first signal and the third signal may be heterogeneous signals. For example, the first signal may be a data signal, the third signal may be a control signal including a command and an address, or vice versa, and such first and third signals may be applied to embodiments of the inventive concept. The third pin 630 may include a third tab 630TAB and a third tie bar 630TB. The third tab 630TAB may extend in a first direction D1 (e.g., toward the edge 110E of the body 110). In the third tab 630TAB, the third signal may pass. The third tie bar 630TB may protrude from the end 630TAB_T of the third tab 630TAB toward the edge 600E and have a third length. In this case, the third length may be smaller than the second length of the second tie bar 620TB of the second pin 620. For example, the third length may be the same as the first length of the first tie bar 610TB of the first pin 610.

[0066] The fourth pin 640 may have an end portion spaced apart from the edge 600E by a second distance and to which a second power supply voltage is applied. The second distance may be the distance between the edge 600E and the end portion of the second pin 620. The second power supply voltage may be, for example, ground (or ground voltage). The fourth pin 640 may include a fourth tab 640TAB and a fourth tie bar 640TB. The fourth pin 640 may correspond to a ground pin in the same manner as the second pin 620.

[0067] In one or more embodiments, the first pin 610 , the second pin 620 , the third pin 630 , and the fourth pin 640 may be arranged side by side in a parallel direction with respect to the edge 600E.

[0068] In one or more embodiments, the first pin 610, the second pin 620, the third pin 630 and the fourth pin 640 may be arranged sequentially and adjacent in the second direction D2. For example, the first pin 610 and the second pin 620 may be adjacent and arranged side by side in the second direction D2, the second pin 620 and the third pin 630 may be adjacent and arranged side by side in the second direction D2, and the third pin 630 and the fourth pin 640 may be adjacent and arranged side by side in the second direction D2. That is, the second pin 620 may be arranged between the first pin 610 and the third pin 630, and the third pin 630 may be arranged between the second pin 620 and the fourth pin 640. However, the embodiment is not limited thereto. That is, the signal pin and the ground pin may be arranged sequentially one by one. For example, the first pin 610 may be a DQ4 pin defined by the JEDEC specification, the third pin 630 may be a DQ0 pin defined by the JEDEC specification, and the second pin 620 and the fourth pin 640 may be a VSS pin or a ground pin defined by the JEDEC specification. However, the embodiment is not limited thereto.

[0069] Figure 7 is a plan view illustrating an arrangement of a plurality of pins according to one or more example embodiments.

[0070] Reference Figure 7 , the PCB 100 may include a first pin 710, a second pin 720, a third pin 730, and a fourth pin 740. The first pin 710 and the third pin 730 may correspond to a signal pin, and the second pin 720 and the fourth pin 740 may correspond to a ground pin. The first pin 710, the second pin 720, the third pin 730, and the fourth pin 740 may be included in the first edge region 141 or the second edge region 142.

[0071] In one or more embodiments, the first pin 710 and the third pin 730 may be arranged adjacently between the second pin 720 and the fourth pin 740. That is, two signal pins may be arranged adjacent to each other, and the ground pin may be arranged adjacent to two adjacent signal pins. For example, the first pin 710 may be a DQS0_c pin defined by the JEDEC specification, the third pin 730 may be a DQS0_t pin defined by the JEDEC specification, and the second pin 720 and the fourth pin 740 may be a VSS pin or a ground pin defined by the JEDEC specification. However, the embodiment is not limited thereto.

[0072] Figure 8 is a plan view illustrating a plurality of pins according to one or more embodiments.

[0073] Reference Figure 8, PCB 100 may include a first pin 810, a second pin 820, a third pin 830, and a fourth pin 840. The first pin 810 and the third pin 830 may correspond to the signal pin, and the second pin 820 and the fourth pin 840 may correspond to the ground pin. A portion of the lug disposed in each of the first pin 810, the second pin 820, the third pin 830, and the fourth pin 840 may be removed so that the lug edge and the end of the lug may be formed. For example, the lug edge 840TAB_E disposed in the fourth pin 840 may be formed, and the end 840TAB_T of the lug may be formed. That is, the corner of the lug of the fourth pin 840 may be removed to form the lug edge 840TAB_E, and the lug edge 840TAB_E may be formed at an angle between 0 and 90 degrees relative to the first direction D1 and / or the second direction D2. The lug edge and the end of the lug may be formed in each of the first pin 810, the second pin 820, and the third pin 830. Therefore, there is an effect of reducing the manufacturing cost of the plated metal.

[0074] Fig. 9 is a plan view of a PCB according to one or more embodiments.

[0075] Reference Fig. 9 , a semiconductor chip 20 different from the semiconductor chip 10 may be further mounted on the PCB 100. Although the semiconductor chips 10 and 20 are shown only in a quadrangular shape, the semiconductor chips 10 and 20 may be mounted on the PCB 100 in the form of a package sealed by a sealing material, rather than in the form of a bare chip.

[0076] The semiconductor chip 20 may be a buffer chip or a registered clock driver (RCD), and the buffer chip may be placed between the DRAM and the memory controller to relay data transmission. For example, the semiconductor chip 20 implemented as a buffer chip may be an advanced memory buffer (AMB), which is connected to all DRAMs installed on the memory module to store data transmitted from the memory controller in the DRAM, read the requested data from the DRAM, send the requested data to the memory controller, and deliver the data and the request of the memory controller to the AMB of the memory module installed in the next slot. By setting such a buffer chip, a memory module with a large transmission bandwidth and a high capacity can be realized. When the buffer chip is additionally installed in the installation area of ​​the main body 110, the memory module may be referred to as a registered DIMM (RDIMM), a low load DIMM (LRDIMM), etc. In addition, the memory module may be a DDR5-based memory module.

[0077] Fig.10is a plan view of a PCB according to one or more embodiments.

[0078] Reference Fig.10 , on the PCB 100, a DQ resistor 30 (or a DQ buffer or a data buffer) for stabilizing a data signal or a DQ signal may be further mounted. In this case, the semiconductor chip 10 may be a memory chip based on DDR4. Therefore, the memory module may be a UDIMM based on DDR4. Fig. 9 The semiconductor chip 20 may be further mounted on Fig.10 PCB 100. Therefore, the memory module may be a DDR4-based RDIMM or a DDR4-based LRDIMM. According to one or more embodiments described above, the DQ resistor 30 is further mounted on the PCB 100, thereby improving the resistance and robustness of the memory module to ESD.

[0079] Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig.11E and Fig.11F is a cross-sectional view illustrating a method of manufacturing a PCB according to one or more example embodiments.

[0080] Reference Fig.11A First, a PCB original board (e.g., a PCB tray) may be prepared. The PCB tray may include a board layer 110-1 and copper foils 130-1 and 130-2 formed on the top and bottom surfaces of the board layer 110-1. The PCB tray may be referred to as a copper clad laminate (CCL) as a base material for making a PCB. In addition, in one or more embodiments, the copper foils 130-1 and 130-2 may be formed on both sides of the board layer 110-1, but in some cases, any one copper foil may be formed only on one side of the board layer 110-1. The board layer 110-1 may include a resin (e.g., epoxy resin or phenolic resin) as an insulator. Although the resin has excellent insulation properties, the resin has weak strength and has a large dimensional change according to temperature, so paper, glass woven fabric, reinforcement material, etc. may be added to form the board layer 110-1. For example, the board layer 110-1 may include a material such as FR4 (epoxy resin + glass fiber) or FR2 (phenolic resin + paper).

[0081] Reference Fig. 11B, when the copper foils 130-1 and 130-2 are patterned, a first internal wiring 130-1a may be formed on the top surface of the board layer 110-1, and a second internal wiring 130-2a may be formed on the bottom surface of the board layer 110-1. In one or more embodiments, wiring may be formed on both surfaces of the board layer 110-1, but wiring may be formed only on one surface of the board layer 110-1. An insulating substrate (e.g., PCB) having wiring formed only on one side of the board layer 110-1 may be referred to as a single-layer PCB, and a PCB having corresponding wiring formed on both sides of the board layer 110-1 may be referred to as a double-layer PCB. The process of patterning the copper foils 130-1 and 130-2 may be performed by photolithography. For example, first, a laminate film may be completely coated on the copper foils 130-1 and 130-2. Then, after a mask of a desired (or desired) wiring shape is manufactured, ultraviolet rays may be emitted to the laminate film through the mask. After ultraviolet rays are emitted to the laminate film, the laminate film of the ultraviolet irradiated portion may be removed by a developing process. After etching the exposed copper foil using the laminate film remaining after the removal as an etching mask, the laminate film may be removed, and a process of patterning the copper foil may be performed. In one or more embodiments, although the first internal wiring 130-1a and the second internal wiring 130-2a are formed symmetrically with respect to the board layer 110-1, in some cases, the first internal wiring 130-1a and the second internal wiring 130-2a may be formed asymmetrically. In addition, the first internal wiring 130-1a and the second internal wiring 130-2a may include copper, but the materials of the first internal wiring 130-1a and the second internal wiring 130-2a are not limited to copper. For example, the first internal wiring 130-1a and the second internal wiring 130-2a may include various metals such as aluminum, silver and nickel. In addition, the first internal wiring 130-1a and the second internal wiring 130-2a may include a single layer or multiple layers.

[0082] Reference Fig. 11C, after forming the first internal wiring 130-1a and the second internal wiring 130-2a, an insulator (such as prepreg) may be laminated on both surfaces of the board layer 110-1, and thus, an upper insulating layer 140-1 and a lower insulating layer 140-2 may be formed. Prepreg may be an intermediate material for a fiber-reinforced composite material, and may indicate a molding material in which a matrix resin is preliminarily injected (impregnated) into reinforcing fibers. Generally, the prepreg may be stacked on the board layer 110-1, heated, pressed, and then cured to form a multi-layer PCB substrate. In one or more embodiments, a three-layer PCB may be formed by stacking prepreg on both surfaces of the board layer 110-1, but the PCB of one or more embodiments described herein is not limited to three layers. For example, a five-layer or more-layer PCB may be formed by stacking four or more prepregs. The board layer 110-1, the first internal wiring 130-1a, the second internal wiring 130-2a, the upper insulating layer 140-1, and the lower insulating layer 140-2 may be constructed in the body 110 of the PCB 100. When the copper foil is included in the outermost layer other than the insulator, the insulator (such as prepreg) may be stacked. For example, the copper foil may be included on both sides of the board layer 110-1. Fig. 11C The process can then be executed FIG. 11D to FIG. 11F technology.

[0083] Reference Fig.11D , a contact hole H penetrating the upper insulating layer 140-1a and the lower insulating layer 140-2a may be formed. 1 and H 2 . Through the contact hole H 1 and H 2 The contact hole H may be formed by various methods. 1 and H 2 For example, the contact hole H may be formed by a drill or a laser. 1 and H 2 In addition, the contact hole H may be formed by an etching process such as photolithography. 1 and H 2 In one or more embodiments, although the contact hole H is formed in a symmetrical structure with respect to the plate layer 110 - 1 1 and H 2 , but in some cases, the contact hole H may be formed asymmetrically 1 and H 2 .

[0084] Reference Fig.11E , in forming the contact hole H 1 and H 2Thereafter, plating layers 150-1 and 150-2 may be formed on the upper insulating layer 140-1a and the lower insulating layer 140-2a, and the contact holes H 1 and H 2 The plating layers 150-1 and 150-2 are formed to form the contact hole H' 1 and H' 2 The plating layers 150-1 and 150-2 may be formed by non-electrolyte plating and electrolyte plating. For example, non-electrolyte plating may be performed first, and then electrolyte plating may be performed using the non-electrolyte plating layer as a metal seed. As shown, the plating layers 150-1 and 150-2 may be formed not only on the upper insulating layer 140-1a and the lower insulating layer 140-2a, but also on the contact hole H'. 1 and H' 2 The plated layers 150-1 and 150-2 are formed inside. The plated layer portions on the top surfaces of the upper insulating layer 140-1a and the lower insulating layer 140-2a can be formed through the contact holes H' 1 and H' 2 The plating portions in the first and second internal wirings 130-1a and 130-2a are electrically connected. In one or more embodiments, the plating layers 150-1 and 150-2 may include copper, which is the same material as the first and second internal wirings 130-1a and 130-2a. In some cases, the plating layers 150-1 and 150-2 may include a metal different from copper (such as Ni or Ni / Cu). Fig.11E The process can form Figure 5 The step difference between the end of the protrusion provided in the ground pin and the end of the protrusion provided in the signal pin is shown in FIG.

[0085] Reference Fig.11F , a patterning process may be performed on the plating layers 150-1 and 150-2, thereby forming the first external wiring 150-1a and the second external wiring 150-2a. The patterning of the plating layers 150-1 and 150-2 may be performed by an etching method similar to the patterning of the copper foil described above. The contact hole H' may be maintained. 1 and H' 2 The first external wiring 150-1a and the second external wiring 150-2a may be formed by plating the inside, and a contact 155 connecting the first external wiring 150-1a and the second internal wiring 130-1a and the second internal wiring 130-2a may be formed. The first external wiring 150-1a and the second external wiring 150-2a may include an external wiring layer exposed to the outside in the PCB. The external wiring layer may include wiring exposed in an area where a chip is mounted and pins exposed in an edge portion.

[0086] Thereafter, the final PCB may be completed through a photoresist coating process, a surface treatment process (such as plating or an organic solderability protection (OSP) process) using nickel, gold, etc. only in a plated area of ​​a pin, a wiring process, a bare board test (BBT) process, etc. The wiring process may refer to a process of cutting and separating a large original substrate into individual PCBs, and the BBT process refers to an electrical testing process for the individual PCBs.

[0087] Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E and Fig.12F is a cross-sectional view illustrating a method of processing a surface of a pin according to one or more example embodiments. Specifically, Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E and Fig.12F is a cross-sectional view illustrating a surface treatment process of performing a plating process on a plated region of a pin to form a signal pin and a ground pin according to an embodiment.

[0088] Reference Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E and Fig.12F , an operation of forming a first pin and a second pin from a resulting structure of forming an external wiring layer can be performed, the first pin including a first protrusion to which a signal is applied and a first tie bar having a first length, and the second pin including a second protrusion to which a ground voltage is applied and a second tie bar having a second length longer than the first length.

[0089] Reference Fig. 12A , after performing the photo solder resist coating process, a first wet film WFLM1 may be disposed on a portion of the tie bar in the coating region PSR so that a portion of the tie bar is masked during plating. The portion where the first wet film WFLM1 is disposed may correspond to a non-plating region. A distance a1 between an end of the first wet film WFLM1 and an end of the protrusion may be about 38 μm, but the embodiment is not limited thereto.

[0090] Reference Fig. 12B , the first dry film DFLM1 may be disposed on a portion of the protrusion in the coating region PSR, and thus may mask a portion of the protrusion during plating. The distance a1 may be about 38 μm, but the embodiment is not limited thereto.

[0091] Reference Fig. 12CPlating using metal such as nickel or gold may be performed in the plating region PLT except for a portion masked by the first dry film DFLM1 and the first wet film WFLM1 in the coating region PSR, and a stripping process for removing the first dry film DFLM1 and the first wet film WFLM1 may be performed.

[0092] Reference Fig.12D , the second wet film WFLM2 may be arranged on a non-plated area corresponding to a portion of the tie bar in the coating region PSR, a portion of the plating region PLT corresponding to the tie bar, and a portion of the plating region PLT corresponding to the protrusion. Therefore, the area on which the second wet film WFLM2 is arranged may be masked. A distance a2 from an end of the protrusion to an end of the second wet film WFLM2 may be about 95 μm, but the embodiment is not limited thereto.

[0093] Reference Fig.12E The second dry film DFLM2 may be disposed in the non-plating region corresponding to a portion of the tab in the coating region PSR and on a portion of the plating region PLT so that the region in which the second dry film DFLM2 is disposed may be masked. The distance a2 may be about 95 μm, but the embodiment is not limited thereto.

[0094] Reference Fig.12F , a portion of the tie bar of the coating region PSR may be etched in a state where the second wet film WFLM2 and the second dry film DFLM2 are disposed, and a stripping process for removing the second dry film DFLM2 and the second wet film WFLM2 may be performed. A length a3 of the tie bar remaining after the etching process for a portion of the tie bar may be about 130 μm at maximum, but the embodiment is not limited thereto.

[0095] In one or more embodiments, performing Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E and Fig.12F The pins of the process shown in the figure may be signal pins, but the embodiment is not limited thereto. According to the embodiment, the ground pins and the signal pins are subjected to Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E and Fig.12F In the process shown in FIG. 1 , the process of etching the tie bar may be different for each pin, so that the length of the tie bar disposed in the ground pin is greater than the length of the tie bar disposed in the signal pin.

[0096] Fig.13 is a perspective view illustrating an example of a substrate according to one or more example embodiments.

[0097] Reference Fig.13 PCB manufacturing processes may include the processing of large raw substrates such as FIG. 11A to FIG. 12F The series of processes shown in FIG, and the process of separating the original substrate into individual PCBs along the cutting lines. Fig.13 , for example, an operation of separating the resulting product having the external wiring layer formed on the original substrate according to the cutting line and separating the resulting product into separate PCBs having a first edge on which the first pin and the second pin are arranged is performed. In the PCB manufacturing process of the inventive concept, the ground pin GP and the signal pin SP may have tie bars of different lengths, and according to an embodiment, the distance between the end of the protrusion provided in each of the ground pin GP and the signal pin SP and the edge of the PCB may be different.

[0098] Each of the one or more embodiments provided in the above description is not exclusive of association with one or more features of additional examples or additional embodiments that are also provided herein or that are not provided herein but are consistent with the disclosure.

[0099] While the disclosure has been particularly shown and described with reference to disclosed embodiments, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A printed circuit board, comprising: a body having an edge and a first surface, the semiconductor chip being disposed on the first surface; The first pin includes: a first tab extending toward an edge of the body in a first direction parallel to the first surface and configured to receive a first signal corresponding to communication between the outside and the semiconductor chip, and a first tie rod protruding from an end of the first tab toward an edge of the main body, the first tie rod having a first length along a first direction; and A second pin is adjacent to the first pin, and the second pin includes: a second tab extending in a first direction toward an edge of the body and configured to receive a ground voltage, and The second tie rod protrudes from an end of the second protruding piece toward an edge of the main body, and the second tie rod has a second length along the first direction that is greater than the first length.

2. The printed circuit board according to claim 1, wherein: A first sub-spacing between an edge of the body and an end of the first tie bar is larger than a second sub-spacing between an edge of the body and an end of the second tie bar.

3. The printed circuit board according to claim 2, wherein: The first sub-interval is less than or equal to 700 microns.

4. The printed circuit board according to claim 2, wherein: The second sub-interval is at least 100 microns.

5. The printed circuit board according to claim 1, wherein A third sub-space between an end of the first tab and an edge of the body is greater than or equal to a fourth sub-space between an end of the second tab and an edge of the body.

6. The printed circuit board according to claim 1, wherein The subject also includes: notch, at the edge of the main body; a first edge region on a first side of the body; and a second edge region, on a second side of the body, The gap is between the first edge region and the second edge region. The first pin and the second pin are both in the first edge region or the first pin and the second pin are both in the second edge region, and The first tie rod and the second tie rod are respectively located on the same side of the first pin and the second pin.

7. The printed circuit board according to claim 1, wherein: The subject also includes: notch, at the edge of the main body; a first edge region on a first side of the body; and a second edge region, on a second side of the body, The gap is between the first edge region and the second edge region. Wherein, the first pin is in the first edge region, wherein the first tie rod is located on a first side of the first pin, wherein the second pin is in the second edge region, and The second tie rod is located on a second side of the second pin, and the second side of the second pin is different from the first side of the first pin.

8. The printed circuit board according to claim 1, further comprising a third pin, the third pin comprising: a third tab extending in the first direction toward an edge of the body and configured to receive a second signal different from the first signal; as well as The third tie rod protrudes from an end of the third protruding piece toward an edge of the main body, and the third tie rod has a third length along the first direction that is smaller than the second length.

9. The printed circuit board according to claim 8, wherein: The first pin, the second pin and the third pin are sequentially arranged in a second direction perpendicular to the first direction, wherein the first pin and the second pin are adjacent to each other, and The second pin and the third pin are adjacent to each other.

10. The printed circuit board according to claim 8, wherein: The first pin is adjacent to the third pin, and The third pin is adjacent to the second pin and is between the first pin and the second pin.

11. A memory module, comprising: Semiconductor chips; as well as Printed circuit boards, including: a main body, a semiconductor chip being arranged on the main body, a first pin spaced apart from an edge of the body by a first distance, the first pin including an end terminal to which a first signal is applied, and The second pin is spaced apart from the edge of the body by a second distance smaller than the first distance, and includes an end terminal to which a second power supply voltage having a level lower than that of a first power supply voltage corresponding to power supply to the semiconductor chip is applied.

12. The memory module according to claim 11, wherein: The first pin includes: a first tie bar extending toward an edge of the body and spaced apart from the edge of the body by a first subspace, and a first tab extending toward an edge of the body and spaced from the edge of the body by a second subspace that is larger than the first subspace, and Wherein, the second pin includes: a second tie bar extending toward an edge of the body and spaced from the edge of the body by a third sub-space smaller than the first sub-space, and The second tab extends toward the edge of the main body and is spaced apart from the edge of the main body by a fourth subspace that is larger than the third subspace.

13. The memory module according to claim 12, wherein: The first sub-interval is less than or equal to 700 microns, and The third sub-interval is at least 100 micrometers.

14. The memory module according to claim 11, wherein: The printed circuit board also includes: a third pin spaced apart from an edge of the body by a first distance, the third pin including an end to which a third signal is applied, and The first pin, the second pin and the third pin are arranged in a direction parallel to the edge of the main body.

15. The memory module according to claim 14, wherein: The first pin is arranged adjacent to the second pin, and The second pin is arranged adjacent to the third pin.

16. The memory module according to claim 14, wherein: The first pin is arranged adjacent to the third pin, and The second pin is arranged to be adjacent to the first pin or the third pin.

17. The memory module according to claim 14, wherein: The printed circuit board also includes: a fourth pin spaced apart from an edge of the body by a second distance, the fourth pin including an end to which a second power supply voltage is applied, and The first pin, the second pin, the third pin and the fourth pin are arranged in a direction parallel to the edge of the main body.

18. The memory module according to claim 17, wherein: The second pin is disposed between the first pin and the third pin, and The third pin is arranged between the second pin and the fourth pin.

19. The memory module according to claim 17, wherein: The subject also includes: notch, at the edge of the main body; a first edge region on a first side of the body; and a second edge region, on a second side of the body, The gap is between the first edge region and the second edge region. The first pin and the second pin are both in the first edge region. The third pin and the fourth pin are both in the second edge region. The shape of the first pin is symmetrical to the shape of the third pin, and The shape of the second pin is symmetrical to the shape of the fourth pin.

20. A method for manufacturing a printed circuit board, the method comprising: forming an internal wiring layer on the board layer; Providing an insulating layer on the board layer and the internal wiring layer; forming a contact hole penetrating the insulating layer; forming an external wiring layer on the insulating layer; forming a first pin, the first pin comprising a first protrusion to which a signal is applied and a first tie bar having a first length; forming a second pin to form a resulting product, the second pin comprising a second tab to which a ground voltage is applied and a second tie bar having a second length greater than the first length; as well as The resultant product is separated along the cutting line into a printed circuit board having a first edge portion, and the first lead and the second lead are disposed on the first edge portion.

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