Circuit board and method of manufacturing circuit board
By improving the circuit board structure, using solder balls to protect the connection and forming the groove portion and connecting pad, the problem of underfill components oozing in the stacked package is solved, and the reliability of the package and the performance of electronic products are improved.
Patent Information
- Application Number
- CN202411141375.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-13
- Filing Date
- 2024-08-20
- Publication Date
- 2025-05-13
AI Technical Summary
In a stacked package (POP) structure, after connecting the upper and lower packages with solder balls, the bottom fill components are prone to seep out, resulting in a reduced reliability between the packages and affecting the performance of electronic products.
By improving the board structure of the circuit board, using solder balls to protect the connection, forming grooves and connection pads, avoiding the leakage of the underfill material and ensuring the assembleability of the package.
It effectively avoids the leakage of the underfill material, improves the reliability between the packages, and ensures the performance of electronic products and the yield of packaging and assembly.
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Figure CN119997357A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a circuit board and a method of manufacturing the circuit board. Background Art
[0002] Electronic products tend to become increasingly miniaturized and multifunctional, so that packaging technology is also constantly developing. In particular, the package-on-package (POP) structure plays an important role in improving the performance and functionality of electronic products. The POP structure integrates various functions, enables miniaturization, and includes multi-layer packaging to perform connections between upper and lower packages. Solder balls are usually used for connection, and the solder balls provide electrical and mechanical connections between packages, while maintaining the conductivity of each package.
[0003] However, if the interposer substrate and the memory substrate are mounted up and down in the POP structure and connection using solder balls is performed, certain problems may occur. If the bottom fill component is injected after the lower package is connected to the upper package using solder balls, a phenomenon in which the bottom fill component seeps out to the connection part using solder balls is found. Because the seepage phenomenon deteriorates the reliability between the packages and affects the performance of electronic products, there is a need for improved packaging technology to solve this problem. Summary of the invention
[0004] An aspect of the disclosed embodiment is to provide a circuit board and a method of manufacturing the circuit board, which ensure package assemblability by improving a board structure to protect connection parts using solder balls that provide connection between packages in a packaging process to prevent seepage of an underfill material.
[0005] However, the problems to be solved by the embodiments of the present disclosure are not limited to the above-mentioned problems, and various extensions can be made within the scope of the technical concept included in the present disclosure.
[0006] According to an embodiment, a circuit board includes: an insulating layer having a first surface and a second surface facing each other and including a groove portion recessed inward from the first surface of the insulating layer; a first connection pad embedded in the insulating layer and exposed from the first surface of the insulating layer; and a first protective layer covering the insulating layer and being opened to expose the first connection pad and the groove portion from the first surface of the insulating layer.
[0007] The first protective layer may include a first opening exposing the first connection pad and a second opening exposing the groove portion.
[0008] In terms of width along a first direction parallel to the first surface of the insulating layer, a width of the second opening may be greater than a width of the groove portion.
[0009] In terms of width along a first direction parallel to the first surface of the insulating layer, a width of the first opening may be smaller than a width of the first connection pad.
[0010] A bottom surface of the groove portion may be disposed away from an exposed surface of the first connection pad.
[0011] A bottom surface of the groove portion may be disposed further away from the first surface of the insulating layer than a bottom surface of the first connection pad.
[0012] A recessed depth of the groove portion may be greater than a thickness of the first connection pad along a second direction perpendicular to the first surface of the insulating layer.
[0013] A recessed depth of the groove portion may be smaller than a thickness of the insulating layer along a second direction perpendicular to the first surface of the insulating layer.
[0014] The groove portion may be disposed adjacent to the first connection pad.
[0015] The circuit board may further include a plurality of first connection pads, wherein the groove portion may be provided between first connection pads adjacent to each other among the plurality of first connection pads.
[0016] An exposed surface of the first connection pad may be coplanar with the first surface of the insulating layer.
[0017] The circuit board may further include a second connection pad disposed to protrude from the second surface of the insulating layer.
[0018] The circuit board may further include a second protection layer partially covering the insulating layer and the second connection pads on the second surface of the insulating layer.
[0019] The insulating layer may include a prepreg sheet (PPG).
[0020] The protection layer may include a solder resist (SR).
[0021] According to an embodiment, the method for manufacturing the circuit board includes: forming a conductive layer including a first metal on a seed layer including a second metal; patterning a first plating resist covering the conductive layer, and plating the first metal to form a protruding pattern layer on the conductive layer; patterning a second plating resist covering the conductive layer and the protruding pattern layer, and plating the second metal to form a connecting pad on the conductive layer; forming an insulating layer to cover the protruding pattern layer and the connecting pad; and removing the protruding pattern layer by etching the protruding pattern layer, and forming an inwardly recessed groove portion on the surface of the insulating layer.
[0022] The method may further include forming a protection layer on the surface of the insulating layer, the protection layer being opened to expose the connection pad and the groove portion.
[0023] The second metal may include copper (Cu), and the first metal may include tin (Sn).
[0024] The groove part may be formed at a portion corresponding to the protrusion pattern layer.
[0025] The circuit board according to the disclosed embodiments can ensure package assemblability by improving the board structure (or substrate structure) to protect the connection portion using solder balls that provide connection between packages in the packaging process to prevent the underfill material from seeping out.
[0026] Based on the circuit board according to the embodiment, a connection pad can be formed at a circuit board manufactured using an embedded trace substrate (ETS) method, and a board structure without a step difference between an embedded copper pattern and a surface of a polypropylene glycol (PPG) insulating layer can be manufactured, so that the package assembly yield is improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 is a cross-sectional view showing a circuit board according to an embodiment.
[0028] Figures 2 to 17 It shows the manufacturing Figure 1 A cross-sectional view of the process of manufacturing a circuit board is shown. DETAILED DESCRIPTION
[0029] The present disclosure will be described more fully below with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. The drawings and description are to be considered illustrative rather than restrictive in nature. Throughout the specification, the same or similar reference numerals represent the same or similar elements. In the drawings, for ease of description, the size (e.g., thickness) of each element is arbitrarily shown, and the present disclosure is not necessarily limited to the size and (e.g., thickness) as shown in the drawings.
[0030] In addition, the drawings are only for easy understanding of the embodiments disclosed in this specification, and the technical concepts disclosed in this specification are not limited by the drawings, and it should be understood that the present disclosure includes all modifications, equivalents or alternatives within the spirit and technical scope of the present disclosure.
[0031] Terms including ordinal numbers such as first, second, etc. may be used to describe various constituent elements, but the constituent elements are not limited by these terms. These terms are used only for the purpose of distinguishing one constituent element from another constituent element.
[0032] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "over" another element, the element may be directly on the other element, or intervening elements may also be present. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, throughout the specification, the words "on" or "over" a target element will be understood as being disposed above or below the target element, and will not necessarily be understood as being disposed on the "upper side" based on a direction opposite to the direction of gravity.
[0033] In the present application, terms such as "include" or "have" are intended to indicate the presence of the features, quantities, steps, operations, constituent elements, parts or combinations thereof described in the specification, and should be understood as not excluding the possibility of the presence or addition of one or more other features, quantities, steps, operations, constituent elements, parts or combinations thereof. In addition, unless explicitly described to the contrary, the word "include" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of the stated elements without excluding any other elements.
[0034] Furthermore, throughout the specification, the phrase “on a plane” means observing a target portion from the top, and the phrase “on a cross section” means observing a cross section formed by vertically cutting the target portion from the side.
[0035] In addition, throughout the specification, "connection" means a case where two or more constituent elements are directly connected, or a case where two or more constituent elements are indirectly connected via another constituent element, or a case where they are physically connected or electrically connected, and "connection" may include a case where substantially integral parts (although they are referred to by different names according to positions or functions) are connected to each other.
[0036] Figure 1 is a cross-sectional view showing a circuit board according to an embodiment.
[0037] Reference Figure 1 According to the present embodiment, the circuit board 100 includes an insulating layer 110, circuit wiring embedded in the insulating layer 110, and protective layers 131 and 135 covering at least one surface (e.g., a portion of at least one surface) of the insulating layer 110 (e.g., in the present disclosure, the understanding of "covering" may be that only a portion of the covered object is covered). The insulating layer 110 and the circuit wiring may have an embedded trace substrate (ETS) structure. The circuit board 100 may be a printed circuit board that can be used for a semiconductor package.
[0038] The insulating layer 110 may have a first surface 110a and a second surface 110b opposite to each other, and may include a resin insulating layer. The insulating layer 110 may be a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a resin (for example, a prepreg) prepared by impregnating a reinforcing material (such as glass fiber or an inorganic filler) in a thermosetting resin or a thermoplastic resin. In addition, the insulating layer 110 may include a thermosetting resin and / or a photocurable resin, but the present disclosure is not limited thereto.
[0039] The circuit wiring may be embedded in the insulating layer 110, and may include a first connection pad 121 exposed from the insulating layer 110 on the first surface 110a and a second connection pad 125 protruding from the second surface 110b of the insulating layer 110. The circuit wiring may include a via 123 penetrating the insulating layer 110 to connect the first connection pad 121 and the second connection pad 125, and may include a wiring extending within the insulating layer 110 without being exposed. The circuit wiring may include copper (Cu), and may be connected to a terminal of an external circuit component through the first connection pad 121 exposed from the insulating layer 110 and the second connection pad 125 protruding from the insulating layer 110.
[0040] In this case, the exposed surface of the first connection pad 121 may be coplanar with the first surface 110a and may not form a step difference. That is, even if the insulating layer 110 has the ETS structure, the exposed surface of the first connection pad 121 embedded in the insulating layer 110 may not be recessed from the surface of the insulating layer 110.
[0041] The protective layers 131 and 135 may include a first protective layer 131 covering the first surface 110a of the insulating layer 110 and a second protective layer 135 covering the second surface 110b. The first protective layer 131 may be opened to expose a portion of the first connection pad 121 located on the same surface as the first surface 110a. The second protective layer 135 may cover a portion of the second connection pad 125 and a portion of the second surface 110b of the insulating layer 110, and the second protective layer 135 may also be opened to expose a portion of the second connection pad 125. The protective layers 131 and 135 may include a solder resist layer.
[0042] The insulating layer 110 may include a groove portion 115 recessed inward from the first surface 110a. The first protective layer 131 covering the insulating layer 110 may be opened to expose the groove portion 115. Therefore, the first protective layer 131 may include a first opening 131a to expose the first connection pad 121 and a second opening 131b to expose the groove portion 115. In terms of the width along the first direction parallel to the first surface 110a of the insulating layer 110, the width of the second opening 131b may be formed to be larger than the width of the groove portion 115. In addition, in terms of the width along the first direction, the width of the first opening 131a may be formed to be smaller than the width of the first connection pad 121.
[0043] The bottom surface of the groove portion 115 may be disposed further away from the surface of the insulating layer 110 (i.e., the first surface 110a) than the bottom surface of the first connection pad 121 (i.e., the surface of the first connection pad 121 opposite to the exposed surface of the first connection pad 121). In this case, the recessed depth of the groove portion 115 may be formed to be greater than the thickness of the first connection pad 121 along the second direction perpendicular to the first surface 110a of the insulating layer 110. In addition, the recessed depth of the groove portion 115 may be formed to be less than the thickness of the insulating layer 110 along the second direction.
[0044] The first connection pad 121 may be provided in plural, and the groove portion 115 may be provided adjacent to the first connection pad 121. In addition, the groove portion 115 may be provided between the first connection pads 121 adjacent to each other.
[0045] In the packaging process, an electronic component (not shown) may be mounted on the circuit board 100 by a solder ball (not shown) provided at the first connection pad 121. In this case, an underfill material may be injected between the electronic component and the circuit board 100. Underfill seepage may occur in which the injected underfill material overflows from the first opening 131a of the first protective layer 131 that exposes the first connection pad 121 to flow to the surrounding area. The groove portion 115 adjacent to the first connection pad 121 may accommodate the overflowed underfill material, so that the overflowed underfill material can be prevented from flowing into another surrounding first connection pad 121. Therefore, the groove portion 115 adjacent to the first connection pad 121 can prevent contamination.
[0046] according to Figure 1 In the embodiment shown, an insulating layer 110, two connection pads 121 and 125 and a via 123 connecting the two connection pads 121 and 125 are shown, but the present disclosure is not limited thereto. In addition, a larger number of stacked insulating layers and a larger number of stacked circuit wiring layers may be included, and this also falls within the scope of the present disclosure.
[0047] Figures 2 to 17 It shows the manufacturing Figure 1 A cross-sectional view of the process of manufacturing a circuit board is shown.
[0048] Reference Figures 2 to 5 , a carrier substrate 60 in which a first seed layer 71 and a conductive layer 75 are provided on at least one surface thereof is prepared, and a protruding pattern layer 78 is formed on the conductive layer 75 by a protruding pattern forming process. The carrier substrate 60 may be a board in which a copper foil layer 62 is laminated on both surfaces of an insulating material 61, and the first seed layer 71 and the copper foil layer 62 may be separated from each other. The insulating material 61 may be a double separated core (DCF) layer. The conductive layer 75 may be formed on the first seed layer 71 by plating (see Figure 2 ). The conductive layer 75 may include a first metal, and the first seed layer 71 may include a second metal. The first metal may be a different metal from the second metal, and etching conditions of the first metal and the second metal may be different. For example, the first metal may include tin (Sn), and the second metal may include copper (Cu).
[0049] The first plating resist pattern 83 that can be removed by exposure and development may be formed only at a portion of the carrier substrate 60 other than a portion where the protruding pattern layer 78 is to be formed (see Figure 3 The protruding pattern layer 78 may be formed by plating a first metal having conductivity at a portion of the conductive layer 75 exposed by the opening of the patterned first plating resist pattern 83 (see Figure 4 After forming the protruding pattern layer 78, the first resist pattern 83 is removed (see Figure 5 ).
[0050] Although the present embodiment shows that the protruding pattern layer 78 is formed on both surfaces of the carrier substrate 60 , the protruding pattern layer 78 may be formed only on one surface of the carrier substrate 60 , and this also falls within the scope of the present disclosure.
[0051] Reference Figures 6 to 8 , the first connection pad 121 is formed on the conductive layer 75 by a circuit forming process. The second plating resist pattern 85 that can be removed by exposure and development may be formed only on the portion of the conductive layer 75 except for the portion where the first connection pad 121 is to be formed (see Figure 6 The first connection pad 121 may be formed by plating a second metal having conductivity at a portion of the conductive layer 75 exposed by the opening of the patterned second plating resist pattern 85 (see Figure 7 A portion of the conductive layer 75 and the protruding pattern layer 78 may be covered with the second plating resist pattern 85, and the second plating resist pattern 85 may be removed after forming the first connection pad 121 (see Figure 8 ).
[0052] Reference Fig. 9, the insulating layer 110A is laminated so that the first connection pad 121 is embedded, and a second seed layer 125A is formed on the upper surface of the insulating layer 110A. The second seed layer 125A may be formed to form the second connection pad 125, and the material of the second seed layer 125A may not be limited as long as the material is a conductive metal, for example, copper (Cu) is generally used as the material of the second seed layer 125A.
[0053] The insulating layer 110A may include a resin insulating layer. The insulating layer 110A may be a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a resin (e.g., a prepreg) prepared by impregnating a reinforcing material (such as glass fiber or an inorganic filler) in a thermosetting resin or a thermoplastic resin. In addition, the insulating layer 110A may include a thermosetting resin and / or a photocurable resin, but the present disclosure is not limited thereto.
[0054] Reference Figures 10 to 13 , the second connection pad 125 may be formed on the insulating layer 110A by a circuit forming process. The second connection pad 125 may be formed using a method similar to the method used to form the first connection pad 121, and the second connection pad 125 may include the same type of material as the first connection pad 121. In this case, in order to form a via hole 123 connecting the first connection pad 121 and the second connection pad 125, the second seed layer 125A and the insulating layer 110A are partially etched to expose a portion of the first connection pad 121 (see Fig.10 ), and a plating process may be performed on the exposed portion of the first connection pad 121. In addition, a third plating resist pattern 87 that can be removed by exposure and development may be formed only at a portion other than a portion where the second connection pad 125 is to be formed on the second seed layer 125A (see Fig.11 The second connection pad pattern 125B may be formed by plating a second metal having conductivity on a portion of the second seed layer 125A exposed through the opening of the patterned third plating resist pattern 87 (see Fig.12 After forming the second connection pad pattern 125B, the third plating resist pattern 87 is removed (see Fig.13 ). Therefore, the embedded pattern plate portion may be completed on both sides of the carrier substrate 60.
[0055] According to the illustrated embodiment, each of the embedded pattern plate parts is shown as including an insulating layer 110 and a first connection pad 121 and a second connection pad 125 as two metal layers, but the present disclosure is not limited thereto. In addition, a larger number of stacked insulating layers and a larger number of stacked circuit wiring pattern layers may be included, and this also falls within the scope of the present disclosure.
[0056] Reference Fig.14, an embedded pattern plate is prepared by separating the first seed layer 71 from the carrier substrate 60. A pair of embedded pattern plates may be obtained by separating the first seed layer 71 formed on both surfaces of the carrier substrate 60 from the copper foil layer 62, and processes may be applied individually to each of the pair of embedded pattern plates.
[0057] Reference Fig.15 , through Fig.14 The embedded pattern plate obtained in the embodiment of the present invention is subjected to alkali etching to remove the first seed layer 71 and the second seed layer 125A. After the first seed layer 71 and the second seed layer 125A are removed, the conductive layer 75 and the protruding pattern layer 78 are disposed on one side of the insulating layer 110 where the first connection pad 121 is embedded, and the second connection pad 125 protrudes from the other side of the insulating layer 110. During the alkali etching, the first seed layer 71 made of the second metal and the second seed layer 125A made of the second metal are etched and removed, but the conductive layer 75 made of the first metal and the protruding pattern layer 78 made of the first metal remain without being etched.
[0058] Reference Fig.16 , by etching Fig.15 The conductive layer 75 and the protruding pattern layer 78 are removed by using the embedded pattern plate obtained in the embodiment of the present invention. To this end, the etching process may be performed using an etching solution that does not etch the second metal included in the connection pads 121 and 125 while etching the first metal included in the conductive layer 75 and the protruding pattern layer 78. For example, by using a tin (Sn) stripper, tin (Sn) may be removed, and copper (Cu) may not be etched so that it is not removed.
[0059] After the conductive layer 75 and the protruding pattern layer 78 are removed from the embedded pattern plate, the first connection pad 121 is exposed from one surface (i.e., the first surface 110a) of the insulating layer 110, and the groove portion 115 is formed in the insulating layer 110. Because the protruding pattern layer 78 is removed, the groove portion 115 is formed by being recessed inward from one surface of the insulating layer 110 where the first connection pad 121 is exposed. Because the first connection pad 121 made of the second metal is not etched by the etching solution that etches the first metal, the exposed surface of the first connection pad 121 may be coplanar with the one surface of the insulating layer 110. As an example, the groove portion 115 may be formed at a portion corresponding to the protruding pattern layer 78.
[0060] Reference Fig.17 The first protective layer 131 and the second protective layer 135 are formed to cover Fig.16A portion of the insulating layer 110 located at two corresponding surfaces of the embedded pattern plate obtained in the present invention and a portion of the connection pads 121 and 125. The first protective layer 131 and the second protective layer 135 may include a solder resist layer. The first protective layer 131 may be patterned to include a first opening 131a and a second opening 131b, the first opening 131a being used to expose the first connection pad 121, and the second opening 131b being used to expose the groove portion 115 on one surface of the insulating layer 110 that exposes the first connection pad 121. The width of the second opening 131b may be formed to be greater than the width of the groove portion 115 in terms of the width along the first direction parallel to one surface of the insulating layer 110. In addition, the width of the first opening 131a may be formed to be less than the width of the first connection pad 121 in terms of the width along the first direction. The second protective layer 135 may be opened to expose at least a portion of the second connection pad 125 on the other surface (i.e., the second surface 110b) of the insulating layer 110 on which the second connection pad 125 is provided.
[0061] While the present disclosure has been described in conjunction with what are presently considered to be practical embodiments, it will be understood that the present disclosure is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims
1. A circuit board, comprising: an insulating layer having a first surface and a second surface facing each other, and including a groove portion recessed inwardly from the first surface of the insulating layer; a first connection pad embedded in the insulating layer and exposed from the first surface of the insulating layer; as well as A first protection layer covers the insulating layer and is opened to expose the first connection pad and the groove portion from the first surface of the insulating layer.
2. The circuit board according to claim 1, wherein: The first protection layer includes a first opening exposing the first connection pad and a second opening exposing the groove portion.
3. The circuit board according to claim 2, wherein: In terms of width along a first direction parallel to the first surface of the insulating layer, a width of the second opening is greater than a width of the groove portion.
4. The circuit board according to claim 2, wherein: In terms of width along a first direction parallel to the first surface of the insulating layer, a width of the first opening is smaller than a width of the first connection pad.
5. The circuit board according to claim 1, wherein: The bottom surface of the groove portion is disposed away from the exposed surface of the first connection pad.
6. The circuit board according to claim 5, wherein: The bottom surface of the groove portion is disposed further away from the first surface of the insulating layer than the bottom surface of the first connection pad.
7. The circuit board according to claim 5, wherein: The recessed depth of the groove portion is greater than the thickness of the first connection pad along a second direction perpendicular to the first surface of the insulating layer.
8. The circuit board according to claim 5, wherein: The recessed depth of the groove portion is smaller than the thickness of the insulating layer along a second direction perpendicular to the first surface of the insulating layer.
9. The circuit board according to claim 1, wherein: The groove portion is disposed adjacent to the first connection pad.
10. The circuit board according to claim 1, further comprising a plurality of first connection pads, wherein: The groove portion is disposed between first connection pads adjacent to each other among the plurality of first connection pads.
11. The circuit board according to claim 1, wherein: An exposed surface of the first connection pad is coplanar with the first surface of the insulating layer. 12 . The circuit board according to claim 1 , further comprising a second connection pad disposed on the second surface of the insulating layer. 13 . The circuit board according to claim 12 , further comprising a second protection layer partially covering the insulating layer and the second connection pads on the second surface of the insulating layer.
14. The circuit board according to claim 1, wherein: The insulating layer includes a prepreg.
15. The circuit board according to claim 1, wherein: The protective layer includes a solder resist.
16. A method for manufacturing a circuit board, comprising: forming a conductive layer including a first metal on the seed layer including a second metal; patterning a first plating resist covering the conductive layer, and plating the first metal to form a protruding pattern layer on the conductive layer; patterning a second plating resist covering the conductive layer and the protruding pattern layer, and plating the second metal to form a connection pad on the conductive layer; forming an insulating layer to cover the protruding pattern layer and the connection pad; as well as The protruding pattern layer is removed by etching the protruding pattern layer, and a groove portion recessed inwardly is formed on a surface of the insulating layer. 17 . The method according to claim 16 , further comprising forming a protection layer on the surface of the insulating layer, the protection layer being opened to expose the connection pad and the groove portion.
18. The method according to claim 16, wherein: The second metal includes copper and the first metal includes tin.
19. The method according to claim 16, wherein: The groove portion is formed at a portion corresponding to the protruding pattern layer.