Semiconductor Structure and Semiconductor Device

Abstract

The present application provides a semiconductor structure and a semiconductor device. The semiconductor structure includes: a substrate; an epitaxial layer located on the surface of the substrate; a first doped region located in the epitaxial layer, the surface of the first doped region away from the substrate being a partial surface of the epitaxial layer away from the substrate, and the doping type of the first doped region being different from that of the epitaxial layer; at least two second doped regions located in the epitaxial layer and respectively located on both sides of the first doped region in a predetermined direction, the surfaces of the two second doped regions away from the substrate being partial surfaces of the epitaxial layer away from the substrate, and the doping type of the second doped region being different from that of the first doped region; and at least one channel region located in the epitaxial layer and at least on the surfaces of the at least two second doped regions close to the substrate, and the doping type of the channel region being the same as that of the first doped region. The present application solves the problem in the prior art that the lateral dimension of the cell of a silicon carbide MOSFET device is large, resulting in a large chip size.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a semiconductor device. Background Art

[0002] Traditional planar silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices have a lateral channel, and the lateral size of the cell is relatively large. The grooved-gate silicon carbide MOSFET designs the channel vertically, saving the lateral channel size, which is the main technical route to improve the channel density at present.

[0003] Limited by the feature size and lithography accuracy of semiconductor process equipment, the existing planar-gate silicon carbide MOSFET and grooved-gate silicon carbide MOSFET have limited effects on reducing the lateral size of the cell. Summary of the Invention

[0004] The main purpose of the present application is to provide a semiconductor structure and a semiconductor device to solve the problem that the large lateral size of the cell in the existing silicon carbide MOSFET device leads to a large chip size.

[0005] To achieve the above object, according to one aspect of the present application, a semiconductor structure is provided, including: a substrate; an epitaxial layer located on the surface of the substrate; a first doped region located in the epitaxial layer, the surface of the first doped region away from the substrate being a partial surface of the epitaxial layer away from the substrate, and the doping type of the first doped region being different from that of the epitaxial layer; at least two second doped regions located in the epitaxial layer and respectively located on both sides of the first doped region in a predetermined direction, the surface of the two second doped regions away from the substrate being a partial surface of the epitaxial layer away from the substrate, and the doping type of the second doped region being different from that of the first doped region, the predetermined direction being perpendicular to the thickness direction of the substrate; at least one channel region located in the epitaxial layer and at least on the surface of the two second doped regions close to the substrate, and the doping type of the channel region being the same as that of the first doped region.

[0006] Optionally, there are two channel regions, and the two channel regions are respectively located on both sides of the first doped region in the predetermined direction, and the channel regions are respectively located on the surface of the second doped regions close to the substrate.

[0007] Optionally, there is one channel region, and it is located on the surface of the two second doped regions close to the substrate and on the surface of the first doped region close to the substrate.

[0008] Optionally, the semiconductor structure further includes: at least two gate structures, which are respectively located on both sides of the first doped region in the predetermined direction, and are located on a part of the surface of the second doped region away from the substrate, on the sidewalls of the second doped region, on the sidewalls of the channel region, on a part of the surface of the epitaxial layer away from the substrate, and on a part of the sidewalls of the epitaxial layer.

[0009] Optionally, the epitaxial layer includes: a first sub-epitaxial layer located on the surface of the substrate; a second sub-epitaxial layer located on a part of the surface of the first sub-epitaxial layer away from the substrate. In the predetermined direction, the length of the first sub-epitaxial layer is greater than the length of the second sub-epitaxial layer. The first doped region, the second doped region, and the channel region are all located in the second sub-epitaxial layer. The sidewalls of the second doped region are part of the sidewalls of the second sub-epitaxial layer. The sidewalls of the channel region are part of the sidewalls of the second sub-epitaxial layer. The surface of the first doped region away from the substrate is a part of the surface of the second sub-epitaxial layer away from the substrate. The surface of the second doped region away from the substrate is a part of the surface of the second sub-epitaxial layer away from the substrate. The two gate structures are located on a part of the surface of the second doped region away from the substrate, on the sidewalls of the second sub-epitaxial layer, and on a part of the surface of the first sub-epitaxial layer away from the substrate.

[0010] Optionally, the semiconductor structure further includes: at least one third doped region, which is located in the epitaxial layer and at least on one side of the channel region close to the substrate. The doping type of the third doped region is the same as that of the first doped region. The doping concentration of the third doped region is less than the doping concentration of the first doped region, and the doping concentration of the third doped region is greater than the doping concentration of the channel region.

[0011] Optionally, there is one third doped region. When there are two channel regions, the third doped region is located on the surface of the first doped region close to the substrate. When there is one channel region, the third doped region is located on a part of the surface of the channel region close to the substrate.

[0012] Optionally, there are two third doped regions, and they are at least located on a part of the surface of the gate structure close to the substrate.

[0013] Optionally, the gate structure includes: a gate oxide layer, which is located on a part of the surface of the second doped region away from the substrate, on the sidewalls of the second doped region, on the sidewalls of the channel region, on a part of the surface of the epitaxial layer away from the substrate, and on a part of the sidewalls of the epitaxial layer; a gate, which is located on the surface of the gate oxide layer away from the substrate and on the sidewalls of the gate oxide layer.

[0014] Optionally, the semiconductor structure further includes: a first metal layer located on the surface of the first doped region away from the substrate and on a partial surface of the second doped region away from the substrate; and a second metal layer located on the surface of the substrate away from the epitaxial layer.

[0015] According to another aspect of the present application, there is provided a semiconductor device including any one of the semiconductor structures described above.

[0016] Applying the technical solution of the present application, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a first doped region located in the epitaxial layer, at least two second doped regions, and at least one first channel region. Among them, the doping type of the first doped region is different from that of the epitaxial layer. The two second doped regions are respectively located on both sides of the first doped region in a predetermined direction. The doping type of the second doped region is different from that of the first doped region. The channel region is at least located on the surface of the at least two second doped regions close to the substrate, and the doping type of the channel region is the same as that of the first doped region. Compared with the problem in the prior art that the lateral dimension of the SiC MOSFET device cell is large, resulting in a large chip size, in the present application, the first doped region is located between the two second doped regions, and the channel region is at least located on the surface of the at least two second doped regions close to the substrate. That is, not only the channel region is vertically arranged, but also other lateral structures of the cell (the second doped region, the first doped region, the JFET region) are designed as longitudinal structures, realizing the superposition of multiple regions in the longitudinal direction, ensuring that the lateral dimension of the cell is small, thereby ensuring that the chip size is small, ensuring a high chip area utilization efficiency, and further ensuring a high power density of the SiC device. Description of the Drawings

[0017] The specification drawings forming a part of the present application are used to provide a further understanding of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0018] Figure 1 A schematic cross-sectional structure diagram of a semiconductor structure provided according to an embodiment of the present application is shown;

[0019] Figure 2 A schematic cross-sectional structure diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0020] Figure 3 A schematic cross-sectional structure diagram of still another semiconductor structure provided according to an embodiment of the present application is shown;

[0021] Figure 4 A schematic cross-sectional structure diagram of still another semiconductor structure provided according to an embodiment of the present application is shown.

[0022] Among them, the above-mentioned drawings include the following reference numerals:

[0023] 10. Substrate; 11. Epitaxial layer; 12. First doped region; 13. Second doped region; 14. Channel region; 15. Gate structure; 111. First sub-epitaxial layer; 112. Second sub-epitaxial layer; 16. Third doped region; 151. Gate oxide layer; 152. Gate; 17. First metal layer; 18. Second metal layer. Detailed implementation manners

[0024] It should be noted that the following detailed description is illustrative and is intended to provide further description of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs.

[0025] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary implementation manners according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0026] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element can be directly on the other element, or there can also be an intermediate element. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element can be "directly connected" to the other element, or "connected" to the other element through a third element.

[0027] As introduced in the background art, in the prior art, the large lateral dimension of the silicon carbide MOSFET device cell results in a large chip size. To solve the above problems, the embodiments of the present application provide a semiconductor structure and a semiconductor device.

[0028] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention.

[0029] In this embodiment, a semiconductor structure is provided, as Figures 1 to 4 shown, including:

[0030] Substrate 10;

[0031] Epitaxial layer 11, located on the surface of the above-mentioned substrate 10;

[0032] The first doping region 12 is located in the epitaxial layer 11. The surface of the first doping region 12 away from the substrate 10 is a partial surface of the epitaxial layer 11 away from the substrate 10. The doping type of the first doping region 12 is different from that of the epitaxial layer 11.

[0033] At least two second doping regions 13 are located in the epitaxial layer 11 and are respectively located on both sides of the first doping region 12 in a predetermined direction. The surfaces of the two second doping regions 13 away from the substrate 10 are partial surfaces of the epitaxial layer 11 away from the substrate 10. The doping type of the second doping region 13 is different from that of the first doping region 12. The predetermined direction is perpendicular to the thickness direction of the substrate 10.

[0034] At least one channel region 14 is located in the epitaxial layer 11 and is at least located on the surfaces of the at least two second doping regions 13 close to the substrate 10. The doping type of the channel region 14 is the same as that of the first doping region 12.

[0035] Through the above embodiments, the semiconductor structure includes a substrate, an epitaxial layer on the surface of the substrate, a first doping region in the epitaxial layer, at least two second doping regions, and at least one first channel region. Among them, the doping type of the first doping region is different from that of the epitaxial layer. The two second doping regions are respectively located on both sides of the first doping region in a predetermined direction. The doping type of the second doping region is different from that of the first doping region. The channel region is at least located on the surfaces of the at least two second doping regions close to the substrate. The doping type of the channel region is the same as that of the first doping region. Compared with the problem in the prior art that the lateral size of the cell of the silicon carbide MOSFET device is large, resulting in a large chip size, in this application, the first doping region is located between the two second doping regions, and the channel region is at least located on the surfaces of the at least two second doping regions close to the substrate, that is, not only the channel region is vertically arranged, but also other lateral structures (second doping region, first doping region, JFET region) of the cell are designed as longitudinal structures, realizing the superposition of multiple regions in the longitudinal direction, ensuring that the lateral size of the cell is small, thus ensuring that the chip size is small, ensuring a high chip area utilization efficiency, and further ensuring a high power density of the silicon carbide device.

[0036] Specifically, the second doping region is located in the epitaxial layer and surrounds the first doping region in a predetermined direction.

[0037] Specifically, the doping concentration of the above-mentioned substrate is generally heavily doped. The doping type of the above-mentioned substrate is the same as that of the above-mentioned epitaxial layer, and the doping concentration of the above-mentioned substrate is greater than that of the above-mentioned epitaxial layer. In the embodiments of the present application, the doping type of the above-mentioned substrate is N-type, and the doping type of the above-mentioned epitaxial layer is N-type. The material of the above-mentioned substrate includes but is not limited to silicon carbide and diamond. The above-mentioned substrate has a supporting effect and has the characteristics of low on-resistance and low contact resistance. The doping concentration of the above-mentioned substrate is 1E19 cm -3 -1E20 cm -3 , and the doping concentration of the above-mentioned epitaxial layer is 1E15 cm -3 -1E16 cm -3 .

[0038] Specifically, ion implantation technology can be used to form the above-mentioned first doping region. The doping concentration of the above-mentioned first doping region is 1E18 cm -3 -1E21 cm -3 . In the embodiments of the present application, the doping type of the above-mentioned first doping region is P-type, and the doping particles of the above-mentioned first doping region include but are not limited to Al and B.

[0039] Specifically, ion implantation technology can be used to form the above-mentioned second doping region. The doping concentration of the above-mentioned second doping region is 1E18 cm -3 -1E21 cm -3 . The doping concentration of the above-mentioned second doping region is greater than that of the above-mentioned epitaxial layer. In the embodiments of the present application, the doping type of the above-mentioned second doping region is N-type, and the doping particles of the above-mentioned second doping region include but are not limited to N and P.

[0040] Specifically, ion implantation technology can be used to form the above-mentioned channel region. The doping concentration of the above-mentioned channel region is 1E17 cm -3 -1E21 cm -3 . The doping concentration of the above-mentioned channel region is less than that of the above-mentioned first doping region. In the embodiments of the present application, the doping type of the above-mentioned channel region is P-type, and the doping particles of the above-mentioned channel region include but are not limited to Al and B.

[0041] In an exemplary embodiment, as Figure 1 and Figure 2As shown, there are two such channel regions 14. The two channel regions 14 are respectively located on both sides of the first doping region 12 in the above-mentioned predetermined direction, and the channel regions 14 are respectively located on the surfaces of the second doping regions 13 close to the substrate 10. In this embodiment, there are two channel regions, and they are respectively located on both sides of the first doping region in the predetermined direction. The corresponding layout of the channel regions and the second doping regions helps to form a more uniform electric field distribution, and enables the channel regions and the second doping regions to be stacked in the vertical direction, thereby further reducing the lateral size of the cell while maintaining the device performance, and further ensuring a higher integration degree of the device.

[0042] In other embodiments, such as Figure 3 and Figure 4 As shown, there is one such channel region 14, and it is located on the surfaces of the two second doping regions 13 close to the substrate 10 and on the surface of the first doping region 12 close to the substrate 10. In this embodiment, there is one channel region, and it is located on the surfaces of the two second doping regions close to the substrate and on the surface of the first doping region close to the substrate. Designing the first doping region, the second doping region and the channel region as a stacked structure can further stack multiple regions in the vertical direction and further reduce the cell size.

[0043] In some other exemplary embodiments, such as Figures 1 to 4 As shown, the semiconductor structure further includes: at least two gate structures 15, which are respectively located on both sides of the first doping region 12 in the above-mentioned predetermined direction, and are located on the partial surfaces of the second doping regions 13 away from the substrate 10, on the sidewalls of the second doping regions 13, on the sidewalls of the channel regions 14, on the partial surfaces of the epitaxial layer away from the substrate, and on the partial sidewalls of the epitaxial layer. In this embodiment, the gate structures are located on the sidewalls and partial surfaces away from the substrate of the second doping regions, and at the corresponding positions of the channel regions and the epitaxial layer. Such a layout can enhance the control ability of the channel current, improve the switching speed and efficiency of the device. In addition, the gate structures are respectively located on both sides of the first doping region in the predetermined direction, and this design can make the layout of the device more compact and further improve the integration degree of the device.

[0044] In some alternative solutions, such as Figures 1 to 4As shown, the above-mentioned epitaxial layer 11 includes: a first sub-epitaxial layer 111 located on the surface of the above-mentioned substrate 10; a second sub-epitaxial layer 112 located on a partial surface of the above-mentioned first sub-epitaxial layer 111 away from the above-mentioned substrate 10. In the above-mentioned predetermined direction, the length of the above-mentioned first sub-epitaxial layer 111 is greater than the length of the above-mentioned second sub-epitaxial layer 112. The above-mentioned first doping region 12, the above-mentioned second doping region 13, and the above-mentioned channel region 14 are all located in the above-mentioned second sub-epitaxial layer 112. The sidewall of the above-mentioned second doping region 13 is a partial sidewall of the above-mentioned second sub-epitaxial layer 112. The sidewall of the above-mentioned channel region 14 is a partial sidewall of the above-mentioned second sub-epitaxial layer 112. The surface of the above-mentioned first doping region 12 away from the above-mentioned substrate 10 is a partial surface of the above-mentioned second sub-epitaxial layer 112 away from the above-mentioned substrate 10. The surface of the above-mentioned second doping region 13 away from the above-mentioned substrate 10 is a partial surface of the above-mentioned second sub-epitaxial layer 112 away from the above-mentioned substrate 10. The two above-mentioned gate structures 15 are located on the partial surface of the above-mentioned second doping region 13 away from the above-mentioned substrate 10, on the sidewall of the above-mentioned second sub-epitaxial layer 112, and on the partial surface of the above-mentioned first sub-epitaxial layer 111 away from the above-mentioned substrate 10. In this embodiment, by designing the first doping region, the second doping region, and the channel region in the second sub-epitaxial layer, a more compact device structure can be achieved, thereby further improving the integration degree of the device.

[0045] In other embodiments, as Figures 1 to 4 shown, the thickness of the above-mentioned first sub-epitaxial layer 111 is greater than the thickness of the above-mentioned second sub-epitaxial layer 112. In this embodiment, the larger thickness of the first sub-epitaxial layer helps to disperse heat and reduce the heat accumulation of the device during high-power operation, thereby further improving the thermal stability of the device.

[0046] In still other alternative solutions, as Figures 1 to 4 shown, the above-mentioned semiconductor structure further includes: at least one third doping region 16 located in the above-mentioned epitaxial layer 11 and at least on one side of the above-mentioned channel region 14 close to the above-mentioned substrate 10. The doping type of the above-mentioned third doping region 16 is the same as the doping type of the above-mentioned first doping region 12. The doping concentration of the above-mentioned third doping region 16 is less than the doping concentration of the above-mentioned first doping region 12, and the doping concentration of the above-mentioned third doping region 16 is greater than the doping concentration of the above-mentioned channel region 14. In this embodiment, the third doping region is used to form a JFET structure. The JFET can adjust the electric field inside the device and control the current, which helps to improve the switching speed of the device and adjust the on-resistance. In addition, the doping concentration gradient design of the third doping region helps to improve the electrical characteristics of the device.

[0047] Specifically, the above-mentioned third doping region can be formed by using ion implantation technology. The doping concentration of the above-mentioned third doping region is 1E18cm -3 -1E21cm -3In the embodiments of the present application, the doping type of the above-mentioned third doping region is P-type, and the doping particles in the above-mentioned channel region include, but are not limited to, Al and B.

[0048] In some alternative solutions, such as Figure 1 and Figure 4 shown, there is one of the above-mentioned third doping regions 16. As Figure 1 shown, when there are two in the above-mentioned channel region 14, the above-mentioned third doping region 16 is located on the surface of the above-mentioned first doping region 12 close to the above-mentioned substrate 10. As Figure 4 shown, when there is one in the above-mentioned channel region 14, the above-mentioned third doping region 16 is located on a partial surface of the above-mentioned channel region 14 close to the above-mentioned substrate 10. In this embodiment, by arranging the third doping region on the surface of the first doping region or the channel region close to the substrate, the electrical characteristics of the doping region can be more effectively controlled, thereby further optimizing the performance of the device.

[0049] In the above embodiment, the above-mentioned third doping region is located in the above-mentioned first sub-epitaxial layer and the above-mentioned second sub-epitaxial layer.

[0050] In other embodiments, such as Figure 2 and Figure 3 shown, there are two of the above-mentioned third doping regions 16, and at least located on a partial surface of the above-mentioned gate structure 15 close to the above-mentioned substrate 10. In this embodiment, by arranging the third doping region on a partial surface of the gate structure close to the substrate, the functional area of the device can be further increased without increasing the lateral size of the device, which further helps to improve the integration of the semiconductor device.

[0051] In the above embodiment, the two above-mentioned third doping regions are located in the above-mentioned first sub-epitaxial layer.

[0052] In an exemplary embodiment, such as Figures 1 to 4 shown, the above-mentioned gate structure 15 includes: a gate oxide layer 151, located on a partial surface of the above-mentioned second doping region 13 far from the above-mentioned substrate 10, on the sidewalls of the above-mentioned second doping region 13, on the sidewalls of the above-mentioned channel region 14, on a partial surface of the above-mentioned epitaxial layer 11 far from the above-mentioned substrate 10, and on a partial sidewall of the above-mentioned epitaxial layer 11; a gate 152, located on the surface of the above-mentioned gate oxide layer 151 far from the above-mentioned substrate 10 and on the sidewalls of the above-mentioned gate oxide layer 151. In this embodiment, the gate oxide layer, as an insulating layer between the gate and the semiconductor, can effectively isolate the gate from the semiconductor, prevent current leakage, and further improve the stability and reliability of the device; the gate can control the conductivity of the channel region, and the change of the gate voltage can cause the change of the number of carriers (electrons or holes) in the channel region, thereby controlling the on-off state of the device.

[0053] Specifically, methods such as thermal oxidation, PECVD (Plasma Enhanced Chemical Vapor Deposition), and ALD (Atomic Layer Deposition) can be used to form the above-mentioned gate oxide layer. The materials of the above-mentioned gate oxide layer include but are not limited to silicon dioxide (SiO2), hafnium oxide (HfO2), aluminum oxide (Al2O3), and aluminum nitride (AlN). The thickness of the above-mentioned gate oxide layer is 10nm - 1000nm.

[0054] Specifically, the materials of the above-mentioned gate include but are not limited to polysilicon and silicon carbide. The dopants of the above-mentioned gate include but are not limited to P, N, and B. The doping concentration of the above-mentioned gate is 1E18cm -3 -1E20cm -3 . The above-mentioned gate has the characteristics of high temperature resistance and low resistance.

[0055] In an exemplary embodiment, as Figures 1 to 4 shown, the above-mentioned semiconductor structure further includes: a first metal layer 17, located on the surface of the first doped region 12 away from the substrate 10 and on a part of the surface of the second doped region 13 away from the substrate 10; a second metal layer 18, located on the surface of the substrate 10 away from the epitaxial layer 11. In this embodiment, the first metal layer serves as the source electrode, and the second metal layer serves as the drain electrode, which can provide good conductivity, contribute to the transmission and collection of current, and improve the conductive performance of the device.

[0056] Specifically, the above-mentioned first metal layer is deposited on the front surface of the device, and deposition can be carried out by means such as evaporation and sputtering. The materials of the above-mentioned first metal layer include but are not limited to Ti, Al, Ni, and Au. The above-mentioned first metal layer can short-circuit the first doped region and the second doped region.

[0057] Specifically, the above-mentioned second metal layer is deposited on the back surface of the device, and deposition can be carried out by means such as evaporation and sputtering. The materials of the above-mentioned second metal layer include but are not limited to Ti, Al, Ni, and Au.

[0058] Specifically, in the semiconductor structure provided by the embodiments of the present application, since the second doping region, the channel region, the JFET region, etc. are the same implantation window, the number of relevant photomasks can be effectively saved, and doping in the specified region can be achieved by modifying the implantation conditions and annealing conditions. The semiconductor structure provided by the embodiments of the present application can save chip area and increase channel density: the semiconductor structure not only changes the traditional lateral dimensions (including the N+ region (i.e., the second doping region), the channel region, the JFET region) to vertical stacking, shortening the lateral dimensions, but also the remaining lateral dimensions including P+ (i.e., the first doping region), gate oxide (gate oxide layer), polysilicon (gate) etc. can be reduced based on the minimum process capabilities.

[0059] The embodiments of the present application also provide a method for manufacturing a semiconductor structure, including the following steps:

[0060] Step S101: Provide a substrate;

[0061] Step S102: Form an epitaxial layer on the surface of the above-mentioned substrate;

[0062] Step S103: Form a first doping region in the above-mentioned epitaxial layer. The surface of the first doping region far from the above-mentioned substrate is a partial surface of the epitaxial layer far from the above-mentioned substrate, and the doping type of the first doping region is different from the doping type of the above-mentioned epitaxial layer;

[0063] Step S104: Form at least two second doping regions in the above-mentioned epitaxial layer. The two second doping regions are respectively located on both sides of the first doping region in a predetermined direction. The surfaces of the two second doping regions far from the above-mentioned substrate are partial surfaces of the epitaxial layer far from the above-mentioned substrate. The doping type of the second doping region is different from the doping type of the first doping region, and the predetermined direction is perpendicular to the thickness direction of the above-mentioned substrate;

[0064] Step S105: Form at least one channel region in the above-mentioned epitaxial layer. The channel region is at least located on the surface of the above-mentioned epitaxial layer close to the above-mentioned substrate between the two second doping regions, and the doping type of the channel region is the same as the doping type of the first doping region.

[0065] In other embodiments, forming at least one channel region in the above-mentioned epitaxial layer includes: forming two above-mentioned channel regions in the above-mentioned epitaxial layer. The two above-mentioned channel regions are respectively located on both sides of the first doping region in the above-mentioned predetermined direction, and the above-mentioned channel regions are respectively located on the surface of the above-mentioned epitaxial layer close to the above-mentioned substrate corresponding to the second doping regions.

[0066] Specifically, first, a substrate is provided; then an epitaxial layer is formed on the surface of the substrate; then a first doping region is obtained by opening holes through a first mask and performing ion implantation; then two channel regions are obtained by opening holes through a second mask and performing ion implantation, and the two channel regions are respectively located on both sides of the first doping region in a predetermined direction; then the second mask is reused and ion implantation is performed to obtain two second doping regions, and the second doping regions are respectively located on the surfaces of the channel regions away from the substrate. Among them, the channel regions and the second doping regions share the same mask (i.e., the same implantation window), which can effectively save the number of relevant photolithography masks, and doping in a specified region can be achieved by modifying the implantation conditions and annealing conditions.

[0067] An embodiment of the present application further provides a semiconductor device, including: any one of the above semiconductor structures.

[0068] In the above embodiment, the semiconductor device includes a semiconductor structure. Among them, the semiconductor structure includes a substrate, an epitaxial layer on the surface of the substrate, a first doping region in the epitaxial layer, at least two second doping regions, and at least one first channel region. Among them, the doping type of the first doping region is different from that of the epitaxial layer, the two second doping regions are respectively located on both sides of the first doping region in a predetermined direction, the doping type of the second doping region is different from that of the first doping region, the channel region is at least located on the surface of the two second doping regions close to the substrate, and the doping type of the channel region is the same as that of the first doping region. Compared with the problem in the prior art that the lateral size of the cell of the silicon carbide MOSFET device is large, resulting in a large chip size, in the present application, the first doping region is located between the two second doping regions, and the channel region is at least located on the surface of the two second doping regions close to the substrate, that is, not only the channel region is vertically arranged, but also other lateral structures of the cell (the second doping region, the first doping region, the JFET region) are designed as longitudinal structures, realizing the superposition of multiple regions in the longitudinal direction, ensuring that the lateral size of the cell is small, thereby ensuring that the chip size is small, ensuring a high chip area utilization efficiency, and further ensuring a high power density of the silicon carbide device.

[0069] Specifically, in the embodiment of the present application, the above semiconductor device is a silicon carbide MOSFET device.

[0070] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0071] 1), In the semiconductor structure of the present application, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a first doped region located in the epitaxial layer, at least two second doped regions, and at least one first channel region. Among them, the doping type of the first doped region is different from that of the epitaxial layer, the two second doped regions are respectively located on both sides of the first doped region in a predetermined direction, the doping type of the second doped region is different from that of the first doped region, the channel region is at least located on the surface of the two second doped regions close to the substrate, and the doping type of the channel region is the same as that of the first doped region. Compared with the problem in the prior art that the lateral dimension of the cell of the silicon carbide MOSFET device is large, resulting in a large chip size, in the present application, the first doped region is located between the two second doped regions, and the channel region is at least located on the surface of the two second doped regions close to the substrate, that is, not only the channel region is vertically arranged, but also other lateral structures of the cell (the second doped region, the first doped region, the JFET region) are designed as longitudinal structures, realizing the superposition of multiple regions in the longitudinal direction, ensuring that the lateral dimension of the cell is small, thereby ensuring that the chip size is small, ensuring a high chip area utilization efficiency, and further ensuring a high power density of the silicon carbide device.

[0072] 2), In the semiconductor device of the present application, the semiconductor device includes a semiconductor structure. Among them, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a first doped region located in the epitaxial layer, at least two second doped regions, and at least one first channel region. Among them, the doping type of the first doped region is different from that of the epitaxial layer, the two second doped regions are respectively located on both sides of the first doped region in a predetermined direction, the doping type of the second doped region is different from that of the first doped region, the channel region is at least located on the surface of the two second doped regions close to the substrate, and the doping type of the channel region is the same as that of the first doped region. Compared with the problem in the prior art that the lateral dimension of the cell of the silicon carbide MOSFET device is large, resulting in a large chip size, in the present application, the first doped region is located between the two second doped regions, and the channel region is at least located on the surface of the two second doped regions close to the substrate, that is, not only the channel region is vertically arranged, but also other lateral structures of the cell (the second doped region, the first doped region, the JFET region) are designed as longitudinal structures, realizing the superposition of multiple regions in the longitudinal direction, ensuring that the lateral dimension of the cell is small, thereby ensuring that the chip size is small, ensuring a high chip area utilization efficiency, and further ensuring a high power density of the silicon carbide device.

[0073] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; An epitaxial layer located on the surface of the substrate; A first doped region located in the epitaxial layer, the surface of the first doped region away from the substrate being a partial surface of the epitaxial layer away from the substrate, and the doping type of the first doped region being different from the doping type of the epitaxial layer; At least two second doped regions located in the epitaxial layer and respectively on both sides of the first doped region in a predetermined direction, the surfaces of the two second doped regions away from the substrate being partial surfaces of the epitaxial layer away from the substrate, the doping type of the second doped region being different from the doping type of the first doped region, and the predetermined direction being perpendicular to the thickness direction of the substrate; At least one channel region located in the epitaxial layer and at least on the surfaces of the at least two second doped regions close to the substrate, the doping type of the channel region being the same as the doping type of the first doped region; The semiconductor structure further comprises: At least one third doped region located in the epitaxial layer and at least on the side of the channel region close to the substrate, the doping type of the third doped region being the same as the doping type of the first doped region, the doping concentration of the third doped region being less than the doping concentration of the first doped region, and the doping concentration of the third doped region being greater than the doping concentration of the channel region.

2. The semiconductor structure according to claim 1, wherein There are two channel regions, and the two channel regions are respectively on both sides of the first doped region in the predetermined direction, and the channel regions are correspondingly located on the surfaces of the second doped regions close to the substrate.

3. The semiconductor structure according to claim 1, characterized in that, There is one channel region, and it is located on the surfaces of the two second doped regions close to the substrate and on the surface of the first doped region close to the substrate.

4. The semiconductor structure according to claim 2 or 3, characterized in that, The semiconductor structure further comprises: At least two gate structures respectively on both sides of the first doped region in the predetermined direction, and located on the partial surfaces of the second doped regions away from the substrate, the sidewalls of the second doped regions, the sidewalls of the channel regions, the partial surfaces of the epitaxial layer away from the substrate, and the partial sidewalls of the epitaxial layer.

5. The semiconductor structure according to claim 4, wherein The epitaxial layer comprises: A first sub-epitaxial layer located on the surface of the substrate; A second sub-epitaxial layer located on the partial surface of the first sub-epitaxial layer away from the substrate. In the predetermined direction, the length of the first sub-epitaxial layer is greater than the length of the second sub-epitaxial layer. The first doped region, the second doped region, and the channel region are all located in the second sub-epitaxial layer. The sidewalls of the second doped regions are partial sidewalls of the second sub-epitaxial layer. The sidewalls of the channel regions are partial sidewalls of the second sub-epitaxial layer. The surface of the first doped region away from the substrate is the partial surface of the second sub-epitaxial layer away from the substrate. The surfaces of the second doped regions away from the substrate are partial surfaces of the second sub-epitaxial layer away from the substrate. The two gate structures are located on the partial surfaces of the second doped regions away from the substrate, the sidewalls of the second sub-epitaxial layer, and the partial surfaces of the first sub-epitaxial layer away from the substrate.

6. The semiconductor structure according to claim 1, wherein There is one third doped region. When there are two channel regions, the third doped region is located on the surface of the first doped region close to the substrate. When there is one channel region, the third doped region is located on a partial surface of the channel region close to the substrate.

7. The semiconductor structure according to claim 4, wherein There are two third doped regions, and they are at least located on a partial surface of the gate structure close to the substrate.

8. The semiconductor structure according to claim 4, wherein The gate structure includes: A gate oxide layer, which is located on the surface of the second doped region away from the substrate, on the sidewalls of the second doped region, on the sidewalls of the channel region, on the surface of the epitaxial layer away from the substrate, and on partial sidewalls of the epitaxial layer; A gate, which is located on the surface of the gate oxide layer away from the substrate and on the sidewalls of the gate oxide layer.

9. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes: A first metal layer, which is located on the surface of the first doped region away from the substrate and on a partial surface of the second doped region away from the substrate; A second metal layer, which is located on the surface of the substrate away from the epitaxial layer.

10. A semiconductor device, characterized in that, A semiconductor structure according to any one of claims 1 to 9.

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