Germanium-silicon groove preparation method

Abstract

The invention provides a germanium-silicon groove preparation method, which comprises the following steps of: forming a PMOS (P-channel Metal Oxide Semiconductor) gate structure and an NMOS (N-channel Metal Oxide Semiconductor) gate structure on a semiconductor substrate, arranging a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer in hard mask layers of the PMOS gate structure and the NMOS gate structure, exposing the second silicon nitride layer through a gate side wall, and covering a germanium-silicon mask layer, a patterned photoresist protection NMOS gate structure is formed, the germanium-silicon mask layer exposed in the PMOS region is etched, a groove is formed, and at least part of the second silicon nitride layer is reserved at the top of the PMOS gate to protect the silicon oxide layer; according to the method, the first silicon nitride layer and the germanium-silicon mask layer are etched, germanium-silicon deposition is carried out, and the residual second silicon nitride layer and the germanium-silicon mask layer are removed together through wet etching, so that the height difference of the hard mask layer caused by the conventional process of the PMOS gate and the NMOS gate is eliminated, the process load is avoided, the process steps are simplified, and the process cost is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a method for preparing a germanium silicon groove. Background Art

[0002] In the field of semiconductor technology, the characteristic size of transistors has entered the nanometer level. Improving the performance of current mainstream CMOS devices by scaling them down is subject to more and more physical and process limitations. In order to improve the performance of NMOS and PMOS transistors in CMOS devices, stress engineering has received more and more attention from the industry.

[0003] In the prior art, channel compressive stress is generally introduced by epitaxial silicon germanium (SiGe) source and drain (i.e. SiGe technology), and the lattice constant mismatch between the source, drain and channel is used to control the strain size, thereby improving the hole mobility to improve the performance of PMOS. In the prior art, a layer of silicon nitride is usually deposited on the gate structure, and the SiGe groove area is defined by photoresist, and then the silicon nitride layer that does not cover the photoresist area is removed by dry etching, and a groove is etched on the Si substrate; finally, TMAH (Tetramethylammonium Hydroxide) tetramethylammonium hydroxide is used for wet etching to obtain the SiGe groove, and then SiGe is deposited by epitaxial growth process, and then the SiGe mask layer is removed.

[0004] In the existing process for manufacturing diamond-shaped silicon-germanium grooves, see Figure 1 A hard mask layer 220 including silicon nitride and silicon oxide and a silicon germanium mask layer 250 are stacked from bottom to top on the top of the PMOS and NMOS gate structures; in the process of defining and forming the silicon germanium groove, refer to Figure 2-3 , part of the silicon oxide at the top of the hard mask layer 220 on the top of the PMOS gate structure will be consumed, resulting in a difference in the height of the hard mask layer 220 of the subsequent PMOS gate structure and the NMOS gate structure. In the subsequent process, the height difference of the hard mask layer 220 will bring about differences in the film layer height of the subsequent process and other influences. Therefore, it is usually necessary to take certain processes to eliminate this height difference, which undoubtedly makes the process flow more complicated.

[0005] Therefore, how to optimize the existing process method to eliminate the height difference of the hard mask layer and reduce the process load has become an important technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0006] In view of the shortcomings of the prior art mentioned above, the object of the present invention is to provide a method for preparing a germanium silicon groove, which is used to solve the problem of height difference between the hard mask layer of the PMOS gate structure and the NMOS gate structure caused by the production of germanium silicon grooves in PMOS, avoid process load, thereby simplifying the process steps and reducing process costs.

[0007] To achieve the above object, the present invention provides a method for preparing a germanium silicon groove, comprising the following steps:

[0008] A semiconductor substrate is provided, wherein the semiconductor substrate includes a PMOS region having an N-well region and an NMOS region having a P-well region, a PMOS gate structure is formed on the PMOS region and an NMOS gate structure is formed on the NMOS region, and a hard mask layer is provided on the PMOS gate structure and the NMOS gate structure, and the hard mask layer includes, from bottom to top, a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer;

[0009] forming a gate sidewall spacer, wherein the gate sidewall spacer exposes the second silicon nitride layer and covers the silicon oxide layer;

[0010] Forming a silicon germanium mask layer above the semiconductor substrate, wherein the silicon germanium mask layer covers the semiconductor substrate and encapsulates the PMOS gate structure and the NMOS gate structure;

[0011] forming a bottom anti-reflection layer and a patterned photoresist on the silicon germanium mask layer, and retaining the photoresist located in the NMOS region;

[0012] The bottom anti-reflection layer without photoresist protection in the PMOS region is removed by etching to expose the germanium silicon mask layer;

[0013] Etching the exposed silicon germanium mask layer to define a groove region of the PMOS gate structure;

[0014] Performing etching based on the defined groove area to form a groove in the semiconductor substrate;

[0015] removing the bottom anti-reflective layer and the patterned photoresist;

[0016] forming a germanium silicon epitaxial layer in the groove;

[0017] The remaining silicon germanium mask layer and the second silicon nitride layer are removed.

[0018] Optionally, the material of the silicon germanium mask layer includes silicon nitride treated with oxygen.

[0019] Optionally, after forming the groove, the thickness of the second silicon nitride layer on the PMOS gate structure is in the range of

[0021] Optionally, the gate sidewall spacer is flush with the upper surface of the silicon oxide layer.

[0022] Optionally, the material of the gate spacer includes SiCN, which cannot be removed by a phosphoric acid solution, and the gate spacer is formed by a dry etching process.

[0023] Optionally, the dry etching gas includes one or a combination of CF4, CHF3, CH2F2, CH3F, and C4F8.

[0024] Optionally, the step of forming the groove includes plasma etching the germanium silicon mask layer using a F-containing gas to define the groove area; and plasma etching the semiconductor substrate using HBr or Cl2.

[0025] Optionally, the method further includes a step of wet etching the groove to form a diamond-shaped groove.

[0026] Optionally, the method for preparing the germanium silicon epitaxial layer includes a selective epitaxial growth process and a molecular beam epitaxial growth process.

[0027] Optionally, the method of removing the silicon germanium mask layer and the second silicon nitride layer comprises wet etching, wherein the etching solution comprises phosphoric acid.

[0028] As described above, the present invention provides a method for preparing a silicon germanium groove, wherein a PMOS gate structure and an NMOS gate structure are first formed on a semiconductor substrate, a first silicon nitride layer, a silicon oxide layer, and a second silicon nitride layer are arranged in the hard mask layer of the PMOS gate structure and the NMOS gate structure, and the second silicon nitride layer is exposed through the gate sidewall, and then the silicon germanium mask layer is covered, and a patterned photoresist is formed to protect the NMOS gate structure, the silicon germanium mask layer exposed in the PMOS area is etched to form a groove, and at least a portion of the second silicon nitride layer is retained on the top of the PMOS gate to protect the silicon oxide layer; then silicon germanium is deposited, and the remaining second silicon nitride layer and the silicon germanium mask layer are removed together by wet etching, thereby eliminating the hard mask layer height difference caused by conventional processes between the PMOS and NMOS gates, avoiding process load, simplifying process steps, and reducing process costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the structure after photoresist patterning in the prior art.

[0030] Figure 2 It is a schematic diagram of the structure after forming a germanium silicon groove in the prior art.

[0031] Figure 3 It is a schematic diagram of the structure after the germanium silicon mask layer is removed in the prior art.

[0032] Figure 4 It is a flow chart of the preparation process of forming a germanium silicon groove in an embodiment of the present invention.

[0033] Figures 5-6 It is a schematic diagram showing the formation of a hard mask stack and a gate structure according to an embodiment of the present invention.

[0034] Figures 7-8 It is a schematic diagram of the structure after forming the gate sidewall in an embodiment of the present invention.

[0035] Fig. 9 It is a schematic diagram of the structure after being covered with a germanium silicon mask layer in an embodiment of the present invention.

[0036] Fig.10 It is a schematic diagram of the structure after the photoresist is patterned in an embodiment of the present invention.

[0037] Fig.11 It is a schematic diagram of the structure after exposing the SiGe mask layer in the PMOS region in an embodiment of the present invention.

[0038] Fig.12 It is a schematic diagram of the structure after defining the recessed region of the PMOS gate structure in an embodiment of the present invention.

[0039] Fig.13 It is a schematic diagram of the structure after the groove is formed in the embodiment of the present invention.

[0040] Fig.14 It is a schematic diagram of the structure after removing the photoresist and the bottom anti-reflection layer in an embodiment of the present invention.

[0041] Fig.15 It is a schematic diagram of the structure after forming a diamond-shaped groove in an embodiment of the present invention.

[0042] Fig.16 It is a schematic diagram of the structure after forming a germanium silicon epitaxial layer in an embodiment of the present invention.

[0043] Fig.17 It is a schematic diagram of the structure after the second silicon nitride layer and the silicon germanium mask layer are removed in an embodiment of the present invention.

[0044] Description of Reference Numerals

[0045] 100 Semiconductor Substrate

[0046] 110 N well region

[0047] 120 P well region

[0048] 201 PMOS Gate Structure

[0049] 202 NMOS Gate Structure

[0050] 211 PMOS gate layer

[0051] 212 NMOS gate layer

[0052] 220 Hard mask layer

[0053] 221 first silicon nitride layer

[0054] 222 Silicon oxide layer

[0055] 223 Second silicon nitride layer

[0056] 230 Gate sidewall

[0057] 241 High K Dielectric Layer

[0058] 242 TiN layer

[0059] 243 SiON layer

[0060] 250 SiGe mask layer

[0061] 260 grooves

[0062] 261 Germanium Silicon Epitaxial Layer

[0063] 310 Bottom anti-reflection layer

[0064] 320 Photoresist DETAILED DESCRIPTION

[0065] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0066] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0067] For ease of description, spatial relational terms such as “under”, “below”, “below”, “below”, “over”, etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.

[0068] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0069] Example

[0070] In this embodiment, only 28HKMG is used as an example for description, but it is not limited to this. Figures 4 to 17 , which illustrates the structural schematic diagram of each step in preparing the germanium silicon groove. The preparation of the germanium silicon groove is introduced below in conjunction with the accompanying drawings of the specification.

[0071] First, see Figure 4 and Figure 5-6 , perform step S1, provide a semiconductor substrate 100, the semiconductor substrate 100 includes a PMOS region having an N-well region 110 and an NMOS region having a P-well region 120, a PMOS gate structure 201 is formed on the PMOS region and an NMOS gate structure 202 is formed on the NMOS region, and a hard mask layer 220 is provided on the PMOS gate structure 201 and the NMOS gate structure 202, and the hard mask layer 220 includes, from bottom to top, a first silicon nitride layer 221, a silicon oxide layer 222 and a second silicon nitride layer 223.

[0072] Specifically, in this step, refer to Figure 5The PMOS gate structure 201 and the NMOS gate structure 202 are first deposited on the semiconductor substrate 100 to form gate structure layers, wherein the PMOS gate structure 201 includes a PMOS gate layer 211, the hard mask layer 220, and a high-K dielectric layer 241; the NMOS gate structure 202 includes an NMOS gate layer 212, the hard mask layer 220, and the high-K dielectric layer 241; the PMOS gate layer 211 includes a metal gate layer, a silicon gate layer, a silicide gate layer, etc.; The NMOS gate layer 212 includes a metal gate layer, a silicon gate layer, a silicide gate layer, etc.; the high-K dielectric layer 241 includes one or more of a HfO2 layer, a HfSiO layer, a HfSiON layer, a TiO2 layer and a Ta2O3 layer; preferably, in the present embodiment, the PMOS gate layer 211 and the NMOS gate layer 212 are polysilicon gate layers, and the polysilicon gate layer serves as a pseudo gate structure and will be replaced by a metal gate layer later, which will not be described in detail here; the high-K dielectric layer 241 is a HfO2 layer.

[0073] Furthermore, a SiON layer 243 is provided between the semiconductor substrate 100 and the high-K dielectric layer 241 . The SiON layer 243 , as a transition layer, can effectively improve the interface between the high-K dielectric layer 241 and the semiconductor substrate 100 .

[0074] Furthermore, a TiN layer 242 is provided between the HfO2 layer and the polysilicon gate layer, serving as a bottom barrier metal (BBM) to protect the HfO2.

[0075] For example, see Figure 6 In order to protect the gate structure from damage during subsequent etching and processing, the PMOS gate structure 201 and the NMOS gate structure 202 are provided with the hard mask layer 220, and the hard mask layer 220 includes the first silicon nitride layer 221, the silicon oxide layer 222 and the second silicon nitride layer 223. The thickness of the first silicon nitride layer 221 is in the range of The thickness of the silicon oxide layer 222 is in the range of The thickness of the second silicon nitride layer 223 is in the range of In this embodiment, the second silicon nitride layer 223 is used as a sacrificial layer to protect the silicon oxide layer 222 and the first silicon nitride layer 221 .

[0076] Of course, in some other embodiments, the PMOS gate structure 201 and the NMOS gate structure 202 may also be low-K gate structures, which is not limited in this embodiment.

[0077] Next, see Figure 4 and Figure 7-Figure 8 , performing step S2 to form a gate spacer 230 , wherein the gate spacer 230 exposes the second silicon nitride layer 223 and covers the silicon oxide layer 222 .

[0078] As an example, the gate sidewall 230 is a layer of SiCN film deposited by atomic layer deposition or chemical vapor deposition as the gate sidewall, and anisotropic dry etching is used to make the SiCN on both sides of the gate thicker in the vertical direction, and there is no SiCN residue on the surface of the second silicon nitride layer 223. At the same time, by adjusting the sidewall etching profile, the height of the gate sidewall 230 is flush or nearly flush with the upper surface of the silicon oxide layer 222 to form the gate sidewall. The dry gas includes one or a combination of CF4, CHF3, CH2F2, CH3F, and C4F8. The SiCN material is a carbon-containing silicon nitride material and cannot be removed by a phosphoric acid solution. The setting of the gate sidewall 230, on the one hand, defines the subsequent LDD range, and on the other hand, avoids the problem that the gate sidewall 230 is too high above the silicon oxide layer 222 after the subsequent phosphoric acid stripping removes the second silicon nitride layer 223, thereby affecting the flatness of the subsequent film formation.

[0079] Next, see Figure 4 and Fig. 9 , executing step S3 , forming a germanium silicon mask layer 250 on the semiconductor substrate 100 , wherein the germanium silicon mask layer 250 covers the semiconductor substrate 100 and encapsulates the PMOS gate structure 201 and the NMOS gate structure 202 .

[0080] Specifically, in order to better cover the subsequent photoresist 320 and the bottom anti-reflection layer 310, the surface of the silicon germanium mask layer 250 is treated with O2 plasma to form a thinner oxide layer, which can effectively remove the poisoning effect caused by the base of silicon nitride and improve exposure and development.

[0081] Next, see Figure 4 and Fig.10 , executing step S4, forming a bottom anti-reflection layer 310 and the patterned photoresist 320 on the SiGe mask layer 250, and retaining the photoresist 320 located in the NMOS region.

[0082] Specifically, the photoresist 320 is formed on the silicon germanium mask layer 250 , and then exposed and developed. In order to reduce light reflection during the photolithography process, the photoresist 320 is usually coated with the bottom anti-reflection layer 310 during the coating process.

[0083] Next, see Figure 4 and Fig.11, executing step S5, removing the bottom anti-reflection layer 310 without photoresist protection in the PMOS region by etching, exposing the SiGe mask layer 250 to define the groove region of the PMOS gate structure 201.

[0084] Next, see Figure 4 and Fig.12 , executing step S6, etching the exposed silicon germanium mask layer to define a recessed region of the PMOS gate structure.

[0085] Specifically, the germanium silicon mask layer 250 is formed by dry etching, and the process conditions of the dry etching include: a pressure range of 1 to 50 mTorr, for example, 1 mTorr, 5 mTorr, 10 mTorr, 20 mTorr, 30 mTorr, 40 mTorr, 50 mTorr, etc., any value within this range; etching is performed using a F-containing gas, and the F-containing gas includes one or a combination of CF4, CHF3, CH2F2, CH3F or C4F8. Among them, the flow range of CF4 is 20 to 200 sccm, such as 20 sccm, 50 sccm, 100 sccm, 150 sccm, 200 sccm, etc. Any value within this range; the flow range of CHF3 is 20 to 200 sccm, such as 20 sccm, 50 sccm, 100 sccm, 150 sccm, 200 sccm, etc. Any value within this range; the flow range of CH2F2 is 20 to 200 sccm, such as 20 sccm, 50 sccm, 100 sccm, 150 sccm, 200 sccm, etc. Any value within this range; the flow range of CH3F is 20 to 200 sccm, such as 20 sccm, 50 sccm, 100 sccm, 150 sccm, 200 sccm, etc. any value within this range; the flow range of C4F8 is 10-60sccm, for example, 10sccm, 20sccm, 30sccm, 40sccm, 50sccm, 60sccm, etc., any value within this range; in addition, the range of its RF power is 100-2000w, for example, 100w, 200w, 400w, 600w, 1000w, 1500w, 2000w, etc., any value within this range; the area of ​​the subsequent germanium silicon groove is defined by the above process conditions, while protecting the gate sidewall 230, it also covers the top of the gate sidewall 230 to form a protection for the top corner position of the PMOS gate structure 201, so as to avoid the top corner position being damaged during the subsequent etching process and affecting the structure of the silicon oxide layer 222 of the hard mask layer 220.

[0086] Next, see Figure 4 and Fig.13, executing step S7, etching is performed based on the defined groove area to form a groove 260 in the semiconductor substrate 100.

[0087] Specifically, the groove 260 is formed in the semiconductor substrate 100 by dry etching, and the semiconductor substrate 100 is etched by one or a combination of HBr or Cl2, and the pressure range is 1 to 50 mTorr, such as 1 mTorr, 5 mTorr, 10 mTorr, 20 mTorr, 30 mTorr, 40 mTorr, 50 mTorr, etc.; the flow rate range of HBr is 50 to 500 sccm, such as 50 sccm, 100 sccm, 200 sccm, 250 sccm, 400 sccm, 500 sccm, etc.; the flow rate range of Cl2 is 50-500sccm, such as 50sccm, 100sccm, 200sccm, 250sccm, 400sccm, 500sccm, etc.; the range of RF power is 100-2000w, such as 100w, 200w, 400w, 600w, 1000w, 1500w, 2000w, etc., so that the groove 260 is formed on both sides of the PMOS gate structure 201 after etching, and the thickness range of the second silicon nitride layer 223 is The silicon oxide layer 222 is protected from damage.

[0088] Next, see Figure 4 and 14 , perform step S8 to remove the bottom anti-reflection layer 310 and the patterned photoresist 320 .

[0089] Specifically, the photoresist 320 and the bottom anti-reflection layer 310 may be removed by dry stripping.

[0090] For further information, see Fig.15 The groove 260 can also be wet-etched to form a diamond-shaped groove. The diamond-shaped groove can be formed by wet etching, or by two-step wet etching to control its critical size, thereby improving the control of the diamond-shaped groove morphology, thereby improving the performance of the PMOS device and the consistency of parameters between devices.

[0091] Furthermore, the solution used for the wet etching includes TMAH. The concentration of the TMAH ranges from 1.0 wt% to 30.5 wt%, the temperature ranges from 20° C. to 80° C., and the TMAH solution contains low concentration of difluoric acid (DHF).

[0092] Next, see Figure 4 and Fig.16 , executing step S9 to form a silicon-germanium epitaxial layer 261 in the groove 260 .

[0093] Specifically, before the growth of the silicon germanium epitaxial layer 261, the groove 260 is usually required to be pre-cleaned to remove the oxide layer naturally grown in the groove. In addition, the method of the silicon germanium epitaxial layer 261 includes forming the silicon germanium epitaxial layer 261 in the groove 260 using an epitaxial process, and the epitaxial process may include selective epitaxial growth (SEG), molecular beam epitaxy, and other suitable epitaxial processes or a combination thereof.

[0094] Next, see Figure 4 and Fig.17 , perform step S10 to remove the remaining silicon germanium mask layer 250 and the second silicon nitride layer 223 .

[0095] Specifically, in this step, phosphoric acid of a predetermined concentration is used to remove the silicon germanium mask layer 250, the second silicon nitride layer 223 on the PMOS gate structure 201, and the second silicon nitride layer 223 on the NMOS gate structure 202. In this embodiment, the thickness of the second silicon nitride layer 223 on the PMOS gate is in the range of The thickness of the second silicon nitride layer 223 located on the NMOS gate is in the range of The second silicon nitride layer 223 is used as a sacrificial layer to protect the silicon oxide layer 222; subsequently, a phosphoric acid solution is used to simultaneously remove the silicon germanium mask layer 250 and the second silicon nitride layer 223, thereby achieving the effect that the PMOS gate structure 201 and the NMOS gate structure 202 are located at the same height, avoiding the process load caused by the different heights of the PMOS gate structure 201 and the NMOS gate structure 202 in the subsequent process, simplifying the process steps and reducing the process cost.

[0096] In summary, the present invention provides a method for preparing a silicon germanium groove, which first forms a PMOS gate structure and an NMOS gate structure on a semiconductor substrate, and arranges a first silicon nitride layer, a silicon oxide layer, and a second silicon nitride layer in the hard mask layer of the PMOS gate structure and the NMOS gate structure, and exposes the second silicon nitride layer through the gate sidewall, and then covers the silicon germanium mask layer, and forms a patterned photoresist to protect the NMOS gate structure, and etches the silicon germanium mask layer exposed in the PMOS area to form a groove, and retains at least a portion of the second silicon nitride layer on the top of the PMOS gate to protect the silicon oxide layer; then silicon germanium is deposited, and the remaining second silicon nitride layer and the silicon germanium mask layer are removed together by wet etching, thereby eliminating the hard mask layer height difference caused by conventional processes between the PMOS and NMOS gates, avoiding process load, simplifying process steps, and reducing process costs.

[0097] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a germanium silicon groove, characterized in that: The following steps are involved: A semiconductor substrate is provided, wherein the semiconductor substrate includes a PMOS region having an N-well region and an NMOS region having a P-well region, a PMOS gate structure is formed on the PMOS region and an NMOS gate structure is formed on the NMOS region, and a hard mask layer is provided on the PMOS gate structure and the NMOS gate structure, and the hard mask layer includes, from bottom to top, a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer; forming a gate sidewall spacer, wherein the gate sidewall spacer exposes the second silicon nitride layer and covers the silicon oxide layer; Forming a silicon germanium mask layer above the semiconductor substrate, wherein the silicon germanium mask layer covers the semiconductor substrate and encapsulates the PMOS gate structure and the NMOS gate structure; forming a bottom anti-reflection layer and a patterned photoresist on the silicon germanium mask layer, and retaining the photoresist located in the NMOS region; The bottom anti-reflection layer without photoresist protection in the PMOS region is removed by etching to expose the germanium silicon mask layer; Etching the exposed silicon germanium mask layer to define a groove region of the PMOS gate structure; Performing etching based on the defined groove area to form a groove in the semiconductor substrate; removing the bottom anti-reflective layer and the patterned photoresist; forming a silicon germanium epitaxial layer in the groove; The remaining silicon germanium mask layer and the second silicon nitride layer are removed.

2. The method for preparing a silicon germanium groove according to claim 1, characterized in that: The material of the silicon germanium mask layer includes silicon nitride treated with oxygen.

3. The method for preparing a silicon germanium groove according to claim 1, characterized in that: After forming the groove, the thickness of the second silicon nitride layer on the PMOS gate structure is in the range of 4. The method for preparing a silicon germanium groove according to claim 1, characterized in that: The height of the gate sidewall is flush with the upper surface of the silicon oxide layer.

5. The method for preparing a silicon germanium groove according to claim 1, characterized in that: The material of the gate spacer includes SiCN, which cannot be removed by a phosphoric acid solution, and the gate spacer is formed by a dry etching process.

6. The method for preparing a silicon germanium groove according to claim 5, characterized in that: The dry etching gas includes one or a combination of CF4, CHF3, CH2F2, CH3F, and C4F8.

7. The method for preparing a silicon germanium groove according to claim 1, characterized in that: The step of forming the groove includes using a gas containing F to perform plasma etching on the germanium silicon mask layer to define the groove area; and using HBr or Cl2 to perform plasma etching on the semiconductor substrate.

8. The method for preparing a silicon germanium groove according to claim 7, characterized in that: The method further comprises the step of wet etching the groove to form a diamond-shaped groove.

9. The method for preparing a silicon germanium groove according to claim 1, characterized in that: The method for preparing the germanium silicon epitaxial layer includes a selective epitaxial growth process and a molecular beam epitaxial growth process.

10. The method for preparing a silicon germanium groove according to claim 1, characterized in that: The method for removing the silicon germanium mask layer and the second silicon nitride layer comprises wet etching, wherein the etching solution comprises phosphoric acid.

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