Transistor, preparation method thereof and chip

Abstract

The invention relates to the technical field of semiconductor manufacturing, and provides a transistor, a preparation method thereof and a chip. The preparation method comprises the following steps: providing a silicon substrate; depositing a first multilayer structure; the first multilayer structure comprises a first silicon oxide layer, a metal layer and a second silicon oxide layer which are deposited in sequence; etching a plurality of long holes; adopting a metal oxide precursor as a raw material, and performing atomic layer deposition treatment on the long hole to form an annular gate oxide layer on the surface of the corresponding metal layer in the long hole; depositing a second multilayer structure in the long hole; the second multi-layer structure comprises a first n-type silicon germanide layer, a p-type silicon germanide layer and a second n-type silicon germanide layer which are deposited in sequence; and depositing an electrode to obtain the transistor. According to the preparation method, the compatibility of the TFET and the CMOS can be realized, the influence of unstable factors such as photoresist quality and exposure precision in a photoetching process is avoided, the channel length is effectively reduced, the interference in the use process of the transistor can be reduced, the use reliability is improved, and the overall performance is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a transistor and a preparation method thereof, and a chip. Background Art

[0002] In the field of semiconductor technology, transistors are core components, and their performance improvement is crucial to the development of integrated circuits. As electronic devices continue to develop towards miniaturization and high performance, the requirements for transistors are becoming increasingly stringent. Traditional photolithography technology is a key factor in determining the channel length of transistors. However, as the feature size continues to shrink, photolithography technology is gradually approaching its physical limit, making it difficult to further reduce the channel length.

[0003] Existing transistor technologies, such as the Fin Field-Effect Transistor (TFET) and the Complementary Metal-Oxide-Semiconductor (CMOS) technologies, have their own advantages in integrated circuits. TFET has the potential for low power consumption, while CMOS technology dominates current integrated circuits. However, in actual manufacturing, attempts to integrate TFET and CMOS technologies on the same chip mostly use more traditional planar structures or simple hybrid methods, which makes it difficult to achieve a vertical structure around the gate and fail to fully utilize the advantages of both technologies. There are certain limitations in performance and integration, resulting in the performance of the transistor failing to meet usage requirements.

[0004] Therefore, there is an urgent need for a transistor with a small channel length, a simple preparation method, and the ability to improve overall performance. Summary of the invention

[0005] The present application provides a transistor and a method for preparing the same, which can achieve TFET and CMOS compatibility, reduce the channel length, and improve the overall performance of the transistor.

[0006] The first aspect of the present application provides a method for preparing a transistor, comprising: S1: providing a silicon substrate; S2: depositing a first multilayer structure on a first surface of the silicon substrate; the first multilayer structure comprises a first silicon oxide layer, a metal layer and a second silicon oxide layer deposited in sequence; S3: etching a plurality of long holes on the first multilayer structure; the hole-forming direction of the long holes is opposite to the deposition direction of the first multilayer structure, and the length of the long holes is the same as the thickness of the first multilayer structure; S4: using an aluminum oxide precursor as a raw material, performing an atomic layer deposition process on the long holes to form an annular gate oxide layer on the surface of the metal layer corresponding to the long holes; the length of the gate oxide layer is the same as the thickness of the metal layer; S5: Depositing a second multilayer structure; the second multilayer structure includes a first n-type silicon germanium layer, a p-type silicon germanium layer and a second n-type silicon germanium layer deposited in sequence; wherein the first n-type silicon germanium layer corresponds to the first silicon oxide layer and has the same thickness, the p-type silicon germanium layer corresponds to the gate oxide layer, and the thickness of the p-type silicon germanium layer is the same as the length of the gate oxide layer, and the second n-type silicon germanium layer corresponds to the second silicon oxide layer and has the same thickness; S6: repeating S2 to S5 M times; M is a positive integer greater than or equal to 1; S7: depositing electrodes on the second surface of the silicon substrate and on the side of the first multilayer structure facing away from the silicon substrate; the first surface and the second surface are two opposite surfaces of the silicon substrate to obtain a transistor.

[0007] In some feasible implementations, S3 includes: preparing a first mask structure, the first mask structure including an array structure; etching the first mask structure and the first multilayer structure covered by the first mask structure to obtain a plurality of long holes.

[0008] In some feasible implementations, S3 includes: preparing a second mask structure, the second mask structure including a patterned mask structure; etching the first multilayer structure not covered by the second mask structure to obtain a plurality of long holes; and removing the second mask structure.

[0009] In some feasible implementations, the distance between the axes of any two adjacent long holes is greater than or equal to 500 micrometers.

[0010] In some feasible implementations, the thickness of the first silicon oxide layer and the second silicon oxide layer is 100-500 nanometers; the thickness of the metal layer is 1-20 nanometers; and the width of the gate oxide layer is 5-10 nanometers.

[0011] In some feasible implementations, the first silicon oxide layer and the second silicon oxide layer have the same thickness.

[0012] In some feasible implementations, the metal layer is an aluminum layer, and the metal oxide precursor is aluminum oxide.

[0013] In some feasible implementations, the preparation method further includes: S8: performing annealing treatment on the transistor.

[0014] The method for preparing a transistor provided in the first aspect of the present application breaks through the limitation of the channel length by traditional photolithography, and proposes the concept and implementation method that the channel length is determined by the gate metal thickness (metal layer) and is independent of photolithography, which provides a new way to reduce the size of transistors and improves the use demand of miniaturization of transistors. It effectively realizes the compatibility of complementary TFET and CMOS technology with a vertical topology structure of a surround gate (Gate-All-Around, GAA). Through the selection of specific materials and processes, the material and process problems of different technologies in integration are solved. Moreover, the gate oxide layer, as a channel, can be controlled in length, breaking through the limitation of photolithography, and is not affected by unstable factors such as photoresist quality and exposure accuracy in the photolithography process. It can effectively reduce the channel length, reduce interference during the use of transistors, and improve the reliability of use.

[0015] The transistor provided in the second aspect of the present application includes: a silicon substrate; a first multilayer structure deposited on the first surface of the silicon substrate, the silicon substrate including a first silicon oxide layer, a metal layer and a second silicon oxide layer; a plurality of first multilayer structures; a plurality of long holes formed in the first multilayer structure; the length of the long holes is the same as the thickness of the first multilayer structure; an annular gate oxide layer formed on the corresponding metal layer in the long holes; the length of the gate oxide layer is the same as the thickness of the metal layer; a second multilayer structure deposited on the long holes; the second multilayer structure includes a first n-type silicon germanium layer, a p-type silicon germanium layer and a second n-type silicon germanium layer; wherein the first n-type silicon germanium layer corresponds to the first silicon oxide layer and has the same thickness, the p-type silicon germanium layer corresponds to the gate oxide layer, and the thickness of the p-type silicon germanium layer is the same as the length of the gate oxide layer, and the second n-type silicon germanium layer corresponds to the second silicon oxide layer and has the same thickness; two electrodes are respectively deposited on the second surface of the silicon substrate and on the side of the first multilayer structure facing away from the silicon substrate.

[0016] The transistor provided in the second aspect of the present application is prepared by the method for preparing the transistor provided in the first aspect. The beneficial technical effects thereof can be found in the first aspect and will not be described in detail here.

[0017] The chip provided in the third aspect of the present application includes: a circuit and a transistor provided in the second aspect and applied to the circuit.

[0018] The chip provided in the third aspect of the present application includes the transistor in the second aspect. The beneficial technical effects thereof can be found in the first aspect and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 It is a schematic diagram of a process for preparing a transistor provided in an embodiment of the present application; Figure 2 It is a schematic diagram of the manufacturing process flow of the first transistor provided in the embodiment of the present application; Figure 3 It is a schematic diagram of a process flow of preparing a mask structure provided in an embodiment of the present application; Figure 4 is a schematic diagram of the distribution of long holes provided in an embodiment of the present application; Figure 5 is a schematic diagram of a manufacturing process flow of a second transistor provided in an embodiment of the present application; Figure 6 It is a schematic diagram of the positions of the long holes in the multiple first multi-layer structures provided in the embodiment of the present application.

[0021] Graphic marking: 100-transistor; 10-silicon substrate; 11-first surface; 12-second surface; 20-first multilayer structure; 21-first silicon oxide layer; 22-metal layer; 23-second silicon oxide layer; 30-long hole; 40-gate oxide layer; 50-second multilayer structure; 51-first n-type silicon germanium layer; 52-p-type silicon germanium layer; 53-second n-type silicon germanium layer; 60-electrode; 200-mask layer; 201-first mask structure; 202-second mask structure. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be described clearly below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments of the present application, other embodiments obtained by ordinary technicians in this field without making creative work all belong to the protection scope of the present application.

[0023] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0024] In addition, in the present application, directional terms such as "upper", "lower", "inner" and "outer" are defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to the changes in the orientation of the components placed in the drawings.

[0025] In order to facilitate the understanding of this application, the concepts mentioned in this application are first briefly introduced.

[0026] TFET technology: Fin field effect transistor, which is a three-dimensional transistor structure. By changing the channel from a plane to a fin-like three-dimensional structure, the gate's ability to control the channel is increased, the short channel effect is alleviated to a certain extent, and the performance and density of the transistor are improved. However, when FinFET technology is further reduced in size, it also faces problems such as insufficient gate control over the channel, and the manufacturing process is more complex. By simply stacking transistors in the vertical direction to increase transistor density. However, this method often does not fully consider the electrical isolation between layers and the optimization of gate control, which makes it difficult to significantly reduce the effective gate length, and is prone to problems such as interlayer interference, limiting performance improvements.

[0027] CMOS is the core technology of modern integrated circuit (IC) manufacturing. It realizes low-power and highly integrated electronic devices by combining N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS) and P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (PMOS) complementarily.

[0028] Reducing the channel length is crucial to improving the switching speed of transistors and reducing power consumption. Photolithography technology is usually used to reduce the channel length. In extreme ultraviolet lithography (EUV), as the feature size shrinks and approaches the physical limit, although a smaller line width can be achieved, the equipment cost is high, the process is complex, and there are problems such as photoresist resolution, which limit the further reduction of the channel length. It is difficult to meet the needs of increasing the switching speed of transistors and reducing power consumption.

[0029] In order to further reduce the channel length, a combination of TFET and CMOS can be used, but in actual manufacturing, it is difficult to effectively combine these two technologies, especially when realizing the gate-all-around (GAA) vertical topology, which faces challenges such as material compatibility and process integration. Moreover, these two technologies cannot play their respective advantages, limiting the overall performance improvement. At the same time, the traditional planar transistor structure has gradually encountered bottlenecks in increasing density, and simply relying on reducing the size of transistors to increase density will lead to problems such as short channel effects. Interlayer electrical isolation and gate control optimization are not fully considered, and the effective gate length is difficult to reduce. It is also easy to cause interlayer interference, which affects the performance and reliability of the transistor, which is not conducive to a significant increase in transistor density and reduces the overall performance of the transistor.

[0030] In order to solve the above technical problems, the embodiment of the present application provides a method for preparing a transistor, so that the channel length is not restricted by the photolithography technology, but is only determined by the gate metal length, and an arbitrarily small channel length is achieved, thereby improving the switching speed of the transistor, reducing power consumption, and overcoming the technical problem that the traditional photolithography technology cannot reduce the channel length. It can realize TFET and CMOS technology with a vertical topology structure of a surround gate (GAA), give full play to the advantages of the two technologies, solve the problems of material compatibility and process integration, improve the overall performance of the transistor, and then improve the overall performance of the integrated circuit.

[0031] Figure 1 It is a schematic flow chart of a method for preparing a transistor provided in an embodiment of the present application.

[0032] Figure 2 It is a schematic diagram of the manufacturing process flow of the first transistor provided in an embodiment of the present application.

[0033] See also Figure 1 and Figure 2 , the transistor can be implemented by the following steps S1 to S7.

[0034] S1: Provide a silicon substrate 10.

[0035] S2: depositing a first multilayer structure 20 on the first surface 11 of the silicon substrate 10; the first multilayer structure 20 comprises a first silicon oxide layer 21, a metal layer 22 and a second silicon oxide layer 23 which are deposited in sequence.

[0036] Among them, step S2 can be implemented by the following steps S21 to S23.

[0037] Step S21 : depositing a first silicon oxide layer 21 on the first surface 11 of the silicon substrate 10 .

[0038] In step S21 , a first silicon oxide layer 21 (silicon dioxide SiO 2 ) may be deposited on the first surface 11 of the silicon substrate 10 by chemical vapor deposition (CVD). The deposition temperature may be 350° C.-450° C., and the thickness of the first silicon oxide layer 21 may be 100-500 nanometers.

[0039] For example, the deposition temperature of the first silicon oxide layer 21 may be one of 350° C., 375° C., 400° C., 425° C. or 450° C. The thickness of the first silicon oxide layer 21 may be one of 100 nm, 200 nm, 300 nm, 400 nm or 500 nm.

[0040] Step S22 : depositing a metal layer 22 on the first silicon oxide layer 21 .

[0041] In step S22 , a metal layer 22 may be deposited on the surface of the first silicon oxide layer 21 by physical vapor deposition (PVD). The deposition temperature may be room temperature, and the thickness of the metal layer 22 may be 1-20 nanometers.

[0042] For example, the thickness of the metal layer 22 may be one of 1 nanometer, 5 nanometers, 10 nanometers, 15 nanometers or 20 nanometers.

[0043] Step S23 : depositing a second silicon oxide layer 23 on the surface of the metal layer 22 .

[0044] In step S23 , the deposition process of the second silicon oxide layer 23 may be the same as the deposition process of the first silicon oxide layer 21 , the deposition temperature may be 350° C.-450° C., and the deposition thickness may be 100-500 nanometers.

[0045] For example, the deposition temperature of the second silicon oxide layer 23 may be one of 360° C., 380° C., 410° C., or 440° C. The thickness of the second silicon oxide layer 23 may be one of 120 nanometers, 150 nanometers, 250 nanometers, 350 nanometers, or 450 nanometers.

[0046] In a specific implementation, the deposition temperature and thickness of the first silicon oxide layer 21 and the second silicon oxide layer 23 may be the same.

[0047] The thickness mentioned in the above implementation refers to the size of a certain structural layer along the deposition direction. Figure 2 As shown in the example, the thickness is the dimension of a certain structural layer in the vertical direction.

[0048] In a specific implementation, the metal layer 22 may be an aluminum layer, and the metal oxide precursor may be aluminum oxide. Of course, in other implementations, the metal layer 22 may also be other types of metal layers. Correspondingly, the metal oxide precursor may be adaptively adjusted according to the actual metal layer 22.

[0049] After step S2 is completed, we can get Figure 2 The structure shown in (a).

[0050] S3 : etching a plurality of long holes 30 on the first multilayer structure 20 .

[0051] The forming direction of the long hole 30 is opposite to the deposition direction of the first multilayer structure 20, and the length of the long hole 30 is the same as the thickness of the first multilayer structure 20. The plurality of long holes 30 are arranged in an array.

[0052] Specifically, step S3 can be implemented by the following steps S31 to S33.

[0053] Figure 3 It is a schematic diagram of a process flow for preparing a mask structure provided in an embodiment of the present application.

[0054] Step S31 : preparing a mask layer 200 on the first multi-layer structure 20 .

[0055] The mask layer 200 may be prepared by using photoresist, and the thickness of the photoresist may be uniform by spin coating. The thickness of the mask layer 200 may be 100-200 nanometers.

[0056] After step S31 is completed, it can be obtained Figure 3 (a) in the figure.

[0057] Step S32: preparing a first mask structure 201 .

[0058] In step S32, the photolithography pattern is transferred to the photoresist using a designed photolithography mask. Through the exposure of the photolithography equipment, the photoresist undergoes a photochemical reaction, and the properties of the photoresist in the exposed area change. The exposure time and dose are precisely adjusted according to the photoresist characteristics and the parameters of the photolithography equipment, for example, the exposure time is 10-30 seconds, and the exposure dose is 10-20 mJ / cm2. Development treatment is performed to remove the photoresist in the exposed or unexposed part (determined according to the photoresist type), thereby forming an accurate pattern on the photoresist layer, which will serve as a mask for the subsequent etching process. Among them, the first mask structure 201 includes a plurality of patterns, and the plurality of patterns are arranged in the form of an array. Among them, the pattern can be circular, square, etc., and the shape of the pattern is the same as the cross-sectional shape of the long hole 30 formed subsequently.

[0059] After step S32 is completed, it can be obtained Figure 3 The structure shown in (b).

[0060] Step S33 : etching the first mask structure 201 and the first multilayer structure 20 covered by the first mask structure 201 to obtain a plurality of long holes 30 .

[0061] In step S33, the structure after photolithography is placed in an inductively coupled plasma (ICP) dry etching device. According to the photoresist pattern, the second silicon oxide layer 23, the metal layer 22 and the first silicon oxide layer 21 are etched using plasma generated by fluorine-containing gas. By precisely controlling the etching gas flow, power and time, the etching depth and accuracy are ensured to meet the design requirements.

[0062] In some feasible implementations, the etching gas may be carbon tetrafluoride (CF4), the flow rate may be 10-20 sccm, the power may be 100-200 watts, and the etching time may be 5-10 minutes to etch the second silicon oxide layer 23 , the metal layer 22 and the first silicon oxide layer 21 to form the long hole 30 .

[0063] After step S33 is completed, Figure 2 The structure shown in (b).

[0064] In another feasible implementation, step S3 may also be implemented by the following steps: step S31, and step S34 to step S36.

[0065] Step S34: preparing a second mask structure 202 .

[0066] The process used in step S34 may be the same as that in step S32. The second mask structure 202 includes a patterned mask structure; the patterned mask structure may be a pattern obtained by removing the array structure from the mask structure. The array structure here is the same as that in step S32.

[0067] After step S34 is completed, it can be obtained Figure 3 The structure shown in (c).

[0068] Step S35 : etching the first multilayer structure 20 not covered by the second mask structure 202 to obtain a plurality of long holes 30 .

[0069] Different from the above implementation, in this step, what is etched is the first multilayer structure 20 that is not covered by the second mask structure 202, exposing the array structure.

[0070] After step S35 is completed, it can be obtained Figure 3 The structure shown in (d).

[0071] Step S36: removing the second mask structure 202 .

[0072] After step S36 is completed, Figure 2 The structure shown in (b).

[0073] In step S3 , the length of the long hole 30 is the same as the thickness of the first multilayer structure 20 , that is, the long hole 30 penetrates the first multilayer structure 20 , and the bottom of the long hole 30 exposes a portion of the first surface 11 of the silicon substrate 10 .

[0074] It should be emphasized that in the actual preparation process, the long holes 30 are arranged in an array. In order to better demonstrate the hole forming process, Figure 2 and Figure 3 The number of the long hole 30 shown in the figure is only one, and is not particularly limited.

[0075] Figure 4 It is a schematic diagram of the distribution of long holes provided in an embodiment of the present application.

[0076] See also Figure 4 As shown, Figure 4 (a) to (d) are respectively long holes 30 in different array forms. Figure 4 As shown in (a), the long holes 30 are circular holes arranged in a rectangular array, and the first multilayer structure 20 and the silicon substrate 10 are circular. Figure 4 As shown in (b), the long holes 30 are circular holes arranged in a ring array, and the first multilayer structure 20 and the silicon substrate 10 are circular. Figure 4 As shown in (c), the long holes 30 are square holes arranged in a rectangular staggered array, and the first multilayer structure 20 and the silicon substrate 10 are circular. Figure 4 As shown in (d), the long holes 30 are circular holes arranged in a rectangular array, and the first multilayer structure 20 and the silicon substrate 10 are square.

[0077] That is to say, the cross section of the long hole 30 can be circular or square. The first multilayer structure 20 and the silicon substrate 10 can be circular or square. Of course, the cross-sectional shape of the long hole 30 can also be other shapes, and the shapes of the first multilayer structure 20 and the silicon substrate 10 can also be other shapes. The cross-sectional shape of the long hole 30, the shapes of the first multilayer structure 20 and the silicon substrate 10 can be adaptively adjusted according to actual use requirements, and at the same time, the cross-sectional shape of the long hole 30, the shapes of the first multilayer structure 20 and the silicon substrate 10 can be combined and adjusted.

[0078] In some feasible implementations, the distance D between the axes of any two adjacent long holes 30 is greater than or equal to 500 microns. For example, D can be one of 500 microns, 550 microns, 600 microns or 800 microns. Of course, D can also be other values ​​greater than 500 microns.

[0079] Step S4 : using a metal oxide precursor as a raw material, performing an atomic layer deposition process on the long hole 30 to form a ring-shaped gate oxide layer 40 on the surface of the metal layer 22 corresponding to the long hole 30 .

[0080] In a specific implementation, the metal layer 22 is an aluminum layer, and the metal oxide precursor is aluminum oxide. The gate oxide layer 40 formed is aluminum oxide. The etched structure is placed in an atomic layer deposition device (ALD). Using aluminum oxide (Al2O3) precursor as a raw material, an Al2O3 gate oxide layer 40 is formed on the surface of the aluminum layer exposed in the long hole 30 by atomic layer deposition. The width and quality of the Al2O3 gate oxide layer 40 are ensured by precisely controlling the deposition temperature, precursor pulse time, and cycle number.

[0081] In a specific implementation, the deposition temperature of the gate oxide layer 40 may be 300-400° C., the precursor pulse time may be 0.1-0.5 seconds, and the number of cycles may be determined according to the required width of the gate oxide layer 40. For example, if the growth width is 5-10 nanometers, the number of cycles may be 100-200 times.

[0082] After step S4 is completed, Figure 2 It should be emphasized that the width of the gate oxide layer 40 of Al2O3 refers to the growth dimension of the gate oxide layer 40 along the direction perpendicular to the thickness of the metal layer 22. It can be understood that Figure 2 The length of the gate oxide layer 40 is the length in the vertical direction, and the length of the gate oxide layer 40 is the same as the thickness of the metal layer 22 .

[0083] Combination Figure 2 As shown, the gate oxide layer 40 grows along the x-axis direction, the width (thickness) direction of the gate oxide layer 40 is the x-axis direction, and the length (or height) direction is the y-axis. The metal layer 22 grows along the y-axis direction, and the thickness direction of the metal layer 22 is the y-axis.

[0084] In the transistor preparation method provided in the embodiment of the present application, the limitation of the channel length by traditional photolithography is broken, and the concept and implementation method that the channel length is determined by the gate metal thickness (metal layer 22) and is independent of photolithography are proposed, which provides a new way to reduce the size of transistors and improves the use demand of transistor miniaturization. It effectively realizes the compatibility of complementary TFET and CMOS technology with a surround gate (GAA) vertical topology. Through the selection of specific materials and processes, the material and process problems of different technologies in integration are solved. Moreover, the gate oxide layer 40 as a channel can be controlled in length, breaking through the limitation of photolithography, and is not affected by unstable factors such as photoresist quality and exposure accuracy in the photolithography process. It can effectively reduce the channel length, reduce interference during the use of transistors and improve the reliability of use.

[0085] Step S5 : depositing a second multilayer structure 50 in the long hole 30 ; the second multilayer structure 50 comprises a first n-type silicon germanium layer 51 , a p-type silicon germanium layer 52 and a second n-type silicon germanium layer 53 which are deposited in sequence.

[0086] Specifically, step S5 can be implemented by the following steps S51 to S53.

[0087] Step S51 : growing a first n-type silicon germanium layer 51 (SiGe—n+) in the long hole 30 .

[0088] The first n-type silicon germanium layer 51 (SiGe-n+) corresponds to the first silicon oxide layer 21 and has the same thickness.

[0089] Step S52 : growing a p-type silicon germanium layer 52 in the enclosed region of the first n-type silicon germanium layer 51 and the annular gate oxide layer 40 .

[0090] The p-type silicon germanium layer 52 (SiGe-p) corresponds to the gate oxide layer 40 , and the thickness of the p-type silicon germanium layer 52 (SiGe-p) is the same as the length of the gate oxide layer 40 .

[0091] Step S53 : growing a second n-type silicon germanium layer 53 on the p-type silicon germanium layer 52 .

[0092] The second n-type silicon germanium layer 53 (SiGe—n+) corresponds to the second silicon oxide layer 23 and has the same thickness.

[0093] In step S51 to step S53, the structure after forming the gate oxide layer 40 can be placed in a metal-organic chemical vapor deposition device (Metal-Organic Chemical Vapor Deposition, MOCVD) or a molecular beam epitaxy device (Molecular Beam Epitaxy, MBE) device. The growth temperature can be 500-700°C, the pressure can be 10-100 mTorr, and the gas flow rate can be adjusted according to the material source and growth rate requirements. For example, if the silicon source gas flow rate can be 5-10sccm, the germanium source gas flow rate is 1-3sccm, and the growth thickness is determined according to the requirements.

[0094] Specifically, when MOCVD is used, parameters such as growth temperature, pressure, and doping conditions of the first n-type silicon germanium layer 51 , the p-type silicon germanium layer 52 , and the second n-type silicon germanium layer 53 can be adaptively adjusted according to actual conditions.

[0095] In some feasible implementations, when MOCVD is used, a gas containing a semiconductor material source such as a silicon-germanium alloy can be introduced into a reaction chamber, and selective epitaxial growth is performed in the region defined by the gate oxide and other regions under preset temperature, pressure and gas flow conditions. For example, when preparing, for example, growing a 1-20 nanometer p-type silicon germanium layer 52, a channel region of a transistor is formed.

[0096] In some feasible implementations, when MBE is used, epitaxial growth can be performed by precisely controlling parameters such as the evaporation rate of the molecular beam and the temperature of the silicon substrate 10 .

[0097] After step S5 is completed, Figure 2 The structure shown in (d).

[0098] Figure 5 It is a schematic diagram of the manufacturing process flow of the second transistor provided in the embodiment of the present application.

[0099] S6: Repeat S2 to S5 M times.

[0100] In step S6, a combined structure of the annular gate oxide layer 40, the second multilayer structure 50 and the first multilayer structure 20 is repeatedly prepared on the prepared first multilayer structure 20. After step S6 is completed, Figure 5 The structure shown in (a).

[0101] Wherein, M is a positive integer greater than or equal to 1. That is, M can be a positive integer such as 1, 2, 3 or 5. Of course, M can also be other positive integers greater than or equal to 1.

[0102] For example, when M is 1, steps S2 to S5 are performed repeatedly once, that is, the number of the combined structures of the annular gate oxide layer 40 , the second multilayer structure 50 , and the first multilayer structure 20 is two.

[0103] The method of covering one layer of the first multilayer structure 20 on another layer of the first multilayer structure 20, in combination with other manufacturing processes, can effectively reduce the effective gate length and significantly improve the transistor density. At the same time, it avoids problems such as interlayer interference in traditional stacking methods, significantly improves the transistor density, and meets the ever-growing functional requirements of chips.

[0104] Figure 6 It is a schematic diagram of the positions of the long holes in the multiple first multi-layer structures provided in the embodiment of the present application.

[0105] See also Figure 6 , the distribution of the long holes 30 in the first multilayer structure 20 is described by taking M as 2 as an example. Figure 6 The illustration is only for exemplary purposes and does not show the entire structure.

[0106] See also Figure 6 As shown in (a), the long holes 30 of the first layer and the long holes 30 of the second layer are arranged in a staggered manner, and the long holes 30 of the first layer and the long holes 30 of the third layer are arranged in opposite positions.

[0107] See also Figure 6 As shown in (b), the long holes 30 of the first layer and the long holes 30 of the second layer are arranged in opposite positions, and the long holes 30 of the first layer and the long holes 30 of the third layer are arranged in staggered positions.

[0108] Of course, in other specific implementations, the positions of the long holes 30 between adjacent layers can correspond or be staggered. The long holes 30 between different layers can be adaptively adjusted according to actual usage requirements. Among them, the parameters such as the shape, size, and specific array distribution form of the long holes 30 are all included.

[0109] S7: depositing electrodes 60 on the second surface 12 of the silicon substrate 10 and the side of the first multilayer structure 20 facing away from the silicon substrate 10 , respectively, to obtain the transistor 100 ; the first surface 11 and the second surface 12 are two opposite surfaces of the silicon substrate 10 .

[0110] An electrode 60 is deposited on both sides of the prepared structure, so that a transistor 100 can be obtained.

[0111] After step S7 is completed, the following can be obtained: Figure 5 The transistor 100 is shown in (b).

[0112] S8: performing annealing treatment on the transistor.

[0113] The annealing process can ensure electrical isolation and connection adaptability between the first multilayer structures 20 .

[0114] The transistor preparation method provided in the embodiment of the present application integrates a series of processes such as photolithography, inductively coupled plasma dry etching, gate oxide (aluminum oxide) formation, and selective epitaxial growth (using metal organic chemical vapor deposition or molecular beam epitaxy). The innovative channel preparation method is compatible with a variety of preparation technologies, and the various parameter ranges can cooperate with each other to prepare a transistor structure with a multi-layer stack and a surrounding gate vertical topology structure, which can effectively improve the performance of the transistor 100.

[0115] Corresponding to the above-mentioned method for manufacturing a transistor, the present application further provides an embodiment of a transistor 100. The transistor 100 provided in the embodiment of the present application is manufactured by the method for manufacturing a transistor in the above-mentioned embodiment.

[0116] See also Figure 5 As shown in (b), the transistor 100 provided in the embodiment of the present application includes a silicon substrate 10 , a first multilayer structure 20 , a long hole 30 , a ring-shaped gate oxide layer 40 , a second multilayer structure 50 and an electrode 60 .

[0117] The first multilayer structure 20 is deposited on the first surface 11 of the silicon substrate 10, and the silicon substrate 10 includes a first silicon oxide layer 21, a metal layer 22, and a second silicon oxide layer 23. There are multiple first multilayer structures 20. The first multilayer structure 20 can be prepared by step S2 in the above embodiment.

[0118] A plurality of long holes 30 are formed in the first multilayer structure 20; the length of the long holes 30 is the same as the thickness of the first multilayer structure 20. The long holes 30 can be prepared by step S3 in the above embodiment.

[0119] The annular gate oxide layer 40 is formed on the corresponding metal layer 22 in the long hole 30. The gate oxide layer 40 can be prepared by step S4 in the above embodiment.

[0120] The second multilayer structure 50 is deposited on the long hole 30; the second multilayer structure 50 includes a first n-type silicon germanium layer 51, a p-type silicon germanium layer 52, and a second n-type silicon germanium layer 53; wherein the first n-type silicon germanium layer 51 corresponds to the first silicon oxide layer 21 and has the same thickness, the p-type silicon germanium layer 52 corresponds to the gate oxide layer 40 and the thickness of the p-type silicon germanium layer 52 is the same as the length of the gate oxide layer 40, and the second n-type silicon germanium layer 53 corresponds to the second silicon oxide layer 23 and has the same thickness.

[0121] The second multilayer structure 50 can be prepared by step S5 in the above embodiment.

[0122] The two electrodes 60 are respectively deposited on the second surface 12 of the silicon substrate 10 and the side of the first multilayer structure 20 facing away from the silicon substrate 10. The second multilayer structure 50 can be prepared by step S7 in the above embodiment.

[0123] Corresponding to the above transistor 100, the present application further provides an embodiment of a chip. The chip provided in the embodiment of the present application includes a circuit and a transistor 100 involved in or prepared in the above embodiment and applied to the circuit.

[0124] It should be noted that those skilled in the art will easily think of other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any variation, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary technical means in the art that are not disclosed in the present application.

[0125] It should be understood that the present application is not limited to the precise construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof, the true scope being indicated by the present application.

Claims

1. A method for preparing a transistor, characterized in that: include: S1: Provide silicon substrate; S2: depositing a first multilayer structure on the first surface of the silicon substrate; the first multilayer structure comprises a first silicon oxide layer, a metal layer, and a second silicon oxide layer deposited in sequence; S3: etching a plurality of long holes on the first multilayer structure; the forming direction of the long holes is opposite to the deposition direction of the first multilayer structure, and the length of the long holes is the same as the thickness of the first multilayer structure; S4: using a metal oxide precursor as a raw material, performing an atomic layer deposition process on the long hole to form a ring-shaped gate oxide layer on the surface of the metal layer corresponding to the long hole; the length of the gate oxide layer is the same as the thickness of the metal layer; S5: depositing a second multilayer structure in the long hole; the second multilayer structure comprises a first n-type silicon germanium layer, a p-type silicon germanium layer, and a second n-type silicon germanium layer deposited in sequence; wherein the first n-type silicon germanium layer corresponds to the first silicon oxide layer and has the same thickness, the p-type silicon germanium layer corresponds to the gate oxide layer, and has the same thickness as the gate oxide layer, and the second n-type silicon germanium layer corresponds to the second silicon oxide layer and has the same thickness; S6: Repeat S2 to S5 M times; M is a positive integer greater than or equal to 1; S7: depositing electrodes on the second surface of the silicon substrate and on a side of the first multilayer structure facing away from the silicon substrate, respectively, to obtain a transistor; the first surface and the second surface are two opposite surfaces of the silicon substrate.

2. The method for preparing a transistor according to claim 1, characterized in that: S3 includes: preparing a first mask structure, wherein the first mask structure includes an array structure; The first mask structure and the first multi-layer structure covered by the first mask structure are etched to obtain a plurality of long holes.

3. The method for preparing a transistor according to claim 1, characterized in that: S3 includes: preparing a second mask structure, wherein the second mask structure includes a patterned mask structure; Etching the first multilayer structure not covered by the second mask structure to obtain a plurality of long holes; The second mask structure is removed.

4. The method for preparing a transistor according to claim 2 or 3, characterized in that: The distance between the axes of any two adjacent long holes is greater than or equal to 500 microns.

5. The method for preparing a transistor according to claim 4, characterized in that: The thickness of the first silicon oxide layer and the second silicon oxide layer are both 100-500 nanometers; The thickness of the metal layer is 1-20 nanometers; The width of the gate oxide layer is 5-10 nanometers.

6. The method for preparing a transistor according to claim 5, characterized in that: The first silicon oxide layer and the second silicon oxide layer have the same thickness.

7. The method for preparing a transistor according to claim 1, characterized in that: The metal layer is an aluminum layer, and the metal oxide precursor is aluminum oxide.

8. The method for preparing a transistor according to claim 1, characterized in that: The preparation method further comprises: S8: performing annealing treatment on the transistor.

9. A transistor, characterized in that: The transistor is prepared by the method for preparing a transistor according to any one of claims 1 to 8, wherein the transistor comprises: Silicon substrate; A first multilayer structure is deposited on a first surface of the silicon substrate, wherein the silicon substrate comprises a first silicon oxide layer, a metal layer, and a second silicon oxide layer; the number of the first multilayer structure is multiple; a plurality of long holes formed in the first multilayer structure; the length of the long holes being the same as the thickness of the first multilayer structure; An annular gate oxide layer is formed on the corresponding metal layer in the long hole; the length of the gate oxide layer is the same as the thickness of the metal layer; a second multilayer structure, deposited on the long hole; the second multilayer structure comprises a first n-type silicon germanium layer, a p-type silicon germanium layer, and a second n-type silicon germanium layer; wherein the first n-type silicon germanium layer corresponds to the first silicon oxide layer and has the same thickness, the p-type silicon germanium layer corresponds to the gate oxide layer, and the thickness of the p-type silicon germanium layer is the same as the length of the gate oxide layer, and the second n-type silicon germanium layer corresponds to the second silicon oxide layer and has the same thickness; Two electrodes are respectively deposited on the second surface of the silicon substrate and on a side of the first multilayer structure facing away from the silicon substrate.

10. A chip, characterized in that: include: A circuit and a transistor as claimed in claim 9 applied to the circuit.

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