Isolation structures in transistor devices and methods of forming

Abstract

The invention discloses an isolation structure in a transistor device and a forming method. A device includes a first semiconductor fin and a second semiconductor fin and an isolation structure between the first semiconductor fin and the second semiconductor fin, the isolation structure including: an internal shallow trench isolation (STI) region; a first liner layer along sidewalls and a bottom surface of the inner STI region; and an STI hard mask on a top surface of the internal STI region. The STI hard mask and the first liner layer each include a higher nitrogen concentration than the internal STI region.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to an isolation structure and a formation method in a transistor device. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material over a semiconductor substrate and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated in a given area. However, as the minimum feature size decreases, other problems arise that need to be solved. Summary of the invention

[0004] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising: a first semiconductor fin and a second semiconductor fin; an isolation structure between the first semiconductor fin and the second semiconductor fin, the isolation structure comprising: an internal shallow trench isolation (STI) region; a first liner layer along the sidewalls and bottom surface of the internal STI region; and an STI hard mask on the top surface of the internal STI region, wherein the STI hard mask and the first liner layer both include a higher nitrogen concentration than the internal STI region; a plurality of nanostructures above the first semiconductor fin; and a gate structure above the isolation structure and the first semiconductor fin, wherein the gate structure surrounds each of the plurality of nanostructures.

[0005] According to a second aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor fin; a plurality of nanostructures above the semiconductor fin; a first and a second source / drain region, in the semiconductor fin, the plurality of nanostructures extending between the first and the second source / drain regions; a shallow trench isolation (STI) region along the sidewall of the semiconductor fin; a nitride liner below the STI region, the nitride liner covering the bottom surface and the sidewall of the STI region; a nitride hard mask above the STI region, the nitride hard mask covering the top surface of the STI region; and a gate structure surrounding the plurality of nanostructures, the gate structure overlapping a first portion of the nitride hard mask.

[0006] According to a third aspect of the present disclosure, a method for forming a semiconductor device is provided, comprising: etching a trench in a substrate to define a first semiconductor fin and a second semiconductor fin, the trench being disposed between the first semiconductor fin and the second semiconductor fin; forming a first liner on and along the sidewalls of the trench; forming a shallow trench isolation (STI) region on the first liner; forming a hard mask on the STI region, wherein a first material of the hard mask and a second material of the first liner have etching selectivity to a third material of the STI region; and forming a gate structure on and along the sidewalls of the first semiconductor fin, wherein the gate structure covers at least a portion of the hard mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood through the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0008] Figure 1 An example of a nanostructured field effect transistor (nanoFET) according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.18C , Fig.19A , Fig.19B , Fig.19C , Fig.19D , Fig. 20A , Fig. 20B , Fig. 20C , Fig.21A , Fig.21B , Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.23C , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.25C , Fig.26A , Fig.26B , Fig.26C , Fig.27A , Fig.27B , Fig.27C is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments.

[0010] Fig.28A , Fig.28B and Fig.28C Various cross-sectional views of a nanoFET are shown in accordance with some embodiments.

[0011] Fig.29A , Fig.29B and Fig.29C Various cross-sectional views of a nanoFET are shown in accordance with some embodiments.

[0012] Fig. 30A , Fig. 30B and Fig. 30C Various cross-sectional views of a nanoFET are shown in accordance with some embodiments. DETAILED DESCRIPTION

[0013] The present disclosure will now be described with reference to the accompanying drawings, … The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, spatially relative terms (e.g., "below," "lower," "above," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in a figure relative to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0015] In various embodiments, isolation regions (e.g., shallow trench isolation (STI) regions) are formed between and around the fins of the transistor to provide isolation between the various active regions of the transistor and to isolate the transistor from other adjacent transistors in the integrated circuit die. A protective liner may be formed to cover the sidewalls, bottom surfaces, and top surfaces of the isolation region to reduce isolation losses during subsequent cleaning and / or etching processes performed to manufacture the transistor. When the internal isolation region is made of oxide, the external protective liner may be a nitride layer. In this way, the protective liner may provide etching selectivity to the encapsulated isolation region and reduce isolation losses (e.g., STI losses) during subsequently applied cleaning / etching processes. In addition, the nitrogen concentration of the protective liner may be adjusted, depending on the acceptable tolerance for isolation losses, which allows the embodiment method to be selectively adjusted to achieve a desired device configuration. Thus, manufacturing defects may be reduced and the electrical performance of the resulting device may be improved.

[0016] Embodiments are described below in a specific context, namely, dies including nanoFETs. However, various embodiments may be applied to dies including other types of transistors (eg, fin field effect transistors (FinFETs), planar transistors, etc.) instead of or in combination with nanoFETs.

[0017] Figure 1 An example of a nanoFET (e.g., a nanowire FET, a nanosheet FET (nanoFET), etc.) according to some embodiments is shown in a three-dimensional view. The nanoFET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, etc.) on a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region of the nanoFET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. An isolation structure 68 (also referred to as an STI structure 68) is disposed between adjacent fins 66, and the fins 66 may protrude from between adjacent isolation regions 68 and be higher than these adjacent isolation regions 68. In Figure 1, the isolation structure 68 is shown as a single layer. However, as will be described in subsequent paragraphs, in various embodiments, the isolation structure 68 is a multilayer structure that, for example, includes a protective liner that covers the sidewalls and side surfaces of the internal isolation region. Although the isolation structure 68 is described / shown as being separated from the substrate 50, as used herein, the term "substrate" may refer only to a semiconductor substrate or to a combination of a semiconductor substrate and an isolation region. In addition, although the bottom portion of the fin 66 is shown as being a single continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 66 refers to the portion that extends between adjacent isolation structures 68.

[0018] The gate dielectric layer 100 is over the top surface of the fin 66 and along the top surface, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is over the gate dielectric layer 100. The epitaxial source / drain regions 92 are disposed on the fin 66 on the opposite side of the gate dielectric layer 100 and on the opposite side of the gate electrode 102. The source / drain region(s) may be referred to individually as a source or a drain, or collectively as a source and a drain, depending on the context.

[0019] Figure 1 Reference cross sections used in subsequent figures are also shown. Cross section AA' is along the longitudinal axis of gate electrode 102 and in a direction, e.g., perpendicular to the direction of current flow between epitaxial source / drain regions 92 of the nanoFET. Cross section BB' is perpendicular to cross section AA' and parallel to the longitudinal axis of fin 66 of the nanoFET and in the direction of current flow, e.g., between epitaxial source / drain regions 92 of the nanoFET. Cross section CC' is parallel to cross section AA' and extends through the epitaxial source / drain regions of the nanoFET. For clarity, subsequent figures refer to these reference cross sections.

[0020] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices such as planar FETs or fin field effect transistors (FinFETs).

[0021] Figures 2 to 27C is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figures 4 to 12 , Fig.13A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A and Fig.27A Shows Figure 1 Reference cross section AA' is shown. Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.18C , Fig.19B , Fig.19D , Fig. 20B , Fig.21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B , Fig.26B and Fig.27B Shows Figure 1 Reference cross section BB' is shown. Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig.19C , Fig. 20C , Fig.25C , Fig.26C and Fig.27C Shows Figure 1 Reference cross section CC' shown.

[0022] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., doped with a p-type dopant or an n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination of the foregoing.

[0023] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device such as an NMOS transistor, for example, an n-type nano FET, and the p-type region 50P can be used to form a p-type device such as a PMOS transistor, for example, a p-type nano FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be set between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0024] In addition, Figure 2 In the embodiment of the present invention, a multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustration purposes, as discussed in more detail below, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region of a nanoFET in the p-type region 50P. In addition, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form a channel region of a nanoFET in the n-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nanoFET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nanoFET in the p-type region 50P.

[0025] In other embodiments, the first semiconductor layer 51 can be removed and the second semiconductor layer 53 can be patterned to form a channel region of a nanoFET in both the n-type region 50N and the p-type region 50P. In some embodiments, the second semiconductor layer 53 can be removed and the first semiconductor layer 51 can be patterned to form a channel region of a nanoFET in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P can have the same material composition (e.g., silicon or another semiconductor material) and can be formed simultaneously. Fig.28A , Fig.28B and Fig.28C A structure resulting from such an embodiment, for example, in which the channel regions in both the p-type region 50P and the n-type region 50N include silicon is shown.

[0026] For illustrative purposes, the multilayer stack 64 is shown as including three layers each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of the first semiconductor layer 51 and the second semiconductor layer 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), or molecular beam epitaxy (MBE). In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nano FET, such as silicon germanium, and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nano FET, such as silicon or silicon carbon, etc. For illustrative purposes, the multilayer stack 64 is shown as having a bottommost semiconductor layer suitable for a p-type nano FET. In some embodiments, the multilayer stack 64 may be formed so that the bottommost layer is a semiconductor layer suitable for an n-type nano FET.

[0027] The first semiconductor material and the second semiconductor material can be materials having high etching selectivity to each other. Thus, in the n-type region 50N, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the n-type nanoFET. Similarly, in the p-type region 50P, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the p-type nanoFET.

[0028] Reference now FIG. 3A to FIG. 3C According to some embodiments, fins 66 are formed in the substrate 50, and nanostructures 55 are formed in the multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in the multilayer stack 64 and the substrate 50 by etching trenches 58 in the multilayer stack 64 and the substrate 50, respectively. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic. During the etching process, a hard mask 56 can be used to define the pattern of the fins 66 and the nanostructures 55. The hard mask 56 can include any suitable insulating material, such as oxides, nitrides, and oxynitrides, as well as oxycarbonitrides, etc. In some embodiments, as Figure 3BAs shown in the detailed view of the hard mask 56 in FIG. 5 , the hard mask 56 may be a multi-layer structure. For example, the hard mask 56 may include an interfacial oxide layer 56A, a nitride layer 56B (e.g., a silicon nitride layer) on the interfacial oxide layer 56A, and an oxide layer 56C (e.g., a silicon oxide layer) on the nitride layer 56B. Other combinations of (one or more) layers constituting the hard mask 56 may be used in other embodiments. Each layer of the hard mask 56 may be formed on the nanostructure 55 using an acceptable process (e.g., thermal oxidation, physical vapor deposition (PVD), CVD, ALD, a combination of the foregoing, etc.).

[0029] The fins 66 and nanostructures 55 may be patterned by any suitable method. For example, the fins 66 and nanostructures 55 may be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. Typically, the double patterning process or the multi-patterning process combines a photolithography process with a self-aligned process, thereby allowing the generation of patterns with, for example, a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and a photolithography process is used to pattern the sacrificial layer. A self-aligned process is used to form spacers along the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 66 and nanostructures 55.

[0030] Forming the nanostructure 55 by etching the multilayer stack 64 may further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from the first semiconductor layer 51, and second nanostructures 54A-C (collectively referred to as second nanostructures 54) from the second semiconductor layer 53. The first nanostructure 52 and the second nanostructure 54 may further be collectively referred to as nanostructure 55.

[0031] For illustration purposes, Figure 3A The fins 66 in the n-type region 50N and the p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N can be greater or thinner than the fins 66 in the p-type region 50P. Figure 3A Each fin 66 and each nanostructure 55 are shown as having a uniform width in various portions, but in other embodiments, the fin 66 and / or the nanostructure 55 may have tapered sidewalls such that the width of each fin 66 and / or each nanostructure 55 continues to increase in the direction toward the substrate 50. In such an embodiment, each nanostructure 55 may have a different width and be trapezoidal in shape. In addition, the bottom surface of the trench 58 between the fins 66 may be rounded and include a Figure 3C For ease of illustration only, the concave and / or convex portions shown are Figure 3A The specific structure shows the subsequent process steps, but the embodiments are also applicable to Figure 3C structures or other fin / nanostructure configurations.

[0032] exist Figures 4 to 11 In the embodiment, an isolation structure 68 is formed in the trench 58 and adjacent to the fin 66. The isolation structure 68 can be formed by depositing an insulating material layer over the substrate 50, the fin 66, the nanostructure 55, and the hard mask 56, and then patterning the insulating material layer under the nanostructure 55. Figure 4 , a first liner layer 68A is deposited over the upper surfaces of the substrate 50, the fins 66, the nanostructures 55, and the hard mask 56 along the sidewalls and bottom surfaces of the trench 58 and along the sidewalls of the fins 66, the nanostructures 55, and the hard mask 56. The first liner layer 68A may be an oxide layer (e.g., a silicon oxide layer, etc.), which may be formed by any suitable process, such as a thermal oxidation process, CVD, ALD, etc. In some embodiments, the first liner layer 68A has a multi-layer structure having an oxide layer formed on a semiconductor layer (e.g., a silicon layer). In such an embodiment, a semiconductor layer may be first formed on the sidewalls and bottom surfaces of the trench 58 by CVD, ALD, VPE, MBE, etc. Then an oxide layer (e.g., a silicon oxide layer) may be formed on the semiconductor layer using the above process.

[0033] After depositing the first liner layer 68A, a second liner layer 68B is deposited over the first liner layer 68A and along the sidewalls and bottom surface of the trench 58. The second liner layer 68B may extend over the upper surfaces of the substrate 50, the fins 66, the nanostructures 55, and the hard mask 56 and along the sidewalls of the fins 66, the nanostructures 55, and the hard mask 56. The first liner layer 68A may be a nitride layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxycarbonitride layer, etc.), which may be deposited by any suitable deposition process (e.g., CVD, ALD, etc.). In a specific embodiment, the second liner layer 68B is a SiON layer or SiCON, wherein the silicon atomic percentage is in the range of 28% to 38%; the carbon atomic percentage is in the range of 0% to 8%; the oxygen atomic percentage is in the range of 50% to 60%; and the nitrogen atomic percentage is in the range of 4% to 13%. For example, the second liner layer 68B may include 33 at% silicon, 3 at% carbon, 55 at% oxygen, and 9 at% nitrogen. In some embodiments, the second liner layer 68B is deposited by an ALD process at a temperature in the range of 550° C. to 650° C. During the ALD process, a silicon-based precursor, a nitrogen-based precursor, and O2 may be flowed to form the second liner layer 68B.

[0034] Then, an internal shallow trench isolation (STI) material 68C is formed on the second liner layer 68B to overfill the remaining portion of the trench 58. The STI material 68C may include an oxide (e.g., silicon oxide, etc.), which may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In an embodiment in which the STI material 68C is formed by an FCVD process, an annealing process may be performed once the insulating material is formed. The annealing process may cause nitrogen to diffuse from the second liner layer 68B into the overlying STI material 68C and the first liner layer 68A below. However, even after annealing, among the first liner layer 68A, the second liner layer 68B, and the STI material 68C, the nitrogen concentration in the second liner layer 68B may remain the highest. Specifically, a nitrogen peak may be detected between the STI material 68C and the surrounding oxide layer of the first liner layer 68A. The first liner layer 68A can be used as a buffer layer to protect the fin 66 and the nanostructure 55 from undesired nitrogen diffusion during the annealing process. In addition, the second liner layer 68B can protect the overlying STI material 68C from over-etching in a subsequent process (e.g., a process for removing the nanostructures 52 and / or 54). It has been observed that by forming the second liner layer 68B as described above to have a nitrogen atomic percentage in the range of 4% to 13%, the second liner layer 68B can be easily formed while also providing a sufficiently high etching selectivity to prevent over-etching of the STI material 68C in subsequent processing steps. Therefore, manufacturing defects in the resulting transistor device can be reduced and electrical performance can be improved.

[0035] exist Figure 5 and Figure 6 Then, a removal process is applied to the first liner layer 68A, the second liner layer 68B and the STI material 68C to remove the excess insulating material on the nanostructure 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, or a combination thereof may be used, such as Figure 5 The planarization process can also remove the hard mask 56 and expose the nanostructure 55, so that the top surfaces of the nanostructure 55, the first liner layer 68A, the second liner layer 68B, and the STI material 68C are flush after the planarization process is completed.

[0036] Then, in Figure 6In the embodiment of the present invention, the first liner layer 68A, the second liner layer 68B and the STI material 68C are recessed below the nanostructure 55. The first liner layer 68A, the second liner layer 68B and the STI material 68C are recessed so that the upper portion of the fin 66 in the n-type region 50N and the p-type region 50P protrudes from the top surface of the first liner layer 68A, the second liner layer 68B and the STI material 68C. In addition, the top surface of the first liner layer 68A, the second liner layer 68B and the STI material 68C can have a flat surface, a convex surface, a concave surface (e.g., a dish shape) as shown in the figure, or a combination of the foregoing items. The top surface of the first liner layer 68A, the second liner layer 68B and the STI material 68C can be formed to be flat, convex, and / or concave by appropriate etching. The first liner layer 68A, the second liner layer 68B, and the STI material 68C may be recessed using one or more acceptable etching processes (e.g., an etching process that is selective to the materials of the first liner layer 68A, the second liner layer 68B, and the STI material 68C), for example, etching the insulating materials of the first liner layer 68A, the second liner layer 68B, and the STI material 68C at a faster rate than etching the materials of the fins 66 and the nanostructures 55. After the recessing, the STI material 68C may be referred to as an STI region 68C.

[0037] exist Figure 7 In the embodiment of the present invention, a third liner layer 68D is deposited on and along the sidewalls of the fin 66 and the nanostructure 55, and further deposited on the top surfaces of the inner STI region 68C, the first liner layer 68A, and the second liner layer 68B. The third liner layer 68D may be a nitride layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxycarbonitride layer, etc. In a specific embodiment, the third liner layer 68D is a SiN layer, wherein the silicon atomic percentage is within a range of 62% to 72%, and the nitrogen atomic percentage is within a range of 28% to 38%. For example, the third liner layer 68D may include 67at% silicon and 33at% nitrogen.

[0038] In some embodiments, the third liner layer 68D is deposited by a non-conformal deposition process, such as a plasma enhanced CVD (PECVD) process, etc. The non-conformal deposition process can form the sidewall portion of the third liner layer 68D to have a thickness T1 that is less than the thickness T2 of the lateral portion of the third liner layer 68D. The non-conformal deposition process can facilitate patterning and selective removal of the sidewall portion of the third liner layer 68D, which will be discussed in more detail later. In some embodiments, the ratio of thickness T1 to thickness T2 can be in the range of 0.15 to 0.23. It has been observed that when the ratio of thicknesses T1 and T2 is within the above range, portions of the third liner layer 68D can be selectively removed to achieve the desired isolation structure 68 (see Fig.11) without unduly complicating the manufacturing process.

[0039] In some embodiments, the non-conformal deposition process is a PECVD process. The PECVD process may be performed at a temperature in the range of 400°C to 500°C. During the PECVD process, a silicon-based precursor and H2 gas may be flowed into the chamber to form a silicon-based material layer (e.g., a silicon layer) over and along the sidewalls of the fins 66 and the nanostructures 55. The silicon-based precursor flowing to form the third liner 68D may have the same or different chemical composition as the silicon-based precursor flowing to form the second liner 68B. After or while depositing the silicon-based material layer, a plasma treatment may be applied to treat the silicon-based material layer with nitrogen-containing radicals to form the third liner layer 68D. The plasma treatment may be applied in a direction perpendicular to the top surface of the substrate 50, as indicated by arrow 62. The orientation of the plasma treatment results in differences in thickness T1 and T2 between the sidewall portion and the lateral portion of the third liner layer 68D, respectively. Furthermore, the orientation of the plasma treatment may produce an improved quality film (eg, increased nitrogen uniformity) in lateral portions of the third liner layer 68D as compared to sidewall portions of the third liner layer 68D.

[0040] exist Figure 8 and Fig. 9 , an upper portion 68D-U of the third liner layer 68D is removed. The upper portion 68D-U of the third liner layer 68D may include a lateral portion of the third liner layer 68D disposed above the nanostructure 55. Removing the upper portion 68D-U of the third liner layer 68D may include depositing a mask layer 69 on the third liner layer 68D, such as Figure 8 As shown. Mask layer 69 may extend over nanostructures 55. In some embodiments, mask layer 69 is a backside anti-reflective coating (BARC) layer deposited by PVD or the like. In other embodiments, other materials and / or deposition processes are possible.

[0041] Later, in Fig. 9 In the process, one or more etching processes can be performed to remove the upper portion 68D-U of the third liner layer 68D. For example, a back etching process can be applied to the mask layer 69 to expose the upper portion 68D-U of the third liner layer 68D. Then, for example, the upper portion 68D-U of the third liner layer 68D can be etched away by an anisotropic etching process. In some embodiments, the anisotropic etching process is a dry etching using H3PO4, H3PO5, p33, etc. as an etchant. The remaining portion of the mask layer 69 protects the sidewalls and bottom portion of the third liner layer 68D when removing the upper portion 68D-U of the third liner layer 68D. After removing the upper portion 68D-U, a suitable etching and / or cleaning process can also be used to remove the remaining mask layer 69. The resulting structure is Fig.10Shown in.

[0042] exist Fig.11 Then, the sidewall portions 68D-S are removed from the sidewalls of the nanostructures 55 and the fins 66 (see Fig.10 ), while the bottom portion 68D-B remains on the top surface of the inner STI region 68C. Removing the sidewall portion 68D-S may include an etching process, such as an isotropic etching process. In some embodiments, the isotropic etching process is a wet etching using HPO3 or the like as an etchant. As discussed above, due to the non-conformal deposition process (e.g., PECVD) used to deposit the third liner layer 68D, the sidewall portion 68D-S is formed to be thinner than the bottom portion 68D-B. For example, the ratio of the thickness T1 of the sidewall portion 68D-S to the thickness T2 of the bottom portion 68D-B may be in the range of 0.15 to 0.23 (see Figure 7 ). The relative thinness of the sidewall portion 68D-S compared to the bottom portion 68D-B allows the sidewall portion 68D-S to be completely removed before the bottom portion 68D-B is completely removed when an isotropic etching process is applied. As a result, the above-described non-conformal deposition process allows the third liner layer 68D to be selectively etched away from the sidewalls of the nanostructures 55 and the fins 66, while still leaving a bottom, lateral portion of the third liner layer 68D to cover the inner STI region 68C.

[0043] After removing the sidewall portion 68D-S, the remaining third liner layer 68D may also be referred to as an STI hard mask 68D. Thus, an isolation structure 68 is formed. The isolation structure 68 includes a first liner layer 68A, a second liner layer 68B, an inner STI region 68C, and an STI hard mask 68D. The second liner layer 68B and the STI hard mask 68D are made of a material that protects the inner STI region 68C during subsequent processing steps (e.g., subsequent etching and / or cleaning processes). Specifically, the second liner layer 68B protects the bottom surface and sidewalls of the inner STI region 68C, and the STI hard mask 68D protects the upper surface of the STI region 68C. In this way, the combined second liner layer 68B and the STI hard mask 68D can completely surround and encapsulate the STI region 68C to protect the inner STI region 68C from being exposed to the etchant of the subsequent etching / cleaning process.

[0044] The (one or more) materials of the second liner layer 68B and the STI hard mask 68D can be selected to have high etching selectivity to the material of the inner STI region 68C relative to the same etching process. For example, the (one or more) materials of the second liner layer 68B and the STI hard mask 68D can be selected to resist the etchant of the material of the inner STI region 68C. For example, one or more etchants can etch the materials of the second liner layer 68B and the STI hard mask 68D at least ten times slower than the material of the inner STI region 68C. In some embodiments, when the inner STI region 68C is an oxide, the second liner layer 68B and the STI hard mask 68D are made of a nitride having the above-mentioned nitrogen percentage. The nitrogen concentration of the second liner layer 68B and the STI hard mask 68D can be higher than the nitrogen concentration of the inner STI region 68C. It has been observed that when the second liner layer 68B has a nitrogen atomic percentage in the range of 4% to 13% and the STI hard mask 68D has a nitrogen atomic percentage in the range of 28% to 38% (both described above), the second liner layer 68B and the STI hard mask 68D can be easily formed while also providing sufficient etching selectivity to prevent over-etching of the STI region 68C in subsequent processing steps. Therefore, excessive loss of the inner STI region 68C can be avoided, manufacturing defects can be reduced, and device performance can be improved. In some embodiments, the nitrogen concentration of the STI hard mask 68D is greater than the nitrogen concentration of the second liner layer 68B because the STI hard mask 68D will be more exposed to the etchant in subsequent processing steps. Therefore, having a higher nitrogen concentration in the STI hard mask 68D improves its ability to withstand etching and improves protection of the inner STI region 68C below.

[0045] The second liner layer 68B and the STI hard mask 68D may have thicknesses T3 and T4, respectively, both of which are at least 2 nm. It has been observed that when the thicknesses T3 and T4 are less than 2 nm, the inner STI region 68C is not adequately protected, and an unacceptably high degree of etching of the inner STI region 68C occurs in subsequent processing. The thickness T3 of the second liner layer 68B may be less than, equal to, or greater than the thickness T4 of the STI hard mask 68D. In some specific embodiments, the thickness T4 of the STI hard mask 68D may be in the range of 5 nm to 10 nm.

[0046] In addition, Fig.11In the embodiment with different well types, a photoresist or other mask (not shown separately) can be used to implement different implantation steps of the n-type region 50N and the p-type region 50P. For example, a photoresist can be formed over the fins 66 and nanostructures 55 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed by using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, or antimony, etc., which is implanted into the region, and its concentration is about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0047] After or before implanting the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66 and nanostructures 55 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, or indium, etc., implanted into the region, and its concentration ranges from about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0048] After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may avoid implantation, but in-situ doping and implantation doping may be used together.

[0049] exist Fig.12In the embodiment of the present invention, a dummy dielectric layer 70 is formed on the fin 66 and / or the nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, or a combination thereof, and the dummy dielectric layer 70 may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 may be deposited on the dummy dielectric layer 70, and the dummy gate layer 72 may then be planarized, for example, by CMP. The mask layer 74 may be deposited on the dummy gate layer 72. The dummy gate layer 72 may be a conductive material or a non-conductive material, and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 72 may be made of other materials with high etch selectivity relative to etching of the isolation region. The mask layer 74 may include, for example, silicon nitride or silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55 for illustration purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited so that the dummy dielectric layer 70 covers the isolation structure 68, so that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the isolation structure 68.

[0050] FIG. 13A to FIG. 27C Various additional steps in the fabrication of example devices are shown. Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig.19C , Fig. 20A , Fig. 20C , Fig.21A , Fig.22A , Fig.23C , Fig.25C , Fig.26C and Fig.27C Features in either region 50N or region 50P are shown, and Fig.13A , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.18C , Fig.19B , Fig.19D , Fig. 20B , Fig.21B , Fig. 22B , Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A and 27B Features in two regions, region 50N and region 50P, are shown. Fig.13A and Fig. 13B In the embodiment, the mask layer 74 (see Fig.12 ) can be patterned using acceptable photolithography and etching techniques to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of the mask 78 can be used to physically separate each dummy gate 76 from an adjacent dummy gate 76. The dummy gate 76 can also have a length direction that is substantially perpendicular to the length direction of the corresponding fin 66.

[0051] exist Fig.14A and Fig. 14B In Fig.13A and Fig. 13B A first spacer layer 80 and a second spacer layer 82 are formed on the structure shown. The first spacer layer 80 and the second spacer layer 82 are then patterned to serve as spacers for forming self-aligned source / drain regions. Fig.14A and Fig. 14B , a first spacer layer 80 is formed on: the top surface of the isolation structure 68; the top surface and sidewalls of the fin 66, the nanostructure 55, and the mask 78; and the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed of silicon oxide, silicon nitride, or silicon oxynitride, etc., using a technique such as thermal oxidation or deposition by CVD, ALD, etc. The second spacer layer 82 may be formed of a material having a different etch rate from the material of the first spacer layer 80, such as silicon oxide, silicon nitride, or silicon oxynitride, etc., and the second spacer layer 82 may be deposited by CVD or ALD, etc.

[0052] After forming the first spacer layer 80 and before forming the second spacer layer 82, an implantation for lightly doped source / drain (LDD) regions (not shown separately) may be performed. In embodiments with different device types, similar to the above, Fig.11, a mask (e.g., photoresist) may be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type (e.g., p-type) of impurities may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type (e.g., n-type) of impurities may be implanted into the exposed fins 66 and nanostructures 52 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a doping resistance of 1x10 15 Atom / cm 3 About 1x10 19 Atom / cm 3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0053] exist Fig.15A and Fig. 15B , the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83, respectively. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used to self-align the subsequently formed source / drain regions, and to protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), or an anisotropic etching process (e.g., a dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etching rate from the material of the first spacer layer 80, so that the first spacer layer 80 can be used as an etching stop layer when the second spacer layer 82 is patterned, and so that the second spacer layer 82 can be used as a mask when the first spacer layer 80 is patterned. For example, the second spacer layer 82 may be etched using an anisotropic etching process, wherein the first spacer layer 80 serves as an etch stop layer, and wherein the remaining portion of the second spacer layer 82 forms the second spacer 83, as shown in FIG. Fig.15A Thereafter, when the exposed portion of the first spacer layer 80 is etched, the second spacer 83 is used as a mask to form the first spacer 81, as shown in FIG. Fig.15A shown.

[0054] like Fig.15A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the sidewalls of the nanostructure 55. Fig. 15BAs shown, in some embodiments, the second spacer layer 82 may be removed from the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, the sidewalls of the dummy gate 76, and the sidewalls of the dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 may remain on the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0055] It should be noted that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or more spacers may be used, a different sequence of steps may be used (e.g., the first spacer 81 may be patterned before depositing the second spacer layer 82), and / or additional spacers may be formed and removed, etc. In addition, different structures and steps may be used to form n-type devices and p-type devices.

[0056] exist Fig.16A and Fig. 16B In some embodiments, a first recess 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. An epitaxial source / drain region is subsequently formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. Fig.16A As shown, the top surface of the isolation structure 68 (e.g., the top surface of the STI hard mask 68D) can be flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 can be etched so that the bottom surface of the recess 86 is set lower than the top surface of the isolation structure 68; and so on. The fin 66, the nanostructure 55, and the substrate 50 can be etched to form the first recess 86 by using an anisotropic etching process such as RIE, NBE, etc. During the etching process for forming the first recess 86, the first spacer 81, the second spacer 83, and the mask 78 mask some portions of the fin 66, the nanostructure 55, and the substrate 50. Each layer of the nanostructure 55 and / or the fin 66 can be etched using a single etching process or a multiple etching process. After the first groove 86 reaches the desired depth, a timed etching process can be used to stop etching the first recess 86.

[0057] exist Fig.17A and 17B In the embodiment, the portion of the sidewall of the layer formed of the first semiconductor material (e.g., the first nanostructure 52) of the multilayer stack 64 exposed by the first recess 86 is etched to form a sidewall recess 88 in the n-type region 50N, and the portion of the sidewall of the layer formed of the second semiconductor material (e.g., the second nanostructure 54) of the multilayer stack 64 exposed by the first recess 86 is etched to form a sidewall recess 88 in the p-type region 50P. Fig. 17B The sidewalls of the first and second nanostructures 52, 54 in the sidewall recess 88 are shown as straight, but the sidewalls may be concave or convex (see, e.g., Fig.18C ). The sidewalls may be etched using an isotropic etching process (e.g., wet etching, etc.). A mask (not shown) may be used to protect the p-type region 50P while etching the first nanostructure 52 using an etchant selective to the first semiconductor material, such that the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52 in the n-type region 50N. Similarly, a mask (not shown) may be used to protect the n-type region 50N while etching the second nanostructure 54 using an etchant selective to the second semiconductor material, such that the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54 in the p-type region 50P. In an embodiment where the first nanostructure 52 includes, for example, SiGe and the second nanostructure 54 includes, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. can be used to etch the sidewalls of the first nanostructure 52 in the n-type region 50N, and a wet or dry etching process using hydrogen fluoride, another fluorine-based etchant, etc. can be used to etch the sidewalls of the second nanostructure 54 in the p-type region 50P.

[0058] exist 18A to 18C In the embodiment, a first internal spacer 90 is formed in the side wall recess 88. Fig.17A and Fig. 17B An internal spacer layer (not shown separately) is deposited over the structure shown to form a first internal spacer 90. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions are formed in the recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are replaced with corresponding gate structures.

[0059] The inner spacer layer may be deposited by a conformal deposition process such as CVD or ALD. The inner spacer layer includes a material such as silicon nitride or silicon oxynitride, but any suitable material may be used, such as a low-k material having a k value of less than about 3.5. The inner spacer layer may then be anisotropically etched to form a first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are shown flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and flush with the sidewalls of the first nanostructure 52 in the p-type region 50P, the outer sidewalls of the first inner spacer 90 may extend beyond the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively, or may be recessed relative to the sidewalls of the second nanostructure 54 and / or the first nanostructure 52.

[0060] In addition, despite the Fig.18B , the outer sidewall of the first inner partition 90 is shown as straight, but the outer sidewall of the first inner partition 90 may be concave or convex. As an example, Fig.18C Embodiments are shown in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed relative to the sidewalls of the second nanostructure 54 in the n-type region 50N. Embodiments are also shown in which the sidewalls of the second nanostructure 54 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed relative to the sidewalls of the first nanostructure 52 in the p-type region 50P. The inner spacer layer can be etched by an anisotropic etching process such as RIE or NBE. The first inner spacer 90 can be used to prevent subsequent etching processes (e.g., etching processes used to form gate structures) from affecting subsequently formed source / drain regions (e.g., as described below with respect to FIG. 19A to FIG. 19C The destruction of the epitaxial source / drain regions 92) in question.

[0061] exist Figures 19A to 19C In the embodiment, an epitaxial source / drain region 92 is formed in the first recess 86. In some embodiments, the source / drain region 92 may apply stress to the second nanostructure 54 in the n-type region 50N and / or the first nanostructure 52 in the p-type region 50P, thereby improving performance. Fig.19B As shown, epitaxial source / drain regions 92 are formed in first recesses 86 such that each dummy gate 76 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate epitaxial source / drain regions 92 from dummy gates 76, and first internal spacers 90 are used to separate epitaxial source / drain regions 92 from nanostructures 55 by an appropriate lateral distance so that epitaxial source / drain regions 92 are not short-circuited with the gate of a subsequently formed resulting nanoFET.

[0062] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by masking the p-type region 50P (e.g., PMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 may include any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may include a material that applies tensile strain on the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, or silicon phosphide. The epitaxial source / drain region 92 may have a surface that is convex relative to the corresponding upper surface of the nanostructure 55, and may have a facet.

[0063] The epitaxial source / drain region 92 in the p-type region 50P (e.g., PMOS region) can be formed by masking the n-type region 50N (e.g., NMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 may include any acceptable material suitable for a p-type nanoFET. For example, if the first nanostructure 52 is silicon germanium, the epitaxial source / drain region 92 may include a material that applies compressive strain on the first nanostructure 52, such as silicon germanium, boron-doped silicon germanium, germanium, or germanium tin, etc.

[0064] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions (followed by annealing). The source / drain regions may have a dopant density of about 1x10 19 Atom / cm 3 About 1x10 21 Atom / cm 3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 92 may be doped in situ during growth.

[0065] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of nanostructures 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nanoFET to merge, such as Fig.19A In other embodiments, after the epitaxial process is completed, adjacent source / drain regions 92 remain separated, such as Fig.19C As shown. Fig.19A and Fig.19C In the illustrated embodiment, the first spacer 81 can be formed to the top surface of the isolation structure 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 can cover a portion of the sidewall of the nanostructure 55, thereby further blocking epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 can be adjusted to remove the spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI structure 68.

[0066] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to have different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In an embodiment where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited on the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited on the second semiconductor material layer 92B.

[0067] Fig.19D An embodiment is shown in which the sidewalls of the first nanostructure 52 in the n-type region 50N and the sidewalls of the second nanostructure 54 in the p-type region 50P are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed relative to the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. Fig.19D As shown, the epitaxial source / drain regions 92 may be formed to contact the first inner spacer 90 and may extend over the sidewalls of the second nanostructures 54 in the n-type region 50N and over the sidewalls of the first nanostructures 52 in the p-type region 50P.

[0068] exist FIG. 20A to FIG. 20C In Fig.13A , Fig.19B and Fig.19A A first interlayer dielectric (ILD) 96 is deposited on the structure shown. It should be noted that FIG. 14A to FIG. 19D The process remains basically unchanged Fig.13A. The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 78, and the first spacer 81. The CESL 94 may include a dielectric material (e.g., silicon nitride, silicon oxide, or silicon oxynitride, etc.) having an etch rate different from that of the material of the overlying first ILD 96.

[0069] exist Fig.21A and Fig.21B In the embodiment of the present invention, a planarization process such as CMP may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surface of the dummy gate 76, the top surface of the first spacer 81, and the top surface of the first ILD 96 are flush within process variations. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0070] exist Fig.22A and Fig. 22B In the embodiment of the present invention, the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps to form a second recess 98. Some portions of the dummy gate dielectric 71 in the second recess 98 are also removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate 76 at a faster rate than etching the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or covers some portions of the nanostructure 55, which are used as channel regions in the subsequently completed nanoFET. The portions of the nanostructure 55 used as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 may be used as an etch stop layer when the dummy gate 76 is etched. The dummy gate dielectric 71 may then be removed after the dummy gate 76 is removed.

[0071] exist FIG. 23A to FIG. 23C , the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed, thereby extending the second recess 98. The first nanostructure 52 may be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process (e.g., wet etching, etc.) using an etchant selective to the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI structure 68 remain relatively unetched compared to the first nanostructure 52. In an embodiment where the first nanostructure 52 includes, for example, SiGe and the second nanostructures 54A-54C include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH4OH), etc., may be used to remove the first nanostructure 52 in the n-type region.

[0072] The second nanostructures 54 in the p-type region 50P may be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process (e.g., wet etching, etc.) using an etchant that is selective to the material of the second nanostructures 54, while the first nanostructures 52, the substrate 50, and the STI structures 68 remain relatively unetched compared to the second nanostructures 54. In embodiments where the second nanostructures 54 include, for example, SiGe and the first nanostructures 52 include, for example, Si or SiC, the second nanostructures 54 in the p-type region 50P may be removed using hydrogen fluoride, another fluorine-based etchant, etc.

[0073] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P may be formed simultaneously, for example, by removing the first nanostructure 52 in both the n-type region 50N and the p-type region 50P or by removing the second nanostructure 54 in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions of the n-type nanoFET and the p-type nanoFET may have the same material composition, such as silicon, silicon germanium, etc. Fig.28A , Fig.28B and Fig.28C The structure resulting from such an embodiment is shown, in which the channel regions in both the p-type region 50P and the n-type region 50N are provided by the second nanostructure 54 and include, for example, silicon.

[0074] In various embodiments, since the STI hard mask 68D and the second liner layer 68B provide increased etch resistance to the inner STI region 68C, the STI structure 68 in both the n-type region 50N and the p-type region 50P is relatively unetched. Figures 12 to 23CIn the process step of , STI structure 68 can be exposed to one or more etchants that etch inner STI region 68C at a greater rate (e.g., at least 10 times greater) than etching each of STI hard mask 68D and second liner layer 68B. Although the etchant can still reduce the overall thickness of STI structure 68, STI loss is maintained at an acceptably low amount. For example, the thickness of STI hard mask 68D can be reduced from its original thickness T4 (see also Fig.11 ) is reduced to thickness T5. In some embodiments, the loss of STI hard mask 68D (e.g., the difference between thickness T4 and T5) can be less than 5 nm, thereby leaving sufficient isolation in the resulting transistor device and improving device performance. In some embodiments, the original thickness T4 of STI hard mask 68D can be in the range of 5 nm to 10 nm, and the thickness T5 of STI hard mask 68D after additional processing can be in the range of 2 nm to 5 nm. In addition, as Fig.23C As shown, during certain processes described above (e.g., during removal of dummy gate 76, dummy gate dielectric 71, and selection of nanostructure 55), some portions of STI hard mask 68D may be covered by CESL 94 and first ILD 96. Therefore, these covered portions of STI hard mask 68D directly below first ILD 96 may be etched less than the exposed portions of STI hard mask 68D (see FIG. Fig.23A For example, the covered portions of the STI hard mask 68D may have a thickness T5 that is 1 / 4 of the exposed portions of the STI hard mask 68D (see FIG. Fig.23A ) Different thickness T6 (see Fig.23C ). In some embodiments, thickness T6 may be greater than thickness T5. In some embodiments, thickness T6 may also be less than original thickness T4.

[0075] In other embodiments, thickness T6 may be less than thickness T5. For example, in embodiments where portions of STI hard mask 68D outside of dummy gate 76 are removed during a previous processing step, thickness T6 may be zero. For example, during a dummy gate patterning step, STI hard mask 68D may be completely removed except for the area directly covered by dummy gate 76. In such embodiments, STI hard mask 68D may not be formed directly under first ILD 96. FIG. 30A to FIG. 30C Such an embodiment is shown.

[0076] exist Fig.24A and Fig. 24B, a gate dielectric layer 100 and a gate electrode 102 are formed for replacing the gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. In the n-type region 50N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and on the top surface, sidewalls, and bottom surface of the second nanostructure 54, and in the p-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and on the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer 100 may also be deposited on the top surface of the first ILD 96, the top surface of the CESL 94, the top surface of the first spacer 81, and the top surface of the STI structure 68.

[0077] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, or combinations thereof, etc. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer on the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The formation method of the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0078] The gate electrodes 102 are respectively deposited on the plurality of gate dielectric layers 100 and fill the remaining portion of the second recess 98. The gate electrodes 102 may include a metal-containing material, for example, titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, a combination of the foregoing, or a multilayer thereof. Fig.24A and 24B , a single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of liner layers, any number of work function tuning layers, and filler materials. Any combination of these layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54 in the n-type region 50N and between the second nanostructure 54A and the substrate 50, and may be deposited between adjacent first nanostructures 52 in the p-type region 50P.

[0079] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by a different process, such that the gate dielectric layer 100 may be a different material and / or have a different number of layers, and / or the gate electrode 102 in each region may be formed by a different process, such that the gate electrode 102 may be a different material and / or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0080] After filling the second recess 98, a planarization process such as CMP may be performed to remove excess portions of the material of the gate dielectric layer 100 and the gate electrode 102 that are above the top surface of the first ILD 96. The remaining portions of the material of the gate electrode 102 and the gate dielectric layer 100 thus form a replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure."

[0081] exist FIG. 25A to FIG. 25C In the embodiment of the present invention, the gate structure (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed so that a recess is formed directly above the gate structure and between the opposing portions of the first spacer 81. A gate mask 104 including one or more layers of dielectric material (e.g., silicon nitride or silicon oxynitride, etc.) is filled in the recess, and a planarization process is then performed to remove excess portions of the dielectric material extending above the first ILD 96. A gate contact (e.g., as described below with reference to FIG. 1 ) is subsequently formed. Fig.27A and Fig.27B The gate contact 114 discussed penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102 .

[0082] like FIG. 25A to FIG. 25C As further shown, the second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, and can be deposited by any suitable method such as CVD or PECVD.

[0083] exist FIG. 26A to FIG. 26C, the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a third recess 108 exposing the surface of the epitaxial source / drain region 92 and / or the surface of the gate structure. The third recess 108 may be formed by etching using an anisotropic etching process (e.g., RIE or NBE, etc.). In some embodiments, the third recess 108 may be etched through the second ILD 106 and the first ILD 96 using a first etching process; the third recess 108 may be etched through the gate mask 104 using a second etching process; and then the third recess 108 may be etched through the CESL 94 using a third etching process. A mask (e.g., a photoresist) may be formed over the second ILD 106 and the mask may be patterned to mask a portion of the second ILD 106 in the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, the third recess 108 extends into the epitaxial source / drain region 92, and / or the gate structure, and the bottom of the third recess 108 may be flush with the epitaxial source / drain region 92 and / or the gate structure (e.g., at the same height, or at the same distance from the substrate), or lower than the epitaxial source / drain region 92 and / or the gate structure (e.g., closer to the substrate). Fig.26B The recess 108 is shown as exposing the epitaxial source / drain region 92 and the gate structure in the same cross-section, but in various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed in different cross-sections, thereby reducing the risk of shorting of subsequently formed contacts. After forming the third recess 108, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing a metal (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof) that reacts with the underlying epitaxial source / drain region 92 semiconductor material (e.g., silicon, silicon germanium, germanium) over the exposed portion of the epitaxial source / drain region 92 to form a silicide or germanide region, and then performing a thermal annealing process to form the silicide region 110. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, the silicide region 110 may also be a germanide region, or a silicon-germanide region (e.g., a region including silicide and germanide). In an embodiment, the silicide region 110 includes TiSi and has a thickness in a range between about 2 nm and about 10 nm.

[0084] Next, in FIG. 27A to FIG. 27CIn the embodiment of the present invention, contacts 112 and 114 (also referred to as contact plugs) are formed in the third recess 108. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to the conductive features below (e.g., the gate electrode 102 and / or the silicide region 110 in the illustrated embodiment). Contact 114 is electrically coupled to the gate structure 102 and may be referred to as a gate contact, and contact 112 is electrically coupled to the silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

[0085] FIG. 28A to FIG. 28C Cross-sectional views of devices according to some alternative embodiments are shown. Fig.28A Shows Figure 1 Reference cross section AA' is shown. Fig.28B Shows Figure 1 Reference cross section BB' is shown. Fig.28C Shows Figure 1 Reference cross section C-C' is shown. FIG. 28A to FIG. 28C In the drawings, the same reference numerals denote FIG. 27A to FIG. 27C The same components are formed by the same process. For example, FIG. 28A to FIG. 28C The structure includes an isolation structure 68, and the isolation structure 68 includes an inner STI region 68C surrounded by a second liner layer 68B and an STI hard mask 68D. The STI hard mask 68D may have a thickness T5 as described above (see Fig.28A ) and T6 (see Fig.28C ). However, in FIG. 28A to FIG. 28C In the embodiment, the channel regions in the n-type region 50N and the p-type region 50P include the same material. For example, the second nanostructure 54 including silicon provides channel regions for the p-type nanoFETs in the p-type region 50P and the n-type nanoFETs in the n-type region 50N. FIG. 28A to FIG. 28CThe structure of can be formed, for example, by: removing the first nanostructure 52 from both the p-type region 50P and the n-type region 50N; depositing the gate dielectric layer 100 and the gate electrode 102P (e.g., suitable for the gate electrode of the p-type nanoFET) around the second nanostructure 54 in the p-type region 50P; and depositing the gate dielectric layer 100 and the gate electrode 102N (e.g., suitable for the gate electrode of the n-type nanoFET) around the second nanostructure 54 in the n-type region 50N. In such an embodiment, the material of the epitaxial source / drain region 92 can be different in the n-type region 50N compared to the p-type region 50P, as explained above.

[0086] FIG. 29A to FIG. 29C Cross-sectional views of devices according to some alternative embodiments are shown. Fig.29A Shows Figure 1 Reference cross section AA' is shown. Fig.29B Shows Figure 1 Reference cross section BB' is shown. Fig.29C Shows Figure 1 Reference cross section C-C' is shown. FIG. 29A to FIG. 29C In the drawings, the same reference numerals denote FIG. 27A to FIG. 27C The same components are formed by the same process. For example, FIG. 29A to FIG. 29C The structure includes an isolation structure 68, and the isolation structure 68 includes an inner STI region 68C surrounded by a second liner layer 68B and an STI hard mask 68D. The STI hard mask 68D may have a thickness T5 as described above (see Fig.29A ) and T6 (see Fig.29C ). However, in FIG. 29A to FIG. 29C , the channel region 54 in the n-type region 50N and the channel region 52 in the p-type region 50P can have different sizes within the same device. For example, as part of the patterned nanostructures 55, as described above, the size of the nanostructures can increase as they are closer to the substrate 50. Therefore, in the n-type region 50N, the channel region 54C can be smaller (e.g., smaller in width) than the channel region 54B, and the channel region 54B can be smaller (e.g., smaller in width) than the channel region 54A. Similarly, in the p-type region 50P, the channel region 52C can be smaller (e.g., smaller in width) than the channel region 52B, and the channel region 52B can be smaller (e.g., smaller in width) than the channel region 52A. The patterning process can also round the edges (e.g., corners) of the channel regions 52 and 54.

[0087] FIG. 30A to FIG. 30C Cross-sectional views of devices according to some alternative embodiments are shown. Fig. 30A Shows Figure 1 Reference cross section AA' is shown. Fig. 30B Shows Figure 1 Reference cross section BB' is shown. Fig. 30C Shows Figure 1 Reference cross section C-C' is shown. FIG. 30A to FIG. 30C In the drawings, the same reference numerals denote FIG. 27A to FIG. 27C The same components are formed by the same process. For example, FIG. 30A to FIG. 30C The structure includes an isolation structure 68, and the isolation structure 68 includes an inner STI region 68C surrounded by a second liner layer 68B and an STI hard mask 68D. The STI hard mask 68D may have a thickness T5 as described above (see Fig.29A ). However, in FIG. 30A to FIG. 30C In the embodiment of the present invention, the STI hard mask 68D may be removed from the regions outside the gate structure 100 / 102. For example, during the various processing steps described above (e.g., as part of patterning the dummy gate), the exposed regions of the STI hard mask 68D may be completely removed. Thus, the cross section CC' may not include the STI hard mask 68D (see FIG. Fig. 30C ), and no STI hard mask 68D remains directly under the first ILD 96. In such an embodiment, the CESL 94 may be in direct contact with the inner STI region 68C and some portions of the first and second liners 68A / 68B.

[0088] In various embodiments, isolation regions are formed between and around the fins of the transistor to provide isolation between the various active regions of the transistor. A protective liner may be formed to cover the sidewalls, bottom surface, and top surface of the isolation region to reduce isolation losses during subsequent cleaning and / or etching processes performed to manufacture the transistor. When the inner isolation region is made of oxide, the outer protective liner may be a nitride layer. In this way, the protective liner may provide etching selectivity to the encapsulated isolation region and reduce isolation losses (e.g., STI losses) during subsequently applied cleaning / etching processes. Thus, manufacturing defects may be reduced and the electrical performance of the resulting device may be improved.

[0089] In an embodiment, a device includes a first semiconductor fin and a second semiconductor fin and an isolation structure between the first semiconductor fin and the second semiconductor fin, the isolation structure including: an inner shallow trench isolation (STI) region; a first liner layer along the sidewalls and bottom surface of the inner STI region; and an STI hard mask on the top surface of the inner STI region, wherein the STI hard mask and the first liner layer each include a higher nitrogen concentration than the inner STI region. The device also includes: a plurality of nanostructures on the first semiconductor fin; and a gate structure on the isolation structure and the first semiconductor fin, wherein the gate structure surrounds each of the plurality of nanostructures. Optionally, in some embodiments, the isolation structure also includes a second liner layer along the sidewalls and bottom surface of the inner STI region, wherein the second liner layer is disposed between the first semiconductor fin and the first liner layer. Optionally, in some embodiments, the first liner layer has a higher nitrogen concentration than the second liner layer. Optionally, in some embodiments, the second liner layer includes: a silicon liner layer; and an oxide liner layer on the silicon liner layer. Optionally, in some embodiments, the first liner layer has a different material composition than the STI hard mask. Optionally, in some embodiments, the STI hard mask has a nitrogen concentration in the range of 28at% to 38at%. Optionally, in some embodiments, the first liner layer has a nitrogen concentration in the range of 4at% to 14at%.

[0090] In an embodiment, a device includes: a semiconductor fin; a plurality of nanostructures above the semiconductor fin; a first and a second source / drain region, in the semiconductor fin, the plurality of nanostructures extending between the first and the second source / drain region; a shallow trench isolation (STI) region along the sidewall of the semiconductor fin; a nitride liner below the STI region, the nitride liner covering the bottom surface and the sidewall of the STI region; a nitride hard mask above the STI region, the nitride hard mask covering the top surface of the STI region; and a gate structure surrounding the plurality of nanostructures, the gate structure overlapping a first portion of the nitride hard mask. Optionally, in some embodiments, the device further includes an oxide liner below the nitride liner, the oxide liner covering the bottom surface and the sidewall of the STI region. Optionally, in some embodiments, the device further includes a dielectric layer surrounding the gate structure, the dielectric layer overlapping a second portion of the nitride hard mask. Optionally, in some embodiments, the first portion of the nitride hard mask has a first thickness, wherein the second portion of the nitride hard mask has a second thickness, and wherein the first thickness is less than the second thickness. Optionally, in some embodiments, the nitride hard mask has a different material composition than the nitride liner. Optionally, in some embodiments, the nitrogen concentration of the nitride hard mask is greater than the nitrogen concentration of the nitride liner.

[0091] In an embodiment, a method includes: etching a trench in a substrate to define a first semiconductor fin and a second semiconductor fin, the trench being disposed between the first semiconductor fin and the second semiconductor fin; forming a first liner over and along the sidewalls of the trench; forming a shallow trench isolation (STI) region over the first liner; forming a hard mask over the STI region, wherein a first material of the hard mask and a second material of the first liner have an etching selectivity to a third material of the STI region; and forming a gate structure over and along the sidewalls of the first semiconductor fin, wherein the gate structure covers at least a portion of the hard mask. Optionally, in some embodiments, the first liner and the hard mask each have a higher nitrogen concentration than the STI region. Forming the first liner and forming the STI region include: depositing a first liner layer over and along the sidewalls of the trench; depositing an insulating material over the first liner layer; and after depositing the insulating material, etching back the first liner layer to form the first liner, and etching back the insulating material to form the STI region. Optionally, in some embodiments, forming the hard mask includes: forming the hard mask after etching back the first liner layer to form the first liner and etching back the insulating material to form the STI region. Optionally, in some embodiments, forming the hard mask includes: depositing a second liner layer over the top surface of the first semiconductor fin, over the sidewalls of the first semiconductor fin, and over the top surface of the STI region; and removing a first portion of the second liner layer, the first portion of the second liner layer being disposed over the top surface of the first semiconductor fin; and removing a second portion of the second liner layer, the second portion of the second liner layer being disposed on the sidewalls of the first semiconductor fin, wherein after removing the second portion of the second liner layer, a third portion of the second liner layer defines the hard mask, the third portion of the second liner layer being disposed over the top surface of the STI region. Optionally, in some embodiments, removing the first portion of the second liner layer includes: depositing a mask over the second liner layer; planarizing the mask to expose the first portion of the second liner layer; etching the first portion of the second liner layer while covering the second portion and the third portion of the second liner layer with the mask; and removing the mask. Optionally, in some embodiments, depositing the second liner layer includes a non-conformal deposition process, which deposits the first portion of the second liner layer and the third portion of the second liner layer to have a greater thickness than the second portion of the second liner layer, and wherein removing the second portion of the second liner layer includes an isotropic etching process.

[0092] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0093] Example

[0094] Example 1. A semiconductor device, comprising: a first semiconductor fin and a second semiconductor fin; an isolation structure, between the first semiconductor fin and the second semiconductor fin, the isolation structure comprising: an inner shallow trench isolation (STI) region;

[0095] A first liner layer along the sidewalls and bottom surface of the inner STI region; and an STI hard mask on the top surface of the inner STI region, wherein the STI hard mask and the first liner layer each include a higher nitrogen concentration than the inner STI region; a plurality of nanostructures above the first semiconductor fin; and a gate structure above the isolation structure and the first semiconductor fin, wherein the gate structure surrounds each of the plurality of nanostructures.

[0096] Example 2. A semiconductor device according to Example 1, wherein the isolation structure further comprises a second liner layer, the second liner layer is along the sidewall and bottom surface of the inner STI region, wherein the second liner layer is disposed between the first semiconductor fin and the first liner layer.

[0097] Example 3. The semiconductor device of Example 2, wherein the first liner layer has a higher nitrogen concentration than the second liner layer.

[0098] Example 4. The semiconductor device of Example 2, wherein the second liner layer comprises: a silicon liner layer; and an oxide liner layer on the silicon liner layer.

[0099] Example 5. The semiconductor device of Example 1, wherein the first liner layer has a different material composition than the STI hard mask.

[0100] Example 6. The semiconductor device of Example 1, wherein the STI hard mask has a nitrogen concentration in a range of 28 at % to 38 at %.

[0101] Example 7. The semiconductor device of Example 6, wherein the first liner layer has a nitrogen concentration in a range of 4 at % to 14 at %.

[0102] Example 8. A semiconductor device comprising: a semiconductor fin; a plurality of nanostructures above the semiconductor fin; a first and a second source / drain region, in the semiconductor fin, the plurality of nanostructures extending between the first and the second source / drain regions; a shallow trench isolation (STI) region along the sidewall of the semiconductor fin; a nitride liner below the STI region, the nitride liner covering the bottom surface and the sidewall of the STI region; a nitride hard mask above the STI region, the nitride hard mask covering the top surface of the STI region; and a gate structure surrounding the plurality of nanostructures, the gate structure overlapping a first portion of the nitride hard mask.

[0103] Example 9. The semiconductor device according to Example 8 further includes an oxide liner, the oxide liner being below the nitride liner, the oxide liner covering a bottom surface and sidewalls of the STI region.

[0104] Example 10. The semiconductor device of Example 8, further comprising a dielectric layer surrounding the gate structure, the dielectric layer overlapping the second portion of the nitride hard mask.

[0105] Example 11. The semiconductor device of Example 10, wherein the first portion of the nitride hard mask has a first thickness, wherein the second portion of the nitride hard mask has a second thickness, and wherein the first thickness is less than the second thickness.

[0106] Example 12. The device of Example 8, wherein the nitride hard mask has a different material composition than the nitride liner.

[0107] Example 13. The semiconductor device of Example 12, wherein a nitrogen concentration of the nitride hard mask is greater than a nitrogen concentration of the nitride liner.

[0108] Example 14. A method for forming a semiconductor device, comprising: etching a trench in a substrate to define a first semiconductor fin and a second semiconductor fin, the trench being disposed between the first semiconductor fin and the second semiconductor fin; forming a first liner over and along the sidewalls of the trench; forming a shallow trench isolation (STI) region over the first liner; forming a hard mask over the STI region, wherein a first material of the hard mask and a second material of the first liner have etching selectivity to a third material of the STI region; and forming a gate structure over and along the sidewalls of the first semiconductor fin, wherein the gate structure covers at least a portion of the hard mask.

[0109] Example 15. The method of Example 14, wherein the first liner and the hard mask each have a higher nitrogen concentration than the STI region.

[0110] Example 16. A method according to Example 14, wherein forming the first liner and forming the STI region include: depositing a first liner layer on and along the sidewalls of the trench; depositing an insulating material on the first liner layer; and after depositing the insulating material, etching back the first liner layer to form the first liner, and etching back the insulating material to form the STI region.

[0111] Example 17. The method of Example 16, wherein forming the hard mask comprises forming the hard mask after etching back the first liner layer to form the first liner and etching back the insulating material to form the STI region.

[0112] Example 18. A method according to Example 14, wherein forming the hard mask includes: depositing a second liner layer over the top surface of the first semiconductor fin, over the sidewalls of the first semiconductor fin, and over the top surface of the STI region; and removing a first portion of the second liner layer, the first portion of the second liner layer being disposed over the top surface of the first semiconductor fin; and removing a second portion of the second liner layer, the second portion of the second liner layer being disposed on the sidewalls of the first semiconductor fin, wherein after removing the second portion of the second liner layer, a third portion of the second liner layer defines the hard mask, the third portion of the second liner layer being disposed over the top surface of the STI region.

[0113] Example 19. A method according to Example 18, wherein removing the first portion of the second liner layer includes: depositing a mask over the second liner layer; flattening the mask to expose the first portion of the second liner layer; etching the first portion of the second liner layer while using the mask to cover the second portion and the third portion of the second liner layer; and removing the mask.

[0114] Example 20. A method according to Example 18, wherein depositing the second liner layer includes a non-conformal deposition process, the non-conformal deposition process deposits the first portion of the second liner layer and the third portion of the second liner layer to have a greater thickness than the second portion of the second liner layer, and wherein removing the second portion of the second liner layer includes an isotropic etching process.

Claims

1. A semiconductor device, comprising: a first semiconductor fin and a second semiconductor fin; an isolation structure between the first semiconductor fin and the second semiconductor fin, the isolation structure comprising: Internal shallow trench isolation (STI) region; a first liner layer along the sidewalls and bottom surface of the inner STI region; and an STI hard mask on a top surface of the inner STI region, wherein the STI hard mask and the first liner layer each include a higher nitrogen concentration than the inner STI region; a plurality of nanostructures on the first semiconductor fin; and A gate structure is above the isolation structure and the first semiconductor fin, wherein the gate structure surrounds each of the plurality of nanostructures.

2. The semiconductor device according to claim 1, wherein The isolation structure further includes a second liner layer along sidewalls and a bottom surface of the inner STI region, wherein the second liner layer is disposed between the first semiconductor fin and the first liner layer.

3. The semiconductor device according to claim 2, wherein: The first liner layer has a higher nitrogen concentration than the second liner layer.

4. The semiconductor device according to claim 2, wherein: The second lining layer comprises: a silicon liner layer; and An oxide liner layer is above the silicon liner layer.

5. The semiconductor device according to claim 1, wherein The first liner layer has a different material composition than the STI hard mask.

6. The semiconductor device according to claim 1, wherein The STI hard mask has a nitrogen concentration in a range of 28 at % to 38 at %.

7. The semiconductor device according to claim 6, wherein: The first liner layer has a nitrogen concentration in a range of 4 at % to 14 at %.

8. A semiconductor device comprising: Semiconductor fins; a plurality of nanostructures on the semiconductor fin; first and second source / drain regions, wherein the plurality of nanostructures extend between the first and second source / drain regions in the semiconductor fin; a shallow trench isolation (STI) region along a sidewall of the semiconductor fin; a nitride liner, below the STI region, the nitride liner covering a bottom surface and sidewalls of the STI region; a nitride hard mask, above the STI region, the nitride hard mask covering a top surface of the STI region; as well as A gate structure surrounds the plurality of nanostructures, and the gate structure overlaps the first portion of the nitride hard mask. 9 . The semiconductor device according to claim 8 , further comprising an oxide liner below the nitride liner, the oxide liner covering a bottom surface and a sidewall of the STI region.

10. A method for forming a semiconductor device, comprising: etching a trench in a substrate to define a first semiconductor fin and a second semiconductor fin, the trench being disposed between the first semiconductor fin and the second semiconductor fin; forming a first liner over and along the sidewalls of the trench; forming a shallow trench isolation (STI) region on the first liner; forming a hard mask over the STI region, wherein a first material of the hard mask and a second material of the first liner have an etching selectivity to a third material of the STI region; and A gate structure is formed over and along sidewalls of the first semiconductor fin, wherein the gate structure covers at least a portion of the hard mask.

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