A temperature-adjusting curvature compensation circuit for a concave-curve bandgap reference source

Abstract

The present invention relates to the field of integrated circuit design, and specifically to a temperature-adjusting curvature compensation circuit for a concave curve bandgap reference source. Specifically, a piecewise linear compensation method is adopted, clearly dividing the low-temperature range and the high-temperature range. In the low-temperature range, the compensation circuit turns on relevant transistors to generate a negative temperature coefficient compensation current, and this current changes with temperature showing a specific pattern, which can accurately compensate for the change of the reference voltage at low temperatures; the same is true in the high-temperature range. This piecewise and accurate compensation method can better meet the requirements of the concave curve bandgap reference source in different temperature segments, improve the overall temperature compensation effect, better ensure the performance consistency of the system in different temperature environments, avoid system errors caused by reference voltage fluctuations, and improve the reliability and accuracy of the entire system. Moreover, the circuit structure of the present invention is simple, without the need for additional trimming resistors or switches, effectively saving chip area.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and specifically to a temperature-adjusted curvature compensation circuit for a concave-curve bandgap reference source. Background Art

[0002] Bandgap reference voltage sources are widely used in analog circuits, digital circuits, and mixed-signal circuits, such as operational amplifiers, linear voltage regulators, memories, analog-to-digital converters, etc. Traditional bandgap reference voltage sources are limited by the structure of bipolar transistors, with a minimum supply voltage higher than 1.25V and significant temperature drift problems. Traditional bandgap reference voltage sources may exhibit a convex curve or a concave curve in terms of temperature characteristics. Existing temperature compensation techniques are mostly designed for convex curves, such as exponential curvature compensation, piecewise non-linear compensation, etc. However, for bandgap reference voltage sources with concave-curve characteristics, these compensation techniques have limited effects and it is difficult to achieve high-precision compensation over a wide temperature range. Especially in the low-temperature region (-40°C to 0°C) and the high-temperature region (75°C to 140°C), the temperature drift problem of the concave curve is particularly prominent. Summary of the Invention

[0003] The present invention provides a temperature-adjusted curvature compensation circuit for a concave-curve bandgap reference source, which can significantly reduce temperature drift over a wide temperature range.

[0004] To achieve the object of the present invention, the technical solution adopted is: a temperature-adjusted curvature compensation circuit for a concave-curve bandgap reference source, comprising

[0005] a sub-1V bandgap reference source part, a temperature-adjusted curvature compensation circuit part, and a reference voltage output part. The sub-1V bandgap reference source part includes transistors, operational amplifiers, resistors, and triodes, and is used to output a basic reference current Iref with a temperature coefficient, which is then multiplied by the output resistance R OUT of the reference voltage output part to generate a basic reference voltage Vref;

[0006] The temperature-adjusted curvature compensation circuit part is divided into a low-temperature region temperature compensation module and a high-temperature region temperature compensation module, which are composed of enhancement-mode PMOS transistors and enhancement-mode NMOS transistors. Through different connection methods and the magnitudes of the width-to-length ratios, current mirroring and subtraction operations are realized, and appropriate low-temperature compensation current A3I NTC or high-temperature compensation current B3I PTC is generated in different temperature ranges; and then multiplied by the resistor RC of the reference voltage output part to generate a low-temperature compensation voltage V NTC or high-temperature compensation voltage V PTC , reducing the drift of the reference voltage with temperature and generating a compensation reference voltage V ref1 independent of temperature.

[0007] As a preferred technical solution for a temperature-adjusting curvature compensation circuit of a concave-curve bandgap reference source, the sub-1V bandgap reference source part includes operational amplifier OP1, operational amplifier OP2, PNP-type triode Q1, PNP-type triode Q2, resistor R1, resistor R2, enhancement-mode PMOS transistor M1, enhancement-mode PMOS transistor M2, and enhancement-mode PMOS transistor M3; the source electrodes of the enhancement-mode PMOS transistor M1, enhancement-mode PMOS transistor M2, and enhancement-mode PMOS transistor M3 are all connected to power supply VDD, the gate electrode of the enhancement-mode PMOS transistor M1 is connected to the output terminal of operational amplifier OP2, the gate electrodes of the enhancement-mode PMOS transistor M2 and enhancement-mode PMOS transistor M3 are connected to the output terminal of operational amplifier OP1, the drain electrode of the enhancement-mode PMOS transistor M1, the non-inverting input terminal of operational amplifier OP2, and one end of resistor R2 are connected, the drain electrode of the enhancement-mode PMOS transistor M2, the inverting input terminal of operational amplifier OP1, the inverting input terminal of operational amplifier OP2, and the emitter electrode of PNP-type triode Q1 are connected, the drain electrode of the enhancement-mode PMOS transistor M3, the non-inverting input terminal of operational amplifier OP1, and one end of resistor R1 are connected, the other end of resistor R1 and the emitter electrode of PNP-type triode Q2 are connected, and the other end of resistor R2, the base electrode and collector electrode of PNP-type triode Q1, and the base electrode and collector electrode of PNP-type triode Q2 are all grounded.

[0008] As a preferred technical solution for a temperature-adjusting curvature compensation circuit of a concave-curve bandgap reference source, the width-to-length ratios of the enhancement-mode PMOS transistor M1, enhancement-mode PMOS transistor M2, and enhancement-mode PMOS transistor M3 are width W = 2μm and length L = 2μm.

[0009] As a preferred technical solution for a temperature-adjusting curvature compensation circuit of a concave-curve bandgap reference source, the low-temperature region temperature compensation circuit of the temperature-adjusting curvature compensation circuit part includes enhancement-mode PMOS transistor MA1, enhancement-mode NMOS transistor MA2, enhancement-mode PMOS transistor MA3, enhancement-mode NMOS transistor MA4, enhancement-mode PMOS transistor MA5, enhancement-mode PMOS transistor MA6, enhancement-mode NMOS transistor MA7, and enhancement-mode NMOS transistor MA8;

[0010] The source electrodes of the enhancement-mode PMOS transistor MA1, enhancement-mode PMOS transistor MA3, enhancement-mode PMOS transistor MA5, and enhancement-mode PMOS transistor MA6 are all connected to power supply V DD, the gate of the enhanced PMOS transistor MA1 is connected to the output terminal of the operational amplifier OP2, the gate of the enhanced PMOS transistor MA3 is connected to the output terminal of the operational amplifier OP1, the drain of the enhanced PMOS transistor MA1, the drains and gates of the enhanced NMOS transistors MA2 and MA4 are connected, the drain of the enhanced PMOS transistor MA3, the drains of the enhanced NMOS transistors MA4, the drains and gates of the enhanced PMOS transistors MA5 and MA6, and the gate of the enhanced PMOS transistor MA6 are connected, the drain of the enhanced PMOS transistor MA6, the drains and gates of the enhanced NMOS transistors MA7 and MA8 are connected, the drain of the enhanced NMOS transistor MA8 is connected to the connection point of the resistor R3 and the resistor RC in the reference voltage output section, and the sources of the enhanced NMOS transistors MA2, MA4, MA7, and MA8 are all grounded.

[0011] As a preferred technical solution of a temperature-adjusting curvature compensation circuit for a concave-curve bandgap reference source, the width-to-length ratios of the enhanced PMOS transistor MA1, the enhanced NMOS transistor MA2, the enhanced PMOS transistors MA5 and MA6, and the enhanced NMOS transistor MA7 are the same as the width-to-length ratio of the enhanced PMOS transistor M1 in the sub-1V bandgap reference source section. The width-to-length ratio of the enhanced PMOS transistor MA3 is A1 times the width-to-length ratio of the enhanced PMOS transistor MA1, the width-to-length ratio of the enhanced PMOS transistor MA4 is A2 times the width-to-length ratio of the enhanced PMOS transistor MA1, and the width-to-length ratio of the enhanced PMOS transistor MA8 is A3 times the width-to-length ratio of the enhanced PMOS transistor MA1.

[0012] As a preferred technical solution of a temperature-adjusting curvature compensation circuit for a concave-curve bandgap reference source, the high-temperature region temperature compensation circuit in the temperature-adjusting curvature compensation circuit section includes an enhanced PMOS transistor MA9, an enhanced NMOS transistor MA10, an enhanced PMOS transistor MA11, an enhanced NMOS transistor MA12, an enhanced PMOS transistor MA13, an enhanced PMOS transistor MA14, an enhanced NMOS transistor MA15, and an enhanced NMOS transistor MA16;

[0013] The sources of the enhanced PMOS transistors MA9, MA11, MA13, and MA14 are all connected to the power supply V DD, the gate of the enhanced PMOS transistor MA9 is connected to the output terminal of the operational amplifier OP1 in the sub-1V bandgap reference source section, the gate of the enhanced PMOS transistor MA11 is connected to the output terminal of the operational amplifier OP2 in the sub-1V bandgap reference source section, the drain of the enhanced PMOS transistor MA9, the drain and gate of the enhanced NMOS transistor MA10, and the gate of the enhanced NMOS transistor MA12 are connected; the drain of the enhanced PMOS transistor MA11, the drain of the enhanced NMOS transistor MA12, the drain and gate of the enhanced PMOS transistor MA13, and the gate of the enhanced PMOS transistor MA14 are connected; the drain of the enhanced PMOS transistor MA14, the drain and gate of the enhanced NMOS transistor MA15, and the gate of the enhanced NMOS transistor MA16 are connected; the drain of the enhanced NMOS transistor MA16 is connected to the connection point of the resistor R3 and the resistor RC in the reference voltage output section; the sources of the enhanced NMOS transistors MA10, MA12, MA15, and MA16 are all grounded.

[0014] As a preferred technical solution of a temperature-adjusted curvature compensation circuit for a concave curve bandgap reference source, the width-to-length ratios of the enhanced PMOS transistor MA9, the enhanced NMOS transistor MA10, the enhanced PMOS transistor MA13, the enhanced PMOS transistor MA14, and the enhanced NMOS transistor MA15 are the same as the width-to-length ratio of the enhanced PMOS transistor M1 in the sub-1V bandgap reference source section. The width-to-length ratio of the enhanced PMOS transistor MA11 is B1 times the width-to-length ratio of the enhanced PMOS transistor MA1, the width-to-length ratio of the enhanced PMOS transistor MA12 is B2 times the width-to-length ratio of the enhanced PMOS transistor MA1, and the width-to-length ratio of the enhanced PMOS transistor MA16 is B3 times the width-to-length ratio of the enhanced PMOS transistor MA1.

[0015] As a preferred technical solution of a temperature-adjusted curvature compensation circuit for a concave curve bandgap reference source, the reference voltage output section includes a resistor R3, a resistor RC, an enhanced PMOS transistor M4, and an enhanced PMOS transistor M5; the sources of the enhanced PMOS transistor M4 and the enhanced PMOS transistor M5 are both connected to the power supply V DD , the gate of the enhanced PMOS transistor M4 is connected to the output terminal of the operational amplifier OP1 in the sub-1V bandgap reference source section, the gate of the enhanced PMOS transistor M5 is connected to the output terminal of the operational amplifier OP2 in the sub-1V bandgap reference source section, the drains of the enhanced PMOS transistor M4 and the enhanced PMOS transistor M5 and one end of the resistor R3 are connected, and this connection point is the compensated reference voltage V ref1 output point; the other end of the resistor R3 is connected to one end of the resistor RC, the other end of the resistor RC is grounded, and the resistor R3 and the resistor RC are connected in series to jointly form the output resistor R OUT, the basic reference current I ref flows through the output resistor R OUT to generate the basic reference voltage V ref , and at the same time, the resistor RC is also used for calculating the low-temperature compensation voltage V NTC or the high-temperature compensation voltage V PTC , jointly determining the compensated reference voltage V of the final output ref1 .

[0016] As a preferred technical solution of a temperature-adjusted curvature compensation circuit for a concave-curve bandgap reference source, the aspect ratios of the enhanced PMOS transistor M4 and the enhanced PMOS transistor M5 are the same as those of the enhanced PMOS transistor M1 in the sub-1V bandgap reference source part.

[0017] Advantages of the present invention: The present invention provides a temperature-adjusted curvature compensation circuit for a concave-curve bandgap reference source, which adopts a segmented linear compensation method, clearly divides the low-temperature range and the high-temperature range. In the low-temperature range, the compensation circuit turns on relevant transistors to generate a negative temperature coefficient compensation current, and this current changes with temperature showing a specific law, which can accurately compensate for the change of the reference voltage at low temperatures; the same is true in the high-temperature range. This segmented and accurate compensation method can better meet the requirements of the concave-curve bandgap reference source in different temperature segments compared with the convex-curve compensation circuit, improve the overall temperature compensation effect, better ensure the performance consistency of the system in different temperature environments, avoid system errors caused by reference voltage fluctuations, and improve the reliability and accuracy of the entire system. And the circuit structure of the present invention is simple, without the need for additional trimming resistors or switches, effectively saving chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. Among them:

[0019] Figure 1 is the principle block diagram of the present invention

[0020] Figure 2 is the circuit schematic diagram of the present invention.

[0021] Reference numerals: low-temperature region temperature compensation circuit 201, high-temperature region temperature compensation circuit 202, sub-1V bandgap reference source part 100, temperature-adjusted curvature compensation circuit part 200, reference voltage output part 300. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] To make the above objects, features and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be made in conjunction with the accompanying drawings of the specification.

[0023] In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0024] Secondly, the so-called "one embodiment" or "embodiment" herein refers to a specific feature, structure or characteristic that may be included in at least one implementation manner of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments.

[0025] Thirdly, the present invention is described in detail in conjunction with schematic diagrams. When detailing the embodiments of the present invention, for the sake of convenience of explanation, the cross-sectional views showing the device structure will be enlarged locally out of the general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width and depth should be included.

[0026] Embodiment 1

[0027] Referring to Figures 1 - 2 , this embodiment provides a temperature-adjusted curvature compensation circuit for a concave-curve bandgap reference source. Specifically, as Figure 1 shown, the present invention includes a sub-1V bandgap reference source part 100, a temperature-adjusted curvature (ATC) compensation circuit part 200, and a reference voltage output part 300. The sub-1V bandgap reference source part is mainly composed of transistors, operational amplifiers, resistors and triodes, and is responsible for outputting a basic positive temperature coefficient current I PT and a negative temperature coefficient current I NT . The sum of the two gives the basic reference current I ref with a temperature coefficient. Then, multiplying it by the output resistor R OUT of the reference voltage output part generates the basic reference voltage V ref . The ATC compensation circuit part can be divided into a low-temperature region temperature compensation circuit 201 and a high-temperature region temperature compensation circuit 202, which are composed of enhancement-mode PMOS transistors and enhancement-mode NMOS transistors. By different connection methods and the magnitudes of the width-to-length ratios, operations such as current mirroring and subtraction are realized, and appropriate low-temperature compensation current A3I NTC or high-temperature compensation current B3I PTC is generated in different temperature ranges. Then, multiplying it by the RC of the reference voltage output part generates the low-temperature compensation voltage V NTCor a high-temperature compensation voltage V PTC , thereby reducing the drift of the reference voltage with temperature and realizing a high-precision, temperature-independent output compensation reference voltage V ref1 .

[0028] As Figure 2 shown, the sub-1V bandgap reference source part includes an operational amplifier OP1, an operational amplifier OP2, a PNP-type triode Q1, a PNP-type triode Q2, a resistor R1, a resistor R2, an enhancement-mode PMOS transistor M1, an enhancement-mode PMOS transistor M2, and an enhancement-mode PMOS transistor M3. The width-to-length dimensions of the enhancement-mode PMOS transistor M1, the enhancement-mode PMOS transistor M2, and the enhancement-mode PMOS transistor M3 are width W = 2μm and length L = 2μm. The sources of the enhancement-mode PMOS transistor M1, the enhancement-mode PMOS transistor M2, and the enhancement-mode PMOS transistor M3 are all connected to the power supply V DD , the gate of the enhancement-mode PMOS transistor M1 is connected to the output terminal of the operational amplifier OP2, the gates of the enhancement-mode PMOS transistor M2 and the enhancement-mode PMOS transistor M3 are connected to the output terminal of the operational amplifier OP1, the drain of the enhancement-mode PMOS transistor M1, the non-inverting input terminal of the operational amplifier OP2, and one end of the resistor R2 are connected, the drain of the enhancement-mode PMOS transistor M2, the inverting input terminal of the operational amplifier OP1, the inverting input terminal of the operational amplifier OP2, and the emitter of the PNP-type triode Q1 are connected, the drain of the enhancement-mode PMOS transistor M3, the non-inverting input terminal of the operational amplifier OP1, and one end of the resistor R1 are connected, the other end of the resistor R1 and the emitter of the PNP-type triode Q2 are connected, and the other end of the resistor R2, the base and collector of the PNP-type triode Q1, and the base and collector of the PNP-type triode Q2 are all grounded (GND).

[0029] The emitter area of Q1 is labeled as (1), and the emitter area of Q2 is labeled as (n). Their area difference and cooperation with the resistor generate a current I with a positive temperature coefficient PT ; at the same time, the negative temperature coefficient characteristic of Q1 itself is used to generate a current I with a negative temperature coefficient NT .

[0030] As Figure 2As shown, the ATC compensation circuit part can be divided into two parts: the low-temperature region temperature compensation circuit and the high-temperature region temperature compensation circuit. The low-temperature region temperature compensation circuit includes an enhancement-mode PMOS transistor MA1, an enhancement-mode NMOS transistor MA2, an enhancement-mode PMOS transistor MA3, an enhancement-mode NMOS transistor MA4, an enhancement-mode PMOS transistor MA5, an enhancement-mode PMOS transistor MA6, an enhancement-mode NMOS transistor MA7, and an enhancement-mode NMOS transistor MA8. The width-to-length ratios of the enhancement-mode PMOS transistor MA1, the enhancement-mode NMOS transistor MA2, the enhancement-mode PMOS transistor MA5, the enhancement-mode PMOS transistor MA6, and the enhancement-mode NMOS transistor MA7 are the same as the width-to-length ratio of the enhancement-mode PMOS transistor M1 in the sub-1V bandgap reference source part. The width-to-length ratio of the enhancement-mode PMOS transistor MA3 is A1 times the width-to-length ratio of the enhancement-mode PMOS transistor MA1. The width-to-length ratio of the enhancement-mode PMOS transistor MA4 is A2 times the width-to-length ratio of the enhancement-mode PMOS transistor MA1. The width-to-length ratio of the enhancement-mode PMOS transistor MA8 is A3 times the width-to-length ratio of the enhancement-mode PMOS transistor MA1. The sources of the enhancement-mode PMOS transistor MA1, the enhancement-mode PMOS transistor MA3, the enhancement-mode PMOS transistor MA5, and the enhancement-mode PMOS transistor MA6 are all connected to the power supply V DD , the gate of the enhancement-mode PMOS transistor MA1 is connected to the output terminal of the operational amplifier OP2 in the sub-1V bandgap reference source part. The gate of the enhancement-mode PMOS transistor MA3 is connected to the output terminal of the operational amplifier OP1 in the sub-1V bandgap reference source part. The drain of the enhancement-mode PMOS transistor MA1, the drain and gate of the enhancement-mode NMOS transistor MA2, and the gate of the enhancement-mode NMOS transistor MA4 are connected. The drain of the enhancement-mode PMOS transistor MA3, the drain of the enhancement-mode NMOS transistor MA4, the drain and gate of the enhancement-mode PMOS transistor MA5, and the gate of the enhancement-mode PMOS transistor MA6 are connected. The drain of the enhancement-mode PMOS transistor MA6, the drain and gate of the enhancement-mode NMOS transistor MA7, and the gate of the enhancement-mode NMOS transistor MA8 are connected. The drain of the enhancement-mode NMOS transistor MA8 is connected to the connection point of the resistor R3 and the resistor RC in the reference voltage output part. The sources of the enhancement-mode NMOS transistor MA2, the enhancement-mode NMOS transistor MA4, the enhancement-mode NMOS transistor MA7, and the enhancement-mode NMOS transistor MA8 are all grounded (GND).

[0031] Generate the low-temperature compensation current A3I through a subtraction circuit and a current mirror structure NTC =A3(A2I NT -A2I PT ).

[0032] Among them, the high-temperature region temperature compensation circuit includes an enhanced PMOS transistor MA9, an enhanced NMOS transistor MA10, an enhanced PMOS transistor MA11, an enhanced NMOS transistor MA12, an enhanced PMOS transistor MA13, an enhanced PMOS transistor MA14, an enhanced NMOS transistor MA15, and an enhanced NMOS transistor MA16. The width-to-length ratios of the enhanced PMOS transistor MA9, the enhanced NMOS transistor MA10, the enhanced PMOS transistor MA13, the enhanced PMOS transistor MA14, and the enhanced NMOS transistor MA15 are the same as the width-to-length ratio of the enhanced PMOS transistor M1 in the sub-1V bandgap reference source part. The width-to-length ratio of the enhanced PMOS transistor MA11 is B1 times the width-to-length ratio of the enhanced PMOS transistor MA1. The width-to-length ratio of the enhanced PMOS transistor MA12 is B2 times the width-to-length ratio of the enhanced PMOS transistor MA1. The width-to-length ratio of the enhanced PMOS transistor MA16 is B3 times the width-to-length ratio of the enhanced PMOS transistor MA1. The sources of the enhanced PMOS transistor MA9, the enhanced PMOS transistor MA11, the enhanced PMOS transistor MA13, and the enhanced PMOS transistor MA14 are all connected to the power supply V DD , the gate of the enhanced PMOS transistor MA9 is connected to the output terminal of the operational amplifier OP1 in the sub-1V bandgap reference source part. The gate of the enhanced PMOS transistor MA11 is connected to the output terminal of the operational amplifier OP2 in the sub-1V bandgap reference source part. The drain of the enhanced PMOS transistor MA9, the drain and gate of the enhanced NMOS transistor MA10, and the gate of the enhanced NMOS transistor MA12 are connected. The drain of the enhanced PMOS transistor MA11, the drain of the enhanced NMOS transistor MA12, the drain and gate of the enhanced PMOS transistor MA13, and the gate of the enhanced PMOS transistor MA14 are connected. The drain of the enhanced PMOS transistor MA14, the drain and gate of the enhanced NMOS transistor MA15, and the gate of the enhanced NMOS transistor MA16 are connected. The drain of the enhanced NMOS transistor MA16 is connected to the connection point of the resistor R3 and the resistor RC in the reference voltage output part. The sources of the enhanced NMOS transistor MA10, the enhanced NMOS transistor MA12, the enhanced NMOS transistor MA15, and the enhanced NMOS transistor MA16 are all grounded (GND).

[0033] Generate the high-temperature compensation current B3I through the subtraction circuit and the current mirror structure PTC =B3(B2I PT -A2I NT )

[0034] Such as Figure 2As shown in the figure, the reference voltage output section includes resistor R3, resistor RC, enhancement-mode PMOS transistor M4, and enhancement-mode PMOS transistor M5. The aspect ratios of the enhancement-mode PMOS transistor M4 and the enhancement-mode PMOS transistor M5 are the same as that of the enhancement-mode PMOS transistor M1 in the sub-1V bandgap reference source section. The sources of the enhancement-mode PMOS transistor M4 and the enhancement-mode PMOS transistor M5 are both connected to the power supply V DD , the gate of the enhancement-mode PMOS transistor M4 is connected to the output terminal of the operational amplifier OP1 in the sub-1V bandgap reference source section, the gate of the enhancement-mode PMOS transistor M5 is connected to the output terminal of the operational amplifier OP2 in the sub-1V bandgap reference source section, the drains of the enhancement-mode PMOS transistor M4 and the enhancement-mode PMOS transistor M5 are connected to one end of the resistor R3, and this connection point is the reference voltage V ref1 output point. The other end of the resistor R3 is connected to one end of the resistor RC, the other end of the resistor RC is grounded (GND), and the resistor R3 and the resistor RC are connected in series to jointly form the output resistor R OUT , and the basic reference current I ref flows through the output resistor R OUT to generate the basic reference voltage V ref , and at the same time, the resistor RC is also involved in the calculation of the low-temperature compensation voltage V NTC or the high-temperature compensation voltage V PTC , and jointly determines the finally output compensated reference voltage V ref1 .

[0035] The enhancement-mode PMOS transistor M4 generates a current I with a positive temperature coefficient through a current mirror structure with the enhancement-mode PMOS transistor M3 in the sub-1V bandgap reference source section PT ; the enhancement-mode PMOS transistor M5 generates a current I with a negative temperature coefficient through a current mirror structure with the enhancement-mode PMOS transistor M1 in the sub-1V bandgap reference source section NT .

[0036] Further Figure 2 The aspect ratios of the enhancement-mode PMOS transistors and enhancement-mode NMOS transistors in the parentheses are marked as multiples of their aspect ratios relative to the aspect ratio of the enhancement-mode PMOS transistor M1

[0037] The present invention provides a temperature-adjusting curvature compensation circuit for a concave-curve bandgap reference source. The circuit adopts a segmented linear compensation method, clearly dividing the low-temperature range and the high-temperature range. In the low-temperature range, the compensation circuit turns on relevant transistors to generate a negative temperature coefficient compensation current, and this current changes with temperature according to a specific law, which can accurately compensate for the change in the reference voltage at low temperatures. Similarly, in the high-temperature range. This segmented and accurate compensation method can better meet the requirements of the concave-curve bandgap reference source in different temperature segments compared with the convex-curve compensation circuit, improving the overall temperature compensation effect, better ensuring the performance consistency of the system in different temperature environments, avoiding system errors caused by reference voltage fluctuations, and improving the reliability and accuracy of the entire system. Moreover, the circuit structure of the present invention is simple, without the need for additional trimming resistors or switches, effectively saving chip area.

[0038] It should be understood that in the development of any actual implementation, such as in any engineering or design project, a large number of specific implementation decisions can be made. Such development efforts may be complex and time-consuming, but for those of ordinary skill in the art who benefit from this disclosure, without excessive experimentation, the development efforts will be a routine task of design, manufacturing, and production.

[0039] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A temperature-adjusted curvature compensation circuit for a concave curve bandgap reference source, characterized in that: include, The sub-1V bandgap reference source part, the temperature adjustment curvature compensation circuit part and the reference voltage output part. The sub-1V bandgap reference source part includes a transistor, an operational amplifier, a resistor and a triode, which is used to output a basic reference current Iref with a temperature coefficient, and then with the output resistor R OUT Multiply to generate a basic reference voltage Vref; The temperature-adjusting curvature compensation circuit is divided into a low-temperature zone temperature compensation module and a high-temperature zone temperature compensation module, which are composed of an enhanced PMOS tube and an enhanced NMOS tube. Through different connection methods and width-to-length ratios, the current mirror and subtraction operations are realized to generate a suitable low-temperature compensation current A3I in different temperature ranges. NTC Or high temperature compensation current B3I PTC ; Then multiply it with the resistance RC of the reference voltage output part to generate the low temperature compensation voltage V NTC Or high temperature compensation voltage V PTC , reduce the drift of the reference voltage with temperature, and generate a temperature-independent compensated reference voltage V ref1 ; The sub-1V bandgap reference source part includes an operational amplifier OP1, an operational amplifier OP2, a PNP transistor Q1, a PNP transistor Q2, a resistor R1, a resistor R2, an enhanced PMOS tube M1, an enhanced PMOS tube M2, and an enhanced PMOS tube M3; the sources of the enhanced PMOS tube M1, the enhanced PMOS tube M2, and the enhanced PMOS tube M3 are all connected to the power supply VDD, the gate of the enhanced PMOS tube M1 is connected to the output end of the operational amplifier OP2, the gate of the enhanced PMOS tube M2, the gate of the enhanced PMOS tube M3 are connected to the output end of the operational amplifier OP1, The drain of the enhanced PMOS tube M1, the non-inverting input terminal of the operational amplifier OP2 and one end of the resistor R2 are connected, the drain of the enhanced PMOS tube M2, the inverting input terminal of the operational amplifier OP1, the inverting input terminal of the operational amplifier OP2 and the emitter of the PNP type transistor Q1 are connected, the drain of the enhanced PMOS tube M3, the non-inverting input terminal of the operational amplifier OP1 and one end of the resistor R1 are connected, the other end of the resistor R1 is connected to the emitter of the PNP type transistor Q2, and the other end of the resistor R2, the base and collector of the PNP type transistor Q1, and the base and collector of the PNP type transistor Q2 are all grounded; The low temperature zone temperature compensation circuit of the temperature adjustment curvature compensation circuit part includes an enhanced PMOS tube MA1, an enhanced NMOS tube MA2, an enhanced PMOS tube MA3, an enhanced NMOS tube MA4, an enhanced PMOS tube MA5, an enhanced PMOS tube MA6, an enhanced NMOS tube MA7, and an enhanced NMOS tube MA8; The sources of the enhanced PMOS tubes MA1, MA3, MA5 and MA6 are all connected to the power supply V DD , the gate of the enhanced PMOS tube MA1 is connected to the output end of the operational amplifier OP2, the gate of the enhanced PMOS tube MA3 is connected to the output end of the operational amplifier OP1, the drain of the enhanced PMOS tube MA1, the drain and gate of the enhanced NMOS tube MA2, and the gate of the enhanced NMOS tube MA4 are connected, the drain of the enhanced PMOS tube MA3, the drain of the enhanced NMOS tube MA4, the drain and gate of the enhanced PMOS tube MA5, and the gate of the enhanced PMOS tube MA6 are connected, the drain of the enhanced PMOS tube MA6, the drain and gate of the enhanced NMOS tube MA7, and the gate of the enhanced NMOS tube MA8 are connected, the drain of the enhanced NMOS tube MA8 is connected to the connection point of the resistor R3 and the resistor RC of the reference voltage output part, and the sources of the enhanced NMOS tubes MA2, MA4, MA7, and MA8 are all grounded; The high temperature zone temperature compensation circuit of the temperature adjustment curvature compensation circuit part includes an enhanced PMOS tube MA9, an enhanced NMOS tube MA10, an enhanced PMOS tube MA11, an enhanced NMOS tube MA12, an enhanced PMOS tube MA13, an enhanced PMOS tube MA14, an enhanced NMOS tube MA15, and an enhanced NMOS tube MA16; The sources of the enhanced PMOS tubes MA9, MA11, MA13 and MA14 are all connected to the power supply V DD The gate of the enhanced PMOS tube MA9 is connected to the output end of the operational amplifier OP1 of the sub-1V bandgap reference source part, the gate of the enhanced PMOS tube MA11 is connected to the output end of the operational amplifier OP2 of the sub-1V bandgap reference source part, the drain of the enhanced PMOS tube MA9, the drain and gate of the enhanced NMOS tube MA10, and the gate of the enhanced NMOS tube MA12 are connected, the drain of the enhanced PMOS tube MA11, the drain of the enhanced NMOS tube MA12, and the enhanced PMOS tube MA13 are connected. The drain and gate of A13 and the gate of the enhanced PMOS tube MA14 are connected, the drain of the enhanced PMOS tube MA14, the drain and gate of the enhanced NMOS tube MA15, and the gate of the enhanced NMOS tube MA16 are connected, the drain of the enhanced NMOS tube MA16 is connected to the connection point of the resistor R3 and the resistor RC of the reference voltage output part, and the sources of the enhanced NMOS tubes MA10, MA12, MA15, and MA16 are all grounded; The reference voltage output part includes a resistor R3, a resistor RC, an enhanced PMOS tube M4 and an enhanced PMOS tube M5; the source electrodes of the enhanced PMOS tube M4 and the enhanced PMOS tube M5 are both connected to the power supply V DD The gate of the enhanced PMOS tube M4 is connected to the output end of the operational amplifier OP1 of the sub-1V bandgap reference source part, the gate of the enhanced PMOS tube M5 is connected to the output end of the operational amplifier OP2 of the sub-1V bandgap reference source part, the drain of the enhanced PMOS tube M4 and the enhanced PMOS tube M5 is connected to one end of the resistor R3, and this connection point is the compensation reference voltage V ref1 Output point; the other end of the resistor R3 is connected to one end of the resistor RC, the other end of the resistor RC is grounded, and the resistor R3 and the resistor RC are connected in series to form an output resistor R OUT , basic reference current I ref Flowing through the output resistor R OUT Generates basic reference voltage V ref At the same time, the resistor RC is also used for low temperature compensation voltage V NTC Or high temperature compensation voltage V PTC The calculation of the final output compensation reference voltage V ref1 .

2. The temperature-adjusting curvature compensation circuit for a concave curve bandgap reference source according to claim 1, characterized in that: The width and length dimensions of the enhanced PMOS tube M1 , the enhanced PMOS tube M2 and the enhanced PMOS tube M3 are width W=2 μm and length L=2 μm.

3. The temperature-adjusting curvature compensation circuit for a concave curve bandgap reference source according to claim 1, characterized in that: The width-to-length ratios of the enhanced PMOS tube MA1, enhanced NMOS tube MA2, enhanced PMOS tube MA5, enhanced PMOS tube MA6 and enhanced NMOS tube MA7 are the same as the width-to-length ratio of the enhanced PMOS tube M1 of the sub-1V bandgap reference source part, the width-to-length ratio of the enhanced PMOS tube MA3 is A1 times the width-to-length ratio of the enhanced PMOS tube MA1, the width-to-length ratio of the enhanced PMOS tube MA4 is A2 times the width-to-length ratio of the enhanced PMOS tube MA1, and the width-to-length ratio of the enhanced PMOS tube MA8 is A3 times the width-to-length ratio of the enhanced PMOS tube MA1.

4. The temperature-adjusting curvature compensation circuit for a concave curve bandgap reference source according to claim 1, characterized in that: The width-to-length ratios of the enhanced PMOS tube MA9, the enhanced NMOS tube MA10, the enhanced PMOS tube MA13, the enhanced PMOS tube MA14 and the enhanced NMOS tube MA15 are the same as the width-to-length ratio of the enhanced PMOS tube M1 of the sub-1V bandgap reference source part, the width-to-length ratio of the enhanced PMOS tube MA11 is B1 times the width-to-length ratio of the enhanced PMOS tube MA1, the width-to-length ratio of the enhanced PMOS tube MA12 is B2 times the width-to-length ratio of the enhanced PMOS tube MA1, and the width-to-length ratio of the enhanced PMOS tube MA16 is B3 times the width-to-length ratio of the enhanced PMOS tube MA1.

5. The temperature-adjusting curvature compensation circuit for a concave curve bandgap reference source according to claim 1, characterized in that: The width-to-length ratio of the enhanced PMOS transistor M4 and the enhanced PMOS transistor M5 is the same as the width-to-length ratio of the enhanced PMOS transistor M1 of the sub-1V bandgap reference source portion.

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