Memory device, operating method of memory device, and memory controller

Abstract

The invention relates to a memory device, an operating method of the memory device, and a memory controller. The storage device may include a memory device and a memory controller. The memory device may include a plurality of physical pages. The memory controller may group the plurality of physical pages into a plurality of pressure physical page groups according to a pressure level of each of the plurality of physical pages, and perform a garbage collection operation on each of the plurality of pressure physical page groups based on the pressure level, the pressure level associated with a read disturb.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0158289, filed on November 15, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a storage device and an operating method thereof. Background Art

[0004] A storage device is a device that stores data under the control of a host device such as a computer or a smart phone. The storage device may include a memory device that stores data and a memory controller that controls the memory device. The memory device is classified into a volatile memory device and a non-volatile memory device.

[0005] In order to improve the reliability of the memory device and extend the service life of the memory device, when the number of failed bits detected exceeds a reference value as a result of a test read operation on a memory block, the memory controller may perform a garbage collection operation of moving valid data stored in the memory block to another memory block. Summary of the invention

[0006] Embodiments of the present disclosure provide a storage device and an operating method thereof, wherein a test read operation is performed only on a physical page group susceptible to read disturbance in a storage block and a partial garbage collection operation is performed on the physical page group according to a result of the test read operation.

[0007] According to an embodiment of the present disclosure, a storage device is provided, which includes: a memory device, including a storage block, the storage block including multiple physical pages; and a memory controller, configured to group the multiple physical pages into multiple stressed physical page groups according to a pressure level of each of the multiple physical pages, and perform a garbage collection operation on each of the multiple stressed physical page groups based on the pressure level, the pressure level being associated with read interference.

[0008] According to another embodiment of the present disclosure, a method for operating a storage device is provided, the method comprising: grouping the multiple physical pages into multiple stressed physical page groups according to the stress level of each of the multiple physical pages included in a storage block of a memory device of the storage device, the stress level being associated with read interference; selecting a target stressed physical page group among the multiple stressed physical page groups based on the stress level; performing a first garbage collection operation on the target stressed physical page group; after performing the first garbage collection operation, receiving an access request from a host, the access request being for another stressed physical page group among the multiple stressed physical page groups that is different from the target stressed physical page group; and performing a second garbage collection operation on the other stressed physical page group after a response to the access request is transmitted to the host.

[0009] According to another embodiment of the present disclosure, a memory controller is provided, which includes: a pressure information storage device, configured to store pressure information about multiple pressure physical page groups, the multiple pressure physical page groups are obtained by grouping multiple physical pages according to the pressure level of each of multiple physical pages included in a storage block, and the pressure level is associated with read interference; a read controller, configured to perform a test read operation on at least one susceptible physical page in a target pressure physical page group among the multiple pressure physical page groups; and a garbage controller, configured to perform a garbage collection operation on each of the multiple pressure physical page groups based on the pressure level. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings; however, the embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the embodiments to those skilled in the art.

[0011] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals refer to the same elements throughout.

[0012] Figure 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0013] Figure 2 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0014] Figure 3 is a diagram illustrating locations of memory blocks and word lines according to an embodiment of the present disclosure.

[0015] Figure 4 is a diagram illustrating a pressure physical page group and pressure information according to an embodiment of the present disclosure.

[0016] Figure 5 is a diagram showing an accessible period of each pressure physical page group.

[0017] Fig. 6A is a diagram illustrating a full garbage collection operation and a partial garbage collection operation according to an embodiment of the present disclosure.

[0018] Figure 6B is a diagram illustrating map update in a partial garbage collection operation according to an embodiment of the present disclosure.

[0019] Figure 6C is a diagram illustrating a stressed physical page group in which a test read is performed and an order in which the test read is performed.

[0020] Figure 7 is a diagram illustrating a test read execution time according to an embodiment of the present disclosure.

[0021] Figure 8 is a flowchart illustrating the operation of a storage device according to an embodiment of the present disclosure.

[0022] Fig. 9 is a flowchart illustrating the operation of a storage device according to an embodiment of the present disclosure.

[0023] Fig.10 is a flowchart illustrating the operation of a storage device according to an embodiment of the present disclosure.

[0024] Fig.11 is a flowchart illustrating the operation of a storage device according to an embodiment of the present disclosure.

[0025] Fig.12 It is shown Figure 1 A diagram of another embodiment of a memory controller is shown. DETAILED DESCRIPTION

[0026] For the purpose of describing the embodiments according to the concept of the present disclosure, the specific structural or functional description disclosed herein is merely illustrative. The embodiments according to the concept of the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0027] Figure 1 is a diagram illustrating a storage device 50 according to an embodiment of the present disclosure.

[0028] Reference Figure 1, the memory device 50 may include a memory device 100 and a memory controller 200 that controls the operation of the memory device 100. The memory device 50 may be a device that stores data under the control of a host.

[0029] The storage device 50 may be manufactured as any of various types of storage devices according to a communication scheme with the host. For example, the storage device 50 may be configured as any of the following storage devices: an SSD, a multimedia card in the form of an MMC and an eMMC, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a peripheral component interconnect (PCI) card type storage device, a high-speed PCI (PCI-e or PCIe) card type storage device, a compact flash (CF) card, a smart media card (SMC), and a memory stick.

[0030] The memory device 50 may be manufactured as any of various package types. For example, the memory device 50 may be manufactured as any of various package types such as package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0031] The memory device 100 may store data. The memory device 100 may operate under the control of the memory controller 200. The memory device 100 may include a plurality of memory blocks. A memory block may include a plurality of memory cells for storing data. Memory cells connected to the same word line may constitute a physical page. A memory block may include a plurality of physical page groups. Each of the plurality of physical page groups may include at least one physical page.

[0032] In an embodiment, the memory device 100 may include a volatile memory and a nonvolatile memory.

[0033] The memory device 100 may receive a command and an address from the memory controller 200, and access an area selected by the address in the storage area. That is, the memory device 100 may perform an operation indicated by the command on the area selected by the address. For example, the memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. In a programming operation, the memory device 100 may program data in an area selected by the address. In a read operation, the memory device 100 may read data stored in an area selected by the address. In an erase operation, the memory device 100 may erase data stored in an area selected by the address.

[0034] The memory controller 200 may control the overall operations of the memory device 50 .

[0035] In an embodiment, the memory controller 200 may receive data and a logical address input from a host, and convert the logical address into a physical address representing an address of a memory cell included in the memory device 100 where data is to be stored.

[0036] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, an erase operation, etc. in response to a request from a host. In a program operation, the memory controller 200 may provide a program command, a physical address, and data to the memory device 100. In a read operation, the memory controller 200 may provide a read command and a physical address to the memory device 100. In an erase operation, the memory controller 200 may provide an erase command and a physical address to the memory device 100.

[0037] In an embodiment, the memory controller 200 may include a stress information storage device 210 , a read controller 220 , and a garbage controller 230 .

[0038] The pressure information storage device 210 may store pressure information about a plurality of pressure physical page groups obtained by grouping a plurality of physical pages according to a pressure level of each of a plurality of physical pages included in a memory block susceptible to read disturbance. The pressure level may be predetermined by a test during the manufacturing process of the memory device 100. The determined pressure level may be set in firmware. The pressure level may be determined based on the physical location of the physical page in the memory block.

[0039] The read controller 220 may perform a test read operation on at least one susceptible physical page in a target stress physical page group among the plurality of stress physical page groups. Whenever the read count of the storage block reaches a predetermined test read count, the read controller 220 may perform a test read operation. Specifically, the read controller 220 may perform a test read operation on the stress physical page group included in the storage block based on the stress information, and detect a fail bit from the result of the test read operation. The read controller 220 may perform a test read operation on the plurality of stress physical page groups individually in the order of stress levels from high to low.

[0040] The garbage controller 230 may perform a garbage collection operation on each of the plurality of pressure physical page groups in order of pressure level from high to low. The garbage collection operation may be a partial garbage collection operation that moves only valid data stored in the target pressure physical page group instead of all valid data stored in the storage block to another storage area.

[0041] Figure 2 is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0042] Reference Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0043] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be connected to the address decoder 121 through the row lines RL. The plurality of memory blocks BLK1 to BLKz may be connected to the read and write (read / write) circuit 123 through the bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells.

[0044] Each of the memory cells of the memory device 100 may be configured as a single level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a triple level cell (TLC) storing three bits of data, or a quad level cell (QLC) storing four bits of data.

[0045] The peripheral circuit 120 may include an address decoder 121 , a voltage generator 122 , a read / write circuit 123 , a data input and output (input / output) circuit 124 , and a sensing circuit 125 .

[0046] The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation.

[0047] The address decoder 121 may be connected to the memory cell array 110 through row lines RL. The row lines RL may include a drain selection line, a word line, a source selection line, and a common source line.

[0048] The address decoder 121 may operate under the control of the control logic 130. The address decoder 121 may receive an address ADDR from the control logic 130.

[0049] The address decoder 121 may decode the block address in the received address ADDR. The address decoder 121 may select at least one memory block among the memory blocks BLK1 to BLKz according to the decoded block address. The address decoder 121 may decode the row address in the received address ADDR. The address decoder 121 may select at least one word line among the word lines of the selected memory block according to the decoded row address. The address decoder 121 may apply the operating voltage Vop supplied from the voltage generator 122 to the selected word line.

[0050] In a programming operation, the address decoder 121 may apply a program voltage to a selected word line, and apply a pass voltage having a level lower than the program voltage to unselected word lines. In a program verification operation, the address decoder 121 may apply a verification voltage to a selected word line, and apply a verification pass voltage having a level higher than the verification voltage to unselected word lines. In a read operation, the address decoder 121 may apply a read voltage to a selected word line, and apply a read pass voltage having a level higher than the read voltage to unselected word lines. In an erase operation, the address decoder 121 may apply a ground voltage to a word line of a selected memory block.

[0051] According to an embodiment of the present disclosure, an erase operation of the memory device 100 may be performed in units of memory blocks. An address ADDR input to the memory device 100 in the erase operation may include a block address.

[0052] According to an embodiment of the present disclosure, the address decoder 121 may decode the column address in the received address ADDR. The decoded column address may be transmitted to the read / write circuit 123. The address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

[0053] The voltage generator 122 may generate a plurality of operating voltages Vop by using an external power supply voltage supplied to the memory device 100. The voltage generator 122 may operate under the control of the control logic 130.

[0054] In an embodiment, the voltage generator 122 may generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 may be used as an operating voltage of the memory device 100.

[0055] In an embodiment, the voltage generator 122 may generate a plurality of operating voltages Vop by using an external power supply voltage or an internal power supply voltage. The voltage generator 122 may generate various voltages required in the memory device 100. For example, the voltage generator 122 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of unselect read voltages.

[0056] In order to generate a plurality of operating voltages Vop having various voltage levels, the voltage generator 122 may include a plurality of pumping capacitors receiving an internal power supply voltage. The voltage generator 122 may generate a plurality of operating voltages Vop by selectively enabling a plurality of pumping capacitors under the control of the control logic 130. The plurality of operating voltages generated by the voltage generator 122 may be supplied to the memory cell array 110 through the address decoder 121.

[0057] The read / write circuit 123 may include first to mth page buffers PB1 to PBm. The first to mth page buffers PB1 to PBm may be connected to the memory cell array 110 through first to mth bit lines BL1 to BLm, respectively. The first to mth page buffers PB1 to PBm may operate under the control of the control logic 130.

[0058] The first to mth page buffers PB1 to PBm may communicate data DATA with the data input / output circuit 124. In a program operation, the first to mth page buffers PB1 to PBm may receive data DATA to be stored through the data input / output circuit 124 and the data lines DL.

[0059] In a programming operation, when a programming voltage is applied to a selected word line, the first to mth page buffers PB1 to PBm may transmit data DATA received through the data input / output circuit 124 to the selected memory cell through the bit lines BL1 to BLm. According to the transmitted data DATA, the memory cell of the selected page may be programmed. The threshold voltage of the memory cell connected to the bit line to which a programming enable voltage (e.g., a ground voltage) is applied may be increased. The threshold voltage of the memory cell connected to the bit line to which a programming inhibit voltage (e.g., a power supply voltage) is applied may be maintained. In a programming verification operation, the first to mth page buffers PB1 to PBm may read the data DATA stored in the selected memory cell from the memory cell through the bit lines BL1 to BLm.

[0060] In a read operation, the read / write circuit 123 may read data DATA from memory cells of a selected page through the bit lines BL1 to BLm and store the read data DATA in the first to mth page buffers PB1 to PBm.

[0061] In an erase operation, the read / write circuit 123 may float the bit lines BL1 to BLm. In an embodiment, the read / write circuit 123 may include a column selection circuit.

[0062] The data input / output circuit 124 may be connected to the first to mth page buffers PB1 to PBm through the data lines DL The data input / output circuit 124 may operate under the control of the control logic 130 .

[0063] The data input / output circuit 124 may include a plurality of input / output buffers (not shown) that receive input data DATA. In a program operation, the data input / output circuit 124 may receive data DATA to be stored from an external controller (not shown). In a read operation, the data input / output circuit 124 may output data DATA transmitted from the first to mth page buffers PB1 to PBm included in the read / write circuit 123 to the external controller.

[0064] In a read operation or a verification operation, the sensing circuit 125 may generate a reference current in response to an enable bit VRYBIT generated by the control logic 130 and output a pass signal PASS / fail signal FAIL to the control logic 130 by comparing a sensing voltage VPB received from the read / write circuit 123 with a reference voltage generated by the reference current.

[0065] The control logic 130 may be connected to the address decoder 121, the voltage generator 122, the read / write circuit 123, the data input / output circuit 124, and the sensing circuit 125. The control logic 130 may control general operations of the memory device 100. The control logic 130 may operate in response to a command CMD transmitted from an external device.

[0066] The control logic 130 may control the peripheral circuit 120 by generating several signals in response to the command CMD and the address ADDR. For example, the control logic 130 may generate an operation signal OPSIG, an address ADDR, a read / write circuit control signal PBSIGNALS, and an enable bit VRYBIT in response to the command CMD and the address ADDR. The control logic 130 may output the operation signal OPSIG to the voltage generator 122, the address ADDR to the address decoder 121, the read / write circuit control signal PBSIGNALS to the read / write circuit 123, and the enable bit VRYBIT to the sensing circuit 125. Moreover, the control logic 130 may determine whether the verification operation is passed or failed in response to the pass signal PASS / fail signal FAIL output by the sensing circuit 125.

[0067] Figure 3 is a diagram illustrating locations of memory blocks and word lines according to an embodiment of the present disclosure.

[0068] Reference Figure 3, the memory block BLK may include a plurality of sub-blocks S1 and S2 stacked in a 3D structure. Each of the plurality of sub-blocks S1 and S2 may include at least one word line. For example, the first sub-block S1 may include a first word line WL1 to a 120th word line WL120. The second sub-block S2 may include a 121st word line WL121 to a 240th word line WL240. The number of word lines included in the memory block BLK is not limited to the present embodiment. Memory cells connected to the same word line may constitute one physical page.

[0069] The pressure level of each physical page can be determined individually based on test results during the manufacturing process.

[0070] Figure 4 is a diagram illustrating a pressure physical page group and pressure information according to an embodiment of the present disclosure.

[0071] The stress physical page group can be determined based on the stress level of each physical page susceptible to read disturbance tested during the manufacturing process of the memory device. In an embodiment, the stress level can be determined based on the physical position of each of the multiple physical pages included in the memory block. This is because, depending on the physical position of the physical page, the characteristics of the memory cells are different from each other, and the effects caused by the read disturbance are different from each other.

[0072] exist Figure 4 In the embodiment, a plurality of physical pages included in a storage block may be grouped into at least one stress physical page group. The number of stress physical page groups included in a storage block may be at least one. The number of physical pages included in each stress physical page group may be at least one. In an embodiment, the number of stress physical page groups included in each storage block may be the same. In an embodiment, for each storage block, the number of stress physical page groups included in each storage block may be different from each other. In an embodiment, the number of physical pages included in each stress physical page group may be the same. In an embodiment, for each stress physical page group, the number of physical pages included in each stress physical page group may be different from each other. At least two stress physical page groups among the plurality of stress physical page groups may include different numbers of physical pages from each other.

[0073] For example, a memory block may include a plurality of physical pages. The plurality of physical pages may include memory cells connected to the first word line WL1 to the second hundred and fourth cross line WL240. The plurality of physical pages may be grouped into a first stress physical page group SPPG1 to a fourth stress physical page group SPPG4. In a test during the manufacturing process, a physical page A whose number of failed bit detections (hereinafter referred to as stress level) exceeds the first stress reference Stress Ref1 may be set to the first stress physical page group SPPG1. A physical page D whose stress level is lower than the first stress reference Stress Ref1 and higher than the second stress reference Stress Ref2 may be set to the second stress physical page group SPPG2. Physical pages B and E whose stress levels are lower than the second stress reference Stress Ref2 and higher than the third stress reference Stress Ref3 may be set to the third stress physical page group SPPG3. Physical pages C and F whose stress levels are lower than the third stress reference Stress Ref3 and higher than the fourth stress reference Stress Ref4 may be set to the fourth stress physical page group SPPG4.

[0074] The test read operation may be performed separately for each stress physical page group. The test read operation may be performed sequentially in order of stress levels from high to low. For example, the test read operation may be performed separately in order from the first stress physical page group SPPG1 to the fourth stress physical page group SPPG4.

[0075] The stress information may include a plurality of stress physical page groups obtained by grouping a plurality of physical pages according to a stress level of each of a plurality of physical pages included in a memory block susceptible to read disturbance.

[0076] Figure 5 is a diagram showing an accessible period of each pressure physical page group.

[0077] Reference Figure 4 and Figure 5 , the memory block may include first to fourth stress physical page groups SPPG1 to SPPG4.

[0078] At time t1, the first pressure physical page group SPPG1 with the highest pressure level may reach the garbage collection trigger reference pressure level, and a partial garbage collection operation of moving valid data stored in the first pressure physical page group SPPG1 to another storage block may be performed. In an embodiment, the garbage collection trigger reference pressure level is the same for each pressure physical page group. In an embodiment, the garbage collection trigger reference pressure level may be different for each pressure physical page group. The second pressure physical page group SPPG2 to the fourth pressure physical page group SPPG4 that have not reached the garbage collection trigger reference pressure level may be accessible. That is, when the storage device receives an access request for the second pressure physical page group SPPG2 to the fourth pressure physical page group SPPG4 from the host, the storage device may provide a response to the access request to the host.

[0079] At time t2, the second pressure physical page group SPPG2 with the second highest pressure level can reach the garbage collection trigger reference pressure level, and a partial garbage collection operation of moving valid data stored in the second pressure physical page group SPPG2 to another storage block can be performed. At time t2, the third pressure physical page group SPPG3 and the fourth pressure physical page group SPPG4 that have not reached the garbage collection trigger reference pressure level can be accessible.

[0080] At time t3, the third pressure physical page group SPPG3 with the third highest pressure level can reach the garbage collection trigger reference pressure level, and a partial garbage collection operation of moving valid data stored in the third pressure physical page group SPPG3 to another storage block can be performed. The fourth pressure physical page group SPPG4 that has not reached the garbage collection trigger reference pressure level can be accessible.

[0081] At time t4, the fourth stress physical page group SPPG4 with the fourth highest stress level can reach the garbage collection trigger reference stress level, and a partial garbage collection operation of moving valid data stored in the fourth stress physical page group SPPG4 to another storage block can be performed. At time t4, the garbage collection operation of all stress physical page groups in the storage block can be completed.

[0082] Fig. 6A is a diagram illustrating a full garbage collection operation and a partial garbage collection operation according to an embodiment of the present disclosure.

[0083] Reference Fig. 6A , the first memory block BLK1 may include first to fourth stress physical page groups SPPG1 to SPPG4.

[0084] In the case of a full garbage collection operation, when the number of fail bits detected in a test read operation on the first stress physical page group SPPG1 exceeds a reference value, all valid data stored in the first storage block BLK1 including the first stress physical page group SPPG1 may be moved to the second storage block BLK2.

[0085] In case of a partial garbage collection operation, when the number of fail bits detected in a test read operation on the first stress physical page group SPPG1 exceeds a reference value, only valid data stored in the first stress physical page group SPPG1 may be moved to the second memory block BLK2 .

[0086] Compared with the complete garbage collection operation, in the case of the partial garbage collection operation, only valid data stored in the first stress physical page group SPPG1 is moved to the second storage block BLK2, so the triggering time of the garbage collection operation can be shortened.

[0087] In addition, in the case of the second to fourth stress physical page groups SPPG2 to SPPG4, the second to fourth stress physical page groups SPPG2 to SPPG4 are accessible. Therefore, unnecessary write operations due to garbage collection can be reduced and the write amplification index (WAI) can be improved.

[0088] Figure 6B is a diagram illustrating map update in a partial garbage collection operation according to an embodiment of the present disclosure.

[0089] Reference Figure 6B , the physical addresses of the first stress physical page group SPPG1 to the fourth stress physical page group SPPG4 included in the first storage block BLK1 may be the first physical address PA 1 to the fourth physical address PA 4, respectively. The logical address to physical address mapping L2P Map may include mapping information between the first logical address LA 1 to the fourth logical address LA 4 and the first physical address PA1 to the fourth physical address PA 4. The physical pages corresponding to the first physical address PA 1 to the fourth physical address PA 4 may be valid pages storing valid data.

[0090] As reference Fig. 6A As described above, when a partial garbage collection operation is performed to move only valid data stored in the first pressure physical page group SPPG1 to the second storage block BLK2, a portion of the logical address to physical address mapping L2P Map may be updated.

[0091] For example, the physical address mapped to the first logical address LA1 may be changed from the first physical address PA1 of the first memory block BLK1 to the fifth physical address PA5 of the second memory block BLK2. Data stored in a physical page corresponding to the first physical address PA1 may be invalidated. Data stored in a physical page corresponding to the fifth physical address PA5 may be validated.

[0092] Therefore, when the storage device receives an access request to the first logical address LA 1 after performing a partial garbage collection operation on only the first stressed physical page group SPPG1, the storage device may access the second storage block BLK2 with reference to the fifth physical address PA 5. When the storage device receives an access request to the second logical address LA 2 to the fourth logical address LA 4, the storage device may access the first storage block BLK1 with reference to the second physical address PA 2 to the fourth physical address PA 4.

[0093] Figure 6C is a diagram illustrating a stressed physical page group in which a test read is performed and an order in which the test read is performed.

[0094] Reference Figure 6C , the first memory block BLK1 may include a first stress physical page group SPPG1 to a fourth stress physical page group SPPG4. The order of stress levels from high to low is the first stress physical page group SPPG1 to the fourth stress physical page group SPPG4. The stress physical page group may include at least one susceptible physical page. The susceptible physical page may be a physical page that is most susceptible to read disturbance in a test during the manufacturing process of the memory device among a plurality of physical pages included in each stress physical page group. The physical pages included in each stress physical page group may have similar characteristics of being susceptible to read disturbance.

[0095] For example, the first stress physical page group SPPG1 may include the first vulnerable physical page Weak PP 1 to the third vulnerable physical page Weak PP 3. The second stress physical page group SPPG2 may include the fourth vulnerable physical page Weak PP 4 to the sixth vulnerable physical page Weak PP 6. The third stress physical page group SPPG3 may include the seventh vulnerable physical page Weak PP 7 to the ninth vulnerable physical page Weak PP 9. The fourth stress physical page group SPPG4 may include the tenth vulnerable physical page Weak PP 10 and the eleventh vulnerable physical page Weak PP11.

[0096] A test read operation may be performed separately for each stress physical page group in order from high to low stress levels. For example, at time a1, the read count of the storage block may reach the first test read count, and a test read operation may be performed on the target stress physical page group of the first storage block BLK1. The first stress physical page group SPPG1 with the highest stress level among the multiple stress physical page groups included in the first storage block BLK1 may be selected as the target stress physical page group. A test read operation may be performed on each of the first susceptible physical page Weak PP 1 to the third susceptible physical page Weak PP 3 that are most susceptible to read disturbance among the multiple physical pages included in the first stress physical page group SPPG1. When the number of failed bits detected in each test read operation exceeds a reference value, a partial garbage collection operation may be performed to move valid data stored in the first stress physical page group SPPG1 to another storage block. The logical address of the valid data stored in the first stress physical page group SPPG1 may be remapped to the physical address of another storage block, and the physical address of the first stress physical page group SPPG1 may be invalidated.

[0097] At time a2, after performing a partial garbage collection operation on the first pressure physical page group SPPG1, a second pressure physical page group SPPG2 with the second highest pressure level among the multiple pressure physical page groups included in the first storage block BLK1 can be selected as the target pressure physical page group. A test read operation can be performed on the second pressure physical page group SPPG2 selected as the target pressure physical page group. A test read operation can be performed on each of the fourth vulnerable physical page Weak PP 4 to the sixth vulnerable physical page Weak PP 6 included in the second pressure physical page group SPPG2. When the number of failed bits detected in each test read operation exceeds a reference value, a partial garbage collection operation of moving valid data stored in the second pressure physical page group SPPG2 to another storage block can be performed. The logical address of the valid data stored in the second pressure physical page group SPPG2 can be remapped to the physical address of another storage block, and the physical address of the second pressure physical page group SPPG2 can be invalidated.

[0098] After performing a partial garbage collection operation on the second stress physical page group SPPG2, a third stress physical page group SPPG3 having the third highest stress level among the multiple stress physical page groups included in the first storage block BLK1 may be selected as a target stress physical page group. A test read operation may be performed on the third stress physical page group SPPG3 selected as the target stress physical page group. A test read operation may be performed on each of the seventh vulnerable physical page Weak PP 7 to the ninth vulnerable physical page Weak PP 9 included in the third stress physical page group SPPG3. When the number of failed bits detected in each test read operation is a reference value or less, no test read operation may be performed on the first storage block BLK1 until the read count of the storage block reaches the time a3 of the second test read count.

[0099] At time a3, the read count of the storage block can reach the second test read count, and a test read operation can be performed on the target stress physical page group of the first storage block BLK1. The third stress physical page group SPPG3 with the third highest stress level among the multiple stress physical page groups included in the first storage block BLK1 can be selected as the target stress physical page group. The third stress physical page group SPPG3 can be the stress physical page group with the highest stress level among the multiple stress physical page groups that do not perform any partial garbage collection operation in the first storage block BLK1 at time a3. A test read operation can be performed on the third stress physical page group SPPG3 selected as the target stress physical page group. A test read operation can be performed on each of the seventh vulnerable physical page Weak PP 7 to the ninth vulnerable physical page Weak PP 9 included in the third stress physical page group SPPG3. When the number of failed bits detected in each test read operation exceeds a reference value, a partial garbage collection operation of moving valid data stored in the third stress physical page group SPPG3 to another storage block can be performed. Logical addresses of valid data stored in the third stress physical page group SPPG3 may be remapped to physical addresses of another memory block, and physical addresses of the third stress physical page group SPPG3 may be invalidated.

[0100] After performing a partial garbage collection operation on the third stress physical page group SPPG3, a fourth stress physical page group SPPG4 having the fourth highest stress level among the multiple stress physical page groups included in the first storage block BLK1 may be selected as a target stress physical page group. A test read operation may be performed on the fourth stress physical page group SPPG4 selected as the target stress physical page group. A test read operation may be performed on each of the tenth vulnerable physical page Weak PP 10 and the eleventh vulnerable physical page Weak PP 11 included in the fourth stress physical page group SPPG4. When the number of failed bits detected in each test read operation is a reference value or less, no test read operation may be performed on the first storage block BLK1 until the read count of the storage block reaches the time a4 of the third test read count.

[0101] At time a4, the read count of the storage block can reach the third test read count, and a test read operation can be performed on the target stress physical page group of the first storage block BLK1. The fourth stress physical page group SPPG4 can be selected as the target stress physical page group. A test read operation can be performed on the fourth stress physical page group SPPG4 selected as the target stress physical page group. A test read operation can be performed on each of the tenth vulnerable physical page Weak PP 10 and the eleventh vulnerable physical page Weak PP 11 included in the fourth stress physical page group SPPG4. When the number of failed bits detected in each test read operation exceeds a reference value, a partial garbage collection operation of moving valid data stored in the fourth stress physical page group SPPG4 to another storage block can be performed. The logical address of the valid data stored in the fourth stress physical page group SPPG4 can be remapped to the physical address of another storage block, and the physical address of the fourth stress physical page group SPPG4 can be invalidated.

[0102] Figure 7 is a diagram illustrating a test read execution time according to an embodiment of the present disclosure.

[0103] Reference Figure 7 When the read count of the memory block reaches a predetermined test read count, a test read operation may be performed. The test read count value may be set differently according to the performance, operating environment, or service life of the memory device.

[0104] For example, when the read count of the storage block reaches the first test read count Count 1, the first test read operation Test Read 1 may be performed. When the read count of the storage block reaches the second test read count Count 2, the second test read operation Test Read 2 may be performed. When the read count of the storage block reaches the third test read count Count 3, the third test read operation Test Read 3 may be performed. The first test read count Count 1 may be set to 750k (i.e., 750,000), the second test read count Count 2 may be set to 800k, and the third test read count Count 3 may be set to 850k. The first step count Step Count 1 as the difference between the first test read count Count 1 and the second test read count Count 2 may be 50k. The second step count Step Count 2 as the difference between the second test read count Count 2 and the third test read count Count 3 may be 50k. Each step count may be set to the same value. In another embodiment, the step counts may be set to be different from each other.

[0105] Figure 8 is a flowchart illustrating the operation of a storage device according to an embodiment of the present disclosure.

[0106] Reference Figure 8 In S801, the storage device may perform a test read operation on a plurality of stressed physical page groups in order of stress levels from high to low among the stressed physical page groups included in the storage block. Specifically, the storage device may perform a test read operation on at least one susceptible physical page in the stressed physical page group.

[0107] In S803, the storage device may perform a garbage collection operation of moving valid data stored in the stress physical page group based on a result obtained by comparing the number of fail bits detected in the test read operation with a reference value. For example, the storage device may move valid data stored in the stress physical page group whose number of fail bits exceeds the reference value to another storage block.

[0108] Fig. 9 is a flowchart illustrating the operation of a storage device according to an embodiment of the present disclosure.

[0109] Reference Fig. 9In S901, the storage device may determine whether the read count of the storage block is equal to a predetermined test read count. When the read count is equal to the test read count (S901, yes) as a result of the determination, the storage device may proceed to S903, and when the read count is different from the test read count (S901, no), the storage device may end the operation.

[0110] In S903, the memory device may perform a test read operation on a susceptible physical page in the stressed physical page group. The susceptible physical page may be a physical page that is most susceptible to read disturbance in a test during the manufacturing process of the memory device among multiple physical pages included in the stressed physical page group.

[0111] In S905, the storage device may determine whether the number of failed bits detected in the test read operation exceeds a reference value. When the number of failed bits exceeds the reference value (S905, yes), the storage device may proceed to S907, and when the number of failed bits is the reference value or less (S905, no), the storage device may end the operation.

[0112] In S907, the storage device may perform a garbage collection operation to move valid data stored in the stressed physical page group to another storage block. The stressed physical page group in the storage block that has not performed any garbage collection operation may be accessible.

[0113] Fig.10 is a flowchart illustrating the operation of a storage device according to an embodiment of the present disclosure.

[0114] Reference Fig.10 , in S1001 , each of n and m may be set to 1 (n=1 and m=1).

[0115] In S1003 , the storage device may perform a read operation on the storage block.

[0116] In S1005, the storage device may determine whether the read count of the storage block is equal to the nth test read count. When the read count is equal to the nth test read count (S1005, yes), the storage device may proceed to S1007, and when the read count is different from the nth test read count (S1005, no), the storage device may proceed to S1003.

[0117] In S1007, the storage device may perform a test read operation on the mth stressed physical page group. The mth stressed physical page group may be a physical page group with an mth highest stress level among a plurality of stressed physical page groups included in the storage block.

[0118] In S1009, the storage device may determine whether the number of failed bits detected in the test read operation exceeds a reference value. When the number of failed bits exceeds the reference value as a result of the determination (S1009, Yes), the storage device may proceed to S1011, and when the number of failed bits is the reference value or less as a result of the determination (S1009, No), the storage device may proceed to S1015.

[0119] In S1011, the storage device may perform a garbage collection operation to move valid data stored in the mth stress physical page group to another storage block. The garbage collection operation performed on the mth stress physical page group may be a partial garbage collection operation.

[0120] In S1013, the storage device may determine whether the garbage collection operation for all stress physical page groups included in the storage block has been completed. When the garbage collection operation for all stress physical page groups is completed (S1013, yes), the storage device may end the operation, and when there is at least one stress physical page group for which the garbage collection operation has not been completed (S1013, no), the storage device may proceed to S1017.

[0121] In S1015 , n may be increased by 1 (ie, n=n+1).

[0122] In S1017 , m may be increased by 1 (ie, m=m+1).

[0123] Fig.11 is a flowchart illustrating the operation of a storage device according to an embodiment of the present disclosure.

[0124] Reference Fig.11 , in S1101 , the storage device may perform a garbage collection operation on the mth pressure physical page group, where m is a natural number of 1 or greater.

[0125] In S1103, the storage device may determine whether there is a queued access request for the (m+1)th pressure physical page group. When, as a result of the determination, there is a queued access request (S1103, yes), the storage device may proceed to S1107, and when, as a result of the determination, there is no queued access request (S1103, no), the storage device may proceed to S1105.

[0126] In S1105 , the storage device may perform a garbage collection operation on the (m+1)th pressure physical page group.

[0127] In S1107 , the storage device may access the (m+1)th stressed physical page group.

[0128] Fig.12 It is shown Figure 1A diagram of another embodiment of a memory controller is shown.

[0129] Reference Fig.12 , the memory controller 1000 may be connected to a host and a memory device. The memory controller 1000 may access the memory device in response to a request from the host.

[0130] Fig.12 The memory controller 1000 shown may be Figure 1 A memory controller 200 is shown.

[0131] The memory controller 1000 may control a write operation, a read operation, an erase operation, and a background operation of the memory device. The memory controller 1000 may provide an interface between the memory device and a host. The memory controller 1000 may drive firmware for controlling the memory device.

[0132] The memory controller 1000 may include a processor 1010 , a random access memory (RAM) 1020 , an error correction code (ECC) engine 1030 , a host interface 1040 , a buffer controller 1050 , a memory interface 1060 , and a bus 1070 .

[0133] The bus 1070 may provide a channel between the components of the memory controller 1000 .

[0134] The processor 1010 may control the general operation of the memory controller 1000 and perform logic operations. The processor 1010 may communicate with an external host through the host interface 1040 and communicate with a memory device through the memory interface 1060. Also, the processor 1010 may communicate with the RAM 1020 through the buffer controller 1050. The processor 1010 may control the operation of the memory device using the RAM 1020 as a working memory, a cache memory, or a buffer memory.

[0135] The processor 1010 may convert a logical block address (LBA) provided by the host into a physical block address (PBA). The flash translation layer (FTL) may receive the LBA and convert the LBA into the PBA using a mapping table.

[0136] When the memory device is a nonvolatile memory, the processor 1010 may randomize data received from the host. The randomized data may be provided to the memory device for programming.

[0137] The processor 1010 may derandomize the data received from the memory device in a read operation. For example, the processor 1010 may derandomize the data received from the memory device using a derandomization seed and output the derandomized data to the host.

[0138] In an embodiment, the processor 1010 may perform randomization and de-randomization through driver software or firmware.

[0139] In an embodiment, the processor 1010 may include a Figure 1 The read controller 1012 and the garbage controller 1011. The read controller 1012 may perform a test read operation on a stress physical page group included in a memory block based on stress information, and detect a fail bit from a result of the test read operation.

[0140] When the number of failed bits detected in the test read operation exceeds a reference value, the garbage controller 1011 may perform a partial garbage collection operation of moving valid data stored in the stressed physical page group to another memory block.

[0141] The RAM 1020 is a volatile memory and may be used as a working memory, a cache memory, or a buffer memory of the processor 1010. The RAM 1020 may store codes and commands executed by the processor 1010. The RAM 1020 may store data processed by the processor 1010. The RAM 1020 may include a static RAM (SRAM) or a dynamic RAM (DRAM).

[0142] In an embodiment, RAM 1020 may include Figure 1 The pressure information storage device 1021 can store pressure information, where the pressure information includes pressure physical page groups included in the storage block and pressure levels of the pressure physical page groups.

[0143] The ECC engine 1030 may perform error correction. The ECC engine 1030 may perform error correction code (ECC) encoding on data to be written to the memory device through the memory interface 1060. The ECC-encoded data may be transmitted to the memory device through the memory interface 1060. The ECC engine 1030 may perform ECC decoding on data received from the memory device through the memory interface 1060. The ECC engine 1030 may be included in the memory interface 1060 as a component of the memory interface 1060.

[0144] The host interface 1040 may communicate with an external host under the control of the processor 1010. The host interface 1040 may communicate with the host using at least one of various communication standards or protocols such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), and Universal Flash Storage (UFS).

[0145] The buffer controller 1050 may control the RAM 1020 under the control of the processor 1010. The memory interface 1060 may communicate commands, addresses, and data with a memory device through a channel under the control of the processor 1010.

[0146] The processor 1010 may control the operation of the memory controller 1000 by using the code. The processor 1010 may load the code from a nonvolatile memory device (eg, a read only memory (ROM)) provided in the memory controller 1000. In another example, the processor 1010 may load the code from the memory device through the memory interface 1060.

[0147] The bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus. The data bus may be configured to transmit data in the memory controller 1000, and the control bus may be configured to transmit control information such as commands and addresses in the memory controller 1000. The data bus and the control bus are separated from each other and may not interfere or affect each other. The data bus may be connected to the host interface 1040, the buffer controller 1050, the ECC engine 1030, and the memory interface 1060. The control bus may be connected to the host interface 1040, the processor 1010, the buffer controller 1050, and the memory interface 1060.

[0148] According to an embodiment of the present disclosure, a storage device and an operating method thereof may be provided, wherein a test read operation is performed only on a stressed physical page group susceptible to read disturbance in a storage block and a garbage collection operation is performed on the stressed physical page group according to the result of the test read operation.

[0149] Although the embodiments of the present disclosure have been shown and described with reference to the specific embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0150] In the above-described embodiments, all operations may be selectively performed or some operations may be omitted. In each embodiment, the operations are not necessarily performed in the order described and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0151] Embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, those terms are only used to describe embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and many modifications can be made within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications can be made based on the technical scope of the present disclosure. In addition, the embodiments can be combined to form additional embodiments.

Claims

1. A storage device, comprising: A memory device comprising a memory block, wherein the memory block comprises a plurality of physical pages; as well as A memory controller groups the plurality of physical pages into a plurality of stressed physical page groups according to a stress level of each of the plurality of physical pages, and performs a garbage collection operation on each of the plurality of stressed physical page groups based on the stress level, the stress level being associated with read disturbance.

2. The storage device according to claim 1, wherein: The memory controller performs a test read operation on at least one susceptible physical page in a target stress physical page group among the multiple stress physical page groups, and when the number of failed bits detected in the test read operation exceeds a reference value, the memory controller performs a garbage collection operation of moving valid data stored in the target stress physical page group to another storage block.

3. The storage device according to claim 2, wherein: The memory controller performs a garbage collection operation on each of the plurality of pressure physical page groups in order of the pressure level from high to low, and The memory controller: selecting a first pressure physical page group with the highest pressure level among the plurality of pressure physical page groups as the target pressure physical page group, and When the garbage collection operation is performed on the first stressed physical page group, a second stressed physical page group having the second highest stress level among the plurality of stressed physical page groups is selected as the target stressed physical page group.

4. The storage device according to claim 3, wherein: After performing the garbage collection operation on the first stressed physical page group, the memory controller accesses the second stressed physical page group when the memory controller receives an access request to the second stressed physical page group from a host before performing the garbage collection operation on the second stressed physical page group.

5. The storage device according to claim 2, wherein: The at least one susceptible physical page includes a physical page most susceptible to the read disturbance among a plurality of physical pages included in the target stress physical page group, and is predetermined during manufacturing of the memory device to be set in firmware.

6. The storage device according to claim 1, wherein: When the read count of the storage block reaches a first test read count, the memory controller performs a test read operation on a target stress physical page group among the multiple stress physical page groups, and when the number of fail bits detected in the test read operation is a reference value or less and when the read count of the storage block reaches a second test read count, the memory controller re-executes the test read operation on the target stress physical page group.

7. The storage device according to claim 1, wherein: The plurality of stressed physical page groups are predetermined during the manufacturing process of the memory device to be set in firmware.

8. The storage device according to claim 1, wherein: The number of the plurality of stressed physical page groups included in the memory block is equal to the number of stressed physical page groups included in another memory block different from the memory block.

9. The storage device according to claim 6, wherein: The first test read count is greater than a difference between the first test read count and the second test read count.

10. The storage device according to claim 1, wherein: At least two stressed physical page groups among the plurality of stressed physical page groups include different numbers of physical pages.

11. The storage device according to claim 6, wherein: The memory controller repeatedly performs the test read operation on the plurality of stressed physical page groups until a garbage collection operation on each of the plurality of stressed physical page groups is completed.

12. A method for operating a storage device, the method comprising: grouping a plurality of physical pages included in a memory block of a memory device of the memory device into a plurality of stressed physical page groups according to a stress level of each of the plurality of physical pages included in a memory block of the memory device, the stress level being associated with read disturbance; selecting a target pressure physical page group among the plurality of pressure physical page groups based on the pressure level; performing a first garbage collection operation on the target pressure physical page group; After performing the first garbage collection operation, receiving an access request from a host, the access request being for another stressed physical page group among the plurality of stressed physical page groups that is different from the target stressed physical page group; as well as After a response to the access request is transmitted to the host, a second garbage collection operation is performed on the other stressed physical page group.

13. The method according to claim 12, further comprising: Before performing the first garbage collection operation, performing a test read operation on at least one susceptible physical page in the target pressure physical page group, The performing of the first garbage collection operation includes: when the number of failed bits detected in the test read operation exceeds a reference value, moving valid data stored in the target stress physical page group to another storage block.

14. The method according to claim 13, wherein: Executing the test read operation includes: When the read count of the memory block reaches a first test read count, performing the test read operation; and When the number of fail bits is the reference value or less and when the read count reaches a second test read count greater than the first test read count, the test read operation is re-performed.

15. The method according to claim 13, wherein: The at least one susceptible physical page includes a physical page most susceptible to the read disturbance among a plurality of physical pages included in the target stress physical page group, and is predetermined during a manufacturing process of the memory device.

16. The method according to claim 12, wherein: Selecting the target pressure physics page group includes: selecting a first pressure physical page group with the highest pressure level among the plurality of pressure physical page groups as the target pressure physical page group; and When a garbage collection operation is performed on the first stressed physical page group, a second stressed physical page group having the second highest stress level among the plurality of stressed physical page groups is selected as the target stressed physical page group.

17. A memory controller comprising: a pressure information storage device storing pressure information about a plurality of pressure physical page groups obtained by grouping a plurality of physical pages included in a memory block according to a pressure level of each of the plurality of physical pages, the pressure level being associated with a read disturbance; a read controller, performing a test read operation on at least one susceptible physical page in a target stressed physical page group among the plurality of stressed physical page groups; as well as A garbage controller performs a garbage collection operation on each of the plurality of pressure physical page groups based on the pressure level.

18. The memory controller according to claim 17, wherein: When the number of failed bits detected in the test read operation exceeds a reference value, the garbage controller performs a garbage collection operation of moving valid data stored in the target stress physical page group to another memory block.

19. The memory controller according to claim 17, wherein: The read controller selects a first stress physical page group with the highest stress level among the multiple stress physical page groups as the target stress physical page group, and when performing the garbage collection operation on the first stress physical page group, the read controller selects a second stress physical page group with the second highest stress level among the multiple stress physical page groups as the target stress physical page group.

20. The memory controller according to claim 17, wherein: When the read count of the storage block reaches a first test read count, the read controller performs a test read operation on a target stress physical page group among the multiple stress physical page groups, and when the number of fail bits detected in the test read operation is a reference value or less and when the read count of the storage block reaches a second test read count, the read controller re-executes the test read operation on the target stress physical page group.

Images