Board card testing method and device, system, equipment, medium and program product

Abstract

The invention provides a board card testing method and device, a system, equipment, a medium and a program product. The method comprises the steps of obtaining a target load; wherein the target load is a load which enables the power of the tested processor to reach the rated power in the processing process; issuing the target load to the tested processor every first preset duration until the test duration reaches a second preset duration; the test duration is the duration from the moment when the target load is issued for the first time to the current moment; obtaining the operation condition of the tested processor, and determining whether the board card where the tested processor is located normally operates the load or not according to the operation condition; the running condition comprises an execution result of processing the target load by the tested processor and / or board card power of a board card where the tested processor is located. Therefore, whether the power supply design of the board card meets the actual use scene or not can be tested by simulating the operation condition of the tested processor in the actual use scene.

Description

Technical Field

[0001] The present application relates to the technical field of board testing, and in particular to a method and apparatus, system, equipment, medium, and program product for testing a board. Background Art

[0002] Servers are usually equipped with motherboards, which are equipped with processors. As the computing power of processors increases, the power of motherboards also increases, which brings great challenges to the power supply design of motherboards. At present, the testing of motherboards usually only involves whether the motherboard can achieve the expected power, and does not pay attention to whether the power supply design of the motherboard meets the actual usage scenarios. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a test method and device, system, equipment, medium, and program product for a board, so as to solve the problem existing in the related art that it is impossible to evaluate whether the power supply design of the board meets the actual usage scenario during the actual use of the board.

[0004] An embodiment of the present application provides a testing method for a board, on which a processor under test is provided, the method comprising: obtaining a target load; wherein the target load is a load that enables the power of the processor under test to reach the rated power during processing; issuing the target load to the processor under test at intervals of a first preset time length until the test duration reaches a second preset time length; the test duration is the duration between the moment when the target load is first issued and the current moment; obtaining the operating status of the processor under test, and determining whether the board on which the processor under test is located is operating normally based on the operating status; the operating status includes the execution result of the processor under test processing the target load and / or the board power of the board on which the processor under test is located.

[0005] In the above implementation, it is considered that during actual use, the processor on the board will not process a task only once, nor will it process a certain task all the time. That is, the load processed by the processor under test is intermittent. By sending the target load to the processor under test at intervals of the first preset time within the second preset time, it is possible to simulate the operation of the processor under test in the actual use scenario, and then evaluate whether the processor on the board can operate normally during actual use according to the operation. Considering that the processor needs the board to provide appropriate power supply when processing the load, if the processor on the board cannot correctly execute the target load or the board power does not meet expectations when the processor on the board is running, then there may be problems with the board power supply design. By simulating the operation of the processor under test in the actual use scenario, it is possible to test whether the board power supply design meets the actual use scenario.

[0006] Furthermore, obtaining the target load includes: obtaining the model of the processor under test; searching for the load type corresponding to the model and the minimum load dimension corresponding to the load type in a preset association relationship; the association relationship records the correspondence between the model, the load type, and the minimum load dimension; wherein the load dimension is used to describe the size of the load; sending an alternative load to the processor under test; the alternative load is: a load belonging to the load type and having the minimum load dimension of the load type; obtaining the actual power of the processor under test when processing the alternative load; if the actual power is less than the rated power, increasing the load dimension to obtain the alternative load dimension, and sending a new alternative load belonging to the load type and having the alternative load dimension to the processor under test; repeating the above process until the actual power is greater than or equal to the rated power; the alternative load when the actual power is greater than or equal to the rated power is the target load.

[0007] In the above implementation, it is considered that different types of processors can drive different types of loads, and due to the different performances of different types of processors, the sizes of the loads they can drive are also different. By obtaining the load type corresponding to the model of the processor under test and the minimum load dimension corresponding to the load type, it is easy to obtain the load that the processor under test can handle. By continuously increasing the load dimension of the load, it is easy to obtain the minimum load that allows the processor under test to reach the rated power.

[0008] Further, the load dimension is increased to obtain an alternative load dimension, including: obtaining the current load dimension; and calculating the sum of the current load dimension and a preset dimension as the alternative load dimension.

[0009] In the above implementation, the alternative load dimension is obtained by directly adding the load dimension to the preset dimension, which is simple to calculate and can conveniently increase the load dimension.

[0010] Further, the target load is sent to the processor under test at intervals of a first preset time until the test time reaches a second preset time, including: repeatedly executing the first test strategy until the test time reaches the second preset time; the first test strategy includes: sending a first preset number of target loads to the processor under test, waiting for the processor under test to process the first preset number of target loads, and then waiting for a third preset time; the third preset time is equal to the time it takes for the processor under test to process the first preset number of target loads; correspondingly, the first preset time is equal to the sum of the third preset time and the time it takes for the processor under test to process the first preset number of target loads.

[0011] In the above implementation, by sending a target load to the processor on the board every first preset time period, it is possible to simulate the actual use process in which the processor on the board continuously receives and processes tasks, so as to determine whether the board power supply design is reasonable in the usage scenario in which the processor on the board continuously receives and processes tasks.

[0012] Furthermore, the target load is sent to the processor under test at intervals of a first preset time until the test time reaches a second preset time, including: repeatedly executing the second test strategy until the test time reaches the second preset time; the second test strategy includes: obtaining a first random number n, sending n target loads to the processor under test; waiting for the processor under test to process n target loads, and then waiting for a fourth preset time; the fourth preset time is equal to the time it takes for the processor under test to process n target loads; accordingly, the first preset time is equal to the sum of the fourth preset time and the time it takes for the processor under test to process n target loads.

[0013] In the above embodiment, by changing the number of target loads issued in each round within the second preset time period, it is possible to simulate the actual use process in which the processor on the board needs to process different numbers of tasks at different times, so as to determine whether the board power supply design is reasonable when the processor on the board receives a large change in the processing volume.

[0014] Furthermore, the target load is sent to the processor under test at intervals of a first preset time until the test time reaches a second preset time, including: repeatedly executing a third test strategy until the test time reaches the second preset time; the third test strategy includes: obtaining a second random number m and a random time, and sending m target loads to the processor under test; waiting for the random time after the processor under test has processed the m target loads; accordingly, the first preset time is equal to the sum of the random time and the time it takes for the processor under test to process the m target loads.

[0015] In the above embodiment, by changing the number of target loads sent in each round within the second preset time period, and changing the waiting time for each target load processing, it is possible to simulate the use scenario of sending tasks to the processor on the board for processing at irregular times and in varying quantities, so as to determine whether the board power supply design is reasonable when the processor on the board receives tasks at irregular times and in varying quantities.

[0016] Furthermore, the random duration is obtained by: obtaining a third random number k; and determining the random duration according to k and the duration for the processor under test to process m target loads.

[0017] In the above implementation, by using the third random number to adjust the time taken by the processor under test to process m target loads, the calculation is simple and the random time can be obtained conveniently.

[0018] Furthermore, the operating status includes the execution result of the processor under test processing the target load and the board power of the board where the processor under test is located; determining whether the board where the processor under test is located is operating normally based on the operating status includes: when the execution result is characterized correctly and the board power is normal, determining that the board where the processor under test is located is operating normally; otherwise, determining that the board where the processor under test is located is operating abnormally.

[0019] In the above implementation, by checking whether the execution result of the processor processing the target load is correct, it can be reflected whether the processor can operate normally. At the same time, by checking whether the board power is normal, it can be reflected whether the power generated by the processor when running reaches the power expected to be achieved by the board. Combining the execution result of the processor processing the target load and the board power can more completely and accurately reflect whether the board power supply design is reasonable.

[0020] Furthermore, the operating condition includes the board power of the board where the processor under test is located; determining whether the board where the processor under test is located is operating normally based on the operating condition, including: when the difference between the board power and the preset power is within a preset range, determining that the board where the processor under test is operating normally; otherwise, determining that the board where the processor under test is operating abnormally; the preset power is equal to half of the rated power.

[0021] In the above embodiment, whether the power of the board is normal can reflect whether the power generated by the processor when running reaches the power design expected to be implemented by the board, and further reflect whether the power supply design of the board is reasonable.

[0022] Furthermore, the operating status includes the execution result of the processor under test processing the target load; determining whether the board card where the processor under test is located is operating normally based on the operating status includes: when the execution result is characterized correctly, determining that the board card where the processor under test is located is operating normally; otherwise, determining that the board card where the processor under test is located is operating abnormally.

[0023] In the above embodiment, by verifying whether the execution result of the processor processing the target load is correct, it can be reflected whether the processor can operate normally, and further whether the board power supply design will cause problems with the processor.

[0024] An embodiment of the present application provides a test system, comprising: a main control processor, connected to a board; the main control processor is used to obtain a target load; the target load is sent to the processor under test at intervals of a first preset time length until the test time length reaches a second preset time length; wherein the target load is a load that enables the power of the processor under test to reach the rated power during processing; the test time length is the time length between the moment when the target load is first sent and the current moment; the operating status of the processor under test is obtained, and whether the board card where the processor under test is located is operating normally according to the operating status; the operating status includes the execution result of the processor under test processing the target load and / or the board power of the board card where the processor under test is located; the processor under test set on the board card is used to receive the target load sent by the main control processor, process the target load, obtain the execution result of processing the target load, and send the execution result to the main control processor.

[0025] An embodiment of the present application provides an electronic device, including a main control processor, a board and a memory, wherein the memory stores computer executable instructions that can be executed by the main control processor, the board is provided with a main control processor, and the main control processor executes the computer executable instructions to implement the above-mentioned board testing method.

[0026] An embodiment of the present application provides a storage medium, which stores computer-executable instructions. When the computer-executable instructions are called and executed by a main control processor, the computer-executable instructions enable the main control processor to implement the above-mentioned board test method.

[0027] An embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed by a main control processor, the above-mentioned board test method is implemented.

[0028] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 A schematic diagram of a flow chart of a board testing method provided in an embodiment of the present application; Figure 2A flow chart of a method for determining a target load provided in an embodiment of the present application; Figure 3 A schematic diagram of a flow chart of another board testing method provided in an embodiment of the present application; Figure 4 A flowchart of another board testing method provided in an embodiment of the present application; Figure 5 A schematic diagram of a flow chart of another board testing method provided in an embodiment of the present application; Figure 6 A test system is provided in an embodiment of the present application.

[0031] Reference numerals: 1: Main control processor; 2: Board; 3: Processor under test. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0033] Embodiment 1: In some embodiments, a main control processor and a board are independently arranged in the same electronic device. One or more processors under test are arranged on the board. The main control processor can interact with the processor on the board.

[0034] In order to solve the problem of how to evaluate whether the power supply design of the board is reasonable during the actual use of the board, the embodiment of the present application provides a test method for the board. Figure 1 As shown, Figure 1 The basic flow chart of the board test method provided in the embodiment of the present application includes: Step S101, obtaining the target load.

[0035] The target load is a load that enables the power of the tested processor to reach the rated power during the processing process. In this way, by using a load that enables the power of the tested processor to reach the rated power during the processing process for testing, it can ensure that the tested processor operates within a safe operating range and avoid potential damage caused by overload. At the same time, it is helpful to understand the performance of the board and the tested processor respectively when the tested processor is at maximum power, so as to more accurately reflect whether the board power supply design is reasonable.

[0036] The processor under test is a processor set on the board. Processors include: GPU (graphics processing unit) processor, TPU (tensor processing unit) processor, NPU (neural network processing unit) processor, etc.

[0037] Exemplarily, if there is one processor A on the board, then processor A is the processor under test, and the target load is a load that enables the power of processor A to reach the rated power during the processing. If there are two processors on the board, for example, processor B and processor C, then processor B and processor C are both processors under test. At this time, for processor B, there will be a load that enables the power of processor B to reach the rated power during the processing. For processor C, there will be a load that enables the power of processor C to reach the rated power during the processing.

[0038] In some embodiments, obtaining the target load may be: obtaining the model of the processor under test; searching for the load type corresponding to the model and the minimum load dimension corresponding to the load type in the preset association relationship; sending an alternative load to the processor under test; obtaining the actual power of the processor under test when processing the alternative load; if the actual power is less than the rated power, increasing the load dimension, obtaining the alternative load dimension, and sending a new alternative load belonging to the load type and having the alternative load dimension to the processor under test; repeating the above process until the actual power is greater than or equal to the rated power; the alternative load when the actual power is greater than or equal to the rated power is the target load.

[0039] The association relationship records the corresponding relationship between the model, the load type, and the minimum load dimension. Optionally, the load type recorded in the association relationship is the type of load that can cause the processor to consume the most energy per unit time.

[0040] The load type refers to the type of load, such as matrix calculation, image, video, etc.

[0041] The load dimension is used to describe the size of the load.

[0042] For example, when the payload is a matrix calculation, the size of the payload can be the number of rows and columns of the matrix; when the payload is a picture, the size of the payload can be the length and width of the picture. When the payload is a video, since the video is essentially composed of multiple frames of pictures, the size of the payload can also be the length and width of each frame of the video.

[0043] Optionally, the candidate load is: a load type corresponding to the model of the processor under test and a load with a minimum load dimension of the load type.

[0044] In one implementation of the above embodiment, increasing the load dimension to obtain an alternative load dimension may include: obtaining a current load dimension; and calculating a sum of the current load dimension and a preset dimension as the alternative load dimension.

[0045] In another implementation of the above embodiment, increasing the load dimension to obtain an alternative load dimension may include: obtaining the number of times the load is sent; the number of times the load is sent is equal to the number of times the alternative load is sent to the processor under test; calculating the product of the number of times the load is sent and the preset dimension to obtain the dimension to be increased; calculating the sum of the minimum load dimension and the dimension to be increased to obtain the alternative load dimension.

[0046] Exemplary, combined Figure 2 As shown, the embodiment of the present application provides a method for determining a target load, for each processor under test, including: Step S201, obtaining the rated power and model of the processor under test.

[0047] Step S202: Searching for the load type corresponding to the model of the processor under test and the minimum load dimension D corresponding to the load type in the preset association relationship.

[0048] Step S203, sending a load corresponding to the load dimension D+pE belonging to the load type to the processor under test, and obtaining the actual power of the processor under test when processing the load at a preset time interval while waiting for the processor under test to complete processing the load; Step S204, after waiting for the processor under test to complete processing the load, determine whether the actual power is greater than or equal to the rated power; if the actual power is less than the rated power, execute step S205; if the actual power is greater than or equal to the rated power, execute step S206.

[0049] Step S205, calculate the sum of p and 1 as a new p, and then execute step S203.

[0050] Step S206, recording the current load dimension as a target dimension that enables the processor under test to reach the rated power; the load corresponding to the target dimension is the target load.

[0051] In the above example, D is the minimum load dimension, E is the preset dimension, and p is the preset parameter. If the initial value of p is 0, it is equivalent to increasing the preset dimension based on the current load dimension after each round of the processor under test processes the load. Starting from dimension D, a load of the corresponding load type and dimension D is sent to the processor under test in the above manner. After each time interval T, the actual power Pa of the processor under test is obtained, and the actual power Pa is compared with the rated power Pe. If Pa does not reach Pe, the issued load dimension is increased by E, and a load of the corresponding load type and dimension D+pE is sent to the processor under test again. The actual power Pa is monitored again, and the above process is repeated until Pa reaches Pe. In this way, a minimum load dimension that allows the processor under test to work at the rated power can be obtained, and then a minimum target load that allows the processor under test to work at the rated power can be obtained.

[0052] Step S102: sending a target load to the processor under test at intervals of a first preset time length until the test duration reaches a second preset time length.

[0053] The test duration is the time from the first time the target load is sent to the current time.

[0054] In some embodiments, the target load may be sent to the processor under test at intervals of a first preset duration until the test duration reaches a second preset duration by the following test method: Method 1: Repeat the first test strategy until the test duration reaches a second preset duration. The first test strategy includes: sending a first preset number of target loads to the processor under test, waiting for the processor under test to process the first preset number of target loads, and then waiting for a third preset duration.

[0055] Correspondingly, the first preset time length is equal to the sum of the third preset time length and the time length for the processor under test to process the first preset number of target loads.

[0056] The first preset number may be set by an engineer according to test requirements.

[0057] The third preset time length is equal to the time length for the processor under test to process the first preset number of target loads.

[0058] Method 2: Repeat the second test strategy until the test duration reaches the second preset duration. The second test strategy includes: obtaining a first random number n, sending n target loads to the processor under test; waiting for the processor under test to process the n target loads, and then waiting for a fourth preset duration.

[0059] Correspondingly, the first preset time length is equal to the sum of the fourth preset time length and the time length for the processor under test to process n target loads.

[0060] The first random number n is a random positive integer.

[0061] The fourth preset time length is equal to the time length for the processor under test to process n target loads.

[0062] Method 3: Repeat the third test strategy until the test duration reaches the second preset duration. The third test strategy includes: obtaining a second random number m and a random duration, sending m target loads to the processor under test; waiting for the processor under test to process the m target loads, and then waiting for a random duration.

[0063] Correspondingly, the first preset duration is equal to the sum of the random duration and the duration for the processor under test to process m target loads.

[0064] The second random number m is a random positive integer.

[0065] In one implementation of the above embodiment, the random duration may be a randomly generated duration.

[0066] In another implementation of the above embodiment, the random duration may also be obtained in the following manner: obtaining a third random number k; and determining the random duration according to k and the duration for the processor under test to process m target loads.

[0067] The third random number k may be a random positive integer.

[0068] In the above implementation, the random duration is determined according to k and the duration for the tested processor to process m target loads, which may be: the product of k and the duration for the tested processor to process m target loads is calculated as the random duration.

[0069] In the above implementation, the random duration is determined according to k and the duration of time for the processor under test to process m target loads, and the quotient of k and m is calculated to obtain the random parameter. The product of the random parameter and the duration of time for the processor under test to process m target loads is calculated as the random duration. In this way, combining two random numbers to calculate the random duration can make the random duration more variable, thereby facilitating a more complete implementation of the scenario of sending tasks to the processor on the board at irregular intervals.

[0070] In the above embodiment, the first preset time length may also be a time length preset by an engineer. The engineer pre-evaluates the time length required for the processor under test to execute the target load and sets the first preset time length to be greater than the time length required for the processor under test to execute the target load.

[0071] In the above embodiment, each time the target load is issued, the time required for the processor under test to execute the target load is recorded, the set coefficient is multiplied by the time required for the processor under test to execute the target load as the waiting time, and the sum of the time required for the processor under test to execute the target load and the waiting time is calculated as the first preset time. At this time, since the waiting time is set according to the time required for the processor under test to execute the target load, it is easy to understand the duty cycle of the processor under test, so as to evaluate whether the power of the board is normal. For example: in the above method one, the first preset time is equal to the sum of the fourth preset time and the time required for the processor under test to process n target loads, and the fourth preset time is equal to the time required for the processor under test to process n target loads. At this time, the fourth preset time is equivalent to the waiting time, and the set coefficient is equivalent to 1. At this time, the processor under test runs the target load for half of the time, and the overall power of the board should be approximately equal to half of the rated power of the board.

[0072] Step S103, obtaining the operating status of the processor under test, and determining whether the board where the processor under test is located is operating normally according to the operating status.

[0073] The operation status includes the execution result of the processor under test processing the target load and / or the board power of the board where the processor under test is located.

[0074] In some embodiments, it is possible to determine whether the execution result of the last time the tested processor processed the target load in the second preset time is correct, and the operation status only includes the execution result of the last time the tested processor processed the target load. It is also possible to randomly determine whether the execution results of several times the tested processor processed the target load in the second preset time are correct, and the operation status includes the execution results of multiple times the tested processor processed the target load. In this case, each execution result that needs to be determined is correct before the execution result representation is considered correct.

[0075] In some embodiments, the power change of the board can be monitored through a preset system management software or interface. The power change of the board can be monitored through the real-time power parameters of the board in the system management software or interface provided by the board manufacturer. The system management software provided by the board manufacturer can be System Management Interface (SMI, a type of system management software).

[0076] In some embodiments, the operating status includes the execution result of the processor under test processing the target load and the board power of the board where the processor under test is located; for the test methods of method one and method two, determining whether the board where the processor under test is located is operating normally based on the operating status may include: when the execution result is characterized correctly and the board power is normal, determining that the board where the processor under test is located is operating normally; otherwise, determining that the board where the processor under test is located is operating abnormally.

[0077] In the above embodiment, whether the execution result is correct can be determined in the following manner: obtaining the execution result; comparing the execution result with the preset result, if the execution result is consistent with the preset result, determining that the execution result is correct; otherwise, determining that the execution result is wrong.

[0078] The preset result can be obtained by calculating the target load sent to the processor under test in advance through the main control processor, and the alternative result is stored in the preset storage space as the preset result.

[0079] In the above embodiment, whether the execution result is correct can also be determined in the following manner: obtaining the execution result; obtaining the target load of the execution result, and performing calculations on the target load to obtain the operation result. Comparing the execution result with the operation result, if the execution result is consistent with the operation result, determining that the execution result is correct; otherwise, determining that the execution result is wrong.

[0080] In the above embodiment, whether the board power is normal can be determined in the following manner: when the difference between the board power and the preset power is within a preset range, the board power is determined to be normal; otherwise, the board power is determined to be abnormal.

[0081] Among them, by specifically setting method 1 and method 2 to run the target load for half of the time and not perform task processing for the remaining half of the time, if the processor under test runs normally, the overall power of the board should be approximately equal to half of the rated power. Therefore, by setting the preset power equal to half of the rated power, it can be determined that the power of the board is normal.

[0082] The preset range can be determined by engineers based on the tolerance of the design. In this way, considering that the power consumption of the processor may also have slight fluctuations when processing the same target load, the power of the board card can be considered normal when the power of the board card is close to the preset power.

[0083] Optionally, the board power may be an average power of the board during the test duration.

[0084] In some embodiments, the operating conditions include the board power of the board where the processor under test is located. For the test methods of method 1 and method 2, determining whether the board where the processor under test is located is operating normally according to the operating conditions includes: if the difference between the board power and the preset power is within a preset range, determining that the board where the processor under test is operating normally; otherwise, determining that the board where the processor under test is operating abnormally; the preset power is equal to half of the rated power.

[0085] In some embodiments, the operation status includes the execution result of the processor under test processing the target load. For the test methods of Mode 1, Mode 2 and Mode 3, determining whether the board where the processor under test is located is operating normally according to the operation status includes: if the execution result characterizes correctly, determining that the board where the processor under test is located is operating normally; otherwise, determining that the board where the processor under test is located is operating abnormally.

[0086] Among them, to determine whether the execution result is correct, refer to the above steps, which will not be repeated here.

[0087] In some embodiments, after determining whether the board where the processor under test is located is operating normally according to the operating conditions, the method may further include: displaying the test result of whether the board where the processor under test is located is operating normally to the user.

[0088] Exemplarily, the load test result of whether the board where the processor under test is located is running normally can be sent to a preset display screen for display, or the load test result of whether the board where the processor under test is located is running normally can be sent to a preset mailbox, etc. The preset display screen can be a display screen of an electronic device bound with corresponding user information.

[0089] In some embodiments, after determining whether the board where the processor under test is located is operating normally based on the operating conditions, if it is determined that the board where the processor under test is located is operating normally, then the board power supply design is determined to be reasonable; if it is determined that the board where the processor under test is located is operating abnormally, then the board power supply design is determined to be unreasonable.

[0090] Accordingly, the test results of whether the board power supply design is reasonable can be displayed to the user.

[0091] Exemplary, combined Figure 3 As shown, the embodiment of the present application provides a method for testing a board, including: Step S301, record the test start time.

[0092] Step S302: Send a first preset number of target loads to the processor under test and record a first working time; wait for the processor under test to complete processing the first preset number of target loads and record a second working time.

[0093] Step S303, calculating the difference between the second working time and the first working time, obtaining a third preset time, and waiting for the third preset time.

[0094] Step S304, after waiting is completed, the third working time is obtained, and the difference between the third working time and the start time is calculated to obtain the test duration.

[0095] Step S305, determine whether the test duration is greater than or equal to the second preset duration; if the test duration is less than the second preset duration, execute step S302. If the test duration is greater than or equal to the second preset duration, execute step S306.

[0096] Step S306, obtaining the average power of the board from the start time to the third working time.

[0097] Step S307, determining whether the execution result of the processor under test processing the target load is correct, if it is correct, executing step S308; if it is not correct, executing step S310.

[0098] Step S308, determining whether the difference between the average power of the board and the preset power is within a preset range; if it is within the preset range, executing step S309; ​​if it is not within the preset range, executing step S310.

[0099] Step S309, output the test result as normal.

[0100] Step S310, outputting the test result as abnormal.

[0101] In this way, by sending a target load to the processor on the board every first preset time period, it is possible to simulate the scenario in which the processor on the board continuously receives and processes tasks during actual use, so as to determine whether the board power supply design is reasonable in the scenario in which the processor on the board continuously receives and processes tasks.

[0102] Exemplary, combined Figure 4 As shown, the embodiment of the present application provides a method for testing a board, including: Step S401, recording the test start time.

[0103] Step S402, obtain a first random number n, send n target loads to the processor under test, and record the fourth working time; wait for the processor under test to complete processing the n target loads, and record the fifth working time.

[0104] Step S403, calculating the difference between the fourth working time and the fifth working time, obtaining a fourth preset time, and waiting for the fourth preset time.

[0105] Step S404, after waiting is completed, the sixth working time is obtained, and the difference between the sixth working time and the start time is calculated to obtain the test duration.

[0106] Step S405, determine whether the test duration is greater than or equal to the second preset duration; if the test duration is less than the second preset duration, execute step S402. If the test duration is greater than or equal to the second preset duration, execute step S406.

[0107] Step S406, obtaining the average power of the board from the start time to the sixth working time.

[0108] Step S407, determining whether the execution result of the processor under test processing the target load is correct, if it is correct, executing step S408; if it is not correct, executing step S410.

[0109] Step S408, determining whether the difference between the average power of the board and the preset power is within a preset range; if it is within the preset range, executing step S409; if it is not within the preset range, executing step S410.

[0110] Step S409: output the test result as normal.

[0111] Step S410, outputting the test result as abnormal.

[0112] In this way, by changing the number of target loads sent in each round within the second preset time period, it is possible to simulate the scenario in which the processor on the board needs to process different numbers of tasks at different times during actual use, so as to determine whether the board power supply design is reasonable when the processor on the board receives a scenario with large changes in the processing volume.

[0113] Exemplary, combined Figure 5 As shown, the embodiment of the present application provides a method for testing a board, including: Step S501, record the test start time.

[0114] Step S502, obtain the second random number m and the third random number k, send m target loads to the processor under test, and record the seventh working time; wait for the processor under test to complete processing the m target loads, and record the eighth working time.

[0115] Step S503, calculate the product between the alternative duration and the random parameter to obtain the random duration; wherein the alternative duration is the difference between the eighth working time and the seventh working time; and the random parameter is the quotient between the third random number and the second random number.

[0116] Step S504, after waiting is completed, the ninth working time is obtained, and the difference between the ninth working time and the start time is calculated to obtain the test duration.

[0117] Step S505, determine whether the test duration is greater than or equal to the second preset duration; if the test duration is less than the second preset duration, execute step S502. If the test duration is greater than or equal to the second preset duration, execute step S506.

[0118] Step S506, determining whether the execution result of the processor under test processing the target load is correct, if it is correct, executing step S507; if it is not correct, executing step S508.

[0119] Step S507, output the test result as normal.

[0120] Step S508: output the test result as abnormal.

[0121] In this way, by changing the number of target loads sent in each round within the second preset time period, and at the same time changing the waiting time after each target load is processed, it is possible to simulate a scenario in which tasks are sent to the processor on the board for processing at irregular intervals and in varying quantities, so as to determine whether the power supply design of the board is reasonable when the processor on the board receives tasks at irregular intervals and in varying quantities.

[0122] In some embodiments, the board can be tested in the above-mentioned way 1, way 2 and way 3 in sequence. If the tests of way 1, way 2 and way 3 are all normal, it is considered that the board where the tested processor is located is operating normally. Otherwise, it is considered that the board where the tested processor is located is operating abnormally. In addition, different first preset numbers can be set to perform the test of way 1 multiple times. For example, the first preset number can be set to 1 for testing. After the test is completed, the first preset number can be set to 5 for testing.

[0123] In other examples, it is assumed that there are two processors on the board, for example: a GPU processor and an NPU processor. The main control processor obtains a load that enables the GPU processor to reach the rated power during the processing process, and the main control processor obtains a load that enables the NPU to reach the rated power during the processing process. Load a is sent to the GPU processor every first preset time interval within the second preset time. At the same time, load b is sent to the NPU processor every first preset time interval within the second preset time. Then the execution result of the GPU processor processing load a and the execution result of the NPU processor processing load b are obtained. If the execution result of the GPU processor processing load a is correct, and the execution result of the NPU processor processing load b is correct, the board can run the load correctly. If the above method one or method two is used to test the GPU processor and the NPU processor, the average power of the board in the second time can also be obtained, and whether the board is running the load normally can be judged by judging whether the average power of the board is approximately equal to half of the rated power of the board.

[0124] Embodiment 2 The same inventive concept, combined Figure 6 As shown, the embodiment of the present application provides a test system, including: a main control processor 1 and a board 2. The main control processor 1 is connected to the board 2; the main control processor 1 is used to obtain a target load; the target load is sent to the processor 3 under test at intervals of a first preset time length until the test time length reaches a second preset time length; the target load is a load that enables the power of the processor 3 under test to reach the rated power during the processing; the test time length is the time length between the moment when the target load is sent for the first time and the current moment; the operation status of the processor 3 under test is obtained, and whether the board where the processor 3 under test is located is operating normally according to the operation status; the operation status includes the execution result of the processor 3 under test processing the target load and / or the board power of the board 2 where the processor 3 under test is located; the processor under test set on the board 2 is used to receive the target load sent by the main control processor 1, process the target load, obtain the execution result of processing the target load, and send the execution result to the main control processor 1.

[0125] The main control processor may be a CPU (central processing unit) processor.

[0126] In some embodiments, the master processor is used to obtain the target load in the following manner: obtain the model of the processor under test; search for the load type corresponding to the model and the minimum load dimension corresponding to the load type in a preset association relationship; the association relationship records the correspondence between the model, the load type, and the minimum load dimension; wherein the load dimension is used to describe the size of the load; send an alternative load to the processor under test; the alternative load is: a load that belongs to the load type and has the minimum load dimension of the load type; obtain the actual power of the processor under test when processing the alternative load; if the actual power is less than the rated power, increase the load dimension, obtain the alternative load dimension, and send a new alternative load that belongs to the load type and has the alternative load dimension to the processor under test; repeat the above process until the actual power is greater than or equal to the rated power; the alternative load when the actual power is greater than or equal to the rated power is the target load.

[0127] In some embodiments, the main control processor is used to increase the load dimension to obtain an alternative load dimension by: obtaining the current load dimension; and calculating the sum of the current load dimension and the preset dimension as the alternative load dimension.

[0128] In some embodiments, the master processor is used to send a target load to the processor under test at intervals of a first preset time until the test time reaches a second preset time in the following manner: repeatedly execute the first test strategy until the test time reaches the second preset time; the first test strategy includes: sending a first preset number of target loads to the processor under test, waiting for the processor under test to process the first preset number of target loads, and then waiting for a third preset time; the third preset time is equal to the time it takes for the processor under test to process the first preset number of target loads; accordingly, the first preset time is equal to the sum of the third preset time and the time it takes for the processor under test to process the first preset number of target loads.

[0129] In some embodiments, the master processor is used to send a target load to the processor under test at intervals of a first preset time until the test time reaches a second preset time in the following manner: repeatedly execute the second test strategy until the test time reaches the second preset time; the second test strategy includes: obtaining a first random number n, sending n target loads to the processor under test; waiting for the processor under test to process the n target loads, and then waiting for a fourth preset time; the fourth preset time is equal to the time it takes for the processor under test to process the n target loads; accordingly, the first preset time is equal to the sum of the fourth preset time and the time it takes for the processor under test to process the n target loads.

[0130] In some embodiments, the master processor is used to send a target load to the processor under test at intervals of a first preset time until the test time reaches a second preset time in the following manner: repeatedly execute a third test strategy until the test time reaches the second preset time; the third test strategy includes: obtaining a second random number m and a random time, and sending m target loads to the processor under test; waiting for the processor under test to process the m target loads, and then waiting for a random time; accordingly, the first preset time is equal to the sum of the random time and the time it takes for the processor under test to process the m target loads.

[0131] In some embodiments, the main control processor is used to obtain the random duration in the following manner: obtain a third random number k; and determine the random duration according to k and the duration for the processor under test to process m target loads.

[0132] In some embodiments, the operation status includes the execution result of the processor under test processing the target load and the board power of the board where the processor under test is located. The main control processor is used to determine whether the board where the processor under test is located is operating normally according to the operation status in the following manner: if the execution result characterizes correctly and the board power is normal, it is determined that the board where the processor under test is located is operating normally; otherwise, it is determined that the board where the processor under test is located is operating abnormally.

[0133] In some embodiments, the operating conditions include the board power of the board where the processor under test is located. The main control processor is used to determine whether the board where the processor under test is located is operating normally according to the operating conditions in the following manner: if the difference between the board power and the preset power is within a preset range, determine that the board where the processor under test is operating normally; otherwise, determine that the board where the processor under test is operating abnormally; the preset power is equal to half of the rated power.

[0134] In some embodiments, the operation status includes the execution result of the processor under test processing the target load. The main control processor is used to determine whether the board where the processor under test is located is operating normally according to the operation status in the following manner: if the execution result characterizes correctly, it is determined that the board where the processor under test is located is operating normally; otherwise, it is determined that the board where the processor under test is located is operating abnormally.

[0135] An embodiment of the present application provides an electronic device, including a main control processor, a board and a memory, wherein the memory stores computer executable instructions that can be executed by the main control processor, and the board is provided with a processor, and the main control processor executes the computer executable instructions to implement the above-mentioned board testing method.

[0136] An embodiment of the present application provides a storage medium storing computer executable instructions, wherein the computer executable instructions are configured to execute the test method of the above-mentioned board.

[0137] An embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed by a main control processor, the above-mentioned board test method is implemented.

[0138] The technical solution of the embodiment of the present application can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present application. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and other media that can store program codes, or a transient storage medium.

[0139] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0140] In the embodiments provided in the present application, it should be understood that the terms "first", "second", etc. in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. Unless otherwise specified, the term "plurality" means two or more. The term "and / or" is a kind of association relationship describing an object, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B, these three relationships. The term "corresponding" can refer to an association relationship or a binding relationship, and A and B correspondingly refer to an association relationship or a binding relationship between A and B.

[0141] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application. At the same time, the above embodiments can be combined with each other to form new embodiments without conflict.

Claims

1. A method for testing a board, characterized in that: The board is provided with a processor under test, and the method comprises: Obtaining a target load; wherein the target load is a load that enables the power of the processor under test to reach the rated power during processing; Sending the target load to the processor under test at intervals of a first preset time length until the test duration reaches a second preset time length; the test duration is the duration between the time when the target load is first sent and the current time; The operating status of the processor under test is obtained, and whether the board where the processor under test is located is operating normally according to the operating status; the operating status includes the execution result of the processor under test processing the target load and / or the board power of the board where the processor under test is located.

2. The method according to claim 1, characterized in that Get the target payload, including: Obtaining the model of the processor under test; Searching for the load type corresponding to the model and the minimum load dimension corresponding to the load type in a preset association relationship; the association relationship records the correspondence between the model, the load type, and the minimum load dimension; wherein the load dimension is used to describe the size of the load; Sending an alternative load to the processor under test; the alternative load is: a load belonging to the load type and having the smallest load dimension of the load type; Obtain the actual power of the processor under test when processing the alternative load; if the actual power is less than the rated power, increase the load dimension to obtain the alternative load dimension, and send a new alternative load belonging to the load type and having the alternative load dimension to the processor under test; repeat the above process until the actual power is greater than or equal to the rated power; the alternative load when the actual power is greater than or equal to the rated power is the target load.

3. The method according to claim 2, characterized in that Increasing the load dimension to obtain an alternative load dimension includes: Obtain the current load dimension; The sum of the current load dimension and the preset dimension is calculated as the candidate load dimension.

4. The method according to claim 1, characterized in that Sending the target load to the processor under test at intervals of a first preset time length until the test time length reaches a second preset time length, including: Repeat the first test strategy until the test duration reaches a second preset duration; The first test strategy includes: sending a first preset number of target loads to the processor under test, waiting for a third preset time after the processor under test has processed the first preset number of target loads; the third preset time is equal to the time it takes for the processor under test to process the first preset number of target loads; Correspondingly, the first preset time duration is equal to the sum of the third preset time duration and the time duration for the processor under test to process a first preset number of target loads.

5. The method according to claim 1, characterized in that Sending the target load to the processor under test at intervals of a first preset time length until the test time length reaches a second preset time length, including: Repeat the second test strategy until the test duration reaches a second preset duration; The second test strategy includes: obtaining a first random number n, sending n target loads to the processor under test; waiting for the processor under test to process the n target loads, and then waiting for a fourth preset time; the fourth preset time is equal to the time it takes for the processor under test to process the n target loads; Correspondingly, the first preset time length is equal to the sum of the fourth preset time length and the time length for the processor under test to process n target loads.

6. The method according to claim 1, characterized in that Sending the target load to the processor under test at intervals of a first preset time length until the test time length reaches a second preset time length, including: Repeat the third test strategy until the test duration reaches the second preset duration; The third test strategy includes: obtaining a second random number m and a random duration, sending m target loads to the processor under test; waiting for the random duration after the processor under test has processed the m target loads; Correspondingly, the first preset duration is equal to the sum of the random duration and the duration for the processor under test to process m target loads.

7. The method according to claim 6, characterized in that The random duration is obtained in the following way: Get a third random number k; The random duration is determined according to k and the duration for the processor under test to process m target loads.

8. The method according to any one of claims 1 to 5, characterized in that: The operation status includes the execution result of the processor under test processing the target load and the board power of the board where the processor under test is located; Determining whether the board where the processor under test is located is operating normally according to the operating conditions includes: When the execution result is characterized as correct and the power of the board is normal, determining the normal operating load of the board where the processor under test is located; Otherwise, it is determined that the board where the processor under test is located is abnormally running under load.

9. The method according to any one of claims 1 to 5, characterized in that: The operating conditions include the board power of the board where the processor under test is located; Determining whether the board where the processor under test is located is operating normally according to the operating conditions includes: When the difference between the board power and the preset power is within a preset range, determining the normal operating load of the board where the processor under test is located; Otherwise, it is determined that the board where the processor under test is located has an abnormal operating load; and the preset power is equal to half of the rated power.

10. The method according to claim 6, characterized in that The operation status includes the execution result of the processor under test processing the target load; Determining whether the board where the processor under test is located is operating normally according to the operating conditions includes: In the case where the execution result is characterized as correct, determining the normal operating load of the board where the processor under test is located; Otherwise, it is determined that the board where the processor under test is located is abnormally running under load.

11. A testing system, characterized in that: include: The main control processor is connected to the board; The master processor is used to obtain a target load; the target load is sent to the processor under test at intervals of a first preset time length until the test duration reaches a second preset time length; wherein the target load is a load that enables the power of the processor under test to reach the rated power during processing; the test duration is the duration between the time when the target load is first sent and the current time; Obtaining the operating status of the processor under test, and determining whether the board where the processor under test is located is operating normally according to the operating status; the operating status includes the execution result of the processor under test processing the target load and / or the board power of the board where the processor under test is located; The processor under test provided on the board is used to receive the target load sent by the main control processor, process the target load, obtain the execution result of processing the target load, and send the execution result to the main control processor.

12. An electronic device, characterized in that: It comprises a main control processor, a board and a memory, wherein the memory stores computer executable instructions that can be executed by the main control processor, the board is provided with the main control processor, and the main control processor executes the computer executable instructions to implement the board testing method described in any one of claims 1 to 10.

13. A storage medium, characterized in that: The storage medium stores computer executable instructions. When the computer executable instructions are called and executed by the main control processor, the computer executable instructions enable the main control processor to implement the board test method according to any one of claims 1 to 10.

14. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a main control processor, the board test method according to any one of claims 1 to 10 is implemented.

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