Heterogeneous reconfigurable signal processing SIP chip

Abstract

The invention relates to a heterogeneous reconfigurable signal processing SIP (Session Initiation Protocol) chip. The physical reconfigurable micro-system architecture comprises three types of sub-micro-systems oriented to three types of applications, namely a control-intensive application, a calculation-intensive application and a data-intensive application. The first sub-microsystem taking the CPU as the core faces to control intensive application, comprises FLASH to realize core configuration and caches SRAM or DDR to realize operation caching, the second sub-microsystem taking the FPGA as the core faces to data intensive application, comprises cache DDR to realize high-speed operation caching, and comprises one or two of high-frequency interface chips such as a high-speed interface chip and a radio frequency chip; and the third sub-microsystem taking the DSP as the core is oriented to a compute-intensive application, and comprises a DDR (Double Data Rate) to realize high-speed caching of data and a high-speed interface chip to realize high-speed transmission of the data.

Description

Technical Field

[0001] The invention relates to a heterogeneous reconfigurable signal processing SIP chip, belonging to the technical field of system-level packaging. Background Art

[0002] As Moore's Law gradually reaches its limit, the development of SoC faces the risk of reduced yield and increased cost. System-level packaging integrates system functions by packaging multiple finished bare chips. It has the characteristics of low cost and rapid production and has become one of the important directions of technological development.

[0003] Existing technologies are mainly used to package heterogeneous chips. The application of SiP has special characteristics. Every time there is a new requirement, the entire substrate needs to be redeveloped, which is very costly. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art and to propose a heterogeneous reconfigurable signal processing SIP chip that can be freely combined and matched according to application requirements to form different signal processing systems.

[0005] The solution to the technical problem of the present invention is: a heterogeneous reconfigurable signal processing SIP chip, the SIP chip comprising a substrate, a first sub-microsystem, a second sub-microsystem, and a third sub-microsystem;

[0006] The bottoms of the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem are independently packaged using substrates of the same size, the same number of pins, and solder balls of the same size and spacing;

[0007] The substrate is divided into four identical areas for encapsulating the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem, and provides supporting peripheral circuits and connection circuits for the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem, so as to form a SIP chip for signal processing;

[0008] The number and position of the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem can be configured according to actual needs.

[0009] Preferably, the first sub-microsystem includes a CPU, a FLASH and a cache;

[0010] FLASH is used to store the CPU configuration program, the cache is used to store the intermediate data during the CPU operation process, and the CPU completes the corresponding signal control function according to the configured program.

[0011] Preferably, the cache is SRAM or DDR.

[0012] Preferably, the second sub-microsystem includes a cache DDR, a data interface chip, an AD, and a DA;

[0013] DDR is used to implement high-speed data caching, high-speed interface chips are used to implement data exchange with the outside, AD is used to perform analog-to-digital conversion on signals, DA is used to perform digital-to-analog conversion on signals, and FPGA completes the corresponding signal processing functions according to the configured program.

[0014] Preferably, the second sub-microsystem includes a cache DDR, a data interface chip, and a radio frequency chip;

[0015] DDR is used to implement high-speed data caching, the interface chip is used to implement data exchange with the outside, the RF chip is used to receive RF signals and perform RF signal processing; FPGA completes the corresponding signal processing function according to the configured program.

[0016] Preferably, the third sub-microsystem includes DSP, cache DDR, data interface chip

[0017] DDR is used to implement high-speed data caching, the data interface chip is used to implement data exchange between the third sub-microsystem and the outside; DSP is used to complete corresponding calculation and processing functions according to the configured program.

[0018] Preferably, the packaging form adopted by the first sub-microsystem, the second sub-microsystem and the third sub-microsystem is plastic packaging or metal cap packaging.

[0019] Preferably, from the perspective of packaging cost, plastic packaging gives priority to packaging all-wire-bonded bare die, followed by full flip-chip packaging, and finally mixed packaging of wire bonding and flip-chip can be used. From the perspective of process implementation, metal caps can only use full flip-chip bare die;

[0020] Preferably, the substrate is packaged in a ceramic BGA package.

[0021] The beneficial effects of the present invention compared with the prior art are:

[0022] (1) The heterogeneous reconfigurable processing SIP chip of the present invention decouples the functions and architectures of different cores so that a single core can independently process some functions, and independently packages different cores and independent supporting circuits to form a sub-microsystem. Different cores are packaged in the packaging to realize the packaging of the overall microsystem and form a microsystem.

[0023] (2) The sub-microsystem of the present invention can realize independent system functions and can be used alone. The overall microsystem can be combined by different sub-microsystems to realize complex system functions.

[0024] (3) The present invention adopts a package-in-package solution and realizes the modular design of the sub-SiP and the reconfiguration of the package-in-package by adopting a standard pad interface method. On the basis of satisfying the functions, it simplifies the design process of the secondary packaging substrate and reduces the cost of the package-in-package. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is the internal composition of the first sub-microsystem of the embodiment of the present invention.

[0026] Figure 2 This is the internal composition of the second sub-microsystem in the embodiment of the present invention.

[0027] Figure 3 This is the internal composition of the third sub-microsystem of the embodiment of the present invention.

[0028] Figure 4 This is the system architecture of the first embodiment of the present invention;

[0029] Figure 5 This is the system architecture of the second embodiment of the present invention;

[0030] Figure 6 This is a first implementation of the second sub-microsystem of the embodiment of the present invention;

[0031] Figure 7 This is a second implementation of the second sub-microsystem of the embodiment of the present invention;

[0032] Figure 8 This is a third implementation of the second sub-microsystem of the embodiment of the present invention;

[0033] Fig. 9 This is the system architecture of the third embodiment of the present invention;

[0034] Fig.10 This is the system architecture of the fourth embodiment of the present invention. DETAILED DESCRIPTION

[0035] The present invention will be further described below in conjunction with the embodiments.

[0036] A heterogeneous reconfigurable signal processing SIP chip, the SIP chip includes a substrate, a first sub-microsystem 1, a second sub-microsystem 2, and a third sub-microsystem 3; Figure 1 , Figure 2 and Figure 3 The three sub-microsystems are based on CPU, DSP and FPGA respectively.

[0037] The bottoms of the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem are independently packaged using substrates of the same size, the same number of pins, and solder balls of the same size and spacing;

[0038] The substrate is divided into four identical areas for encapsulating the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem, and provides supporting peripheral circuits and connection circuits for the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem, so as to form a SIP chip for signal processing;

[0039] The number and position of the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem can be configured according to actual needs.

[0040] Preferably, the first sub-microsystem includes a CPU, a FLASH and a cache;

[0041] FLASH is used to store the CPU configuration program, the cache is used to store the intermediate data during the CPU operation process, and the CPU completes the corresponding signal control function according to the configured program.

[0042] Preferably, the cache is SRAM or DDR, which is used to store intermediate data during the operation of the CPU. The CPU has rich control functions and is suitable for control-intensive applications.

[0043] Preferably, the second sub-microsystem includes a cache DDR, a data interface chip, an AD, and a DA;

[0044] DDR is used to implement high-speed data caching, high-speed interface chips are used to implement data exchange with the outside, AD is used to perform analog-to-digital conversion on signals, DA is used to perform digital-to-analog conversion on signals, and FPGA completes the corresponding signal processing functions according to the configured program.

[0045] Preferably, the second sub-microsystem includes a cache DDR, a data interface chip, and a radio frequency chip; the data interface chips include 8255A, 8250, RS485, PCIE, etc.

[0046] DDR is used to implement high-speed data caching, the interface chip is used to implement data exchange with the outside, the RF chip is used to receive RF signals and perform RF signal processing; FPGA completes the corresponding signal processing function according to the configured program.

[0047] Preferably, the third sub-microsystem includes DSP, cache DDR, data interface chip

[0048] DDR is used to implement high-speed data caching, the data interface chip is used to implement data exchange between the third sub-microsystem and the outside; DSP is used to complete corresponding calculation and processing functions according to the configured program.

[0049] Preferably, the packaging form adopted by the first sub-microsystem, the second sub-microsystem and the third sub-microsystem is plastic packaging or metal cap packaging.

[0050] Preferably, from the perspective of packaging cost, plastic packaging gives priority to packaging all-wire-bonded bare die, followed by full flip-chip packaging, and finally mixed packaging of wire bonding and flip-chip can be used. From the perspective of process implementation, metal caps can only use full flip-chip bare die;

[0051] Preferably, the substrate is packaged in a ceramic BGA package.

[0052] The packaging forms of the cavities of the first sub-microsystem 1, the second sub-microsystem 2 and the third sub-microsystem 3 can be the same or different, but the bottoms of the cavities all use substrates of the same size, and solder balls of the same size and spacing to ensure interface consistency;

[0053] The first sub-microsystem 1, the second sub-microsystem 2 and the third sub-microsystem 3 may be packaged in the form of plastic packaging and metal cap packaging. Plastic packaging is used when the power consumption of the internal device is relatively small, and metal cap packaging is used when the power consumption of the internal device is relatively large.

[0054] From the perspective of packaging cost, plastic packaging gives priority to packaging fully wire-bonded bare die, followed by full flip-chip packaging, and finally mixed packaging of wire bonding and flip-chip can be used. From the perspective of process implementation, metal caps can only be used for fully flip-chip bare die.

[0055] The reconfigurable microsystem selects 2, 3 or 4 of the same or different sub-microsystems 1, sub-microsystem 2 and sub-microsystem 3 for packaging according to application requirements to achieve packaging in packaging. The reconfigurable microsystem architecture adopts ceramic BGA packaging, and its substrate is divided into four completely identical areas for packaging sub-microsystems. The unified packaging substrate can reduce manufacturing costs by increasing the quantity.

[0056] Example 1

[0057] A heterogeneous reconfigurable processing SIP chip for intelligent decision control, whose application architecture is as follows Figure 4 As shown, it includes 1 first sub-microsystem, 2 second sub-microsystems, and 1 third sub-microsystem;

[0058] The first sub-microsystem 1 is used to process control-intensive requirements, and the second sub-microsystem 2 is used to process calculation-intensive requirements.

[0059] The types of bare cores included in the two second sub-microsystems are as follows: Figure 6 and Figure 7 As shown, Figure 6 Sub-microsystem 2 includes DDR, high-speed interface, AD, and DA, which are used to process external analog signals. Figure 7 Sub-microsystem 2 includes DDR, high-speed interface and radio frequency chip. The high-speed interface is used for transmitting information on the data board with the outside, and the radio frequency chip is used for communication.

[0060] Example 2

[0061] A heterogeneous reconfigurable processing SIP chip for intelligent decision control, wherein the application architecture includes one first sub-microsystem and three second sub-microsystems; Figure 5 shown.

[0062] Among them, 3 second sub-microsystems include bare core types and 1 second sub-microsystem such as Figure 6 and 2 Second sub-microsystem Figure 8 As shown, Figure 6 The second sub-microsystem includes DDR, high-speed interface, AD, and DA, which are used to sample and output external analog signals. Figure 7 Sub-microsystem 2 includes a DDR radio frequency chip for multi-channel signal communication;

[0063] Example 3

[0064] A heterogeneous reconfigurable processing SIP chip for intelligent decision control, whose application architecture is as follows Fig. 9 As shown, it includes 1 first sub-microsystem and 1 second sub-microsystem;

[0065] The second sub-microsystem includes bare core types such as Figure 2 As shown, Figure 2 The second sub-microsystem includes DDR, high-speed interface, AD, and DA, which are used to realize external ultra-high frequency sampling and output;

[0066] Example 4

[0067] A heterogeneous reconfigurable processing SIP chip for intelligent decision control, whose application architecture is as follows Fig.10 As shown, it includes 1 first sub-microsystem and 1 third sub-microsystem;

[0068] The third sub-microsystem is used for computationally intensive requirements, and the first sub-microsystem is used for control-intensive microsystems;

[0069] There are many different ways to combine the physical reconfigurable microsystem. The number of sub-microsystems is greater than or equal to 2 and less than or equal to 4, and they can be freely combined according to application requirements. Among the sub-microsystems, the second sub-microsystem can combine the bare cores according to application requirements to improve the flexibility of system application.

[0070] In the packaging form, the size of the substrate, the size of the pins, the spacing and the distribution of the sub-microsystems are consistent. The packaging substrate can be selected according to the application requirements, power consumption, etc. The packaging material can also be selected according to the application requirements. The physical reconfigurable microsystem packaging substrate uses a ceramic substrate to improve the heat dissipation characteristics.

[0071] The sub-microsystems of the present invention can be used alone or combined into a physically reconfigurable microsystem, thereby improving application flexibility. The sub-microsystems are packaged in a substrate form, and metal cover plates, plastic packaging filling, and other forms can be selected according to different heat dissipation requirements. The first sub-microsystem 1, the second sub-microsystem 2, and the third sub-microsystem 3 use the same size of packaging substrates, pin numbers, and solder balls. Based on the sub-microsystem packaging form, a four-cavity reconfigurable microsystem substrate is designed, which can hold four sub-microsystems. There can be two, three, and four sub-microsystems in the physically reconfigurable microsystem, and the sub-microsystem mode can be freely combined.

[0072] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A heterogeneous reconfigurable signal processing SIP chip, characterized in that It includes a substrate, a first sub-microsystem, a second sub-microsystem, and a third sub-microsystem; The bottoms of the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem are independently packaged using substrates of the same size, the same number of pins, and solder balls of the same size and spacing; The substrate is divided into four identical areas for encapsulating the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem, and provides supporting peripheral circuits and connection circuits for the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem, so as to form a SIP chip for signal processing; The number and position of the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem can be configured according to actual needs.

2. According to claim 1, a heterogeneous reconfigurable signal processing SIP chip is characterized in that The first sub-microsystem includes a CPU, FLASH and cache; FLASH is used to store the CPU configuration program, the cache is used to store the intermediate data during the CPU operation process, and the CPU completes the corresponding signal control function according to the configured program.

3. A heterogeneous reconfigurable signal processing SIP chip according to claim 1, characterized in that The cache is SRAM or DDR.

4. According to claim 1, a heterogeneous reconfigurable signal processing SIP chip is characterized in that The second sub-microsystem includes a cache DDR, a data interface chip, an AD, and a DA; DDR is used to implement high-speed data caching, high-speed interface chips are used to implement data exchange with the outside, AD is used to perform analog-to-digital conversion on signals, DA is used to perform digital-to-analog conversion on signals, and FPGA completes the corresponding signal processing functions according to the configured program.

5. According to claim 1, a heterogeneous reconfigurable signal processing SIP chip is characterized in that The second sub-microsystem includes a cache DDR, a data interface chip, and a radio frequency chip; DDR is used to implement high-speed data caching, the interface chip is used to implement data exchange with the outside, the RF chip is used to receive RF signals and perform RF signal processing; FPGA completes the corresponding signal processing function according to the configured program.

6. A heterogeneous reconfigurable signal processing SIP chip according to claim 1, characterized in that The third sub-microsystem includes DSP, cache DDR, data interface chip DDR is used to implement high-speed data caching, the data interface chip is used to implement data exchange between the third sub-microsystem and the outside; DSP is used to complete corresponding calculation and processing functions according to the configured program.

7. A heterogeneous reconfigurable signal processing SIP chip according to claim 1, characterized in that The packaging form adopted by the first sub-microsystem, the second sub-microsystem and the third sub-microsystem is plastic packaging or metal cap packaging.

8. A heterogeneous reconfigurable signal processing SIP chip according to claim 1, characterized in that From the perspective of packaging cost, plastic packaging gives priority to packaging fully wire-bonded bare cores, followed by full flip-chip packaging, and finally mixed packaging of wire bonding and flip-chip can be used. From the perspective of process implementation, metal caps can only be used for fully flip-chip bare cores.

9. The heterogeneous reconfigurable signal processing SIP chip according to claim 1, characterized in that: The substrate is packaged in ceramic BGA packaging.

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