Weight accumulation circuit applied to in-memory calculation

Abstract

The invention discloses a weight accumulation circuit applied to in-memory calculation, and belongs to the field of integrated circuits. The method comprises the following steps of: designing a new weight accumulation circuit for in-memory calculation; by changing the positions and the operation time sequence of the switch pair transistors of the highest-bit capacitor, the highest-bit capacitor is excluded from a charge sharing process and is stored in a capacitor which is irrelevant to weight and has a capacitance value set to be smaller than the capacitance value of a unit capacitor, so that the area of the whole accumulation circuit is greatly reduced; moreover, the charging time of a large capacitor at the highest bit can be avoided in one accumulation period, and the accumulation of different weight voltages can be quickly completed. And meanwhile, the capacitance value of the highest-bit capacitor is very small, so that the parasitic effect of large capacitance on the whole circuit is reduced, and the non-ideal effect of the circuit is reduced. Compared with a traditional multi-group capacitor sampling accumulation circuit, the multi-group capacitor sampling accumulation circuit has the advantages that under the condition that the circuit area overhead is reduced by about 50%, accumulation with higher speed and higher precision can be completed through fewer time sequences.

Description

Technical Field

[0001] The invention relates to a weight accumulation circuit applied to in-memory calculation, belonging to the technical field of integrated circuits. Background Art

[0002] At present, computing in memory (CIM) chips have shown unique advantages in processing convolutional neural network algorithms, computer vision, and big data processing. Computing in memory chips are mainly composed of computing device arrays. For given different signal stimuli applied to the device array, these signals are first multiplied by the weights stored in the device, and then the results are accumulated. The results are quantized into digital signals through the readout circuit and finally transmitted to the digital processing unit. Computing in memory chips can usually efficiently complete vector-matrix multiplication operations, greatly improving the computing speed while ensuring low power consumption.

[0003] The current method of implementing weighted accumulation in the analog domain is to input the result of a stimulus in multiple times. The analog accumulation circuit is responsible for weighted accumulation of multiple operation results of the array, and finally converts the accumulated signal into a digital signal through the ADC for processing. This method can effectively reduce the number of ADC analog-to-digital conversions, thereby reducing power consumption and increasing speed.

[0004] The commonly used weight accumulation methods in the analog domain are weighted capacitor circuits and weighted current mirror circuits. The weighted capacitor circuit uses a weighted capacitor circuit distributed by bit to store multiple currents generated by the storage array under the bit-by-bit digital input, and accumulates them by charge sharing after all weighted capacitors are charged. The circuit structure of 4-bit voltage weight accumulation is shown in the figure. Figure 1 As shown, the switch pair is connected to the corresponding weight capacitor, the lower plate of the capacitor is grounded, and the columns with different weights are connected in parallel. The capacitance values ​​of the weight capacitor array are: C 0 , 2C 0 、4C 0 and 8C 0 . Among them, C 0 is the unit capacitance value. The voltage signal is input to V in port, SW_VIN is turned on, and SW_0, SW_1, SW_2 and SW_3 are turned on in sequence to charge the capacitor. After the capacitor is charged, the switches SW_0, SW_1, SW_2 and SW_3 are turned off to maintain the capacitor charge. After the last capacitor is charged, the switch SW_VIN is turned off, and the other capacitor switches SW_0, SW_1, SW_2 and SW_3 are turned on to share the charge and obtain the accumulated voltage V OUT , the voltage signal is V 0 R+2V 1 R+4V2 R+8V 3 R is accumulated and output. However, in order to achieve the accumulation of high-bit weights, it is necessary to increase the capacitance of the capacitor corresponding to the high-bit weight, and this increase is exponential, which will cause the capacitance of the highest bit to be too large, which will not only occupy a large area and be unfavorable for integration, but also consume a lot of time for the charging and discharging of the capacitor, and the speed is slow. In addition, the large capacitor will bring greater parasitic effects to the circuit, resulting in significant errors.

[0005] at present Figure 1 In order to avoid the problem of too large capacitance of high-bit capacitors, the accumulation circuit shown in the figure uses a current mirror to multiply the high-bit current output by the storage device for the N-bit voltage accumulation circuit, and then converts it into a voltage signal to charge the high-bit capacitor. When the high-bit current is expanded by M times, the converted voltage signal is also expanded by M times accordingly, and the corresponding weight capacitor is scaled by M times, so as to achieve the purpose of ensuring the accumulation of weights while reducing the capacitance of high-bit capacitors. However, when N is large, the expansion multiple of the current mirror will also increase. A larger current mirror will not only bring a lot of extra area and power consumption, but also with the increase of current mirrors, the random mismatch error introduced will also increase, which will bring a lot of errors to the circuit.

[0006] Another typical weighted accumulation structure is to use current mirrors for accumulation calculation, using multiple current mirrors to copy the current generated by the storage device in sequence, where each current mirror uses a different weight to copy, and finally the current copied by each current mirror is accumulated, thus forming an operation of accumulating different currents according to weights. The circuit structure of 4-bit current weighted accumulation is shown in Figure 1. Figure 2 As shown, the input current enters from the first current mirror and flows out from the first current mirror at a current of one times. The corresponding gate voltage is stored in the sample-and-hold circuit. According to the above method, the current is copied from the second, third, and fourth current mirrors at 2, 4, and 8 times, respectively. In this way, the accumulated current can be calculated according to I 1 +2I 2 +4I 3 +8I 4 Although this solution uses multiple sets of current mirrors to achieve different weight accumulation, the increase in the number of current mirrors will not only increase the circuit area, but also reduce the accuracy of the current generated by the storage device due to the process mismatch between the current mirrors; in addition, the larger the weight, the larger the width-to-length ratio of the required current mirror MOS tube, and the larger the area and parasitic effect of the corresponding MOS tube, resulting in an excessively large area and reduced accuracy of the current accumulation circuit, which is not conducive to large-scale integration.

[0007] In summary, the above methods all realize the cumulative calculation of signals, but there are the following problems in the application of storage and computing integrated chips, which greatly limit the performance of the storage and computing integrated chips: First, in the application of traditional accumulation structures in high-precision calculations, the area of ​​the capacitor will increase with the increase of weight, which will introduce a large area power consumption; secondly, the accumulation circuit will introduce additional parasitic effects while introducing a larger area, which will lead to signal delay, attenuation, crosstalk and noise problems, affecting the timing and signal integrity of the circuit, thereby reducing the calculation accuracy of the circuit; these problems jointly restrict the performance of the storage and computing integrated chip. Summary of the invention

[0008] In order to solve the problems of current weight accumulation circuits, such as large circuit area, which is not conducive to integration, and low accumulation calculation accuracy, the present invention provides a weight accumulation circuit for in-memory calculation. The N-bit voltage accumulation weight circuit is composed of a switch pair and a capacitor array. The circuit structure is as follows: Figure 3 As shown, the switch pair is connected to the corresponding weight capacitor, the lower plate of the capacitor is grounded, the lower plate of the highest bit weight capacitor is connected to the drain of the switch pair, and the columns with different weights are connected in parallel. The capacitor array is arranged from left to right: CAP_0, CAP_1, CAP_2, CAP_3, ..., CAP_N-2, CAP_N, CAP_N-1; among them, CAP_0, CAP_1, CAP_2, CAP_3, ..., CAP_N-2 are weight capacitors, CAP_N is a compensation capacitor; CAP_N-1 is the highest bit weight capacitor; the capacitance values ​​are: C 0 , 2 1 C 0 , 2 2 C 0 , 2 3 C 0 , …, 2 N-2 C 0 , C 0 , C M . C 0 is the unit capacitance; the capacitance of the highest bit weight capacitor can take any appropriate value according to the situation. Within the range allowed by the accuracy requirement, the more beneficial value should be smaller than the unit capacitance.

[0009] The working process of the voltage weight accumulation circuit includes:

[0010] (1) The voltage signal is input to the drain end of the input switch pair of the accumulator circuit. The input switch pair gives the input voltage to the corresponding weight of 2. 0 The capacitor is charged, and the amount of charge stored is V 0 C 0 After charging is completed, the corresponding switch tube is turned off and the corresponding weight is 2. 1The capacitor switches and charges it. The charge stored in the capacitor is 2V. 1 C 0 , and so on, the weight is 2 0 ~2 N-2 After charging, the voltage on the upper plate of the compensation capacitor is set to 0.

[0011] (2) After completing the above capacitor charging process, the weight is 2 N-1 The highest bit capacitor is charged to V N-1 After charging, turn on the corresponding weight of 2 0 ~2 N-2 The capacitor switch is turned on, and the switch of the compensation capacitor CAP_N is turned on to connect the upper plates of the capacitors to share the charge. The resulting shared charge Q sharing for:

[0012] Q sharing =V 0 C 0 +2V 1 C 0 +4V 2 C 0 +…2 N-2 V N-2 C 0 (1)

[0013] Among them, V 0 Represents the weighted capacitance C 0 The charging voltage, V 1 Represents the weighted capacitance C 1 The charging voltage, V 2 Represents the weighted capacitance C 2 The charging voltage, V N-2 Indicates the charging voltage of the weight capacitor CAP_N-2. The capacitor CAP_N-1 with the highest bit weight does not participate in charge sharing.

[0014] The total capacitance of the shared capacitor is C total for:

[0015] C total =2 0 C 0 +2 1 C 0 +…2 N-2 C 0 +C 0 =2 N-1 C 0 (2)

[0016] The shared voltage value V sharing for:

[0017]

[0018] After completing the above sharing operation, since the capacitor of the highest bit does not participate in charge sharing, it is necessary to set the voltage V of the capacitor of the highest bit that does not participate in weight accumulation N-1 The shared voltage V with other capacitors after charge sharing sharing Add together to get the final output voltage V out1 , whose expression is:

[0019] V out1 =V sharing +V N-1 (4)

[0020] According to Kirchhoff's voltage law, the output voltage V OUT The expression is:

[0021] V OUT =V sharing -V N-1 (5)

[0022] The present invention makes the charging current direction of the highest bit capacitor opposite to the charging current direction of other capacitors, so the highest bit weight voltage V N-1 The shared voltage V after sharing charge with other capacitors sharing Add together to get the final output voltage V out1 , and the output voltage V OUT The expression is consistent.

[0023] Substituting into the above voltage expression, we get the output V OUT The expression is:

[0024]

[0025] V OUT That is the result of the accumulation of N bit voltage weights.

[0026] The beneficial effects of the present invention are:

[0027] By changing the position and operation timing of the highest bit capacitor switch, the capacitor of the highest bit is excluded from the charge sharing process and stored in a capacitor that is independent of the weight and has a capacitance value set to be less than the unit capacitance value, which greatly reduces the overall accumulation circuit area, and can avoid the charging time of the highest bit large capacitor in one accumulation cycle, and can quickly complete the accumulation of voltages with different weights. At the same time, since the capacitance of the highest bit capacitor is very small, the parasitic effect of the large capacitor on the whole is reduced, the non-ideal effect of the circuit is reduced, and the calculation accuracy of the circuit is improved. Compared with the traditional multi-group capacitor sampling and accumulation circuit, the present invention can reduce the circuit area overhead by about 50%, and complete faster and more accurate accumulation through less timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 It is a typical 4-bit capacitor accumulation structure circuit diagram;

[0030] Figure 2 It is a typical 4-bit current mirror accumulation structure circuit diagram;

[0031] Figure 3 It is a schematic diagram of a capacitor accumulation structure circuit for in-memory calculation proposed by the present invention;

[0032] Figure 4 1 is a schematic diagram of a transimpedance amplifier circuit for IV conversion provided by Embodiment 1 of the present invention;

[0033] Figure 5 It is an overall schematic diagram of a current weight accumulation circuit applied to in-memory calculation provided by the first embodiment of the present invention;

[0034] Figure 6 An overall schematic diagram of a voltage weight accumulation circuit for in-memory calculation provided by Embodiment 2 of the present invention;

[0035] Figure 7 A timing diagram of a voltage weight accumulation circuit for in-memory calculation provided in the second embodiment of the present invention;

[0036] Figure 8 A simulation result diagram of a voltage weight accumulation circuit for in-memory calculation provided in the second embodiment of the present invention;

[0037] Fig. 9 This is a diagram of simulation results of a typical 4-bit voltage weight accumulation circuit provided in the second embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the present invention clearer, the following will further describe the implementation mode of the present invention in detail with reference to the accompanying drawings. First, the basic theoretical knowledge involved in the present invention is introduced as follows:

[0039] Transimpedance Amplifier:

[0040] The transimpedance amplifier consists of a gain of A 0 The single-ended output operational amplifier and feedback resistor are composed of the circuit structure as shown in Figure 4 As shown, the positive input of the operational amplifier is set to the reference voltage V ref , the negative input and output are connected through a feedback resistor to form a voltage parallel negative feedback. The working principle of the transimpedance amplifier is based on Ohm's law and Kirchhoff's current law. When the input current flows through the transimpedance amplifier, according to Ohm's law, the current will produce a voltage drop. At the same time, due to the effect of negative feedback, the output voltage will make the input current equal to the feedback current. When the operational amplifier gain is greater than 60db, it can be considered that the output voltage V ota_out =I in R+V ref .

[0041] Embodiment 1

[0042] This embodiment provides a current weight accumulation method for in-memory calculation. The method takes a 4-bit binary current weight accumulation circuit as an example. Figure 5 As shown, the circuit includes a transimpedance amplifier, six switch pairs and a weight capacitor array corresponding to the switch pairs; the six switch pairs are respectively a first switch pair SW_0, a second switch pair SW_1, a third switch pair SW_2, a fourth switch pair SW_4, a fifth switch pair SW_VIN, and a sixth switch pair SW_3; the weight capacitor array includes a first weight capacitor CAP_0, a second weight capacitor CAP_1, a third weight capacitor CAP_2, a compensation capacitor CAP_4 and a fourth weight capacitor CAP_3.

[0043] The non-inverting input of the transimpedance amplifier is connected to the reference voltage V ref , the inverting input terminal is connected to the input current I in, the inverting input end is also connected to the output end of the cross-group amplifier through a resistor R; in the weight capacitor array, one end of the first switch pair SW_0, the second switch pair SW_1, the third switch pair SW_2 and the fourth switch pair SW_4 are respectively connected to the upper plates of the first weight capacitor CAP_0, the second weight capacitor CAP_1, the third weight capacitor CAP_2 and the compensation capacitor CAP_4, and the lower plates of the first weight capacitor CAP_0, the second weight capacitor CAP_1, the third weight capacitor CAP_2 and the compensation capacitor CAP_4 are connected to each other and grounded; the lower plate of the fourth weight capacitor CAP_3 is connected to the output V out , and is also connected to the lower plates of other weight capacitors through the sixth switch pair SW_3; the upper plate of the fourth weight capacitor CAP_3 is connected to the other ends of the first switch pair SW_0, the second switch pair SW_1, the third switch pair SW_2 and the fourth switch pair SW_4, and is connected to the output end of the transimpedance amplifier through the fifth switch pair SW_VIN; columns with different weights in the capacitor array are connected in parallel.

[0044] The method includes:

[0045] (1) The input current is converted into a voltage through the IV of the transimpedance amplifier and then input into the drain end of the input switch tube of the accumulator circuit;

[0046] (2) The input switch tube charges the capacitor array with the corresponding weight value with the input voltage, stores the charge of the corresponding weight, closes the corresponding switch tube after charging, and then opens the capacitor switch of the next column with the corresponding weight value and charges it, and stores the charge of the corresponding weight, and so on. After multiple currents are converted by IV, the weight capacitors of each column are charged in turn;

[0047] (3) When all capacitors are charged, close the switch of the capacitor with the highest bit weight, open all other capacitor switches to interconnect the upper plates and participate in charge sharing, while the capacitor with the highest bit weight does not participate in charge sharing;

[0048] (4) After sharing is completed, the weighted accumulated value is directly output at the output end, and its weight is determined by the number of input currents;

[0049] The capacitances of the first weight capacitor CAP_0, the second weight capacitor CAP_1, the third weight capacitor CAP_2 and the fourth weight capacitor CAP_3 are: C 0 , 2C 0 、4C 0 and C M , the capacitance of compensation capacitor CAP_4 is C 0 In this example,

[0050] The input voltage in this embodiment includes a reference voltage and a weighted voltage involved in the accumulation, wherein the compensation capacitor is charged to the reference voltage. In this embodiment, the reference voltage is set to V ref =0.9V; the working process of the current weight accumulation circuit includes:

[0051] (1) The fifth switch pair SW_VIN is closed, and all other switches are in the open state;

[0052] (2) Close the first switch pair SW_0, and the storage device outputs current I 0 After IV conversion, V 0 =I 0 R+V ref Then it is input to the drain end of the input switch tube of the accumulation circuit, and the input voltage V 0 Charge the first weighted capacitor CAP_0, and the amount of charge charged is Q 0 =C 0 V 0 ;

[0053] (3) The first switch pair SW_0 is disconnected, and the second switch pair SW_1 is closed. The storage device outputs a current I 1 After IV conversion, V 1 =I 1 R+V ref Then it is input to the drain end of the input switch tube of the accumulation circuit, and the input voltage V 1 The second weight capacitor CAP_1 is charged, and the amount of charge charged is Q 1 =2C 0 V 1 ;

[0054] (4) The second switch pair SW_1 is turned off, and the third switch pair SW_2 is turned on. The storage device outputs a current I 2 After IV conversion, V 2 =I 2 R+V ref Then it is input to the drain end of the input switch tube of the accumulation circuit, and the input voltage V 2 Charge the third weight capacitor CAP_2, and the amount of charge charged is Q 2 =4C 0 V 2 ;

[0055] (5) The third switch pair SW_2 is turned off, and the fourth switch pair SW_4 is turned on. The input reference voltage V ref Charge the compensation capacitor CAP_4 with a charge of Q 4 =C 0 V ref ;

[0056] (6) Disconnect the fourth switch pair SW_4 and close the sixth switch pair SW_3. Optionally, the storage device outputs a current I 3 After being copied by the inverting current mirror, -I 3 , get V through IV conversion 3 =-I 3 R+V ref Then it is input to the drain end of the input switch tube of the accumulation circuit, and the input voltage V 3 The fourth weighted capacitor CAP_3 is charged, and the amount of charge charged is Q 3 =8C 0 V 3 ;

[0057] (7) When all capacitors are charged, the highest bit weight capacitor switch is disconnected, and all other capacitor switches are closed to interconnect the upper plates and participate in charge sharing. The highest bit weight capacitor does not participate in charge sharing.

[0058] (8) After sharing is completed, the binary accumulated value of the current is directly output at the output end of the circuit:

[0059]

[0060] This is equivalent to completing the binary weighted accumulation of the current of the storage and computing device.

[0061] The weighted accumulation circuit provided by the present invention utilizes a plurality of columns of capacitor switch pairs to sequentially store and accumulate the input voltage values, and controls the amount of stored charge by setting the capacitance value of the capacitor to assign a weight to the stored current. Compared with the existing traditional capacitor sampling accumulation and the scheme of accumulation through current mirror and capacitor, the present invention can not only greatly reduce the overall accumulation circuit area, but also avoid the charging time of the highest bit large capacitor in one accumulation cycle, and can quickly complete the accumulation of input current. At the same time, since the upper plate of the highest bit capacitor does not participate in sharing, the high-order large capacitor is avoided without introducing an additional high-power current mirror, reducing the parasitic effect of the large capacitor on the whole, and reducing the non-ideal effect of the circuit.

[0062] Embodiment 2

[0063] This embodiment provides a voltage weight accumulation method for in-memory calculation. The method takes a 4-bit binary voltage weight accumulation circuit as an example. Figure 6As shown, it includes six switch pairs and corresponding weight capacitor arrays; the six switch pairs are respectively the first switch pair SW_0, the second switch pair SW_1, the third switch pair SW_2, the fourth switch pair SW_4, the fifth switch pair SW_VIN, and the sixth switch pair SW_3; the weight capacitor array includes the first weight capacitor CAP_0, the second weight capacitor CAP_1, the third weight capacitor CAP_2, the compensation capacitor CAP_4 and the fourth weight capacitor CAP_3.

[0064] Input voltage V IN The first switch pair SW_0, the second switch pair SW_1, the third switch pair SW_2, the fourth switch pair SW_4 and the upper plate of the fifth weight capacitor CAP_3 are connected through the fifth switch pair SW_VIN; the other ends of the first switch pair SW_0, the second switch pair SW_1, the third switch pair SW_2 and the fourth switch pair SW_4 are respectively connected to the upper plates of the first weight capacitor CAP_0, the second weight capacitor CAP_1, the third weight capacitor CAP_2 and the fourth weight capacitor CAP_4, and the lower plates of the first weight capacitor CAP_0, the second weight capacitor CAP_1, the third weight capacitor CAP_2 and the compensation capacitor CAP_4 are connected to each other and grounded; the lower plate of the fourth weight capacitor CAP_3 is connected to the output V out , and the sixth switch pair SW_3 is connected to the lower plates of other weight capacitors; columns with different weights in the capacitor array are connected in parallel.

[0065] The capacitances corresponding to the first weighted capacitor CAP_0, the second weighted capacitor CAP_1, the third weighted capacitor CAP_2, the compensation capacitor CAP_4 and the fourth weighted capacitor CAP_3 are: C 0 、2C 0 、4C 0 , C M , the capacitance of compensation capacitor CAP_4 is C 0 In this example,

[0066] The input voltage in this embodiment includes a common mode voltage and a weighted voltage involved in the accumulation, wherein the compensation capacitor is only charged to the common mode voltage, and in this embodiment, the common mode voltage is set to 0V;

[0067] The timing sequence of the voltage weight accumulation circuit provided in this embodiment is as follows: Figure 7 As shown, the working process of the voltage weight accumulation circuit includes:

[0068] (1) The fifth switch pair SW_VIN is closed, and all other switches are open;

[0069] (2) Close the first switch SW_0, and the input voltage V0 Charge the first weighted capacitor CAP_0, and the amount of charge charged is Q 0 =C 0 V 0 ;

[0070] (3) Disconnect the first switch pair SW_0 and close the second switch pair SW_1. The input voltage V 1 The second weight capacitor CAP_1 is charged, and the amount of charge charged is Q 1 =2C 0 V 1 ;

[0071] (4) The second switch pair SW_1 is turned off, and the third switch pair SW_2 is turned on. The input voltage V 2 Charge the third weight capacitor CAP_2, and the amount of charge charged is Q 2 =4C 0 V 2 ;

[0072] (5) Disconnect the third switch pair SW_2, close the fourth switch pair SW_4, and input the common mode voltage V 4 The compensation capacitor CAP_4 is charged because the common-mode voltage V 4 The value of is 0, so the amount of charge charged is 0;

[0073] (6) The fourth switch pair SW_4 is turned off, and the sixth switch pair SW_3 is turned on. The input voltage V 3 Reverse charge the fourth weight capacitor CAP_3, and charge the upper plate of the fourth weight capacitor CAP_3 to a voltage of -V 3 ;

[0074] (7) The sixth switch pair SW_3 is turned off, and the first switch pair SW_0, the second switch pair SW_1, the third switch pair SW_2, and the fourth switch pair SW_4 are turned on at the same time. The upper plates of the capacitors are connected to share charge, and the highest bit capacitor does not participate in charge sharing.

[0075] (8) Finally, after the sharing process is completed, the accumulation process of the weight circuit is realized, and the output voltage value after accumulation is expressed as:

[0076]

[0077] It is further illustrated by examples that the invention can not only greatly reduce the area of ​​the overall accumulation circuit, but also avoid the charging time of the large capacitor of the highest bit in one accumulation cycle, and can quickly complete voltage accumulation.

[0078] The voltage weight accumulation circuit of this embodiment is simulated by selecting any set of input voltages (not unique) for simulation. In this experiment, V 0 =8mV, V 1 =4mV, V 2 =2mV, V 3 = -1mV is a set of 4-bit excitation for simulation, such as Figure 8 As shown, M1, M2, M3, M4 and M5 correspond to V 0 、V 1 、V 2 、V 3 and V out The voltage of each bit can be established with sufficiently high accuracy within 20ns, and stabilized within 7ns after charge sharing. The output value is 2.002mV, and the error is no more than 0.1% compared with the theoretical value. The high-precision requirement is achieved while ensuring speed.

[0079] The simulation results of the traditional accumulation circuit are as follows: Fig. 9 As shown, M6, M7, M8, M9 and M10 correspond to V 0 、V 1 、V out 、V 2 and V 3 ; While ensuring that the unit capacitance value is the same as that of the above-mentioned accumulation circuit, the same set of 4-bit voltage excitation is given, and voltage sharing is performed after 4 voltage excitation inputs. From the simulation results, it can be seen that the capacitance of the highest bit can be established to a sufficiently high accuracy within 70ns, and the charge sharing can stably output 2.024mV within 20ns, with an error of 1.2%, which is slow compared to the present invention. At the same time, the capacitance value of the highest bit of the traditional accumulation circuit is often half of the total capacitance value of the entire accumulation circuit. The larger capacitance introduces a large parasitic capacitance to the storage and computing circuit, thereby affecting the accuracy and speed of the entire storage and computing circuit.

[0080] The present invention can achieve a total capacitance value of up to half of that of a traditional accumulation circuit by reasonably selecting the capacitance of the highest bit. Therefore, the present invention has the advantages of higher speed and lower area while ensuring accuracy. Compared with traditional multi-group capacitor sampling and accumulation circuits, the present invention can complete accumulation with less timing and higher accuracy. Simulations have proved that the present invention can effectively improve the accumulation speed and accuracy while reducing the circuit area.

[0081] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0082] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A weight accumulation circuit for in-memory computing, characterized in that: The circuit includes a plurality of switch pairs, a weight capacitor array and a compensation capacitor; the weight capacitor array includes N weight capacitors, which are connected in parallel in order from low to high weights, and the upper plates of the weight capacitors other than the highest bit weight capacitor in the weight capacitor array are respectively connected to the corresponding switch pairs and connected to the input voltage, and the lower plates are grounded; the upper plate of the highest bit weight capacitor is connected to the input voltage, and the lower plate is grounded through the switch pair, and the lower plate of the highest bit weight capacitor is also connected to the circuit output end; the upper plate of the compensation capacitor is connected to the corresponding switch pair, and the lower plate is grounded, connected in parallel with the weight capacitor array and located between the highest bit weight capacitor and other weight capacitors in the weight capacitor array; the input voltage is connected to the weight capacitor array through the switch pair.

2. The circuit according to claim 1, characterized in that The N weighted capacitors in the weighted capacitor array are respectively recorded as: CAP_0, CAP_1, CAP_2, CAP_3, ..., CAP_N-2, CAP_N-1; the capacitance values ​​are respectively: C0, 2 1 C0,2 2 C0,2 3 C0,…,2 N-2 C0, C M ; The compensation capacitor is denoted as CAP_N, and its capacitance is C0; Among them, C0 represents the unit capacitance, CAP_N-1 represents the highest bit weight capacitor, and its capacitance C M The value range is 0.2C0~C0.

3. A weight accumulation method for in-memory computing, characterized in that: The method is implemented based on the weight accumulation circuit described in claim 1 or 2, and the method includes: a voltage signal is input into the weight accumulation circuit through a switch pair, the weight capacitor is charged through the switch pair corresponding to the weight capacitor, and the corresponding switch pair is closed after the charging is completed; the above operation is performed on each weight capacitor until the highest bit weight capacitor is charged; after the charging is completed, the switch pair corresponding to the compensation capacitor is opened to share the charge, wherein the highest bit weight capacitor does not participate in the charge sharing.

4. The method according to claim 3, characterized in that The shared charge Q obtained after charge sharing sharing for: Q sharing =V0C0+2V1C0+4V2C0+…2 N-2 V N-2 C0 Wherein, V0 represents the charging voltage of weight capacitor C0, V1 represents the charging voltage of weight capacitor C1, V2 represents the charging voltage of weight capacitor C2, V N-2 Indicates the charging voltage of the weight capacitor CAP_N-2. The capacitor CAP_N-1 with the highest bit weight does not participate in charge sharing. The total value of the shared capacitor C total for: C total =2 0 C0+2 1 C0+…2 N-2 C0+C0=2 N-1 C0 The voltage value after sharing V sharing for:

5. The method according to claim 4, characterized in that The voltage V of the highest bit capacitor that does not participate in charge sharing N-1 The voltage V after charge sharing with other capacitors sharing Add them together to get the weighted accumulated output V out1 , whose expression is: V out1 =V sharing +V N-1 According to Kirchhoff's law, the output voltage V OUT for: V OUT =V sharing -V N-1 The present invention makes the charging current direction of the highest bit weight capacitor opposite to the charging current direction of other weight capacitors, so the voltage V N-1 The shared voltage V after sharing charge with other weight capacitors sharing The final output voltage V out1 With the output voltage V OUT The expressions are consistent; The shared voltage V sharing Bring in V OUT The output result of voltage weight accumulation is obtained by the expression:

6. A current weight accumulation method for in-memory calculation, characterized in that: The method is implemented based on the circuit and transimpedance amplifier described in claim 1 or 2 and the method described in any one of claims 3 to 6, and the current weight accumulation method includes: Step 1: The input current is converted into a voltage through the IV of the transimpedance amplifier and then input into the drain end of the input switch pair of the weight accumulation circuit; Step 2: The input switch tube charges the capacitor array with the corresponding weight value with the input voltage, stores the charge of the corresponding weight, closes the corresponding switch tube after charging, and then opens the capacitor switch of the next column with the corresponding weight value, and charges it, and stores the charge of the corresponding weight, and so on. After multiple currents are converted by IV, the weight capacitors of each column are charged in turn; Step 3: When all capacitors are charged, close the switch of the capacitor with the highest bit weight, and open all other capacitor switches to interconnect the upper plates and participate in charge sharing. The capacitor with the highest bit weight does not participate in charge sharing. Step 4: After sharing is completed, the weighted accumulated value is directly output at the output end, and its weight is determined by the number of input currents.

7. A voltage weight accumulation method for in-memory calculation, characterized in that: The method realizes voltage weighted accumulation based on the circuit described in claim 1 or 2 and the method described in any one of claims 3 to 6.

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