Apparatus and method for generating clock

Abstract

An apparatus and method for generating a clock are provided. The apparatus includes: a phase-locked loop circuit generating a first clock signal having a specified frequency through an oscillator; a monitoring circuit monitoring a first bit error rate (BER) of a first signal received in response to the first clock signal; and a control logic circuit controlling the phase-locked loop circuit based on the monitoring result. The control logic circuit connects a first boost current source included in the phase-locked loop circuit to the oscillator when the first bit error rate is equal to or greater than a preset threshold value, and disconnects a second boost current source previously connected to the oscillator from the oscillator when the first bit error rate is less than the threshold value.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0159217 filed in the Korean Intellectual Property Office on November 16, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to an apparatus and method for generating a clock. Background Art

[0003] A phase-locked loop (PLL) circuit and a clock generation device including the phase-locked loop circuit can generate a clock signal with a locked phase. For example, the clock signal can be used to send data in a transmitter or to recover data in a receiver. In this case, the phase-locked loop circuit can be divided into a loop-PLL circuit and an inductor-capacitor (LC)-PLL circuit.

[0004] Recently, in order to improve the noise characteristics of a phase-locked loop circuit, a technology for controlling the intensity of power used in the operation of the phase-locked loop circuit has been studied.

[0005] For example, a manner of controlling the operation of the phase-locked loop circuit is adopted using the amount of power required when the signal received by the receiver has the highest noise characteristics.

[0006] However, in this case, even if the noise characteristics of the signal received by the receiver are changed, because the magnitude of power used to control the phase-locked loop circuit is fixed, the power efficiency of the operation of the phase-locked loop circuit may be reduced. Summary of the invention

[0007] The present disclosure relates to an apparatus for generating a clock capable of controlling power applied to a phase locked loop circuit based on the signal quality of a signal received in response to the clock signal.

[0008] In some embodiments, a device for generating a clock may include: a phase-locked loop circuit that generates a first clock signal having a specified frequency through an oscillator; a monitoring circuit that monitors a first bit error rate (BER) of a first signal received in response to the first clock signal; and a control logic circuit that controls the phase-locked loop circuit based on the monitoring result. The control logic circuit may connect a first boost current source included in the phase-locked loop circuit to the oscillator when the first bit error rate is equal to or greater than a preset threshold, and disconnect a second boost current source previously connected to the oscillator from the oscillator when the first bit error rate is less than the threshold.

[0009] In some embodiments, a method for generating a clock may include: monitoring a first bit error rate of a first signal received in response to a first clock signal, the first clock signal having a specified frequency; when the first bit error rate is equal to or greater than a threshold, connecting a first boost current source to an oscillator, the first boost current source being included in a phase-locked loop circuit; and when the first bit error rate is less than the threshold, disconnecting a second boost current source from the oscillator, the second boost current source being previously connected to the oscillator.

[0010] In some embodiments, a device for generating a clock may include: a phase-locked loop circuit that generates a first clock signal having a specified frequency through an inductor-capacitor oscillator; a monitoring circuit that monitors a first bit error rate of a first signal received in response to the first clock signal; and a control logic circuit that controls the phase-locked loop circuit based on the monitoring result. The inductor-capacitor oscillator may include: an inductor-capacitor tank circuit, in which an inductor and a capacitor are connected in parallel, and a plurality of cells, each of which includes a plurality of transistors, the plurality of cells may be connected in parallel to each other, and the control logic circuit may connect a first cell from among the plurality of cells to the inductor-capacitor tank circuit when the first bit error rate is equal to or greater than a threshold value. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0012] Figure 1A is a block diagram illustrating an example of a device for generating a clock.

[0013] Figure 1B Show Figure 1A An example of a configuration in which a control logic circuit controls a phase-locked loop circuit.

[0014] Figure 2 An example of a configuration in which a control logic circuit controls a phase-locked loop circuit using a boost current source is shown.

[0015] Figure 3 An example of a configuration in which a control logic circuit controls a phase-locked loop circuit using an over-clock current source is shown.

[0016] Figure 4A An example of a configuration in which a control logic circuit controls the gain of a loop filter is shown.

[0017] Figure 4B is shown connected to Figure 4A A circuit diagram of an example of a configuration of an oscillator, a phase detector, and a loop filter.

[0018] Figure 4C Shown in Figure 4A Example gain of a loop filter under the control of a control logic circuit.

[0019] Figure 5 An example of a configuration in which a control logic circuit controls a phase-locked loop circuit using a boost current source and an overclock current source is shown.

[0020] Figure 6 An example of a configuration in which a control logic circuit controls a phase-locked loop circuit using a boost current source and a loop filter is shown.

[0021] Figure 7 An example of a configuration in which a control logic circuit controls a phase-locked loop circuit using an overclocked current source and a loop filter is shown.

[0022] Figure 8 An example of a configuration in which a control logic circuit controls a phase-locked loop circuit using a boost current source, an overclocking current source, and a loop filter is shown.

[0023] Fig. 9 is a flow chart illustrating an example of a method for controlling a phase locked loop circuit.

[0024] Fig. 10A is a flow chart illustrating an example of a method for controlling a phase locked loop circuit using a boost current source.

[0025] Fig. 10B is a diagram showing the control logic circuit according to whether it is operated by the background control Fig. 10A The sequence of flowcharts shown in the flowchart is a flowchart of an example of a method of controlling a phase locked loop circuit.

[0026] Fig.11A is a flow chart illustrating an example of a method for controlling a phase locked loop circuit using an overclocked current source.

[0027] Fig. 11B is a flow chart illustrating an example of a method for controlling a phase-locked loop circuit using a boost current source according to a bit error rate (bit error rate) of a second signal.

[0028] Fig.12 is a flow chart illustrating an example of a method for controlling a phase-locked loop circuit by controlling the gain of a loop filter.

[0029] Fig.13 An example of a clock generating device including an LC oscillator is shown.

[0030] Fig.14 is shown for controlling Fig.13 A flowchart of an example of a method of a clock generation apparatus.

[0031] Fig.15is a block diagram showing an example of a clock generation device which also includes a decoder. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the present disclosure will be described clearly and in detail so that those skilled in the art can easily implement the present disclosure.

[0033] Figure 1A : is a block diagram showing an example of an apparatus for generating a clock (hereinafter, a clock generating device). Figure 1B Show Figure 1A An example of a configuration in which a control logic circuit controls a phase-locked loop circuit.

[0034] Reference Figure 1A and Figure 1B , the clock generating device 100 may include a control logic circuit 110 , a monitoring circuit 120 and a phase-locked loop (PLL) circuit 130 .

[0035] In some embodiments, the clock generating apparatus 100 may include a phase-locked loop circuit 130 that generates a first clock signal CK1 having a specified frequency through an oscillator 131 .

[0036] More specifically, the PLL circuit 130 may generate the first clock signal CK1 having a designated frequency through the oscillator 131 based on the control signal CMD received from the control logic circuit 110 .

[0037] For example, the phase-locked loop circuit 130 may receive a reference signal Sref and output a first clock signal CK1 having the same frequency as that of the reference signal Sref through the oscillator 131 .

[0038] In this case, for example, the oscillator 131 may be understood as a digitally controlled oscillator (DCO) controlled by a digital code. However, for another example, the oscillator 131 may be understood as a voltage controlled oscillator (VCO) controlled by an input analog voltage.

[0039] In addition, for example, the oscillator 131 may be referred to as a ring oscillator including a plurality of inverters connected in series, but the present disclosure is not limited thereto.

[0040] In some embodiments, the clock generating apparatus 100 may include a monitoring circuit 120 for monitoring a bit error rate (BER) of the first signal S1 received in response to the first clock signal CK1 .

[0041] More specifically, the monitoring circuit 120 may monitor a first bit error rate B1 of the first signal S1 received by the receiver RX in response to the first clock signal CK1 .

[0042] For example, the monitoring circuit 120 may monitor the first bit error rate B1 of the first signal S1 based on the distribution of the first signal S1 received by the receiver RX in response to the first clock signal CK1.

[0043] As another example, a signal-to-noise ratio (SNR) of the first signal S1 may be monitored based on a distribution of the first signal S1 received by the receiver RX in response to the first clock signal CK1.

[0044] In other words, the monitoring circuit 120 may monitor (or measure) the signal quality (eg, bit error rate; SNR) of the first signal S1 received in response to the first clock signal CK1 .

[0045] In some embodiments, the clock generating apparatus 100 may include a control logic circuit 110 for controlling the phase-locked loop circuit 130 according to a monitoring result (eg, signal quality of the first signal S1 ) of the monitoring circuit 120 .

[0046] The control logic circuit 110 may generate a control signal CMD for controlling the PLL circuit 130 based on the monitoring result of the monitoring circuit 120 .

[0047] The control logic circuit 110 may execute, for example, software (or a program) for controlling at least one different component (e.g., the phase-locked loop circuit 130) of the clock generation device 100, and may perform various data processing or operations. The control logic circuit 110 may include a central processing unit or a microprocessor, and may control the overall operation of the clock generation device 100. Therefore, it can be understood that the following operations performed by the clock generation device 100 are performed under the control of the control logic circuit 110.

[0048] In some embodiments, the control logic circuit 110 may include an algorithm for controlling at least a portion of the components of the phase-locked loop circuit 130. For example, the algorithm may be a software code programmed into the control logic circuit 110. For another example, the algorithm may be hard-coded into the control logic circuit 110, but the present disclosure is not limited thereto.

[0049] In some embodiments, the control logic circuit 110 may control the current input from the PLL circuit 130 to the oscillator 131 according to an algorithm. In addition, the control logic circuit 110 may control the gain of the loop filter (LF) 142 included in the PLL circuit 130 according to an algorithm.

[0050] Reference Figure 1B The control logic circuit 110 may control the magnitude of the current input to the oscillator 131 of the phase-locked loop circuit 130 based on the first bit error rate B1 of the first signal S1.

[0051] More specifically, the control logic circuit 110 may connect at least a portion of the current sources BC1 and OC1 included in the phase-locked loop circuit 130 to the oscillator 131 based on the first bit error rate B1 of the first signal S1. In an example, the current sources BC1 and OC1 may be separated from each other.

[0052] The control logic circuit 110 may connect the first boost current source BC1 to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold. In this case, for example, the preset threshold may be stored in an internal storage space of the clock generating device 100.

[0053] More specifically, the control logic circuit 110 may connect the first boost current source BC1 to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold, so that the first boost current IB1 is applied to the oscillator 131 together with the basic current Io. For example, the basic current Io is output from the basic current source I0.

[0054] For example, the control logic circuit 110 may close the first switch SW1 disposed between the first boost current source BC1 and the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0055] Furthermore, the control logic circuit 110 may connect the first capacitor C1 corresponding to the first boosting current source BC1 to the output node N1 of the oscillator 131 based on the first boosting current source BC1 being connected to the oscillator 131 .

[0056] More specifically, the control logic circuit 110 may connect the first capacitor C1 having a capacitance corresponding to the first boosting current IB1 to the output node N1 of the oscillator 131 in response to the first boosting current source BC1 being connected to the oscillator 131 .

[0057] For example, the control logic circuit 110 may close the second switch SW2 disposed between the first capacitor C1 and the oscillator 131 in response to the first boost current source BC1 being connected to the oscillator 131 .

[0058] However, in this case, referring to Figure 1B , the first capacitor C1 is illustrated as a single capacitor, but the present disclosure is not limited thereto, and the first capacitor C1 may also be referred to as a component in which a plurality of capacitors are connected in series and / or in parallel.

[0059] In some embodiments, the control logic circuit 110 may connect a first over-clock current source OC1 to the oscillator 131 in response to a first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0060] More specifically, the control logic circuit 110 may connect the first overclocking current source OC1 to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold, so that the first overclocking current IO1 is applied to the oscillator 131 together with the base current Io.

[0061] For example, the control logic circuit 110 may close the third switch SW3 disposed between the first overclocking current source OC1 and the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0062] Furthermore, the control logic circuit 110 may control a coefficient of the frequency divider 150 in response to the first overclocking current source OC1 being connected to the oscillator 131 .

[0063] More specifically, the control logic circuit 110 may control the coefficient of the divider 150 in response to the first overclocking current source OC1 being connected to the oscillator 131 using a value obtained by dividing the current input to the oscillator 131 (e.g., the sum of the base current Io and the first overclocking current IO1) by the base current Io.

[0064] In this case, the first overclocking current IO1 may have a current value that is an integer multiple of the basic current Io.

[0065] Therefore, for example, in response to the first overclocking current IO1 having a current value (3×Io) that is three times the basic current Io being applied to the oscillator 131 , the control logic circuit 110 may control the coefficient of the frequency divider 150 to “4”.

[0066] Referring to the above configuration, the control logic circuit 110 may increase the current applied to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0067] Therefore, the control logic circuit 110 may reduce a first bit error rate B1 of the first signal S1 received in response to the first clock signal CK1 output by the oscillator 131 .

[0068] Furthermore, the control logic circuit 110 may control the frequency of a signal output from the oscillator 131 in response to an increase in the current applied to the oscillator 131 .

[0069] Therefore, the control logic circuit 110 may reduce the first bit error rate B1 of the first signal S1 received in response to the first clock signal CK1 and maintain the frequency of the first clock signal CK1.

[0070] Furthermore, the control logic circuit 110 may disconnect at least a portion of the current sources BC1 and OC1 connected to the oscillator 131 from the oscillator 131 in the phase-locked loop circuit 130 .

[0071] More specifically, the control logic circuit 110 may disconnect at least a portion of the current sources BC1 and OC1 previously connected to the oscillator 131 from the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold.

[0072] The control logic circuit 110 may disconnect the first boosting current source BC1 previously connected to the oscillator 131 from the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold. In this case, it is assumed that the first boosting current source BC1 was previously connected to the oscillator 131.

[0073] More specifically, in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold, the control logic circuit 110 may disconnect the first boost current source BC1 from the oscillator 131 , so that the current applied to the oscillator 131 is reduced.

[0074] For example, in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold, the control logic circuit 110 may disconnect the first switch SW1 disposed between the first boost current source BC1 previously connected to the oscillator 131 and the oscillator 131 .

[0075] In addition, the control logic circuit 110 may disconnect the first capacitor C1 corresponding to the first boosting current source BC1 from the output node N1 of the oscillator 131 based on the first boosting current source BC1 being disconnected from the oscillator 131 .

[0076] For example, the control logic circuit 110 may disconnect the second switch SW2 disposed between the first capacitor C1 and the oscillator 131 in response to the first boost current source BC1 being disconnected from the oscillator 131 .

[0077] In addition, in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold, the control logic circuit 110 may disconnect the first overclocking current source OC1 from the oscillator 131. In this case, it is assumed that the first overclocking current source OC1 was previously connected to the oscillator 131.

[0078] More specifically, in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold, the control logic circuit 110 may disconnect the first overclocking current source OC1 from the oscillator 131 , so that the current applied to the oscillator 131 is reduced.

[0079] For example, the control logic circuit 110 may disconnect the third switch SW3 disposed between the first overclocking current source OC1 previously connected to the oscillator 131 and the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold.

[0080] Furthermore, the control logic circuit 110 may control the coefficient of the frequency divider 150 in response to the disconnection between the first overclocking current source OC1 and the oscillator 131 .

[0081] More specifically, the control logic circuit 110 may control the coefficient of the frequency divider 150 with a value obtained by dividing the current input to the oscillator 131 by the base current Io in response to the first overclocking current source OC1 and the oscillator 131 being disconnected.

[0082] For example, the control logic circuit 110 may control the coefficient of the frequency divider 150 to be “1” in response to the disconnection between the first overclocking current source OC1 and the oscillator 131 .

[0083] Referring to the above configuration, the control logic circuit 110 may reduce the current applied to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold.

[0084] Therefore, the control logic circuit 110 can minimize the power consumed by the PLL circuit 130 to generate the first clock signal CK1 .

[0085] Furthermore, the control logic circuit 110 may control the frequency of a signal output from the oscillator 131 in response to a decrease in the current applied to the oscillator 131 .

[0086] Therefore, the control logic circuit 110 can reduce the power consumption of the PLL circuit 130 and maintain the frequency of the first clock signal CK1.

[0087] Therefore, the control logic circuit 110 of the present disclosure may increase or decrease the magnitude of the current (or power) applied to the PLL circuit 130 based on the signal quality (eg, the first bit error rate B1) of the first signal S1 received in response to the first clock signal CK1.

[0088] Therefore, the clock generating apparatus 100 of the present disclosure can improve the power efficiency of the phase-locked loop circuit 130 based on the signal quality of the first signal S1 received in response to the first clock signal CK1.

[0089] Furthermore, the control logic circuit 110 may control the gain of the loop filter 142 based on a phase difference P1 between the first clock signal CK1 generated from the oscillator 131 and the reference signal Sref.

[0090] More specifically, the control logic circuit 110 may detect the phase difference P1 between the first clock signal CK1 and the reference signal Sref by using the phase detector PD 141. In this case, the control logic circuit 110 may detect the phase difference P1 between a signal obtained by dividing the first clock signal CK1 by an arbitrary positive number (e.g., “N”) and the reference signal Sref.

[0091] In addition, the control logic circuit 110 may control the gain of the loop filter 142 based on the phase difference P1.

[0092] More specifically, the control logic circuit 110 may generate a gain control signal Gc for controlling the gain of the loop filter 142 based on a phase difference P1 between the first clock signal CK1 and the reference signal Sref.

[0093] In some embodiments, the control logic circuit 110 may control the gain of the loop filter 142 based on the phase difference P1 between the first clock signal CK1 and the reference signal Sref so that the first bit error rate B1 of the first signal S1 received in response to the first clock signal CK1 is reduced.

[0094] In this case, for example, the control logic circuit 110 may use an autocorrelation technique to control the gain of the loop filter 142. However, reference will be made later to FIG. 4A to FIG. 4C A detailed description thereof is given.

[0095] Referring to the above configuration, the control logic circuit 110 may control the gain of the loop filter 142 to control the signal quality (eg, the first bit error rate B1 ) of the first signal S1 received in response to the first clock signal CK1 .

[0096] Therefore, the clock generating apparatus 100 of the present disclosure can improve the signal quality of the first signal S1 received in response to the first clock signal CK1 without increasing the power consumption applied to the phase-locked loop circuit 130 .

[0097] Figure 2 An example of a configuration in which a control logic circuit controls a phase-locked loop circuit using a boost current source is shown.

[0098] Reference Figure 2 The clock generating device 100A may include a control logic circuit 110, a monitoring circuit 120 and a phase-locked loop circuit 130A.

[0099] in this case, Figure 2 The clock generating device 100A and the phase-locked loop circuit 130A shown in FIG. 1 can be understood as Figure 1A An example of a clock generation device 100 and a phase-locked loop circuit 130 is shown in FIG.

[0100] Therefore, the same reference numerals will be assigned to the same components or substantially the same components as those described above, and repeated contents thereof will be omitted to avoid redundancy.

[0101] In some embodiments, the phase-locked loop circuit 130A may include a plurality of boost current sources BC1 to BCn connected to the oscillator 131 .

[0102] Furthermore, the phase-locked loop circuit 130A may include a plurality of capacitors C1 to Cn connected to the output node N1 of the oscillator 131 .

[0103] In this case, it can be understood that the plurality of capacitors C1 to Cn correspond to the plurality of boosting current sources BC1 to BCn. For example, the plurality of capacitors C1 to Cn may have capacitances corresponding to currents of the plurality of boosting current sources BC1 to BCn, respectively.

[0104] In some embodiments, the control logic circuit 110 may connect at least a portion of the plurality of boost current sources BC1 to BCn to the oscillator 131 in response to a first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0105] For example, the control logic circuit 110 may connect a first boosting current source BC1 among the plurality of boosting current sources BC1 to BCn to the oscillator 131 in response to a first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0106] The control logic circuit 110 may connect the first boosting current source BC1 to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold, so that the first boosting current IB1 is additionally applied to the oscillator 131 together with the base current Io.

[0107] To this end, the control logic circuit 110 may close a switch disposed between the first boost current source BC1 and the oscillator 131 .

[0108] Furthermore, the control logic circuit 110 may connect the first capacitor C1 corresponding to the first boosting current source BC1 to the output node N1 of the oscillator 131 based on the first boosting current source BC1 being connected to the oscillator 131 .

[0109] The control logic circuit 110 may connect the first capacitor C1 having a capacitance corresponding to the first boosting current IB1 to the output node N1 of the oscillator 131 in response to the first boosting current source BC1 being connected to the oscillator 131 .

[0110] To this end, the control logic circuit 110 may close a switch disposed between the first capacitor C1 and the oscillator 131 .

[0111] For another example, the control logic circuit 110 may connect the first capacitor C1 and the second capacitor C2 to the output node N1 of the oscillator 131 in response to the first boost current source BC1 being connected to the oscillator 131 .

[0112] However, when at least a portion of the plurality of boosting current sources BC1 to BCn are connected to the oscillator 131 , the number and configuration of capacitors connected to the output node N1 through the control logic circuit 110 are not limited to the above example.

[0113] Referring to the above configuration, the control logic circuit 110 may increase the current applied to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0114] Therefore, the control logic circuit 110 may reduce a first bit error rate B1 of the first signal S1 received in response to the first clock signal CK1 output by the oscillator 131 .

[0115] Furthermore, the control logic circuit 110 may connect the capacitor to the output node N1 of the oscillator 131 in response to an increase in the current applied to the oscillator 131 .

[0116] Therefore, the control logic circuit 110 can reduce the first bit error rate B1 of the first signal S1 received in response to the first clock signal CK1 while maintaining the frequency of the first clock signal CK1.

[0117] In some embodiments, the control logic circuit 110 may disconnect at least a portion of the plurality of boost current sources BC1 to BCn connected to the oscillator 131 in the phase-locked loop circuit 130A from the oscillator 131 .

[0118] More specifically, in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold, the control logic circuit 110 may disconnect at least a portion of the current sources previously connected to the oscillator 131 from the oscillator 131 .

[0119] For example, in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold, the control logic circuit 110 may disconnect the second boosting current source BC2 previously connected to the oscillator 131 from the oscillator 131 among the plurality of boosting current sources BC1 to BCn. In this case, it is assumed that the second boosting current source BC2 was previously connected to the oscillator 131.

[0120] In response to the first bit error rate B1 of the first signal S1 being less than a preset threshold, the control logic circuit 110 may disconnect the second boost current source BC2 from the oscillator 131 , so that the current applied to the oscillator 131 is reduced.

[0121] To this end, the control logic circuit 110 may open a switch interposed between the oscillator 131 and the second boosting current source BC2 previously connected to the oscillator 131 .

[0122] In addition, in response to the second boost current source BC2 being disconnected from the oscillator 131, the control logic circuit 110 may disconnect the second capacitor C2 corresponding to the second boost current source BC2 from the oscillator 131. To this end, the control logic circuit 110 may disconnect the switch disposed between the second capacitor C2 and the output node N1 of the oscillator 131.

[0123] Referring to the above configuration, the control logic circuit 110 may reduce the current applied to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold.

[0124] Therefore, the control logic circuit 110 can minimize the power consumed by the PLL circuit 130A to generate the first clock signal CK1.

[0125] Therefore, the control logic circuit 110 of the present disclosure may increase or decrease the magnitude of the current (or power) applied to the PLL circuit 130A based on the signal quality of the first signal S1 received in response to the first clock signal CK1 .

[0126] Therefore, the clock generating apparatus 100A of the present disclosure can improve the power efficiency of the phase-locked loop circuit 130A based on the signal quality of the first signal S1 received in response to the first clock signal CK1.

[0127] Figure 3 An example of a configuration in which a control logic circuit controls a phase-locked loop circuit using an overclocked current source is shown.

[0128] Reference Figure 3 The clock generating device 100B may include a control logic circuit 110, a monitoring circuit 120 and a phase-locked loop circuit 130B.

[0129] in this case, Figure 3 The clock generating device 100B and the phase-locked loop circuit 130B shown in FIG. 1 can be understood as Figure 1A An example of a clock generation device 100 and a phase-locked loop circuit 130 is shown in FIG.

[0130] Therefore, the same reference numerals will be assigned to the same components or substantially the same components as those described above, and repeated contents thereof will be omitted to avoid redundancy.

[0131] In some implementations, the phase-locked loop circuit 130B may include a plurality of overclocking current sources OC1 to OCn connected to the oscillator 131 .

[0132] Furthermore, the phase-locked loop circuit 130B may include a frequency divider 150 connected to the output node N1 of the oscillator 131 .

[0133] In some embodiments, the control logic circuit 110 may connect at least a portion of the plurality of overclocking current sources OC1 to OCn to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0134] For example, the control logic circuit 110 may connect the first overclocking current source OC1 among the plurality of overclocking current sources OC1 to OCn to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0135] In response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold, the control logic circuit 110 may connect the first overclocking current source OC1 to the oscillator 131 so that the first overclocking current IO1 is applied to the oscillator 131 together with the base current Io.

[0136] To this end, the control logic circuit 110 may close a switch disposed between the first overclocking current source OC1 and the oscillator 131 .

[0137] Furthermore, the control logic circuit 110 may control the coefficient of the frequency divider 150 in response to the first overclocking current source OC1 being connected to the oscillator 131 .

[0138] The control logic circuit 110 may control the coefficient of the frequency divider 150 to be a value obtained by dividing the current input to the oscillator 131 by the base current Io.

[0139] In this case, the first overclocking current IO1 may have a current value that is a positive integer multiple of the basic current Io. For example, the first overclocking current IO1 may have a current value that is three times the basic current Io.

[0140] Therefore, for example, the control logic circuit 110 may control the coefficient of the frequency divider 150 to be “3” in response to the first overclocking current source OC1 being connected to the oscillator 131 .

[0141] Referring to the above configuration, the control logic circuit 110 may increase the current applied to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0142] Therefore, the control logic circuit 110 may reduce a first bit error rate B1 of the first signal S1 received in response to the first clock signal CK1 output by the oscillator 131 .

[0143] Furthermore, the control logic circuit 110 may control the frequency of a signal output from the oscillator 131 in response to an increase in the current applied to the oscillator 131 .

[0144] Therefore, the control logic circuit 110 can reduce the first bit error rate B1 of the first signal S1 received in response to the first clock signal CK1 while maintaining the frequency of the first clock signal CK1.

[0145] In some embodiments, the control logic circuit 110 may disconnect at least a portion of the plurality of overclocking current sources OC1 to OCn from the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold.

[0146] For example, in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold, the control logic circuit 110 may disconnect the second overclocking current source OC2 previously connected to the oscillator 131 from the oscillator 131 among the plurality of overclocking current sources OC1 to OCn. In this case, it is assumed that the second overclocking current source OC2 was previously connected to the oscillator 131.

[0147] In response to the first bit error rate B1 being less than a preset threshold, the control logic circuit 110 may disconnect a second overclocking current source OC2 previously connected to the oscillator 131 from the oscillator 131 among the plurality of overclocking current sources OC1 to OCn, so that the current applied to the oscillator 131 is reduced.

[0148] To this end, the control logic circuit 110 may turn off the switch disposed between the second overclocking current source OC2 and the oscillator 131 .

[0149] Furthermore, the control logic circuit 110 may control the coefficient of the frequency divider 150 in response to the second overclocking current source OC2 being disconnected from the oscillator 131 .

[0150] For example, the control logic circuit 110 may control the coefficient of the frequency divider 150 to be “1” in response to the disconnection between the second overclocking current source OC2 and the oscillator 131 .

[0151] Referring to the above configuration, the control logic circuit 110 may reduce the current applied to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold.

[0152] Therefore, the control logic circuit 110 can minimize the power consumed by the PLL circuit 130B to generate the first clock signal CK1.

[0153] Therefore, the control logic circuit 110 may increase or decrease the magnitude of the current (or power) applied to the phase-locked loop circuit 130B based on the signal quality of the first signal S1 received in response to the first clock signal CK1.

[0154] Therefore, the clock generating apparatus 100B of the present disclosure can improve the power efficiency of the phase-locked loop circuit 130B based on the signal quality of the first signal S1 received in response to the first clock signal CK1.

[0155] Figure 4A An example of a configuration in which a control logic circuit controls the gain of a loop filter is shown. Figure 4B is shown connected to Figure 4A A circuit diagram of an example of a configuration of an oscillator, a phase detector, and a loop filter. Figure 4C Shown in Figure 4A Example gain of a loop filter under the control of a control logic circuit.

[0156] Refer to FIG. 4A to FIG. 4C The clock generating device 100C may include a control logic circuit 110, a monitoring circuit 120 and a phase-locked loop circuit 130C.

[0157] Furthermore, the phase-locked loop circuit 130C may include a phase detector 141 and a loop filter 142 .

[0158] in this case, Figure 4A The clock generating device 100C and the phase-locked loop circuit 130C shown in FIG. 1 can be understood as Figure 1A An example of a clock generation device 100 and a phase-locked loop circuit 130 is shown in FIG.

[0159] Therefore, the same reference numerals will be assigned to the same components or substantially the same components as those described above, and repeated contents thereof will be omitted to avoid redundancy.

[0160] Refer to Figure 4A and Figure 4B , the phase-locked loop circuit 130C may include a phase detector 141 that compares the phase of the first clock signal CK1 with the phase of the reference signal Sref to output a phase difference P1.

[0161] More specifically, the phase detector 141 may compare the phase of the first clock signal CK1 divided by an arbitrary positive number “N” with the phase of the reference signal Sref to output a phase difference P1 .

[0162] In this case, the phase detector 141 may be referred to as a bang-bang phase detector BBPD that outputs phase error information from each of the first clock signal CK1 and the reference signal Sref, but the present disclosure is not limited thereto.

[0163] Furthermore, the phase-locked loop circuit 130C may include a loop filter 142 connected between the phase detector 141 and the oscillator 131 .

[0164] In some embodiments, the loop filter 142 may apply a proportional gain Kp to the phase difference P1 output from the phase detector 141. In addition, the loop filter 142 may apply an integral path gain Ki to the phase difference P1 through the accumulator ACC.

[0165] Therefore, the loop filter 142 may control the oscillator 131 so that the oscillator 131 outputs a clock signal having the frequency of the reference signal Sref.

[0166] In some implementations, the control logic circuit 110 may generate a gain control signal Gc for controlling the loop filter 142 based on the phase difference P1.

[0167] More specifically, the control logic circuit 110 may provide the gain control signal Gc for controlling the proportional gain Kp of the loop filter 142 to the loop filter 142 based on the phase difference P1.

[0168] Therefore, the control logic circuit 110 may control the proportional gain Kp of the loop filter 142 based on the phase difference P1 between the first clock signal CK1 generated from the oscillator 131 and the reference signal Sref.

[0169] In addition, the control logic circuit 110 can control the phase (or frequency) of the first clock signal CK1 and the first bit error rate B1 of the first signal S1 by controlling the proportional gain Kp of the loop filter 142 .

[0170] In this case, it can be understood that the first bit error rate B1 of the first signal S1 has different values ​​according to the phase of the first clock signal CK1 (or the proportional gain Kp of the loop filter 142 ).

[0171] Reference Figure 4C , the control logic circuit 110 may control the gain of the loop filter 142 so that the first signal S1 has a maximum signal quality (eg, SNR).

[0172] More specifically, the control logic circuit 110 may control the gain of the loop filter 142 to be a first proportional gain Kt corresponding to the minimum value Bm of the first bit error rate B1 , so that the first bit error rate B1 has the minimum value Bm.

[0173] In this case, for example, the control logic circuit 110 may control the proportional gain Kp of the loop filter 142 to be the first proportional gain Kt using an autocorrelation scheme so that the first bit error rate B1 of the first clock signal CK1 has a minimum value Bm.

[0174] However, the method for controlling the proportional gain Kp of the loop filter 142 by the control logic circuit 110 is not limited to the above example.

[0175] Referring to the above configuration, the control logic circuit 110 may control the proportional gain Kp of the loop filter 142 to control the signal quality (eg, the first bit error rate B1 ) of the first signal S1 received in response to the first clock signal CK1 .

[0176] Therefore, the clock generating apparatus 100C of the present disclosure can improve the signal quality of the first signal S1 received in response to the first clock signal CK1 while maintaining the power applied to the phase-locked loop circuit 130C.

[0177] Figure 5 An example of a configuration in which a control logic circuit controls a phase-locked loop circuit using a boost current source and an overclock current source is shown.

[0178] Reference Figure 5 The clock generating device 100D may include a control logic circuit 110, a monitoring circuit 120 and a phase-locked loop circuit 130D.

[0179] in this case, Figure 5 The clock generating device 100D and the phase-locked loop circuit 130D shown in FIG. 1 can be understood as Figure 1A An example of a clock generation device 100 and a phase-locked loop circuit 130 is shown in FIG.

[0180] Therefore, the same reference numerals will be assigned to the same components or substantially the same components as those described above, and repeated contents thereof will be omitted to avoid redundancy.

[0181] In some embodiments, the phase-locked loop circuit 130D may include a plurality of boost current sources BC1 to BCn connected to the oscillator 131. In addition, the phase-locked loop circuit 130D may include a plurality of capacitors C1 to Cn connected to the output node N1 of the oscillator 131.

[0182] In this case, it can be understood that the plurality of capacitors C1 to Cn respectively correspond to the plurality of boosting current sources BC1 to BCn. For example, the plurality of capacitors C1 to Cn may respectively have capacitances corresponding to currents of the plurality of boosting current sources BC1 to BCn.

[0183] In addition, the phase-locked loop circuit 130D may include a plurality of overclocking current sources OC1 to OCn connected to the oscillator 131. In addition, the phase-locked loop circuit 130D may include a frequency divider 150 connected to an output node N1 of the oscillator 131.

[0184] In some embodiments, the control logic circuit 110 may connect at least a portion of the plurality of boost current sources BC1 to BCn to the oscillator 131 in response to a first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0185] For example, the control logic circuit 110 may connect a first boosting current source BC1 among the plurality of boosting current sources BC1 to BCn to the oscillator 131 in response to a first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0186] The control logic circuit 110 may connect the first boosting current source BC1 to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold, so that the first boosting current IB1 is additionally applied to the oscillator 131 together with the base current Io.

[0187] Furthermore, the control logic circuit 110 may connect the first capacitor C1 corresponding to the first boosting current source BC1 to the output node N1 of the oscillator 131 in response to the first boosting current source BC1 being connected to the oscillator 131 .

[0188] Furthermore, when the first bit error rate B1 is greater than or equal to a preset threshold value while at least a portion of the plurality of boost current sources BC1 to BCn are connected to the oscillator 131 , the control logic circuit 110 may connect at least a portion of the overclocking current sources OC1 to OCn to the oscillator 131 .

[0189] For example, when the first bit error rate B1 is greater than or equal to a preset threshold in a state where the first boost current source BC1 is connected to the oscillator 131 , the control logic circuit 110 may connect at least a portion of the plurality of overclocking current sources OC1 to OCn to the oscillator 131 .

[0190] For another example, when the first bit error rate B1 is greater than or equal to a preset threshold when each of the multiple boost current sources BC1 to BCn is connected to the oscillator 131, the control logic circuit 110 may connect the first overclocking current source OC1 to OCn among the multiple overclocking current sources OC1 to OCn to the oscillator 131.

[0191] In addition, the control logic circuit 110 may control the coefficient of the frequency divider 150 in response to the first overclocking current source OC1 being connected to the oscillator 131. In this case, the control logic circuit 110 may also control the coefficient of the frequency divider 150 to a value obtained by dividing the current input to the oscillator 131 by the base current Io.

[0192] For example, the control logic circuit 110 may control the coefficient of the frequency divider 150 to be “3” in response to the first overclocking current IO1 being twice the base current Io being applied to the oscillator 131 through the first overclocking current source OC1 .

[0193] In this case, for example, each of the plurality of overclocking current sources OC1 to OCn may output a second current (eg, first overclocking current IO1 ) greater than a first current (eg, first boosting current IB1 ) output by each of the plurality of boosting current sources BC1 to BCn.

[0194] Through the above configuration, the clock generating apparatus 100D can improve the signal quality of the first signal S1 by increasing the current (or power) applied to the phase-locked loop circuit 130D based on the first bit error rate B1 of the first signal S1.

[0195] In some embodiments, when the first bit error rate B1 of the first signal S1 is less than a preset threshold, the control logic circuit 110 may disconnect at least a portion of the plurality of boost current sources BC1 to BCn from the oscillator 131 .

[0196] For example, in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold, the control logic circuit 110 may disconnect the second boosting current source BC2 previously connected to the oscillator 131 from the oscillator 131 among the plurality of boosting current sources BC1 to BCn.

[0197] Furthermore, in response to the second boosting current source BC2 being disconnected from the oscillator 131 , the control logic circuit 110 may disconnect the second capacitor C2 corresponding to the second boosting current source BC2 from the output node N1 of the oscillator 131 .

[0198] Furthermore, when the first bit error rate B1 is less than a preset threshold value when at least a portion of the plurality of boost current sources BC1 to BCn are disconnected from the oscillator 131 , the control logic circuit 110 may disconnect at least a portion of the overclocking current sources OC1 to OCn from the oscillator 131 .

[0199] For example, when the first bit error rate B1 is less than a preset threshold value when the first boost current source BC1 is disconnected from the oscillator 131 , the control logic circuit 110 may disconnect at least a portion of the plurality of overclocking current sources OC1 to OCn from the oscillator 131 .

[0200] For another example, when the first bit error rate B1 is less than a preset threshold value in a state where each of the plurality of boost current sources BC1 to BCn is disconnected from the oscillator 131, the control logic circuit 110 may disconnect the second overclocking current source OC2 from the oscillator 131. In this case, it is assumed that the second overclocking current source OC2 was previously connected to the oscillator 131.

[0201] In addition, the control logic circuit 110 may control the coefficient of the divider 150 in response to the second overclocking current source OC2 being disconnected from the oscillator 131. In this case, the control logic circuit 110 may control the coefficient of the divider 150 to a value obtained by dividing the current input to the oscillator 131 by the base current Io.

[0202] For example, the control logic circuit 110 may control the coefficient of the frequency divider 150 to be “1” in response to the second overclocking current source OC2 being disconnected from the oscillator 131 .

[0203] Referring to the above configuration, the control logic circuit 110 may control the current applied to the oscillator 131 by using at least a portion of the plurality of boosting current sources BC1 to BCn based on the first bit error rate B1 of the first signal S1 .

[0204] Subsequently, the control logic circuit 110 may control the connection between the plurality of boost current sources BC1 to BCn and the oscillator 131 and then control the current applied to the oscillator 131 by using at least a portion of the plurality of overclocking current sources OC1 to OCn based on the first bit error rate B1 of the first signal S1.

[0205] Therefore, the clock generating apparatus 100D of the present disclosure can improve the accuracy of the operation for controlling the power of the phase-locked loop circuit 130D based on the first bit error rate B1 of the first signal S1.

[0206] Figure 6 An example of a configuration in which a control logic circuit controls a phase-locked loop circuit using a boost current source and a loop filter is shown.

[0207] Reference Figure 6 The clock generating device 100E may include a control logic circuit 110, a monitoring circuit 120 and a phase-locked loop circuit 130E.

[0208] in this case, Figure 6 The clock generating device 100E and the phase-locked loop circuit 130E shown in FIG. 1 can be understood as Figure 1A 1 and 13. Therefore, the same reference numerals will be assigned to the same components or substantially the same components as those described above, and duplicate contents thereof will be omitted to avoid redundancy.

[0209] In some embodiments, the phase-locked loop circuit 130E may include a plurality of boost current sources BC1 to BCn connected to the oscillator 131. In addition, the phase-locked loop circuit 130E may include a plurality of capacitors C1 to Cn connected to the output node N1 of the oscillator 131.

[0210] In some embodiments, the control logic circuit 110 may connect at least a portion of the plurality of boost current sources BC1 to BCn to the oscillator 131 in response to a first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0211] For example, the control logic circuit 110 may connect a first boosting current source BC1 among the plurality of boosting current sources BC1 to BCn to the oscillator 131 in response to a first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0212] The control logic circuit 110 may connect the first boosting current source BC1 to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold, so that the first boosting current IB1 is additionally applied to the oscillator 131 together with the base current Io.

[0213] Furthermore, the control logic circuit 110 may connect the first capacitor C1 corresponding to the first boosting current source BC1 to the output node N1 of the oscillator 131 in response to the first boosting current source BC1 being connected to the oscillator 131 .

[0214] In addition, when the first bit error rate B1 of the first signal S1 is less than a preset threshold, the control logic circuit 110 may disconnect at least a portion of the plurality of boost current sources BC1 to BCn from the oscillator 131 .

[0215] For example, in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold, the control logic circuit 110 may disconnect the second boosting current source BC2 previously connected to the oscillator 131 from the oscillator 131 among the plurality of boosting current sources BC1 to BCn. In this case, it is assumed that the second boosting current source BC2 was previously connected to the oscillator 131.

[0216] Furthermore, in response to the second boosting current source BC2 being disconnected from the oscillator 131 , the control logic circuit 110 may disconnect the second capacitor C2 corresponding to the second boosting current source BC2 from the output node N1 of the oscillator 131 .

[0217] In addition, the control logic circuit 110 may control the connection between at least a portion of the plurality of boost current sources BC1 to BCn and the oscillator 131 and then control the gain of the loop filter 142 based on the phase difference P1 between the first clock signal CK1 generated from the oscillator 131 and the reference signal Sref.

[0218] For example, the control logic circuit 110 may detect the phase difference P1 between the first clock signal CK1 and the reference signal Sref by using the phase detector 141 in a state in which at least a portion of the plurality of boosting current sources BC1 to BCn are connected to the oscillator 131 .

[0219] In addition, the control logic circuit 110 may control the gain of the loop filter 142 based on the phase difference P1. More specifically, the control logic circuit 110 may generate a gain (eg, Figure 4B The gain control signal Gc has a proportional gain Kp).

[0220] In other words, the control logic circuit 110 can control the gain of the loop filter 142 based on the phase difference P1 between the first clock signal CK1 and the reference signal Sref when at least a portion of the multiple boost current sources BC1 to BCn are connected to the oscillator 131, so that the first bit error rate B1 of the first signal S1 received in response to the first clock signal CK1 is reduced.

[0221] Referring to the above configuration, the control logic circuit 110 may control the current applied to the oscillator 131 by using at least a portion of the plurality of boosting current sources BC1 to BCn based on the first bit error rate B1 of the first signal S1 .

[0222] Then, the control logic circuit 110 may improve the signal quality of the first signal S1 by controlling the gain of the loop filter 142 .

[0223] In other words, the clock generating apparatus 100E of the present disclosure can improve the signal quality of the first signal S1 while maintaining the power consumption of the phase-locked loop circuit 130E after controlling the power applied to the phase-locked loop circuit 130E using the boost current source.

[0224] Therefore, the clock generating apparatus 100E of the present disclosure can minimize the power applied to the phase-locked loop circuit 130E to improve the signal quality of the first signal S1.

[0225] Therefore, the clock generating apparatus 100E can minimize the power consumption applied to the phase-locked loop circuit 130E to improve the signal quality of the first signal S1.

[0226] Figure 7 An example of a configuration in which a control logic circuit controls a phase-locked loop circuit using an overclocked current source and a loop filter is shown.

[0227] Reference Figure 7 The clock generating device 100F may include a control logic circuit 110, a monitoring circuit 120 and a phase-locked loop circuit 130F.

[0228] in this case, Figure 7 The clock generating device 100F and the phase-locked loop circuit 130F shown in FIG. 1 can be understood as Figure 1A An example of a clock generation device 100 and a phase-locked loop circuit 130 is shown in FIG.

[0229] Therefore, the same reference numerals will be assigned to the same components or substantially the same components as those described above, and repeated contents thereof will be omitted to avoid redundancy.

[0230] In some embodiments, the phase-locked loop circuit 130F may include a plurality of overclocking current sources OC1 to OCn connected to the oscillator 131. In addition, the phase-locked loop circuit 130F may include a frequency divider 150 connected to an output node N1 of the oscillator 131.

[0231] In some embodiments, the control logic circuit 110 may connect at least a portion of the plurality of overclocking current sources OC1 to OCn to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0232] For example, the control logic circuit 110 may connect the first overclocking current source OC1 among the plurality of overclocking current sources OC1 to OCn to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0233] The control logic circuit 110 may connect the first overclocking current source OC1 to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold, so that the first overclocking current IO1 is additionally applied to the oscillator 131 together with the base current Io.

[0234] In this case, it can be understood that the first overclocking current IO1 has a current amount that is a positive integer multiple of the basic current Io.

[0235] In addition, the control logic circuit 110 may control the coefficient of the divider 150 in response to the first overclocking current source OC1 being connected to the oscillator 131. In this case, the control logic circuit 110 may control the coefficient of the divider 150 to a value obtained by dividing the current input to the oscillator 131 by the base current Io.

[0236] For example, the control logic circuit 110 may control the coefficient of the frequency divider 150 to be “3” in response to the first overclocking current IO1 being twice the base current Io being applied to the oscillator 131 through the first overclocking current source OC1 .

[0237] In addition, when the first bit error rate B1 of the first signal S1 is less than a preset threshold, the control logic circuit 110 may disconnect at least a portion of the plurality of overclocking current sources OC1 to OCn from the oscillator 131 .

[0238] For example, in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold, the control logic circuit 110 may disconnect the second overclocking current source OC2 previously connected to the oscillator 131 from the oscillator 131 among the plurality of overclocking current sources OC1 to OCn. In this case, it is assumed that the second overclocking current source OC2 was previously connected to the oscillator 131.

[0239] In addition, the control logic circuit 110 may control the coefficient of the frequency divider 150 in response to the second overclocking current source OC2 being disconnected from the oscillator 131. For example, in response to the second overclocking current source OC2 being disconnected from the oscillator 131, the coefficient of the frequency divider 150 may be controlled to "1".

[0240] In addition, the control logic circuit 110 can control the connection between at least a portion of the multiple overclocking current sources OC1 to OCn and the oscillator 131, and then control the gain of the loop filter 142 based on the phase difference P1 between the first clock signal CK1 generated by the oscillator 131 and the reference signal Sref.

[0241] For example, the control logic circuit 110 may detect the phase difference P1 between the first clock signal CK1 and the reference signal Sref by using the phase detector 141 in a state in which at least a portion of the plurality of overclocking current sources OC1 to OCn are connected to the oscillator 131 .

[0242] In addition, the control logic circuit 110 may control the gain of the loop filter 142 based on the phase difference P1. More specifically, the control logic circuit 110 may generate a gain (eg, Figure 4B The gain control signal Gc has a proportional gain Kp).

[0243] In other words, the control logic circuit 110 may control the gain of the loop filter 142 based on the phase difference P1 between the first clock signal CK1 and the reference signal Sref after controlling the connection between at least a portion of the multiple overclocking current sources OC1 to OCn and the oscillator 131, so that the first bit error rate B1 of the first signal S1 received in response to the first clock signal CK1 is reduced.

[0244] Referring to the above configuration, the control logic circuit 110 may control the current applied to the oscillator 131 by using at least a portion of the plurality of overclocking current sources OC1 to OCn based on the first bit error rate B1 of the first signal S1 .

[0245] Subsequently, the control logic circuit 110 may improve the signal quality of the first signal S1 by controlling the gain of the loop filter 142 .

[0246] In other words, the clock generating apparatus 100F of the present disclosure can improve the signal quality of the first signal S1 while maintaining power consumption for the phase-locked loop circuit 130F after controlling the power applied to the phase-locked loop circuit 130F using the overclocking current source.

[0247] Therefore, the clock generating apparatus 100F can minimize the power applied to the phase-locked loop circuit 130F to improve the signal quality of the first signal S1.

[0248] Furthermore, therefore, the clock generating apparatus 100F can minimize power consumption applied to the phase-locked loop circuit 130F to improve the signal quality of the first signal S1.

[0249] Figure 8 An example of a configuration in which a control logic circuit controls a phase-locked loop circuit using a boost current source, an overclocking current source, and a loop filter is shown.

[0250] Reference Figure 8 The clock generating device 100G may include a control logic circuit 110, a monitoring circuit 120 and a phase-locked loop circuit 130G.

[0251] in this case, Figure 8 The clock generation device 100G and the phase-locked loop circuit 130G shown in FIG. 1 can be understood as Figure 1A 1 and 13. Therefore, the same reference numerals will be assigned to the same components or substantially the same components as those described above, and duplicate contents thereof will be omitted to avoid redundancy.

[0252] In some embodiments, the phase-locked loop circuit 130G may include a plurality of boost current sources BC1 to BCn connected to the oscillator 131. In addition, the phase-locked loop circuit 130G may include a plurality of capacitors C1 to Cn connected to the output node N1 of the oscillator 131.

[0253] In addition, the phase-locked loop circuit 130G may include a plurality of overclocking current sources OC1 to OCn connected to the oscillator 131. In addition, the phase-locked loop circuit 130G may include a frequency divider 150 connected to an output node N1 of the oscillator 131.

[0254] In some embodiments, the control logic circuit 110 may connect at least a portion of the plurality of boost current sources BC1 to BCn to the oscillator 131 in response to a first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0255] For example, the control logic circuit 110 may connect the first boost current source BC1 to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold, so that the first boost current IB1 is additionally applied to the oscillator 131 together with the base current Io.

[0256] Furthermore, the control logic circuit 110 may connect the first capacitor C1 corresponding to the first boosting current source BC1 to the output node N1 of the oscillator 131 in response to the first boosting current source BC1 being connected to the oscillator 131 .

[0257] Furthermore, when the first bit error rate B1 is greater than or equal to a preset threshold value while at least a portion of the plurality of boost current sources BC1 to BCn are connected to the oscillator 131 , the control logic circuit 110 may connect at least a portion of the overclocking current sources OC1 to OCn to the oscillator 131 .

[0258] For example, when the first bit error rate B1 is greater than or equal to a preset threshold in a state where the first boost current source BC1 is connected to the oscillator 131 , the control logic circuit 110 may connect at least a portion of the plurality of overclocking current sources OC1 to OCn to the oscillator 131 .

[0259] For another example, when the first bit error rate B1 is greater than or equal to a preset threshold when each of the multiple boost current sources BC1 to BCn is connected to the oscillator 131, the control logic circuit 110 may connect the first overclocking current source OC1 among the multiple overclocking current sources OC1 to OCn to the oscillator 131.

[0260] In addition, the control logic circuit 110 may control the coefficient of the frequency divider 150 in a state where the first overclocking current source OC1 is connected to the oscillator 131 , so that the PLL circuit 130G outputs a signal having the same frequency as the first clock signal CK1 .

[0261] Through the above configuration, the clock generating apparatus 100G can improve the signal quality of the first signal S1 by increasing the current (or power) applied to the phase-locked loop circuit 130G based on the first bit error rate B1 of the first signal S1.

[0262] In some embodiments, when the first bit error rate B1 of the first signal S1 is less than a preset threshold, the control logic circuit 110 may disconnect at least a portion of the plurality of boost current sources BC1 to BCn from the oscillator 131 .

[0263] For example, in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold, the control logic circuit 110 may disconnect the second boosting current source BC2 previously connected to the oscillator 131 from the oscillator 131 among the plurality of boosting current sources BC1 to BCn. In this case, it is assumed that the second boosting current source BC2 was previously connected to the oscillator 131.

[0264] Furthermore, in response to the second boosting current source BC2 being disconnected from the oscillator 131 , the control logic circuit 110 may disconnect the second capacitor C2 corresponding to the second boosting current source BC2 from the output node N1 of the oscillator 131 .

[0265] In addition, when the first bit error rate B1 is less than a preset threshold when at least a part of the multiple boost current sources BC1 to BCn are disconnected from the oscillator 131, the control logic circuit 110 may disconnect at least a part of the overclocking current sources OC1 to OCn that have been previously connected to the oscillator 131 from the oscillator 131.

[0266] For example, when the first bit error rate B1 is less than a preset threshold when the first boost current source BC1 is disconnected from the oscillator 131 , the control logic circuit 110 may disconnect at least a portion of the plurality of overclocking current sources OC1 to OCn from the oscillator 131 .

[0267] For another example, when the first bit error rate B1 is less than a preset threshold value in a state where the plurality of boost current sources BC1 to BCn are disconnected from the oscillator 131, the control logic circuit 110 may disconnect the second overclocking current source OC2 from the oscillator 131. In this case, it is assumed that the second overclocking current source OC2 was previously connected to the oscillator 131.

[0268] In addition, the control logic circuit 110 can control the coefficient of the frequency divider 150 when the second overclocking current source OC2 is disconnected from the oscillator 131 , so that the PLL circuit 130G outputs a signal having the same frequency as the first clock signal CK1 .

[0269] Referring to the above configuration, the control logic circuit 110 may increase or decrease the magnitude of current (or power) applied to the phase-locked loop circuit 130G based on the signal quality of the first signal S1 received in response to the first clock signal CK1.

[0270] Therefore, the clock generating apparatus 100G of the present disclosure may improve power efficiency for controlling the operation of the phase-locked loop circuit 130G based on the signal quality of the first signal S1 received in response to the first clock signal CK1 .

[0271] Furthermore, referring to the above configuration, the control logic circuit 110 may control the current applied to the oscillator 131 using at least a portion of the plurality of boosting current sources BC1 to BCn based on the first bit error rate B1 of the first signal S1 .

[0272] Subsequently, the control logic circuit 110 may control the connection between the plurality of boost current sources BC1 to BCn and the oscillator 131 and then control the current applied to the oscillator 131 by using at least a portion of the plurality of overclocking current sources OC1 to OCn based on the first bit error rate B1 of the first signal S1.

[0273] Therefore, the clock generating device 100G of the present disclosure can improve the accuracy of the operation of controlling the power of the phase-locked loop circuit 130G in response to the first bit error rate B1 of the first signal S1.

[0274] In addition, the control logic circuit 110 can control the connection between the oscillator 131 and at least a portion of the multiple boost current sources BC1 to BCn and the multiple overclocking current sources OC1 to OCn, and then control the gain of the loop filter 142 based on the phase difference P1 between the first clock signal CK1 generated from the oscillator 131 and the reference signal Sref.

[0275] For example, when at least a portion of the multiple boost current sources BC1 to BCn and the multiple overclocking current sources OC1 to OCn are connected to the oscillator 131, the control logic circuit 110 can sense the phase difference P1 between the first clock signal CK1 and the reference signal Sref by using the phase detector 141.

[0276] In addition, the control logic circuit 110 may control the gain of the loop filter 142 based on the phase difference P1. More specifically, the control logic circuit 110 may generate a gain (eg, Figure 4B The gain control signal Gc has a proportional gain Kp).

[0277] In other words, the control logic circuit 110 can control the connection between the oscillator 131 and at least a portion of the multiple boost current sources BC1 to BCn and the multiple overclocking current sources OC1 to OCn, and control the gain of the loop filter 142 based on the phase difference P1 between the first clock signal CK1 and the reference signal Sref, so that the first bit error rate B1 of the first signal S1 received in response to the first clock signal CK1 is reduced.

[0278] Referring to the above configuration, the control logic circuit 110 may control the current applied to the oscillator by using at least a portion of the plurality of boosting current sources BC1 to BCn based on the first bit error rate B1 of the first signal S1 .

[0279] Subsequently, the control logic circuit 110 may control the current applied to the oscillator 131 by using at least a portion of the plurality of overclocking current sources OC1 to OCn based on the first bit error rate B1 of the first signal S1 .

[0280] Subsequently, the control logic circuit 110 may improve the signal quality of the first signal S1 by controlling the gain of the loop filter 142 .

[0281] In other words, the clock generating device 100G of the present disclosure can improve the signal quality of the first signal S1 while maintaining the power consumption of the PLL circuit 130G after controlling the power applied to the PLL circuit 130G using the boost current source and the overclocking current source.

[0282] Therefore, the clock generating apparatus 100G can minimize the power applied to the phase-locked loop circuit 130G to improve the signal quality of the first signal S1.

[0283] Furthermore, therefore, the clock generating apparatus 100G can minimize power consumption applied to the phase-locked loop circuit 130G to improve the signal quality of the first signal S1.

[0284] Fig. 9 is a flow chart illustrating an example of a method for controlling a phase locked loop circuit. Fig. 10A is a flow chart illustrating an example of a method for controlling a phase locked loop circuit using a boost current source. Fig. 10B is a diagram showing the operation of the control logic circuit according to whether the control logic circuit is operated by the background control Fig. 10A The sequence of flowcharts shown in the flowchart is a flowchart of an example of a method of controlling a phase locked loop circuit.

[0285] Refer to Fig. 9 , Fig. 10A and Fig. 10B , the clock generating device 100 (or the control logic circuit 110 ) may control the connection between the current source and the oscillator 131 based on the first bit error rate B1 of the first signal S1 .

[0286] Therefore, the control logic circuit 110 may control the power applied to the PLL circuit 130 based on the first bit error rate B1 of the first signal S1.

[0287] Reference Fig. 9 In step S10 , the control logic circuit 110 may monitor a first bit error rate B1 of the first signal S1 .

[0288] More specifically, the control logic circuit 110 may monitor the first bit error rate B1 of the first signal S1 received by the receiver RX in response to the first clock signal CK1 by using the monitoring circuit 120 .

[0289] In some embodiments, the monitoring circuit 120 may monitor the first bit error rate B1 of the first signal S1 based on the distribution of the first signal S1 received by the receiver RX in response to the first clock signal CK1 .

[0290] For example, when the distribution of the first signal S1 is high, the monitoring circuit 120 may determine the first bit error rate B1 of the first signal S1 as high.

[0291] In some embodiments, a signal-to-noise ratio (SNR) of the first signal S1 may be monitored based on a distribution of the first signal S1 received by the receiver RX in response to the first clock signal CK1 .

[0292] In this case, for example, it can be understood that the first bit error rate B1 of the first signal S1 is inversely proportional to the SNR.

[0293] In other words, the monitoring circuit 120 may monitor (or measure) the signal quality (eg, bit error rate, SNR) of the first signal S1 received in response to the first clock signal CK1 .

[0294] In step S20 , the control logic circuit 110 may determine whether a first bit error rate B1 of the first signal S1 is greater than or equal to a preset threshold.

[0295] More specifically, the control logic circuit 110 may determine whether the first bit error rate B1 of the first signal S1 measured by the monitoring circuit 120 is greater than or equal to a preset threshold.

[0296] In some implementations, the control logic circuit 110 may determine whether the SNR of the first signal S1 measured by the monitoring circuit 120 is less than a preset threshold.

[0297] In this case, for example, the preset threshold for the bit error rate may be understood as a reference value for determining possibility of wireless communication using the first signal S1 received through the first clock signal CK1 by the device including the clock generating device 100 , but is not limited thereto.

[0298] In step S31 , the control logic circuit 110 may connect the first boost current source BC1 to the oscillator 131 .

[0299] More specifically, when the first bit error rate B1 of the first signal S1 is greater than or equal to a preset threshold, the control logic circuit 110 may connect the first boost current source BC1 to the oscillator 131 .

[0300] The control logic circuit 110 may connect the first boost current source BC1 to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold, so that the first boost current IB1 is applied to the oscillator 131 together with the base current Io.

[0301] To this end, the control logic circuit 110 may close a switch disposed between the first boost current source BC1 and the oscillator 131 .

[0302] In other words, the control logic circuit 110 may increase the current applied to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to the preset threshold.

[0303] Therefore, the control logic circuit 110 may reduce a first bit error rate B1 of the first signal S1 received in response to the first clock signal CK1 output by the oscillator 131 .

[0304] Furthermore, in step S32, the control logic circuit 110 may disconnect the second boosting current source BC2 previously connected to the oscillator 131 from the oscillator 131. In this case, it is assumed that the second boosting current source BC2 is previously connected to the oscillator 131.

[0305] More specifically, the control logic circuit 110 may disconnect the second boost current source BC2 from the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold, so that the current applied to the oscillator 131 is reduced.

[0306] To this end, the control logic circuit 110 may open a switch interposed between the oscillator 131 and the second boosting current source BC2 previously connected to the oscillator 131 .

[0307] In other words, the control logic circuit 110 may reduce the current applied to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold.

[0308] Therefore, the control logic circuit 110 can minimize the power consumed by the PLL circuit 130 to generate the first clock signal CK1 .

[0309] Referring to the above configuration, the control logic circuit 110 may increase or decrease the magnitude of current (or power) applied to the phase-locked loop circuit 130 based on the signal quality of the first signal S1 received in response to the first clock signal CK1 .

[0310] Therefore, the clock generating apparatus 100 of the present disclosure can improve the power efficiency of the phase-locked loop circuit 130 based on the signal quality of the first signal S1 received in response to the first clock signal CK1.

[0311] Reference Fig. 10A In step S41 , the control logic circuit 110 may connect the first capacitor C1 corresponding to the first boosting current source BC1 to the output node N1 of the oscillator 131 .

[0312] More specifically, the control logic circuit 110 may connect the first capacitor C1 having a capacitance corresponding to the first boosting current IB1 to the output node N1 of the oscillator 131 in response to the first boosting current source BC1 being connected to the oscillator 131 .

[0313] However, when at least a portion of the plurality of boosting current sources BC1 to BCn are connected to the oscillator 131 , the number and configuration of capacitors connected to the output node N1 through the control logic circuit 110 are not limited to the above example.

[0314] In step S42, the control logic circuit 110 may disconnect the second capacitor C2 corresponding to the second boosting current source BC2 from the oscillator 131. In this case, it is assumed that the second boosting current source BC2 is previously connected to the oscillator 131.

[0315] More specifically, the control logic circuit 110 may disconnect the second capacitor C2 corresponding to the second boosting current source BC2 from the oscillator 131 in response to the second boosting current source BC2 being disconnected from the oscillator 131 .

[0316] To this end, the control logic circuit 110 may turn off a switch disposed between the second capacitor C2 and the output node N1 of the oscillator 131 .

[0317] Referring to the above configuration, the control logic circuit 110 may control the connection between the output node N1 of the oscillator 131 and the capacitor in response to a change in the amount of current (or power) applied to the oscillator 131 .

[0318] Therefore, the control logic circuit 110 may control the current (or power) of the phase-locked loop circuit 130 while maintaining the frequency of the first clock signal CK1 output by the phase-locked loop circuit 130 .

[0319] In addition, refer to Fig. 10B , the control logic circuit 110 may be activated in response to the background control signal, and repeatedly execute the operations of step S20 to step S41, or step S20 to step S42.

[0320] More specifically, the control logic circuit 110 may repeatedly perform operations of steps S20 to S41 or S20 to S42 in response to being activated by a background control signal while an electronic device, semiconductor device or semiconductor chip including the clock generating device 100 is operating.

[0321] In this case, the background control signal can be understood as a control signal used to control the signal quality (e.g., bit error rate) of a signal received in response to a clock signal while an electronic device, semiconductor device, or semiconductor chip (chip) including the clock generating device 100 is operating.

[0322] In step S43 , the control logic circuit 110 may determine whether the background control signal is activated.

[0323] In this case, when the background control signal is activated, the control logic circuit 110 may repeatedly perform the operations of step S20 to step S41 or step S20 to step S42 .

[0324] Furthermore, when the background control signal is deactivated, the control logic circuit 110 may terminate the operation of controlling the quality of the signal received in response to the clock signal.

[0325] Fig.11A is a flow chart illustrating an example of a method for controlling a phase locked loop circuit using an overclocked current source. Fig. 11B is a flow chart illustrating an example of a method for controlling a phase-locked loop circuit using a boost current source according to a bit error rate of a second signal.

[0326] Refer to Fig.11A and Fig. 11B , the control logic circuit 110 may connect the first overclocking current source OC1 to the oscillator 131 based on the second bit error rate B2 of the second signal S2.

[0327] More specifically, the control logic circuit 110 may connect the first overclocking current source OC1 to the oscillator 131 based on the second bit error rate of the second signal received in response to the second clock signal output from the oscillator 131 while the first boost current source BC1 is connected to the oscillator 131 .

[0328] In step S49 , the control logic circuit 110 may monitor a second bit error rate of a second signal received in response to a second clock signal output from the oscillator 131 in a state where the first boosting current source BC1 and the first capacitor C1 are connected to the oscillator 131 .

[0329] In this case, the operation of monitoring the second bit error rate of the second signal by the control logic circuit 110 can be understood as Fig. 10A The operation of monitoring the first bit error rate of the first signal by the control logic circuit 110 in step S10 is basically the same.

[0330] In step S50 , the control logic circuit 110 may determine whether a second bit error rate of the second signal is greater than or equal to a preset threshold.

[0331] More specifically, in a state where the first boosting current source BC1 and the first capacitor C1 are connected to the oscillator 131 , the control logic circuit 110 may determine whether the second bit error rate of the second signal is greater than or equal to a preset threshold.

[0332] In some embodiments, the control logic circuit 110 may determine whether the SNR of the second signal measured in a state where the first boosting current source BC1 and the first capacitor C1 are connected to the oscillator 131 is less than a preset threshold.

[0333] In this case, for example, it can be understood that the operation of step S50 is the same as Fig. 9 The operation of step S20 shown in FIG. 1 is basically the same.

[0334] In step S60 , the control logic circuit 110 may connect the first overclocking current source OC1 to the oscillator 131 .

[0335] More specifically, when the second bit error rate of the second signal is greater than or equal to a preset threshold in a state where the first boosting current source BC1 is connected to the oscillator 131 , the control logic circuit 110 may connect the first overclocking current source OC1 to the oscillator 131 .

[0336] When the second bit error rate of the second signal is greater than or equal to a preset threshold when the first boost current source BC1 is connected to the oscillator 131, the control logic circuit 110 may connect the first overclocking current source OC1 to the oscillator 131 so that the first overclocking current source OC1 is applied to the oscillator 131 together with the basic current Io.

[0337] To this end, the control logic circuit 110 may close a switch disposed between the first overclocking current source OC1 and the oscillator 131 .

[0338] Referring to the above configuration, the control logic circuit 110 may control the current applied to the oscillator 131 using at least a portion of the multiple overclocking current sources OC1 to OCn based on the second bit error rate of the second signal after using the first boost current source BC1 to control the current applied to the oscillator 131.

[0339] In this case, for example, it can be understood that the first overclocking current IO1 is greater than the first boosting current IB1.

[0340] Therefore, through the above configuration, the clock generation device 100 of the present disclosure can improve the accuracy of the operation of controlling the current (or power) of the phase-locked loop circuit 130 according to the second bit error rate of the second signal. In addition, in step S70, the control logic circuit 110 can control the frequency divider 150 connected to the output node N1 of the oscillator 131.

[0341] More specifically, the control logic circuit 110 may control the coefficient of the frequency divider 150 in response to the first overclocking current source OC1 being connected to the oscillator 131 .

[0342] For example, in response to the first overclocking current source OC1 being connected to the oscillator 131 , the control logic circuit 110 may control the coefficient of the frequency divider 150 to be a value obtained by dividing the current input to the oscillator 131 by the base current Io.

[0343] In this case, the first overclocking current IO1 may have a current value that is a positive integer multiple of the basic current Io.

[0344] Therefore, for example, in response to the first overclocking current IO1 having a current value (3×Io) that is three times the basic current Io being applied to the oscillator 131 , the control logic circuit 110 may control the coefficient of the frequency divider 150 to “4”.

[0345] In addition, refer to Fig. 11B In step S61 , the control logic circuit 110 may connect the third boost current source BC3 to the oscillator 131 .

[0346] More specifically, when the second bit error rate of the second signal is greater than or equal to a preset threshold in a state where the first boosting current source BC1 is connected to the oscillator 131 , the control logic circuit 110 may connect the third boosting current source BC3 to the oscillator 131 .

[0347] When the second bit error rate of the second signal is greater than or equal to a preset threshold when the first boost current source BC1 is connected to the oscillator 131, the control logic circuit 110 may connect the third boost current source BC3 to the oscillator 131 so that the third boost current IB3 is applied together with the basic current Io.

[0348] To this end, the control logic circuit 110 may close a switch disposed between the third boost current source BC3 and the oscillator 131 .

[0349] Referring to the above configuration, the control logic circuit 110 may control the current applied to the oscillator 131 using at least a portion of the plurality of boosting current sources BC3 to BCn based on the second bit error rate of the second signal after controlling the current applied to the oscillator 131 using the first boosting current source BC1.

[0350] Therefore, through the above configuration, the clock generating device 100 of the present disclosure can improve the accuracy of the operation of controlling the current (or power) of the second bit error rate phase locked loop circuit 130 according to the second signal.

[0351] Furthermore, in step S71 , the control logic circuit 110 may connect the third capacitor C3 to the oscillator 131 .

[0352] More specifically, the control logic circuit 110 may connect the third capacitor C3 corresponding to the third boosting current source BC3 to the oscillator 131 in response to the third boosting current source BC3 being connected to the oscillator 131 .

[0353] To this end, the control logic circuit 110 may close a switch disposed between the third capacitor C3 and the oscillator 131 .

[0354] Referring to the above configuration, the control logic circuit 110 may control the coefficient of the frequency divider 150 connected to the output node N1 of the oscillator 131 in response to a change in the amount of current (or power) applied to the oscillator 131 .

[0355] Therefore, the control logic circuit 110 may control the current (or power) of the phase-locked loop circuit 130 while maintaining the frequency of the first clock signal CK1 output by the phase-locked loop circuit 130 .

[0356] Fig.12 is a flow chart illustrating an example of a method for controlling a phase-locked loop circuit by controlling the gain of a loop filter.

[0357] Reference Fig.12 , the control logic circuit 110 may control the gain of the loop filter 142 based on the phase difference P1 between the first clock signal CK1 and the reference signal Sref.

[0358] More specifically, the control logic circuit 110 may control the gain of the loop filter 142 based on the phase difference P1 between the first clock signal CK1 output from the oscillator 131 and the reference signal Sref when the first boost current source BC1 and the first overclocking current source OC1 are connected to the oscillator 131 .

[0359] In step S80 , the control logic circuit 110 may receive a phase difference P1 between the first clock signal CK1 and the reference signal Sref from the phase detector 141 .

[0360] More specifically, in a state where the first boosting current source BC1 and the first overclocking current source OC1 are connected to the oscillator 131 , the control logic circuit 110 may receive a phase difference P1 between the first clock signal CK1 output from the oscillator 131 and the reference signal Sref.

[0361] In step S90 , the control logic circuit 110 may control the gain of the loop filter 142 based on the phase difference P1 .

[0362] More specifically, the control logic circuit 110 may control the gain of the loop filter 142 based on the phase difference P1 received in a state where the first boosting current source BC1 and the first overclocking current source OC1 are connected to the oscillator 131 .

[0363] The control logic circuit 110 may control the gain of the loop filter 142 based on the phase difference P1 when the first boost current source BC1 and the first overclocking current source OC1 are connected to the oscillator 131 so that the first bit error rate B1 of the first signal S1 is reduced.

[0364] Referring to the above configuration, after using a current source (e.g., a first boost current source BC1 or a first overclocking current source OC1) to control the power applied to the phase-locked loop circuit 130, the control logic circuit 110 can improve the signal quality of the first signal S1 while maintaining the power consumption of the phase-locked loop circuit 130.

[0365] Therefore, the clock generating apparatus 100 of the present disclosure can minimize the power applied to the phase-locked loop circuit 130 to improve the signal quality of the first signal S1.

[0366] Furthermore, therefore, the clock generating apparatus 100 can minimize power consumption applied to the phase-locked loop circuit 130 to improve the signal quality of the first signal S1.

[0367] Fig.13 An example of a clock generating device including an LC oscillator is shown.

[0368] Reference Fig.13 The clock generating device 100H may include a control logic circuit 110, a monitoring circuit 120 and a phase-locked loop circuit 130H.

[0369] in this case, Fig.13 The clock generating device 100H and the phase-locked loop circuit 130H shown in FIG. 1 can be understood as Figure 1A 1 and 13. Therefore, the same reference numerals will be assigned to the same components or substantially the same components as those described above, and duplicate contents thereof will be omitted to avoid redundancy.

[0370] The phase-locked loop circuit 130H may include an LC oscillator 1310 that generates a first clock signal CK1 having a designated frequency.

[0371] In some embodiments, the LC oscillator 1310 may include an inductor-capacitor (LC) tank 1311 including an inductor and a capacitor connected in parallel.

[0372] More specifically, the LC oscillator 1310 may include an inductor-capacitor (LC) tank circuit 1311 connected to a power supply voltage VDD and including an inductor and a capacitor connected in parallel.

[0373] In addition, the LC oscillator 1310 may include a plurality of cells GC1 to GCn each including a plurality of transistors.

[0374] More specifically, the LC oscillator 1310 may include a plurality of cells GC1 to GCn connected in parallel to each other and including a plurality of transistors.

[0375] In this case, for example, each of the plurality of cells GC1 to GCn included in the LC oscillator 1310 may include two NMOS transistors, but the present disclosure is not limited thereto. In addition, it is understood that the plurality of cells GC1 to GCn have substantially the same configuration.

[0376] In some embodiments, at least a portion of the plurality of cells GC1 to GCn may be connected to the inductor-capacitor tank circuit 1311 to reduce the influence of a parasitic resistor due to the inductor-capacitor tank circuit 1311 .

[0377] The control logic circuit 110 may control the number of cells connected to the inductor-capacitor tank circuit 1311 based on the first bit error rate B1 of the first signal S1 .

[0378] More specifically, the control logic circuit 110 may connect or disconnect at least a portion of the plurality of cells GC1 to GCn to the inductor-capacitor tank circuit 1311 based on the first bit error rate B1 of the first signal S1 .

[0379] In some embodiments, the control logic circuit 110 may connect the first cell GC1 to the inductor-capacitor tank circuit 1311 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold.

[0380] In addition, the control logic circuit 110 may connect the third cell GC3 to the inductor-capacitor tank 1311 in response to a second bit error rate of a second signal received in a state where the first cell GC1 is connected to the inductor-capacitor tank 1311 being greater than or equal to a preset threshold.

[0381] In addition, when the first bit error rate B1 of the first signal S1 is less than a preset threshold, the control logic circuit 110 may disconnect the second cell GC2 previously connected to the inductor-capacitor tank circuit 1311 from the inductor-capacitor tank circuit 1311 .

[0382] Furthermore, the control logic circuit 110 may control the gain of the loop filter 142 based on a phase difference P2 between the first clock signal CK1 output from the LC oscillator 1310 and the reference signal Sref.

[0383] The control logic circuit 110 may generate a gain control signal GCS for controlling the gain of the loop filter 142 based on a phase difference P2 between the first clock signal CK1 output from the LC oscillator 1310 and the reference signal Sref.

[0384] More specifically, the control logic circuit 110 can control the connection between at least a portion of the multiple units GC1 to GCn and the inductor-capacitor tank circuit 1311, and then control the gain of the loop filter 142 based on the phase difference P2 between the first clock signal CK1 output from the LC oscillator 1310 and the reference signal Sref.

[0385] For example, the control logic circuit 110 may connect the first cell GC1 to the inductor-capacitor tank circuit 1311 and then control the gain of the loop filter 142 based on the phase difference P2 between the first clock signal CK1 and the reference signal Sref so that the first bit error rate B1 of the first signal S1 is reduced.

[0386] Referring to the above configuration, the control logic circuit 110 can increase or decrease the magnitude of the current (or power) applied to the phase-locked loop circuit 130H by using multiple cells GC1 to GCn included in the LC oscillator 1310 based on the signal quality of the first signal S1 received in response to the first clock signal CK1.

[0387] Therefore, the clock generating apparatus 100H of the present disclosure can improve the power efficiency of the phase-locked loop circuit 130H based on the signal quality of the first signal S1 received in response to the first clock signal CK1.

[0388] Fig.14 is shown for controlling Fig.13 A flowchart of an example of a method of a clock generation apparatus.

[0389] Reference Fig.14 The clock generating device 100H (or the control logic circuit 110 ) may control the connection between the cell and the inductor-capacitor tank circuit 1311 based on the first bit error rate B1 of the first signal S1 .

[0390] Therefore, the control logic circuit 110 may control the power applied to the PLL circuit 130H based on the first bit error rate B1 of the first signal S1.

[0391] In step S1410 , the control logic circuit 110 may monitor a first bit error rate B1 of the first signal S1 .

[0392] More specifically, the control logic circuit 110 may monitor the first bit error rate B1 of the first signal S1 received by the receiver RX in response to the first clock signal CK1 by using the monitoring circuit 120 .

[0393] In some embodiments, the monitoring circuit 120 may monitor the first bit error rate B1 of the first signal S1 based on the distribution of the first signal S1 received by the receiver RX in response to the first clock signal CK1 .

[0394] For example, when the distribution of the first signal S1 is high, the monitoring circuit 120 may determine the first bit error rate B1 of the first signal S1 as high.

[0395] In some embodiments, a signal-to-noise ratio (SNR) of the first signal S1 may be monitored based on a distribution of the first signal S1 received by the receiver RX in response to the first clock signal CK1 .

[0396] In this case, for example, it can be understood that the first bit error rate B1 of the first signal S1 is inversely proportional to the SNR.

[0397] In other words, the monitoring circuit 120 may monitor (or measure) the signal quality (eg, bit error rate, SNR) of the first signal S1 received in response to the first clock signal CK1 .

[0398] In step S1420 , the control logic circuit 110 may determine whether a first bit error rate B1 of the first signal S1 is greater than or equal to a preset threshold.

[0399] More specifically, the control logic circuit 110 may determine whether the first bit error rate B1 of the first signal S1 measured by the monitoring circuit 120 is greater than or equal to a preset threshold.

[0400] In some implementations, the control logic circuit 110 may determine whether the SNR of the first signal S1 measured by the monitoring circuit 120 is less than a preset threshold.

[0401] In this case, for example, the preset threshold for the bit error rate may be understood as a reference value for determining, by the device including the clock generating device 100H, the possibility of wireless communication using the first signal S1 received through the first clock signal CK1, but the present disclosure is not limited thereto.

[0402] In step S1431 , the control logic circuit 110 may connect the first cell GC1 to the inductor-capacitor tank circuit 1311 .

[0403] More specifically, when the first bit error rate B1 of the first signal S1 is greater than or equal to a preset threshold, the control logic circuit 110 may connect the first cell GC1 to the inductor-capacitor tank circuit 1311 .

[0404] The control logic circuit 110 may connect the first cell GC1 to the inductor-capacitor tank circuit 1311 in response to the first bit error rate B1 of the first signal S1 being greater than or equal to a preset threshold, so that the influence of the parasitic resistance of the inductor-capacitor tank circuit 1311 is offset.

[0405] Therefore, the control logic circuit 110 may reduce a first bit error rate B1 of the first signal S1 received in response to the first clock signal CK1 output through the LC oscillator 1310 .

[0406] Furthermore, in step S1432 , the control logic circuit 110 may disconnect the second cell GC2 previously connected to the inductor-capacitor tank circuit 1311 from the inductor-capacitor tank circuit 1311 .

[0407] More specifically, the control logic circuit 110 may disconnect the second cell GC2 from the inductor-capacitor tank circuit 1311 in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold, so that the power applied to the phase-locked loop circuit 130H is reduced.

[0408] Therefore, the control logic circuit 110 can minimize the power consumed by the PLL circuit 130H to generate the first clock signal CK1.

[0409] Referring to the above configuration, the control logic circuit 110 may increase or decrease the magnitude of power applied to the phase-locked loop circuit 130H based on the signal quality of the first signal S1 received in response to the first clock signal CK1 .

[0410] Therefore, the clock generating apparatus 100H of the present disclosure can improve the power efficiency of the phase-locked loop circuit 130H based on the signal quality of the first signal S1 received in response to the first clock signal CK1.

[0411] Fig.15 is a block diagram showing an example of a clock generation device which also includes a decoder.

[0412] Reference Fig.15 The clock generating device 100I may include a control logic circuit 110 , a monitoring circuit 120 , a decoder 1510 and a phase-locked loop circuit 130 .

[0413] in this case, Fig.15 The clock generating device 100I shown in FIG. 1 can be understood as Figure 1A An example of a clock generating apparatus 100 is shown in FIG. Therefore, the same reference numerals will be assigned to components that are the same as or substantially the same as those described above, and duplicate contents thereof will be omitted to avoid redundancy.

[0414] The clock generating apparatus 1001 may further include a decoder 1510 coupled to the control logic circuit 110 .

[0415] In some embodiments, the decoder 1510 may include a lookup table (LUT) including a bit error rate of a signal received from the monitoring circuit 120 and a control signal corresponding to the bit error rate.

[0416] In some implementations, after providing the control signal to the phase-locked loop circuit 130 , the control logic circuit 110 may store the bit error rate of the received signal and the provided control signal in a lookup table.

[0417] In this case, the control logic circuit 110 may store the control signal according to each bit error rate and the bit error rate in a lookup table so that there is linearity between the control signal and the bit error rate.

[0418] In some embodiments, when the first bit error rate B1 of the first signal S1 is greater than or equal to a preset threshold, the control logic circuit 110 may use a lookup table to output a control signal for increasing the amount of power applied to the phase-locked loop circuit 130 .

[0419] Therefore, the control logic circuit 110 may increase the amount of power applied to the phase locked loop circuit 130 .

[0420] In some embodiments, when the first bit error rate B1 of the first signal S1 is less than a preset threshold, the control logic circuit 110 may output a control signal for reducing the amount of power applied to the phase-locked loop circuit 130 using a lookup table.

[0421] Therefore, the control logic circuit 110 may reduce the amount of power applied to the phase locked loop circuit 130 .

[0422] Referring to the above configuration, the control logic circuit 110 may output a control signal corresponding to the bit error rate of the received signal using a previously stored lookup table.

[0423] Therefore, the control logic circuit 110 may control the power (or current) applied to the phase-locked loop circuit 130 .

[0424] Therefore, the clock generating apparatus 100I according to the present disclosure can reduce the power and cost required to generate a control signal for controlling the phase-locked loop circuit 130 according to the bit error rate of the received signal.

[0425] As described above, in response to the first bit error rate B1 of the first signal S1 being greater than or equal to the preset threshold, the control logic circuit 110 of the present disclosure may increase the current applied to the oscillator 131 .

[0426] Therefore, the control logic circuit 110 may reduce a first bit error rate B1 of the first signal S1 received in response to the first clock signal CK1 output by the oscillator 131 .

[0427] Furthermore, the control logic circuit 110 may reduce the current applied to the oscillator 131 in response to the first bit error rate B1 of the first signal S1 being less than a preset threshold.

[0428] Therefore, the clock generating apparatus 100 of the present disclosure can minimize the power consumed by the PLL circuit 130 to generate the first clock signal CK1 .

[0429] Furthermore, the control logic circuit 110 may control a capacitor or a frequency divider connected to the output node N1 of the oscillator 131 while controlling a current applied to the oscillator 131 based on the first bit error rate B1 of the first signal S1 .

[0430] Therefore, the clock generating apparatus 100 of the present disclosure may maintain the frequency of the first clock signal CK1 outputted through the PLL circuit 130 .

[0431] Furthermore, the control logic circuit 110 may increase or decrease the magnitude of current (or power) applied to the PLL circuit 130 based on the signal quality (eg, the first bit error rate ( B1 )) of the first signal S1 received in response to the first clock signal CK1 .

[0432] Therefore, the clock generating apparatus 100 of the present disclosure can improve the power efficiency of the phase-locked loop circuit 130 based on the signal quality of the first signal S1 received in response to the first clock signal CK1.

[0433] Furthermore, the control logic circuit 110 may control the signal quality of the first signal S1 received in response to the first clock signal CK1 by controlling the boost current source and the overclock current source in a preset order.

[0434] The clock generating apparatus 100 of the present disclosure may minimize power applied to the phase-locked loop circuit 130 to improve the signal quality of the first signal S1 .

[0435] Furthermore, therefore, the clock generating apparatus 100 can minimize power consumption applied to the phase-locked loop circuit 130 to improve the signal quality of the first signal S1.

[0436] In some embodiments of the present disclosure, an apparatus for generating a clock may be configured to control power applied to a phase locked loop circuit based on a signal quality of a signal received in response to the clock signal.

[0437] Therefore, according to the apparatus for generating a clock of the present disclosure, the power efficiency of the phase-locked loop circuit can be improved.

[0438] In addition to the above embodiments, simple design modifications or easy changes of the embodiments will fall within the scope of the present disclosure. In addition, the technology that is easily modified using the embodiments of the present disclosure will fall within the scope of the present disclosure. Therefore, the scope of the present disclosure is not limited to the above embodiments, but is defined by the equivalents of the attached claims and the attached claims.

[0439] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to a particular implementation of a particular invention. Specific features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features may be described above as working in a particular combination, one or more features from a combination may be deleted from the combination in some cases, and a combination may involve a sub-combination or a variation of a sub-combination.

[0440] While the present disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that modifications and variations can be made therein without departing from the spirit and scope of the present disclosure as set forth in the following claims.

Claims

1. A device for generating a clock, the device comprising: The phase-locked loop circuit is configured to: generate a first clock signal having a specified frequency through an oscillator; A monitoring circuit is configured to: monitor a first bit error rate of a first signal received based on a first clock signal, thereby generating a monitoring result; as well as A control logic circuit is configured to: control the phase-locked loop circuit based on the monitoring result, Wherein, the control logic circuit is configured as: Based on the first bit error rate being equal to or greater than a threshold, connecting a first boost current source to an oscillator, wherein the first boost current source is included in a phase-locked loop circuit, and Based on the first bit error rate being less than a threshold, the second boost current source is disconnected from the oscillator, wherein the second boost current source is previously connected to the oscillator.

2. The device according to claim 1, wherein: The phase-locked loop circuit includes: a plurality of boost current sources, including a first boost current source and a second boost current source, and a plurality of capacitors corresponding to the plurality of boost current sources, and Wherein, the control logic circuit is configured as: Based on the first boosting current source being connected to the oscillator, a first capacitor corresponding to the first boosting current source among the plurality of capacitors is connected to an output node of the oscillator.

3. The device of claim 2, wherein: The phase-locked loop circuit includes: frequency divider, connected to the output node of the oscillator, and Wherein, the control logic circuit is configured as: Based on the first bit error rate being equal to or greater than a threshold, connecting a first overclocking current source to an oscillator, wherein the first overclocking current source is separated from the first boost current source; and The coefficient of the frequency divider is controlled so that the phase-locked loop circuit is configured to output a signal having the specified frequency in a state where the first overclocking current source is connected to the oscillator.

4. The device as claimed in claim 3, wherein: The phase-locked loop circuit includes a base current source configured to provide a base current to the oscillator, wherein the first overclocking current output from the first overclocking current source has a current amount that is a positive integer multiple of the base current, and The control logic circuit is further configured to control a coefficient of the frequency divider based on the first overclocking current source being connected to the oscillator, the coefficient having a value obtained by dividing the current by the base current, wherein the current is applied to the oscillator.

5. The device of claim 1, wherein: The phase-locked loop circuit includes: a phase detector configured to: output a phase difference between the first clock signal and a reference signal, and a loop filter configured to: control the oscillator based on the phase difference, and The control logic circuit is further configured to: control the gain of the loop filter based on the phase difference so that the first bit error rate is reduced.

6. The device of claim 2, wherein: The control logic circuit is also configured to: Based on the second boosting current source being disconnected from the oscillator, a second capacitor corresponding to the second boosting current source among the plurality of capacitors is disconnected from an output node of the oscillator.

7. The device of claim 3, wherein: The control logic circuit is also configured to: Based on the first bit error rate being less than the threshold, the second overclocking current source is disconnected from the oscillator, and The coefficient of the frequency divider is controlled so that the phase-locked loop circuit is configured to output a signal having the specified frequency in a state where the second overclocking current source is disconnected from the oscillator.

8. The device of claim 2, wherein: The monitoring circuit is further configured to monitor a second bit error rate of a second signal received based on a second clock signal output from a phase-locked loop circuit, wherein the second clock signal is output from the phase-locked loop circuit in a state where the first boost current source and the first capacitor are connected to the oscillator, and The control logic circuit is further configured to: perform the following processing based on the second bit error rate being equal to or greater than the threshold: connecting a third boost current source to the oscillator, wherein the third boost current source is connected in parallel with the first boost current source, and A third capacitor corresponding to the third boost current source is connected to the output node of the oscillator.

9. The device of claim 3, wherein: The first overclocking current source is configured to output a first overclocking current, which is greater than a first boosting current of the first boosting current source.

10. The apparatus of claim 1, further comprising: a decoder comprising a lookup table, the lookup table containing a first bit error rate of a first signal and a control signal corresponding to the first bit error rate, and The control logic circuit is further configured to: send a control signal to the phase-locked loop circuit based on the lookup table, and the control signal corresponds to a first bit error rate of the first signal received from the monitoring circuit.

11. A method for generating a clock, the method comprising: monitoring a first bit error rate of a first signal received based on a first clock signal, the first clock signal having a specified frequency; Based on the first bit error rate being equal to or greater than a threshold, connecting a first boost current source to an oscillator, the first boost current source being included in a phase-locked loop circuit; as well as Based on the first bit error rate being less than a threshold, the second boost current source is disconnected from the oscillator, wherein the second boost current source is previously connected to the oscillator.

12. The method of claim 11, wherein: The phase-locked loop circuit includes a plurality of capacitors corresponding to a plurality of boost current sources, the plurality of boost current sources including a first boost current source and a second boost current source, and Wherein, the method further comprises: Based on the first boosting current source being connected to the oscillator, a first capacitor among the plurality of capacitors is connected to an output node of the oscillator, wherein the first capacitor corresponds to the first boosting current source.

13. The method of claim 12, further comprising: connecting the first overclocking current source to the oscillator based on a second bit error rate of the second signal received according to the second clock signal output from the oscillator being equal to or greater than a threshold value, wherein the first overclocking current source is separated from the first boosting current source, and the second clock signal is output from the oscillator in a state where the first boosting current source and the first capacitor are connected to the oscillator, and The coefficient of the frequency divider connected to the output node is controlled so that the phase-locked loop circuit is configured to output a signal having the specified frequency in a state where the first overclocking current source is connected to the oscillator.

14. The method of claim 13, further comprising: receiving a phase difference between a second clock signal output from the oscillator and a reference signal, the phase difference being received in a state where the first boost current source and the first overclocking current source are connected to the oscillator; as well as A gain of a loop filter included in a phase-locked loop circuit is controlled based on the phase difference to reduce a second bit error rate.

15. The method of claim 12, further comprising: Based on the second boost current source being disconnected from the oscillator, a second capacitor among the plurality of capacitors is disconnected from the output node, wherein the second capacitor corresponds to the second boost current source.

16. A device for generating a clock, the device comprising: A phase-locked loop circuit is configured to: generate a first clock signal having a specified frequency through an inductor-capacitor oscillator; A monitoring circuit is configured to: monitor a first bit error rate of a first signal received based on a first clock signal, thereby generating a monitoring result; as well as A control logic circuit is configured to: control the phase-locked loop circuit based on the monitoring result, Among them, the inductor-capacitor oscillator includes: an inductor-capacitor tank circuit in which the inductor and capacitor are connected in parallel, and a plurality of cells, each of the plurality of cells comprising a plurality of transistors, the plurality of cells being connected in parallel with each other, and The control logic circuit is configured to connect a first unit from the plurality of units to the inductor-capacitor tank circuit based on a first bit error rate being equal to or greater than a threshold.

17. The apparatus of claim 16, wherein: The control logic circuit is further configured to disconnect the second unit from the inductor-capacitor tank circuit based on the first bit error rate being less than a threshold value.

18. The apparatus of claim 16, wherein: The phase-locked loop circuit includes: a phase detector configured to: output a phase difference between a first clock signal and a reference signal, the first clock signal being output from the inductor-capacitor oscillator, and a loop filter configured to control an inductor-capacitor oscillator based on a phase difference, and The control logic circuit is further configured to: based on the connection between the first unit and the inductor-capacitor tank circuit, control the gain of the loop filter based on the phase difference, so that the first bit error rate is reduced.

19. The apparatus of claim 16, further comprising: a decoder comprising a lookup table containing a first bit error rate of a received first signal and a control signal corresponding to the first bit error rate, and The control logic circuit is configured to send a control signal to the phase-locked loop circuit based on a lookup table, and the control signal corresponds to a first bit error rate received from the monitoring circuit.

20. The apparatus of claim 16, wherein: The monitoring circuit is further configured to: monitor a second bit error rate of a second signal received based on a second clock signal output from a phase-locked loop circuit, the second clock signal being output from the phase-locked loop circuit in a state where the first unit is connected to the inductor-capacitor tank circuit, and The control logic circuit is further configured to: based on the second bit error rate being equal to or greater than a threshold, connect the third unit to the inductor-capacitor tank circuit, and connect the third unit to the first unit in parallel.

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