Fast locking circuit, phase-locked loop system and control method

Abstract

The invention provides a fast locking circuit (2) which at least comprises a frequency detection module (21), a second charge pump (22), a VCO oscillation detection circuit (23) and a pulse width detection circuit (24), and the output end of the frequency detection module (21) is connected with the input end of the second charge pump (22) and the input end of the VCO oscillation detection circuit (23). A phase-locked loop system with a fast lock circuit (2) and a corresponding control method for fast lock in a phase-locked loop system are also provided. On the basis of a pure hardware circuit, the locking time of the whole phase-locked loop is shortened by introducing the quick locking module, controlling UP1 pulse signal output in stages and injecting charges into the low-pass filter capacitor by using the charge pump, the working efficiency is greatly improved, and the phase-locked loop is low in cost and easy to popularize.

Description

Technical Field

[0001] The present invention belongs to the field of chips, and specifically, relates to the technical field of phase-locked loops commonly used in chips, especially a built-in phase-locked loop circuit based on a source synchronous interface receiver circuit, and in particular, to a fast locking circuit and a phase-locked loop system provided with the fast locking circuit and a corresponding control method. Background Art

[0002] With the development of integrated circuits, high-speed serial transmission of data between modules has become increasingly important. The phase-locked loop module provides one or more clocks with required frequencies for the serial transmission of high-speed data to ensure that data can be accurately identified during the transmission or reception process.

[0003] The phase-locked loop is a negative feedback system that can realize the automatic tracking of the output signal to the input signal. When a phase error occurs in the system, the phase-locked loop will continuously compare and correct the frequency and phase of the local oscillation signal, and finally make the frequency of the output signal equal to the input reference clock after frequency division, and the loop will enter the locked state to realize automatic phase control.

[0004] The input of the phase-locked loop is a high-stability reference clock signal provided by a crystal oscillator with a frequency of fref. The reference clock signal and the feedback signal of the voltage-controlled oscillator after N-frequency division are simultaneously input into the frequency detector for comparison to generate a phase pulse error signal Up (or Dn); this signal controls the charge pump to output the charging (discharging) current Icp to charge (or discharge) the loop low-pass filter; the loop low-pass filter is connected to the control end of the voltage-controlled oscillator to increase (or decrease) the control voltage Vctrl of the voltage-controlled oscillator, thereby increasing (or decreasing) the output signal frequency of the VCO; after being divided by the frequency divider, the output feedback signal is sent back to the PFD for comparison with fref; this comparison is performed multiple times until the loop is locked, the phases of the input and output signals are aligned or there is a small phase difference, and the system remains stable. The output frequency fout = N·fref, and different output frequencies can be obtained by changing the frequency division ratio N.

[0005] In this process, the delay time of the loop feedback is long, and the phase-locked loop phase-locked time is long. In the actual analog and digital hybrid chip, each module is started in sequence, and the long phase-locked loop phase-locked time will affect the startup speed of the entire chip. Therefore, shortening the lock time in the phase-locked loop technology has always been an important research topic. In order to shorten the phase-locked loop lock time, the method of dynamically adjusting the charge pump current is usually adopted. However, this method not only considers changing the bandwidth, but also changes the loop filter parameters to ensure the stability of the loop. Therefore, it is more complicated, and it causes power consumption to increase while failing to maximize the optimization of the phase-locked loop lock time.

[0006] In the prior art, a technical solution is needed that can quickly shorten the locking time in the phase-locked loop technology, but there is no better and more efficient technical solution. Summary of the invention

[0007] In view of the technical defects existing in the prior art, the present invention provides a phase-locked loop fast locking circuit, which utilizes a method of comparing a phase-locked loop input reference clock with a loop feedback clock period to achieve frequency discrimination of the phase-locked loop frequency locking process, and can greatly shorten the time required for the phase-locked loop to start from power-on to the output frequency stabilizing to a predetermined index, thereby improving the performance index of the phase-locked loop.

[0008] According to one aspect of the present invention, a fast locking circuit 2 is provided, which at least includes a frequency comparison module 21, a second charge pump 22, a VCO oscillation detection circuit 23 and a pulse width detection circuit 24, and the output end of the frequency detection module 21 is connected to the input end of the second charge pump 22 and the pulse width detection circuit 24.

[0009] Preferably, the output of the pulse width detection circuit 24 serves as a control signal of the frequency comparison module 21 .

[0010] Preferably, the frequency comparison module 21 includes at least four binary frequency dividers, a phase selection circuit 25, and a double-edge frequency detector 26. The outputs of the four binary frequency dividers serve as inputs of the phase selection circuit 25, and the output of the double-edge frequency detector 26 serves as the output of the frequency detection module 21.

[0011] Preferably, the input signals of the double-edge frequency detector 26 are Fdiv_fc and Fref_fc respectively.

[0012] Preferably, the double-edge frequency detector 26 at least includes a sixth D flip-flop 261, a seventh D flip-flop 262, and an eighth D flip-flop 263 with a high-level reset function, a first two-to-one data selector 264, a second two-to-one data selector 265, a third two-to-one data selector 266, and a fourth two-to-one data selector 267, and the outputs of the first two-to-one data selector 264 and the second two-to-one data selector 265 are respectively used as inputs of the sixth D flip-flop 261 and the seventh D flip-flop 262, and the output of the eighth D flip-flop 263 is used as inputs of the third two-to-one data selector 266 and the fourth two-to-one data selector 267.

[0013] Preferably, the fast locking circuit 2 further comprises a locking detection circuit 3, which is used to monitor the locking state of the phase-locked loop in real time to ensure the realization of the final locking state.

[0014] Preferably, the lock detection circuit 3 at least includes a first D flip-flop 31 and a second D flip-flop 32 with a high-level set function, a third D flip-flop 33, a fourth D flip-flop 34, and a fifth D flip-flop 35 with a high-level reset function, as well as a first buffer 36, a second buffer 37, a first NOR gate 38, and a first NAND gate 39, wherein the outputs of the first D flip-flop 31 and the second D flip-flop 32 serve as inputs of the first NAND gate 39.

[0015] Preferably, the pulse width detection circuit 24 at least includes a delay module 241 and a ninth D flip-flop 242 and a tenth D flip-flop 243 with a high-level setting function, wherein the output of the delay module 241 serves as the input of the ninth D flip-flop 242, and the output of the ninth D flip-flop 242 serves as the input of the tenth D flip-flop 243.

[0016] According to another aspect of the present invention, a fast locking phase-locked loop system is provided, comprising at least a phase-locked loop circuit 1 consisting of a frequency detector, a first charge pump 11, and a frequency divider, and characterized in that it also includes the above-mentioned fast locking circuit 2.

[0017] According to another aspect of the present invention, a phase-locked loop fast locking control method for the above-mentioned fast locking phase-locked loop system is also provided, characterized in that it comprises the following steps:

[0018] Step a. The oscillation detection circuit 23 detects that the VCO is not oscillating, controls the data selector 14 to output a rising edge pulse, so that the frequency detection module 21 in the fast locking circuit outputs a longer UP1 pulse, and drives the second charge pump 22 to pre-charge the capacitor in the low-pass filter in the phase-locked loop;

[0019] Step b. controlling the second charge pump 22 to accelerate the charging of the capacitor in the low-pass filter through the frequency detection module 21;

[0020] Step c. When the frequency of the reference signal and the frequency of the feedback signal are approximately equal, closing the fast locking circuit 2.

[0021] Preferably, in the above step a, in a variation, when the oscillation detection circuit 23 detects that the VCO output frequency is lower than a first threshold, for example, lower than 100 Hz, the control data selector 14 outputs a rising edge pulse, that is, when the VCO has started to oscillate but the oscillation value is very small, a rising edge pulse is also provided, and its processing logic is the same as the operation mode when the VCO is not oscillating.

[0022] Preferably, step b comprises the following steps:

[0023] Step b1. Perform frequency division operation on the signals from the frequency divider and the reference path at the same time to obtain a signal Fdiv_fc and eight signals Phase1 to Phase8 with the same frequency and different phases;

[0024] Step b2. Select one of the eight clock signals Phase1 to Phase8 as the input signal Fref_fc of the double-edge frequency detector 26 through the phase selection module;

[0025] Step b3. The double-edge frequency detector 26 measures the difference between the rising edge and the falling edge of Fdiv_fc and Fref_fc to compare the frequency of the reference signal with the frequency of the feedback signal, and outputs the corresponding rising pulses UP1, UP1B and falling pulses DN1, DN1B to the second charge pump 22;

[0026] Step b4: The second charge pump 22 charges and discharges the capacitor in the low-pass filter to complete frequency adjustment.

[0027] Preferably, the step b1 further comprises the following steps:

[0028] Step b21. Processing the eight clock signals Phase1 to Phase8 with different phases generated by the frequency divider using a phase sampling circuit to obtain non-overlapping clock signals A1 to A8;

[0029] Step b22. Use 2Fdiv as the input clock signal of the D flip-flop, sample the A1~A8 signals, output B1~B8 signals, and use the B1~B8 as the control end signals of the 8 data selectors, namely the eight clock signals Phase1~Phase8.

[0030] Compared with the prior art, this embodiment is based on a pure hardware circuit. By introducing a fast locking module, the UP1 pulse signal output is controlled in stages, and a charge pump is used to inject charge into the low-pass filter capacitor to reduce the locking time of the overall phase-locked loop. At the same time, when the frequency is close to being equal and entering the phase-locked stage, the fast locking module is turned off to avoid affecting the loop parameters. According to simulation verification, the time required for the phase-locked loop to start from power-on to the output frequency stabilizing to a predetermined index can be effectively shortened. This technical solution is efficient, has low implementation cost compared with the prior art, is easy to apply, and is easy to effectively promote. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0032] Figure 1A schematic diagram showing the overall framework of a phase-locked loop circuit with a fast locking circuit according to a first embodiment of the present invention is shown;

[0033] Figure 2 A schematic diagram of a phase-locked loop system with a fast locking circuit according to a first embodiment of the present invention is shown;

[0034] Figure 3 A circuit diagram of an oscillation detection circuit in a fast locking circuit according to a first embodiment of the present invention is shown;

[0035] Figure 4 A schematic diagram of a frame of a frequency comparison (FC) circuit with a fast locking circuit according to a first embodiment of the present invention is shown;

[0036] Figure 5 A circuit diagram showing a phase selection circuit in a fast locking circuit according to a first embodiment of the present invention is shown;

[0037] Figure 6 A timing diagram of a phase selection circuit in a fast locking circuit according to a first embodiment of the present invention is shown;

[0038] Figure 7 A circuit diagram showing a phase sampling circuit in a fast locking circuit according to a first embodiment of the present invention;

[0039] Figure 8 A timing diagram of a phase sampling circuit corresponding to a control method for fast locking in a phase-locked loop system with a fast locking circuit according to a first embodiment of the present invention is shown;

[0040] Fig. 9 A circuit diagram of a double-edge frequency detector circuit in a fast locking circuit according to a first embodiment of the present invention is shown;

[0041] Fig.10 A schematic diagram showing the timing of input and output signals of a double-edge phase frequency detector corresponding to a control method for fast locking in a phase-locked loop system with a fast locking circuit according to the first embodiment of the present invention;

[0042] Fig.11 A schematic diagram showing simulation results of a double-edge phase frequency detector corresponding to a control method for fast locking in a phase-locked loop system with a fast locking circuit according to the first embodiment of the present invention is shown;

[0043] Fig.12 A circuit diagram of a pulse width detection circuit in a fast locking circuit according to a first embodiment of the present invention is shown;

[0044] Fig.13 A circuit diagram showing a lock detection circuit in a fast lock circuit according to a first embodiment of the present invention; and

[0045] Fig.14 A time diagram showing a comparison between a phase-locked loop circuit including a fast locking circuit and a phase-locked loop circuit not including the fast locking circuit according to the first embodiment of the present invention is shown. DETAILED DESCRIPTION

[0046] In order to better illustrate the technical solution of the present invention, the present invention is further described below in conjunction with the accompanying drawings.

[0047] The embodiment of the present invention provides a phase-locked acceleration circuit based on the built-in PLL of the source synchronous interface receiver circuit. Figure 1 As shown, it includes three parts: the first part is a traditional phase-locked loop circuit 1 (a frequency detector, a first charge pump 11, a low-pass filter, a voltage-controlled oscillator and a frequency divider); the second part is a fast locking circuit 2, the circuit is as shown Figure 2 As shown in the red frame, it is composed of a frequency detection module 21, a second charge pump 22, a VCO oscillation detection circuit 23 and a pulse width detection circuit 24; the third part is a lock detection circuit 3.

[0048] Further, refer to Figures 1 to 3 In the embodiment shown, fast locking is performed in three stages to ensure the optimization of the locking time. The first stage: the output of the voltage-controlled oscillator (VCO) is detected by the oscillation detection circuit. If the VCO does not oscillate or the oscillation output frequency is very small, a rising edge pulse is output through the data selector, so that the frequency detection circuit in the fast locking module outputs a longer UP1 pulse, and drives the charge pump to pre-charge the capacitor in the low-pass filter; the second stage: when the oscillation detector detects that the feedback signal has two rising edges output, it is considered that the VCO has oscillated, and the data selector 14 normally outputs the feedback signal CK_FB. At this time, the phase-locked loop is in a frequency adjustment state, and the frequency detection circuit in the fast locking circuit is used to accelerate the charging of the capacitor in the low-pass filter by the second charge pump 22; the third stage: when the reference frequency and the feedback frequency are close to being equal, the fast locking circuit is turned off, and the circuit is restored to a traditional phase-locked loop circuit to perform a phase adjustment operation.

[0049] The oscillation detection circuit in the first stage is as follows Figure 3As shown, it consists of two D flip-flops with high-level reset function. The data input of the first D flip-flop is connected to the power supply VDD, and the data input of the second D flip-flop is connected to the output of the first D flip-flop. The clock input of the two D flip-flops is the VCO output signal CK_FB. The condition for determining whether the VCO oscillates is to detect whether the VCO output signal outputs two rising edges. The working principle is as follows: when the first rising edge is detected, the output Q of the first D flip-flop jumps to high; when the second rising edge is detected, the second D flip-flop receives the output signal of the first D flip-flop, and the output Ctrl1 signal of the second D flip-flop jumps to high, and the data selector starts to output the VCO output signal CK_FB.

[0050] In the second stage, directly comparing the frequencies of the reference signal and the feedback signal is relatively complicated. First, we start with the concept and measure the period difference between the two signals ( ΔT ) method is used to simplify the comparison of the reference signal and the feedback signal frequency.

[0051] Frequency comparison circuit such as Figure 4 As shown, it includes four binary frequency dividers, a phase selection module (PhaseSelection) 24, a dual-edge frequency detector (Dual Gate PFD) 25, a charge pump (CP) 26 and a pulse detector 27. Preferably, the four binary frequency dividers can use the same binary divider, and according to Figure 4 The specific working principle is as follows: firstly, the feedback signal 2Fdiv and the reference signal 4Fref are divided to obtain the signal Fdiv_fc and eight signals Phase1 to Phase8 with the same frequency and different phases; secondly, one of the eight clock signals Phase1 to Phase8 is selected as the input signal Fref_fc of the double-edge frequency detector through the phase selection module; finally, the double-edge frequency detector measures the difference between the rising edge and the falling edge of Fdiv_fc and Fref_fc to compare the frequency of the reference signal with the frequency of the feedback signal, and outputs the corresponding rising pulses UP1, UP1B and falling pulses DN1, DN1B to the second charge pump.

[0052] In order to ensure that the two signal edges compared by the double-edge frequency and phase detector are what we expect, the present invention provides a phase selection circuit structure, specifically as follows Figure 5As shown, it includes a phase sampling circuit, a D flip-flop and a data selector. The working principle of the phase selection circuit is as follows: first, the phase sampling circuit (Phase Sample) is used to process the 8 reference signals Phase1 to Phase8 with different phases generated by the frequency divider to obtain non-overlapping clock signals A1 to A8; secondly, 2Fdiv is used as the clock signal, and the A1 to A8 signals are sampled through the D flip-flop to output B1 to B8 signals; B1 to B8 are used as the control end signals of the 8 data selectors, which determine the output result of the phase selection circuit, that is, one of the eight clock signals Phase1 to Phase8 is selected as the output. The corresponding timing diagram is shown in FIG. Figure 6 Further, refer to Figure 5 , Figure 6 Those skilled in the art will appreciate that preferably eight phase sampling circuits are provided so as to process eight signals of the frequency divider respectively, and these changes are within the protection scope of the present invention.

[0053] Phase sampling circuit such as Figure 7 As shown, it includes input pair tubes M1 and M2, tail current tube M3, reset tube M4 and an inverter. When the input signal of the phase sampling circuit is Phase1 and Phase2, the output signal of the phase sampling circuit is as follows: Figure 8 As shown. When Phase1 is high, the tail current tube is turned on and the input pair tube works normally. At this time, if Phase2 is low and Phase2B is high, the tail current flows through the right branch, and the right branch output OUTP is low; when Phase1 is low, the tail current tube is turned off and OUTP output jumps to high. OUTP outputs OUT signal through the inverter, and so on, you can get non-overlapping signals A1~A8.

[0054] The circuit diagram of the double-edge frequency detector 26 is as follows Fig. 9 As shown, the double-edge frequency detector 26 at least includes a sixth D flip-flop 261, a seventh D flip-flop 262, and an eighth D flip-flop 263 with a high-level reset function, a first two-to-one data selector 264, a second two-to-one data selector 265, a third two-to-one data selector 266, and a fourth two-to-one data selector 267, and the outputs of the first two-to-one data selector 264 and the second two-to-one data selector 265 are respectively used as inputs of the sixth D flip-flop 261 and the seventh D flip-flop 262, and the output of the eighth D flip-flop 263 is used as inputs of the third two-to-one data selector 266 and the fourth two-to-one data selector 267.

[0055] At the input end of the data selector, transmission gates of equal size are matched with inverters to ensure the consistency of signal delays between Fr_dly and Fr_dlyB, and between Fd_dly and Fd_dlyB at the output ends of the data selector.

[0056] Assume that the phase relationship between the input signals Fref_fc and Fdiv_fc is as follows: Fig.10 As shown, when the data selector control signal C1 is 0, the Fr_dly and Fd_dly signals are output. At this time, the frequency and phase detector responds to the rising edge. When the output phases of the rising edges of the Fr_dly and Fd_dly signals are inconsistent, it will cause the output terminals Q1 and Q2 of the D flip-flops DFF1 and DFF2 to jump high at different times. When Q2 jumps to high and Q1 remains unchanged, the output of the XOR gate is high, and the output of the AND gate AND2 becomes low. The output terminals UP1 and DN1 depend on the input of the selector 0 terminal, that is, the output of the D flip-flop DFF3. At this time, the output terminal C1 of DFF3 still remains at the low level after reset, and C1B still remains at the high level after reset, the output of UP1 is high, and the output of DN1 is low. When the output terminals Q1 and Q2 of DFF1 and DFF2 both jump high, the AND gate outputs a high level. After being delayed by the delay unit, the reset signal jumps to high, the outputs Q1 and Q2 of DFF1 and DFF2 jump to low, the XOR gate output is low, the AND gate AND2 output C2 is low, the UP1 output is low, and the DN1 output is low. The reset signal jumps to high, causing a rising edge pulse on the DFF3 clock, and the DFF3 output C1 jumps to high, and the input data selector output becomes Fr_dlyB and Fd_dlyB; at this time, for the Fr_dly and Fd_dly signals, the frequency and phase detector responds to the falling edge. When the Fd_dly falling edge comes first, the output Q2 of the D flip-flop DFF2 jumps to high while Q1 remains unchanged, the XOR gate output is high, and the output terminals UP1 and DN1 depend on the input of the selector 0 terminal, that is, the output C1 and C1B of the D flip-flop DFF3. At this time, the output terminal C1 of DFF3 still maintains the previous high level state, the output DN1 is high, and the output UP1 is low.

[0057] Consider the following two cases. When the frequency of the feedback signal is higher than that of the reference signal, the phase difference between the two rising edges is smaller than the phase difference between the two falling edges, the output UP has a wider pulse, and the charge pump charges the capacitor within one cycle; when the frequency of the feedback signal is lower than that of the reference signal, the phase difference between the two rising edges is larger than the phase difference between the two falling edges, the output DN has a wider pulse, and the charge pump discharges the capacitor within one cycle. The simulation results of the double-edge frequency detector are shown in Figure 1. Fig.11 shown.

[0058] When the output Ctrl2 of the pulse width detection circuit outputs a high level, the operation of the fast locking circuit is turned off to prevent the fast locking circuit from generating additional ripples during the phase locking process to affect the locking of the phase-locked loop itself.

[0059] Pulse width detection circuit such as Fig.12As shown, it includes two D flip-flops with high-level reset function and a delay module. The principle of the pulse width detection circuit is as follows: when the reset signal Reset is 1, the circuit outputs Q1 and Ctrl2 are low; when the reset signal Reset is 0, the circuit works normally. The UP1 signal outputs the Di signal to the D flip-flop D1 through the delay module, and the UP1 signal is used to sample Di. If the UP1 pulse width is greater than t, the output Q1 jumps to high, Q1B jumps to low, and Ctrl2 remains in the original state 0; if the UP1 pulse width is less than t, the output Q1 jumps to low, Q1B jumps to high, and Ctrl2 output jumps to high.

[0060] For example, preferably, the pulse width detection circuit 24 includes at least a delay module 241 and a ninth D flip-flop 242 and a tenth D flip-flop 243 with a high-level setting function, wherein the output of the delay module 241 serves as the input of the ninth D flip-flop 242, and the output of the ninth D flip-flop 242 serves as the input of the tenth D flip-flop 243.

[0061] Furthermore, a lock detection circuit is introduced to monitor the lock state of the phase-locked loop in real time to ensure the realization of the final lock state. Fig.13 As shown. The sequential logic consists of two D flip-flops with high-level set functions and three D flip-flops with high-level reset functions, two buffers, a NOR gate and a NAND gate. When the set signal Set is at a high level, the outputs Q1 and Q2 of the D flip-flops D1 and D2 with high-level set functions are both high, and Q1B and Q2B are both low, so the output of the NAND gate is high, so that the D flip-flops D3, D4, and D5 with high-level reset functions are reset, and the pll lock signal output by D5 is low, which indicates that the locked state has not been reached. When the set signal Set is at a low level, the circuit works normally.

[0062] For example, in a preferred embodiment, the lock detection circuit 3 includes a first D flip-flop 31 and a second D flip-flop 32 having a high-level set function, a third D flip-flop 33, a fourth D flip-flop 34, and a fifth D flip-flop 35 having a high-level reset function, as well as a first buffer (36), a second buffer 37, a first NOR gate 38, and a first NAND gate 39.

[0063] The input signals of the lock detection circuit 3 are the reference signal Fref and the feedback signal Fdiv of the phase-locked loop circuit. The condition for determining whether the phase-locked loop has reached the locked state is: whether the condition is satisfied for four consecutive cycles. The working principle is as follows: the reference clock signal Fref and the feedback clock signal Fdiv are separated by Δφ (here expressed as time), and both signals are input into D flip-flops D1 and D2 after a delay of τ. Consider the following two cases: When the outputs Q1 and Q2 of D flip-flops D1 and D2 are sampled at the rising edge of the clock, the signals obtained are both low, Q1B and Q2B are both high, and the output after passing through the NAND gate is low. If the outputs of the NAND gate are all low for three consecutive cycles, D4 will output a rising edge. If the outputs of the NAND gate are all low for four consecutive cycles, D5 will output a pll lock signal that jumps to a high potential. This potential indicates that the phase-locked loop circuit has reached a locked state.

[0064] like The signals sampled by D1 and D2 must be one high and one low. The output after passing through the NAND gate is high potential, and the D flip-flops D3, D4, and D5 are reset. The Pll_lock signal output is low, and the circuit is not locked. When the circuit loses lock at a certain moment after being locked, that is, When the sampling is performed, the opposite signals of Q1 and Q2 will reset the output of D5, and the Pll_lock signal will flip to a low potential until the next time it is determined to be in a locked state.

[0065] Further, referring to the above Figures 1 to 14 Those skilled in the art will appreciate that the phase-locked loop system with a fast locking circuit provided by the present invention can achieve fast locking of the phase-locked loop system. Specifically, the fast locking can be achieved by referring to the following steps:

[0066] Step a. When the oscillation detection circuit (23) detects that the VCO is not oscillating or the oscillation output frequency is very low, the data selector (14) is controlled to output a rising edge pulse, so that the frequency detection module (21) in the fast locking module outputs a longer UP1 pulse, and drives the second charge pump (22) to pre-charge the capacitor in the low-pass filter in the phase-locked loop;

[0067] Step b. controlling the second charge pump (22) through the frequency detection module (21) to accelerate the charging of the capacitor in the low-pass filter;

[0068] Step c. When the frequency of the reference signal and the frequency of the feedback signal are approximately equal, closing the fast locking circuit (2).

[0069] Specifically, those skilled in the art understand that, in a preferred embodiment, the VCO oscillation output frequency in step a may be in a range lower than 100 Hz, and these changes are within the protection scope of the present invention;

[0070] Furthermore, in a variation, the step b includes the following steps:

[0071] Step b1. Perform frequency division operation on the signals from the frequency divider and the reference path at the same time to obtain a signal Fdiv_fc and eight signals Phase1 to Phase8 with the same frequency and different phases;

[0072] Step b2. Select one of the eight clock signals Phase1 to Phase8 as the input signal Fref_fc of the double-edge frequency detector through the phase selection module.

[0073] Step b3. The double-edge frequency detector measures the difference between the rising edge and the falling edge of Fdiv_fc and Fref_fc to compare the frequency of the reference signal with the frequency of the feedback signal, and outputs the corresponding rising pulses UP1, UP1B and falling pulses DN1, DN1B to the second charge pump;

[0074] Step b4. The second charge pump charges and discharges the capacitor in the low-pass filter accordingly to achieve the desired frequency adjustment.

[0075] More specifically, the step b2 further includes the following steps:

[0076] Step b21. Processing the eight clock signals Phase1 to Phase8 with different phases generated by the frequency divider using a phase sampling circuit to obtain non-overlapping clock signals A1 to A8;

[0077] Step b22. Use 2Fdiv as the input clock signal of the D flip-flop, sample the A1~A8 signals, and output the B1~B8 signals;

[0078] Step b23. B1~B8 serve as control end signals of 8 data selectors, which determine the output result of the phase selection circuit, that is, one is selected from the eight clock signals Phase1~Phase8 as the output signal Fref_fc of the phase selection circuit.

[0079] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art may make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A fast locking circuit (2), comprising at least a frequency comparison module (21), a second charge pump (22), a VCO oscillation detection circuit (23) and a pulse width detection circuit (24), wherein the output end of the frequency detection module (21) is connected to the input ends of the second charge pump (22) and the pulse width detection circuit (24).

2. The fast locking circuit (2) according to claim 1, characterized in that: The output of the pulse width detection circuit (24) serves as a control signal of the frequency comparison module (21).

3. The fast locking circuit (2) according to claim 1 or 2, characterized in that: The frequency comparison module (21) comprises at least four binary frequency dividers, a phase selection circuit (25), and a double-edge frequency detector (26); the outputs of the four binary frequency dividers serve as inputs of the phase selection circuit (25), and the output of the double-edge frequency detector (26) serves as the output of the frequency detection module (21).

4. The fast locking circuit (2) according to claim 3, characterized in that: The input signals of the double-edge frequency detector (26) are Fdiv_fc and Fref_fc respectively.

5. The fast locking circuit (2) according to claim 3 or 4, characterized in that: The double-edge frequency detector (26) at least comprises a sixth D flip-flop (261), a seventh D flip-flop (262), an eighth D flip-flop (263) having a high-level reset function, a first two-to-one data selector (264), a second two-to-one data selector (265), a third two-to-one data selector (266), and a fourth two-to-one data selector (267), wherein the outputs of the first two-to-one data selector (264) and the second two-to-one data selector (265) are respectively used as inputs of the sixth D flip-flop (261) and the seventh D flip-flop (262), and the output of the eighth D flip-flop (263) is used as inputs of the third two-to-one data selector (266) and the fourth two-to-one data selector (267).

6. The fast locking circuit (2) according to any one of claims 1 to 5, characterized in that: It also includes a lock detection circuit (3) which is used to monitor the lock state of the phase-locked loop in real time to ensure the realization of the final lock state.

7. The fast locking circuit (2) according to claim 6, characterized in that: The lock detection circuit (3) at least comprises a first D flip-flop (31) and a second D flip-flop (32) having a high-level setting function, a third D flip-flop (33), a fourth D flip-flop (34), and a fifth D flip-flop (35) having a high-level reset function, as well as a first buffer (36), a second buffer (37), a first NOR gate (38), and a first NAND gate (39), wherein the outputs of the first D flip-flop (31) and the second D flip-flop (32) serve as inputs of the first NAND gate (39).

8. The fast locking circuit (2) according to any one of claims 1 to 7, characterized in that: The pulse width detection circuit (24) comprises at least a delay module (241) and a ninth D flip-flop (242) and a tenth D flip-flop (243) having a high-level setting function, wherein the output of the delay module (241) serves as the input of the ninth D flip-flop (242), and the output of the ninth D flip-flop (242) serves as the input of the tenth D flip-flop (243).

9. A fast-locking phase-locked loop system, comprising at least a phase-locked loop circuit (1) consisting of a frequency detector, a first charge pump (11), and a frequency divider, characterized in that It also comprises a fast locking circuit (2) according to any one of claims 1 to 8.

10. A phase-locked loop fast locking control method for a fast locking phase-locked loop system according to claim 9, characterized in that: The steps include: Step a. When the oscillation detection circuit (23) detects that the VCO is not oscillating, the data selector (14) is controlled to output a rising edge pulse, so that the frequency detection module (21) in the fast locking circuit outputs a longer UP1 pulse, and drives the second charge pump (22) to pre-charge the capacitor in the low-pass filter in the phase-locked loop; Step b. controlling the second charge pump (22) through the frequency detection module (21) to accelerate the charging of the capacitor in the low-pass filter; Step c. When the frequency of the reference signal and the frequency of the feedback signal are approximately equal, closing the fast locking circuit (2).

11. The control method according to claim 10, wherein step b comprises the following steps: Step b1. Perform frequency division operation on the signals from the frequency divider and the reference path at the same time to obtain a signal Fdiv_fc and eight signals Phase1 to Phase8 with the same frequency and different phases; Step b2. Select one of the eight clock signals Phase1 to Phase8 as the input signal Fref_fc of the double-edge frequency detector (26) through the phase selection module; Step b3. The double-edge frequency detector (26) measures the difference between the rising edge and the falling edge of Fdiv_fc and Fref_fc to compare the frequency of the reference signal with the frequency of the feedback signal, and outputs corresponding rising pulses UP1, UP1B and falling pulses DN1, DN1B to the second charge pump (22); Step b4. The second charge pump (22) charges and discharges the capacitor in the low-pass filter to complete frequency adjustment.

12. The control method according to claim 11, wherein step b1 further comprises the following steps: Step b21. Processing the eight clock signals Phase1 to Phase8 with different phases generated by the frequency divider using a phase sampling circuit to obtain non-overlapping clock signals A1 to A8; Step b22. Use 2Fdiv as the input clock signal of the D flip-flop, sample the A1~A8 signals, output B1~B8 signals, and use the B1~B8 as the control end signals of the 8 data selectors, namely the eight clock signals Phase1~Phase8.

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