Phase synchronization circuit, radio frequency power supply and semiconductor process equipment

Abstract

The invention provides a phase synchronization circuit, a radio frequency power supply and semiconductor process equipment, which are applied to the technical field of semiconductor process equipment, and the circuit comprises a phase-locked loop module, a phase adjustment module and a signal output module provided with a first output port and a second output port, the phase-locked loop module generates a target clock signal based on a preceding-stage synchronizing signal or a reference clock signal, the signal output module provides a driving signal and a synchronizing signal which are in the same phase based on the target clock signal, and the first output port is used for outputting the driving signal to the radio frequency circuit, so that the radio frequency circuit outputs a radio frequency signal according to the driving signal; the second output port is used for outputting a synchronizing signal to a phase synchronizing circuit at a backward stage, the phase adjusting module determines a target phase offset according to the radio frequency power of the radio frequency signal, and the signal output module adjusts the phase of the driving signal according to the target phase offset, so that the phase of the radio frequency signal output by the radio frequency circuit reaches the target phase. Therefore, actual application requirements are met.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor process equipment, and in particular to a phase synchronization circuit, a radio frequency power supply and semiconductor process equipment. Background Art

[0002] RF power supply is a core component of semiconductor process equipment. Taking ICP (Inductively Coupled Plasma) etcher as an example, it usually has two RF power supplies inside, one of which is used to provide energy to start the plasma, and the other is used to control the direction of plasma movement. In addition, according to general process requirements, the two RF power supplies need to work at the same frequency and phase. Therefore, a phase synchronization circuit is needed to synchronize the phase deviation between different RF power supplies to achieve coordinated operation of multiple RF power supplies.

[0003] Combination Figure 1 As shown, taking two RF power supplies as an example, one of them is used as the main power supply and the other is used as the slave power supply. The DDS (Direct Digital Synthesizer) module of the main power supply is connected to the DDS module of the slave power supply. The DDS module of the main power supply provides driving signals to the RF circuit of the main power supply and the DDS module of the slave power supply respectively. The DDS module of the slave power supply drives the RF circuit of the slave power supply according to the driving signal, thereby achieving the same phase operation as the main power supply.

[0004] For the RF power supply, the RF circuit outputs RF power according to the driving signal provided by the DDS module. Due to the influence of the performance of the components of the RF circuit itself, environmental interference and other factors, the phase of the RF signal output by the RF circuit will change with the change of RF power. Therefore, when adjusting the RF power output by the RF power supply, it is necessary to adjust the phase of the driving signal output by the DDS module in real time to ensure that the phase of the RF signal remains unchanged. However, combined with Figure 1 As shown, adjusting the driving signal of the DDS module of the main power supply will cause the phase of the driving signal obtained by the DDS module in the slave power supply to change, thereby changing the phase of the RF signal provided by the slave power supply, and ultimately causing the main power supply and the slave power supply to output RF signals with different phases, making it difficult to meet process requirements. Summary of the invention

[0005] In view of this, the present application is dedicated to providing a phase synchronization circuit, a radio frequency power supply and a semiconductor process equipment to solve the problem that the phase of the radio frequency signal of the main power supply and the slave power supply is different due to the change of radio frequency power, which is difficult to meet the actual application requirements.

[0006] In a first aspect, the present application provides a phase synchronization circuit, comprising: a phase-locked loop module, a phase adjustment module and a signal output module, wherein the signal output module comprises a first output port and a second output port, wherein:

[0007] The phase-locked loop module is used to generate a target clock signal according to the synchronization signal of the previous stage or its own reference clock signal;

[0008] The signal output module is used to provide a driving signal and a synchronization signal according to the target clock signal;

[0009] The first output port is used to output the driving signal to the radio frequency circuit, so that the radio frequency circuit outputs a radio frequency signal according to the driving signal;

[0010] The second output port is used to output the synchronization signal to a subsequent phase synchronization circuit;

[0011] The phase adjustment module is used to determine a target phase offset according to the radio frequency power of the radio frequency signal;

[0012] The signal output module is further used to adjust the phase of the driving signal according to the target phase offset so that the phase of the radio frequency signal output by the radio frequency circuit reaches the target phase.

[0013] In an optional implementation, the phase adjustment module includes: a phase correction module and a configuration module, wherein:

[0014] The phase correction module is used to provide the target phase offset corresponding to the RF power to the configuration module according to a preset mapping relationship between the RF power and the target phase offset;

[0015] The configuration module is used to provide configuration information to the signal output module so that the signal output module sets the frequency and phase of the drive signal and the synchronization signal respectively according to the configuration information; the configuration module is also used to adjust the configuration information according to the target phase offset so that the signal output module adjusts the phase of the drive signal.

[0016] In an optional implementation, the phase-locked loop module is further used to identify a current operating mode of the phase synchronization circuit;

[0017] If the phase synchronization circuit is in the main power mode, the phase-locked loop module is used to generate the target clock signal according to the reference clock signal;

[0018] If the phase synchronization circuit is in a slave power mode, the phase-locked loop module is used to generate the target clock signal according to the synchronization signal of the previous stage.

[0019] In an optional implementation, the phase-locked loop module includes a first input terminal and a second input terminal, the first input terminal is used to receive the synchronization signal of the previous stage, and the second input terminal is used to receive the reference clock signal;

[0020] The phase-locked loop module is used to: if the first input end does not receive the synchronization signal of the previous stage within a preset time length, determine that the phase synchronization circuit is in the main power supply mode; if the first input end receives the synchronization signal of the previous stage within the preset time length, determine that the phase synchronization circuit is in the slave power supply mode.

[0021] In an optional implementation, the signal output module includes: a signal conversion module, a first signal circuit and a second signal circuit, wherein:

[0022] The signal conversion module is connected to the first signal circuit and the second signal circuit respectively;

[0023] The signal conversion module is used to provide a reference drive signal and a reference synchronization signal according to the target clock signal, and to adjust the phase of the reference drive signal according to the target phase offset so as to adjust the phase of the drive signal;

[0024] The first signal circuit is used to convert the reference driving signal into the driving signal;

[0025] The second signal circuit is used for converting the reference synchronization signal into the synchronization signal.

[0026] In an optional implementation, the reference driving signal is a differential signal, and the first signal circuit includes: a first level conversion circuit, a first comparison circuit, a first two-frequency division circuit, and a second level conversion circuit;

[0027] The first level conversion circuit is used to raise the voltage difference of the reference driving signal to a preset value and generate a first differential signal;

[0028] The first comparison circuit is used for converting the first differential signal into a first square wave signal, wherein the frequency of the first square wave signal is the same as the frequency of the first differential signal;

[0029] The first two-frequency dividing circuit is used to perform frequency division processing on the first square wave signal to form a second differential signal with a duty cycle of 50% and a frequency of a set frequency;

[0030] The second level conversion circuit is used for converting the second differential signal into a single-ended signal to form the driving signal.

[0031] In an optional implementation, the first signal circuit further includes: a first filtering circuit, and / or a second driving circuit and a first DC blocking circuit, wherein:

[0032] The first filtering circuit is used to filter out the noise signal of the target frequency band in the reference driving signal;

[0033] The second driving circuit is used to enhance the driving capability of the driving signal;

[0034] The first DC blocking circuit is used for filtering the DC component in the driving signal.

[0035] In an optional implementation, the reference synchronization signal is a differential signal, and the second signal circuit includes: a third level conversion circuit, a second comparison circuit, and a second two-frequency division circuit;

[0036] The third level conversion circuit is used to raise the voltage difference of the reference synchronization signal to a preset value and generate a third differential signal;

[0037] The second voltage comparison circuit is used for converting the third differential signal into a second square wave signal, wherein the frequency of the second square wave signal is the same as the frequency of the third differential signal;

[0038] The second two-frequency dividing circuit is used to perform frequency division processing on the second square wave signal, and output the synchronization signal with a duty cycle of 50% and a frequency of a set frequency.

[0039] In an optional implementation, the second signal circuit further includes: a second filtering circuit, and / or a second driving circuit, wherein:

[0040] The second filtering circuit is used to filter out the noise signal of the target frequency band in the reference synchronization signal;

[0041] The second driving circuit is used to enhance the driving capability of the synchronization signal.

[0042] In a second aspect, the present application provides a radio frequency power supply, comprising: a plurality of radio frequency circuits and a plurality of cascaded phase synchronization circuits as described in any one of the first aspects of the present application, wherein:

[0043] Each stage of the phase synchronization circuit is connected to a corresponding radio frequency circuit, and is used to provide the driving signal to the radio frequency circuit;

[0044] The phase synchronization circuit at the current stage is used to provide the synchronization signal to the phase synchronization circuit at the subsequent stage.

[0045] In a third aspect, the present application provides a semiconductor process equipment, comprising: a process chamber and a radio frequency power supply as described in the second aspect of the present application.

[0046] According to the above content, the phase synchronization circuit provided by the present application, the phase-locked loop module provides a target clock signal according to the synchronization signal or reference clock signal of the previous stage, and the signal module provides a drive signal and a synchronization signal with the same phase according to the target clock signal. With such a setting, the phase synchronization circuit can be synchronized with the previous stage device according to the synchronization signal of the previous stage, or, as a host, provide a synchronization signal to the next stage. Further, the signal output module is provided with two output ports, the first output port is used to output the drive signal, the RF circuit outputs the RF signal according to the drive signal, the phase adjustment module provides the target phase offset of the drive signal according to the RF power of the RF signal, and the signal output module adjusts the phase of the drive signal according to the target phase offset so that the phase of the RF signal reaches the target phase, offsets the phase offset caused by different RF powers, and ensures that the RF signal output by the RF circuit is in phase with the synchronization signal. At the same time, the second output port outputs a synchronization signal to the phase synchronization circuit of the next stage to achieve synchronization with the phase synchronization circuit of the next stage, and the drive signal and the synchronization signal do not affect each other, thereby solving the problem of different phases of the RF signals of the main power supply and the slave power supply due to changes in RF power in the prior art, and meeting the actual application needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 It is a schematic diagram of the connection relationship between the main power supply and the slave power supply for synchronous operation in the prior art.

[0049] Figure 2 It is a structural schematic diagram of a phase synchronization circuit provided by an embodiment of the present invention.

[0050] Figure 3 It is a circuit topology diagram of an input circuit provided by an embodiment of the present invention.

[0051] Figure 4 This is a schematic diagram of an application scenario in which the phase synchronization circuit provided in this application is used to achieve synchronization of different RF power supplies.

[0052] Figure 5 It is a structural schematic diagram of another phase synchronization circuit provided by an embodiment of the present invention.

[0053] Figure 6 It is a diagram of the relationship between radio frequency power and phase offset provided by an embodiment of the present invention.

[0054] Figure 7 It is a circuit topology diagram of an output circuit provided by an embodiment of the present invention.

[0055] Figure 8 It is a circuit topology diagram of a signal output module provided by an embodiment of the present invention.

[0056] Fig. 9 It is a structural block diagram of a semiconductor process equipment provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. According to the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0058] As mentioned above, the RF power supply is a core component of semiconductor process equipment, and the RF signal it outputs is used to ignite and maintain plasma discharge in the process chamber. Taking the ICP (Inductively Coupled Plasma) etcher as an example, two RF power supplies are usually installed inside it, one of which is used as a source RF power supply to load RF power to the upper electrode of the process chamber to provide energy to start the plasma, and the other is used as a bias RF power supply to load RF power to the lower electrode of the process chamber to control the direction of plasma movement. According to the general process requirements in practical applications, the two RF power supplies need to work at the same frequency and phase. Therefore, a phase synchronization circuit is required to synchronize the phase deviation between different RF power supplies to achieve the coordinated operation of multiple RF power supplies.

[0059] Combination Figure 1 As shown, the DDS (Direct Digital Synthesizer) module of the main power supply is connected to the DDS module of the slave power supply. The DDS module of the main power supply provides a driving signal to the RF circuit of the main power supply and the DDS module of the slave power supply through the same signal output port. The RF circuit of the main power supply outputs a RF signal according to the driving signal. At the same time, the DDS module of the slave power supply drives the RF circuit of the slave power supply according to the driving signal, thereby achieving the same phase operation as the main power supply. In other words, the driving signal in the prior art is used as a driving signal to drive the RF circuit to operate, and is also used to achieve synchronization between the RF power supplies.

[0060] For the RF power supply, the RF circuit outputs RF power according to the driving signal provided by the DDS module. Due to the influence of the performance of the components of the RF circuit itself, environmental interference and other factors, the phase of the RF signal output by the RF circuit will change with the change of RF power. Therefore, when adjusting the RF power output by the RF power supply, it is necessary to adjust the phase of the driving signal output by the DDS module in real time to ensure that the phase of the RF signal remains unchanged. However, combined with Figure 1 As shown, the DDS module is connected to its corresponding RF circuit and the subsequent DDS module through the same signal output port. The driving signal provided is also used as a synchronization signal. Adjusting the driving signal of the main power supply DDS module means synchronously adjusting the phase of the driving signal used by the DDS module in the slave power supply, thereby changing the phase of the RF signal provided by the slave power supply, which ultimately leads to different phases of the RF signals output by the main power supply and the slave power supply, making it difficult to meet the process requirements.

[0061] In order to solve the above technical problems, the present application provides a phase synchronization circuit, including a phase-locked loop module, a phase adjustment module and a signal output module. The phase-locked loop module provides a target clock signal according to the synchronization signal or reference clock signal of the previous stage, and the signal output module provides a drive signal and a synchronization signal according to the target clock signal. The phase synchronization circuit can be synchronized with the previous stage device according to the synchronization signal of the previous stage, or provide a synchronization signal to the next stage as a main power supply. At the same time, the signal output module outputs a drive signal to the radio frequency circuit, and the radio frequency circuit outputs a radio frequency signal according to the drive signal. The phase adjustment module determines the target phase offset of the drive signal according to the real-time radio frequency power of the radio frequency signal. The signal output module adjusts the phase of the drive signal according to the target phase offset to offset the phase offset of the radio frequency signal caused by different radio frequency powers, and ensure that the radio frequency signal output by the radio frequency circuit is in phase with the synchronization signal. At the same time, the signal output module outputs a synchronization signal to the phase synchronization circuit of the next stage to achieve synchronization with the phase synchronization circuit of the next stage. The drive signal and the synchronization signal do not affect each other, meeting the actual application requirements.

[0062] Based on the above, see Figure 2 The phase synchronization circuit provided in the present application includes: a phase-locked loop module 10, a phase adjustment module 20 and a signal output module 30.

[0063] The phase-locked loop module 10 is used to generate a target clock signal according to the synchronization signal or reference clock signal of the previous stage. That is, the phase-locked loop module 10 can identify the current working mode of the phase synchronization circuit. If the phase synchronization circuit is in the main power supply mode, that is, the RF power supply to which the phase synchronization circuit belongs is used as the main power supply, the phase-locked loop module 10 generates the target clock signal according to the reference clock signal. Correspondingly, if the phase synchronization circuit is in the slave power supply mode, that is, the RF power supply to which the phase synchronization circuit belongs is used as the slave power supply, the phase-locked loop module 10 generates the target clock signal according to the synchronization signal of the previous stage.

[0064] As an optional implementation, the phase synchronization circuit provided in this embodiment further includes a crystal oscillator 40. Figure 2 As shown, the phase-locked loop module 10 includes a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is used to receive the synchronization signal of the previous stage, the second input terminal is connected to the crystal oscillator 40, and receives the reference clock signal provided by the crystal oscillator 40, and the output terminal of the phase-locked loop module 10 is connected to the signal output module 30, and the phase-locked loop module 10 is mainly used to provide a stable clock source for the signal output module 30.

[0065] According to the above connection relationship, after startup, the phase-locked loop module 10 will monitor whether the first input end receives the synchronization signal of the previous stage. If the first input end does not receive the synchronization signal of the previous stage within the preset time length, the phase-locked loop module 10 determines that the phase synchronization circuit is in the main power mode, and then generates the target clock signal according to the reference clock signal provided by the crystal oscillator 40; on the contrary, if the first input end receives the synchronization signal of the previous stage within the preset time length, the phase-locked loop module 10 determines that the phase synchronization circuit is in the slave power mode, and then generates the target clock signal according to the synchronization signal of the previous stage.

[0066] For example, when the phase synchronization circuit is in the main power mode, the crystal oscillator 40 provides a 50MHz reference clock signal, and the phase-locked loop module 10 provides a target clock signal to the signal output module 30 according to the preset configuration information based on the 50MHZ reference clock signal. For example, the 50MHz reference clock signal is converted into a 20MHz target clock signal. Of course, in actual applications, the reference clock signal can also be converted into a target clock signal of other frequencies according to the actual application requirements and the configuration of the signal output module 30. They are not listed one by one here, and they also fall within the protection scope of the present application without exceeding the core idea of ​​the present application.

[0067] Further, when the phase synchronization circuit is in the slave power mode, the phase-locked loop module 10 generates a target clock signal according to the synchronization signal of the previous stage. Taking the signal frequency of the previous stage synchronization signal between 12.882MHz-14.238MHz, for example, a synchronization signal of 13.56MHz as an example, after the phase-locked loop module 10 receives the synchronization signal through the first input terminal, the phase-locked loop module 10 converts the synchronization signal into a target clock signal according to the preset configuration information. For example, the phase-locked loop module 10 performs a double frequency conversion on the synchronization signal, and outputs the converted signal as the target clock signal to the signal output module 30. Of course, the phase-locked loop module 10 can also perform other processing on the synchronization signal to obtain the target clock signal, which is not described in detail here. Without exceeding the core idea of ​​the present application, it also belongs to the scope of protection of the present application.

[0068] It is understandable that during the transmission process, the synchronization signal from the previous stage will inevitably be affected by factors such as the impedance of the transmission line and the electromagnetic interference of the transmission environment, resulting in deformation of the waveform of the synchronization signal and other changes, affecting the accurate recognition and processing of the synchronization signal by the phase-locked loop module 10.

[0069] According to this, as another optional implementation, the phase synchronization circuit provided in this embodiment further includes an input circuit 50. Figure 2 As shown, the input end of the input circuit 50 is used to receive the synchronization signal of the previous stage, and the output end of the input circuit 50 is connected to the first input end of the phase-locked loop module 10 to provide the aforementioned synchronization signal to the phase-locked loop module 10. Through the input circuit 50, the synchronization signal of the previous stage is converted into a synchronization signal that meets the preset requirements of the phase-locked loop module 10.

[0070] Specifically, the input circuit 50 provided in this embodiment can be based on Figure 3 The input circuit 50 provided in this embodiment includes a third filtering circuit 501 , a second DC blocking circuit 502 , a fourth level conversion circuit 503 , a voltage clamping circuit 504 and a third comparison circuit 505 .

[0071] Combination Figure 3 As shown, the third filtering circuit 501 includes a capacitor C15 and a resistor R18, one end of the capacitor C15 serves as the input end of the input circuit 50, receiving the synchronization signal of the previous stage, for example, a square wave signal or a sine wave signal with a frequency of 12.882MHz-14.238MHz, the other end of the capacitor C15 is connected to one end of the resistor R18, the other end of the resistor R18 is grounded, and the connection point between the capacitor C15 and the resistor R18 is connected to the second DC isolation circuit 502 of the subsequent stage. The high-pass filter network composed of the capacitor C15 and the resistor R18 is used to filter out the low-frequency interference signal in the synchronization signal.

[0072] The second DC blocking circuit 502 includes a capacitor C16, one end of which is connected to the third filter circuit 501, and the other end of which is connected to the fourth level conversion circuit 503. The second DC blocking circuit 502 is mainly used to isolate the DC component.

[0073] The fourth level conversion circuit 503 includes a resistor R17 and a resistor R19, combined with Figure 3 As shown, one end of the resistor R17 is connected to a 3.3V power supply, and the other end is connected to a resistor R19, and the other end of the resistor R19 is grounded. The fourth level conversion circuit 503 converts the amplitude of the signal processed by the second DC isolation circuit 502 into 3.3V, and the common end of the resistors R17 and R19 is connected to pin 2 of the TVS tube D1 and pin 1 of D2, and pin 1 of D1 is connected to 3.3V. Of course, in actual applications, it can also be converted to other amplitudes according to actual control requirements, which will not be described in detail here.

[0074] The voltage clamping circuit 504 includes a voltage-stabilizing diode D1 and a voltage-stabilizing diode D2. The cathode of the voltage-stabilizing diode D1 is connected to a 3.3V power supply, and the anode is connected to the cathode of the voltage-stabilizing diode D2. The anode of the voltage-stabilizing diode D2 is grounded. The voltage clamping circuit 504 is mainly used to prevent the input circuit from being damaged by overvoltage. In practical applications, the voltage clamping circuit can also be constructed in other forms, which are not listed here one by one.

[0075] The third comparison circuit 505 includes a resistor R20, a resistor R21 and a comparator U20, Figure 3 As shown, the connection point of the Zener diode D1 and the Zener diode D2 is connected to the positive input terminal of the comparator U20, and the resistors R20 and R21 are connected in series to form a voltage divider circuit, and the voltage value output after the voltage division is input to the reverse input terminal of the comparator U20, that is, to provide a comparison reference voltage, the 5th pin of the comparator U20 is a power pin connected to the 3.3V power supply, the 2nd pin of U20 is grounded, and the 1st pin of U20 is an output pin, which is used as the output terminal of the input circuit 50 and is connected to the phase-locked loop module 10. The main function of the third comparison circuit 505 is to convert the input signal into a square wave signal that meets the preset requirements of the phase-locked loop module 10.

[0076] On the basis of the optional structure of the above-mentioned phase-locked loop module, the signal output module 30 is provided with a first output port A1 and a second output port A2. It should be noted that the first output port A1 and the second output port A2 are independent output ports, and the operating states of the two do not affect each other, and the signal output module 30 can independently control the phase of the output signal of the first output port A1 and the second output port A2. In one embodiment, during the initial operation, the signal output module 30 provides a drive signal and a synchronization signal of the same frequency and phase according to the target clock signal provided by the phase-locked loop module 10, wherein the first output port A1 is used to output a drive signal to the RF circuit in the RF power supply to which it belongs, so that the RF circuit outputs the RF signal according to the drive signal, and the second output port A2 is used to output a synchronization signal of the same frequency and phase to the phase synchronization circuit of the subsequent stage, so that the phase synchronization circuit of the subsequent stage is synchronized with this circuit. As the power of the RF signal changes, the drive signal output by the signal output module 30 will no longer be synchronized with the synchronization signal after adjustment in the subsequent steps, but the frequency is still the same. The specific implementation of the signal output module 30 will be detailed in the subsequent embodiments, and will not be described in detail here.

[0077] As described, in the process of the RF circuit outputting the RF signal according to the driving signal, due to the influence of factors such as the performance of the components of the RF circuit itself and environmental interference, the phase of the RF signal output by the RF circuit will change at different powers, and a phase offset will occur compared to the target phase. Based on this, the phase adjustment module 20 provides the signal output module 30 with the target phase offset of the driving signal according to the real-time RF power of the RF circuit, and the signal output module 30 adjusts the phase of the driving signal according to the target phase offset, so that the phase of the RF signal output by the RF circuit remains unchanged, thereby ultimately making the RF signal and the synchronization signal in phase.

[0078] Since the synchronization signal output by the second output port A2 of the signal output module 30 will be sent to the phase synchronization circuit of the subsequent stage, the phase synchronization circuit of the subsequent stage can repeat the RF signal phase adjustment process according to the aforementioned content to ensure that the phase of the RF signal is in phase with its own synchronization signal, thereby making the phases of the RF signals output by the RF circuits of the previous and subsequent stages the same.

[0079] It should be noted that the RF power of the RF signal can be obtained by real-time monitoring of the voltage value and current value of the RF signal, wherein the RF power may include forward power, reflected power, and dissipated power, etc. The present application does not specifically limit the specific implementation method of the phase adjustment module 20 to obtain the RF power. As for the specific implementation of the phase adjustment module 20 determining the phase offset of the driving signal according to the RF power, it will be detailed in the subsequent content and will not be described in detail here.

[0080] In summary, in the phase synchronization circuit provided by the present application, the phase-locked loop module provides a target clock signal according to the synchronization signal or reference clock signal of the previous stage, and the signal module provides a driving signal and a synchronization signal with the same phase according to the target clock signal. With such a configuration, the phase synchronization circuit can be synchronized with the previous stage device according to the synchronization signal of the previous stage, or, as a host, provide a synchronization signal to the next stage. Furthermore, the signal output module is provided with two output ports, the first output port is used to output the driving signal, the RF circuit outputs the RF signal according to the driving signal, the phase adjustment module provides the target phase offset of the driving signal according to the RF power of the RF circuit, and the signal output module adjusts the phase of the driving signal according to the target phase offset to offset the phase offset caused by the different RF powers, and ensure that the RF signal output by the RF circuit is in phase with the synchronization signal. At the same time, the second output port outputs a synchronization signal to the phase synchronization circuit of the next stage to achieve synchronization with the phase synchronization circuit of the next stage, and the driving signal and the synchronization signal do not affect each other, thereby solving the problem of different phases of the RF signals of the main power supply and the slave power supply due to changes in RF power in the prior art, and meeting the actual application needs.

[0081] The following uses two RF power supplies as an example to illustrate the process of achieving the same frequency and phase of the RF signals of the RF power supplies according to the phase synchronization circuit provided by the present application. Figure 4 As shown, the main power supply and the slave power supply are respectively provided with the phase synchronization circuit provided by the present application.

[0082] After the main power supply is powered on, the phase-locked loop module 10 in the main power supply detects the signal received at the first input end. Since it is the main power supply, the phase-locked loop module 10 in the main power supply will not receive the synchronization signal of the previous stage within a preset time period, that is, it determines itself as the main power supply, and then generates a target clock signal according to the reference clock signal provided by the crystal oscillator 40, and provides the target clock signal to the signal output module 30.

[0083] The signal output module 30 in the main power supply provides a driving signal and a synchronization signal with the same frequency and phase according to the target clock signal.

[0084] At the same time, the phase adjustment module 20 in the main power supply provides a target phase offset of the driving signal according to the radio frequency power of the radio frequency circuit in the main power supply.

[0085] The signal output module 30 in the main power source adjusts the phase of the driving signal according to the target phase offset, so that the radio frequency signal output by the main power source is in phase with the synchronization signal.

[0086] After the slave power supply is powered on, the phase-locked loop module 10 in the slave power supply detects the signal received at the first input terminal, and receives the synchronization signal provided by the main power supply within a preset time period, that is, it determines itself as a slave power supply, and then generates a target clock signal according to the synchronization signal provided by the main power supply, and provides the target clock signal to the signal output module 30.

[0087] The signal output module 30 in the slave power supply provides a driving signal and a synchronization signal with the same phase according to the target clock signal.

[0088] At the same time, the phase adjustment module 20 in the slave power supply provides a target phase offset of the driving signal according to the RF power of the RF circuit in the slave power supply.

[0089] The signal output module 30 in the slave power source adjusts the phase of the driving signal according to the target phase offset so that the RF signal output by the slave power source is in phase with the synchronization signal. Since the synchronization signal of the slave power source is in phase with the synchronization signal output by the main power source, it can be ensured that the RF signal output by the main power source is in phase with the RF signal output by the slave power source.

[0090] It should be noted that the phase-locked loop module 10 is configured to query whether the first input end of itself receives the synchronization signal according to a preset polling cycle. Once the synchronization signal is received within a preset duration of a polling cycle, the phase-locked loop module 10 immediately switches to the slave power supply mode. Based on this, even if the main power supply and the slave power supply are powered on at the same time, the slave power supply is confirmed to be the main power supply in a short time, and it will switch to the slave power supply within a polling cycle after the main power supply outputs the synchronization signal, thereby ensuring the orderly operation of the entire system.

[0091] Furthermore, according to the above content, it can be seen that the phase synchronization module provided in the present application, when applied to the RF power supply, can independently determine whether the RF power supply to which it belongs works as the main power supply or as a slave power supply, and can realize automatic switching between the main power supply mode and the slave power supply mode. Such a setting can enable the same phase synchronization circuit to be set in different RF power supplies in the semiconductor process equipment. The RF power supply does not need to distinguish the function separately (that is, distinguish whether it is the main power supply or the slave power supply), which can reduce the model of the RF power supply and facilitate the mass production of the RF power supply. Customers no longer need to distinguish between the main power supply or the slave power supply. They only need to connect each RF power supply according to the system topology. The RF power supply can automatically confirm its corresponding operating mode.

[0092] Furthermore, the present application provides another phase synchronization circuit, see Figure 5 As shown, based on the above-mentioned embodiment, the phase synchronization circuit provided in this embodiment further includes a monitoring module 60 and an output circuit 70. At the same time, this embodiment also provides an optional implementation method of the phase adjustment module.

[0093] Combination Figure 5 As shown, the phase adjustment module 20 provided in this embodiment includes a phase correction module 210 and a configuration module 220

[0094] The phase correction module 210 determines a target phase offset corresponding to the current RF power according to a preset mapping relationship between the RF power and the target phase offset, and provides the target phase offset to the configuration module 220 .

[0095] In a possible implementation, the aforementioned preset mapping relationship can be determined as follows. For any RF power source, the phase of the driving signal output by the signal output module is kept unchanged, and any RF power is used as a reference value. According to the preset power step, the RF power of the RF circuit is increased from low to high. At the same time, the phase offset between the RF signal and the driving signal at each RF power is obtained. After accumulating a certain amount of measured data, a quadratic curve of the phase offset varying with power is fitted according to the obtained measured data, such as Figure 6 As shown, the corresponding quadratic curve formula can be further obtained based on the obtained fitting curve as follows.

[0096] Y=―0.00001X 2 +0.0449X-3.6781

[0097] Wherein, Y represents the phase offset between the RF signal and the driving signal, and X represents the RF power.

[0098] The above formula represents the preset mapping relationship between the RF power and the phase offset. Of course, the above preset mapping relationship can also be represented in other forms, for example, Figure 6 The curve shown, for example, includes an array of multiple value pairs, wherein each value pair includes an RF power and a phase offset corresponding to the RF power. Without exceeding the core idea of ​​the present application, any form that can characterize the preset mapping relationship between the RF power and the phase offset is optional and also falls within the scope of protection of the present application.

[0099] Table 1 records the deviation between the phase offset determined according to the above preset mapping relationship and the phase offset actually measured for a certain RF power source.

[0100] Table 1

[0101]

[0102]

[0103] It should be noted that the first row in Table 1 records the RF power of the RF power supply, the second row is the measured phase offset between the actual phase of the RF signal and the target phase at different RF powers, the third row records the target phase offset corresponding to the RF signal at different RF powers determined according to the aforementioned preset mapping relationship, and the fourth row records the deviation between the measured phase offset and the calculated phase offset at the same RF power.

[0104] For example, when the RF power is set to 600W, the measured phase offset before phase adjustment is 19.5°, and the phase offset determined according to the preset mapping relationship is 19.7°, with a difference of 0.2°. Furthermore, as shown in Table 1, the maximum phase deviation between the calculated phase offset and the measured phase offset is only 1.9°, which meets the requirements for phase accuracy in the actual process.

[0105] In an optional implementation, the phase correction module 210 is implemented according to an FPGA (Field Programmable Gate Array). Of course, it can also be implemented according to other types of controllers, such as DSP (Digital Signal Processing) control, or ARM (Advanced RISC Machine) processor, etc., which are not listed here one by one.

[0106] The configuration module 220 provides configuration information to the signal output module 30 so that the signal output module 30 sets the frequency and phase of the drive signal and the synchronization signal respectively according to the configuration information. In practical applications, the configuration information provided by the configuration module 20 can be a target drive signal and a target synchronization signal set according to control requirements. Of course, it can also be frequency information and phase information that meet actual control requirements in other application scenarios, which will not be described in detail here. Furthermore, the configuration module 220 is also used to adjust the configuration information according to the target phase offset provided by the aforementioned phase correction module 210, that is, to modify the configuration information so that the signal output module 30 adjusts the phase of the drive signal according to the adjusted configuration information.

[0107] Combination Figure 5As shown, the configuration module 220 includes a phase setting module 2201 and a configuration submodule 2202. The output end of the phase correction module 210 is connected to the first input end of the configuration submodule 2202, and the output end of the configuration submodule 2202 is connected to the signal output module 30. The phase correction module 210 provides the target phase offset to the configuration submodule 2202, and the configuration submodule 2202 is used to provide the target phase offset corresponding to the current RF power to the signal output module 30, so that the signal output module 30 adjusts the phase of the driving signal according to the obtained target phase offset.

[0108] Furthermore, in actual applications, certain special process requirements require that there is a certain phase difference between the RF signal provided by the main power supply and the RF signal provided by the slave power supply. To meet this application requirement, the output end of the phase setting module 2201 is connected to the second input end of the configuration submodule 2202. The phase setting module 2201 obtains a preset phase offset, which is the phase offset between the RF signals output by the aforementioned main power supply and the slave power supply, and sends the preset phase offset to the configuration submodule 2202, and provides the preset phase offset to the signal output module 30 through the configuration module 220.

[0109] It should be noted that the phase setting module 2201 can obtain the aforementioned preset phase offset in a variety of ways. For example, the phase setting module 2201 communicates with the host computer, and the host computer configures the preset phase offset. For another example, the user directly configures the configuration parameters of the phase setting module 2201, and records the preset phase offset in the configuration parameters, etc., which are not listed one by one here. The present application does not specifically limit the specific implementation method of the phase setting module 2201 to obtain the preset phase offset, and the preset phase offset can be any angle in the range of 0°-360°, and the present application does not limit the specific value of the preset phase offset.

[0110] In practical applications, the phase setting module 2201 can be implemented based on FPGA. Of course, it can also be implemented based on other types of controllers, such as DSP control or ARM processor, etc., which are not listed here one by one.

[0111] The signal output module 30 adjusts the phase of the driving signal according to the target phase offset and the preset phase offset, so that the phase difference between the RF signal and the synchronization signal is the preset phase offset. It should be noted that in actual applications, the target phase offset is adjusted at any time according to the RF power to ensure that the RF signal and the synchronization signal are in phase. On this basis, the phase of the driving signal is further adjusted according to the preset phase offset, so that the phase difference between the RF signal and the synchronization signal is the preset phase offset.

[0112] In the above embodiments, the configuration submodule 2202 is mainly used to configure the signal output module 30 and transmit relevant data to the signal output module. Referring to the above content, the configuration submodule 2202 can also be implemented according to technologies such as FPGA, DSP controller and ARM processor, which will not be described in detail here.

[0113] Furthermore, the phase synchronization circuit provided in this embodiment further includes a monitoring module 60 and an output circuit 70. Figure 5 As shown, the monitoring module 60 is connected to the second output port A2 of the signal output module 30, the output end of the monitoring module 60 is connected to the input end of the output circuit 70, and the output end of the output circuit 70 is further connected to the subsequent phase synchronization circuit (specifically, the phase adjustment module in the phase synchronization circuit).

[0114] The monitoring module 60 is used to collect the driving signal provided by the signal output module 30, and further feed back the obtained driving signal to the upper computer. The upper computer can monitor the relevant parameters of the driving signal according to the obtained driving signal, such as phase, frequency and signal stability, etc. At the same time, the operating state of the phase synchronization circuit can also be determined according to the driving signal. In practical applications, the monitoring module 60 can be implemented according to the input / output port module in the FPGA, and of course, it can also be implemented according to other related technologies, which will not be described in detail here.

[0115] The output circuit 70 is mainly used to improve the driving performance of the synchronization signal. In an optional embodiment, the output circuit 70 can be used as follows Figure 7 The output circuit 70 provided in this embodiment includes a third driving circuit 710 and a third DC blocking circuit 720 .

[0116] Specifically, the third driving circuit 710 includes a NOT gate circuit, the input end of the NOT gate circuit serves as the input end of the output circuit, and the output end of the NOT gate circuit is connected to the third DC isolation circuit 720. The NOT gate circuit can improve the driving ability of the synchronization signal. Further, the third DC isolation circuit 720 includes a capacitor C17, one end of the capacitor C17 is connected to the output end of the NOT gate circuit, and the other end serves as the output end of the output circuit 70 to output the synchronization signal. The main function of the third DC isolation circuit 720 is to isolate the DC component of the synchronization signal and improve the quality of the synchronization signal.

[0117] To summarize, based on the foregoing embodiments, the phase synchronization circuit provided in this embodiment can also configure the phase offset between the RF signal and the synchronization signal through the phase setting module, monitor the signal state of the synchronization signal and improve the signal quality of the synchronization signal. While meeting more special production process requirements, it can also effectively ensure the stability and reliability of the synchronization signal, which helps to improve the reliability of the collaborative operation between the RF power supplies.

[0118] The optional structure of the signal output module involved in each of the above embodiments is introduced below. The signal output module provided in the present application includes a signal conversion module, a first signal circuit and a second signal circuit. The signal input end of the signal conversion module is connected to the phase-locked loop module to receive the target clock signal provided by the phase-locked loop module. Further, the signal conversion module includes two signal output ends, namely a first signal output end and a second signal output end, wherein the first signal output end is connected to the first signal circuit, and the second signal output end is connected to the second signal circuit. The signal conversion module is mainly used to provide a reference drive signal and a reference synchronization signal according to the target clock signal provided by the phase-locked loop module, and to adjust the phase of the reference drive signal according to the target phase offset to adjust the phase of the drive signal. The first signal circuit outputs the aforementioned drive signal according to the obtained reference drive signal, and the second signal circuit outputs the aforementioned synchronization signal according to the obtained reference synchronization signal.

[0119] In a possible implementation, the signal output module may refer to Figure 8 The illustrated embodiment is implemented.

[0120] In the signal output module provided in this embodiment, the signal conversion module 301 is implemented according to the DDS module U12. In combination with the above content, the phase-locked loop module provides a target clock signal for the signal conversion module. Following the previous example, when the phase-locked loop module determines that the phase synchronization circuit is in the main power mode, a 20MHz target clock signal is generated after frequency division processing based on the 50MHz clock signal provided by the crystal oscillator, and the target clock signal is output to the signal conversion module 301; when the phase-locked loop module determines that the phase synchronization circuit is in the slave power mode, the phase-locked loop module generates a target clock signal according to the synchronization signal of the previous stage. For example, the synchronization signal of the previous stage is a signal of 12.882MHz to 14.238MHz. The phase-locked loop module performs double frequency processing on the signal to obtain a target clock signal of 25.764MHz to 28.476MHz, which is finally provided to the signal conversion module 301.

[0121] Further, in Figure 8 In the illustrated embodiment, multiple pins related to the present solution in the DDS module are shown, such as pins numbered 39, 40, 41, 36, 9, 21, 20, 23, 43, 42, and 24. Of course, in practical applications, the DDS module may also include other pins, which can be specifically referred to in the relevant technology and are not listed here one by one. In this embodiment, the DDS module is mainly used to achieve sinusoidal wave output of different frequencies and phases, and the frequency range of its output signal is 25.764MHz to 28.476MHz, and the phase range of the output signal is 0° to 360°.

[0122] Specifically, the pins numbered 39, 40, 41, and 36 in the DDS module are communication interfaces, which are connected to the configuration module in the phase adjustment module. The configuration module completes the initialization of the DDS module and the configuration operations of the output signal, such as configuring the frequency and phase of the drive signal and the synchronization signal. Among them, pin 39 is the chip select pin, which is mainly used to set the enable state of the DDS module. It can be understood that in the enabled state, the DDS module runs normally, and in the disabled state, the DDS module stops running. Pins 40 and 41 together constitute the configuration channel of the DDS module. The configuration module in the phase adjustment module can control pins 40 and 41 respectively. Figure 8 The CH0 port and the CH1 port output the frequency and phase of the signal. Pin 36 is the restart pin, and the configuration module can restart the DDS module according to the control requirements through pin 36.

[0123] Pin 9 is the clock pin of the DDS module, which is connected to the output end of the phase-locked loop module and receives the target clock signal provided by the phase-locked loop module. In an optional implementation, the frequency range of the target clock signal received by pin 9 is 20MHz to 30MHz.

[0124] Pin 43 is the power pin of the DDS module, which is connected to the Vcc power supply to provide the necessary power supply for the normal operation of the DDS module. Pin 42 is the ground pin of the DDS module, which is directly grounded.

[0125] In order to meet the application requirements of transmitting driving signals and synchronization signals through different signal transmission channels, the DDS module includes two signal transmission ports, CH0 and CH1. Figure 8 As shown, pin 21 and pin 20 constitute the CH0 signal transmission port, wherein pin 21 outputs the positive end signal of the differential signal, and pin 20 outputs the negative end signal of the differential signal, and the difference between the positive end signal and the negative end signal, i.e., the frequency signal output by CH0, i.e., the reference drive signal output by the signal conversion module 301 is a differential signal. The principle of the CH1 signal transmission port is the same as that of the CH0 signal transmission port, and the reference synchronization signal output by it is also a differential signal, which will not be repeated here.

[0126] See also Figure 8 As shown, Figure 8 The illustrated embodiments respectively provide optional configurations of the first signal circuit and the second signal circuit.

[0127] Specifically, the first signal circuit includes a first level conversion circuit 306, a first comparison circuit 308, a first two-frequency division circuit 302 and a second level conversion circuit 313. Further, as a preferred implementation, Figure 8In the illustrated embodiment, the first signal circuit may further include a first filter circuit 304 and / or a first drive circuit 310 and a first DC blocking circuit 312 .

[0128] The first level conversion circuit 306 includes a resistor R12 and a resistor R13, one end of the resistor R12 is connected to a 5V power supply, and the other end is connected to one end of R13, and the other end of the resistor R13 is grounded. The resistor R12 and the resistor R13 form a series voltage divider circuit, and the connection end of the two serves as the output end of the voltage divider voltage. The function of the first level conversion circuit 306 is to raise the voltage difference of the reference drive signal to a preset value and generate a first differential signal. For example, when the resistor R13 and the resistor R13 have the same resistance value, the relative value of the reference drive signal can be increased by 2.5V, and the voltage finally output to the subsequent first comparison circuit 308 is within the voltage input range of the first comparison circuit 308.

[0129] The first comparison circuit 308 includes a comparator U13, one end of the inductor L3 in the first filter circuit 304 is connected to the positive input end of the comparator U13, one end of the inductor L5 is connected to the negative input end of the comparator U13, further, the 5th pin of the comparator U13 is connected to the 5V power supply, the 2nd pin is grounded, and the 1st pin is used as the output end of the first comparison circuit 308. The main function of the first comparison circuit 308 is to convert the aforementioned first differential signal into a first square wave signal, and the frequency of the first square wave signal is the same as the frequency of the first differential signal, for example, converting a sine differential signal with a frequency of 27MHz into a square wave signal with a frequency of 27MHz and an amplitude of 5V.

[0130] As mentioned above, in this embodiment, the first two-frequency dividing circuit 302 can be implemented by using a two-frequency dividing circuit in the related art. Figure 8 As shown in the figure, pin 1 of the two-frequency dividing circuit U15 is connected to the output end of the first comparison circuit 308, pins 2 and 3 of the two-frequency dividing circuit U15 are connected and output to the first driving circuit 310, pin 4 of the two-frequency dividing circuit U15 is grounded, pin 8 is connected to a 5V power supply, and pins 6 and 7 have no external connection. The function of the first two-frequency dividing circuit 302 is to divide the first square wave signal to form a second differential signal with a duty cycle of 50% and a set frequency, for example, to divide a square wave signal with a frequency of 27MHz into a frequency signal of 13MHz.

[0131] The second level conversion circuit 313 is used to convert the second differential signal provided by the first two-frequency division circuit 302 into a single-ended signal to form a driving signal. Figure 8As shown, the second level conversion circuit includes a transmission line transformer, and the same-name input terminals of the transmission line transformer, namely port 1 and port 4, are respectively connected to the output terminal of the first DC isolation circuit 312 of the previous stage, port 3 of the transmission line transformer is grounded, and port 4 of the transmission line transformer is connected as the output terminal of the first signal circuit for connecting the radio frequency circuit. In this embodiment, the turns ratio of the transmission line transformer is 1:1, so as to realize the conversion of the differential signal into a single-ended signal output.

[0132] Further, the first filter circuit 304 includes: inductor L4, capacitor C5, capacitor C6, capacitor C8, capacitor C10, inductor L3 and inductor L5, and the first filter circuit 304 is mainly used to filter out the noise signal of the target frequency band in the reference drive signal. Using the previous example, when the DDS module provides a reference drive signal of 25.764MHz to 28.476MHz and the first two-frequency division circuit 302 adopts a two-frequency division ratio, the main function of the first filter circuit 304 is to filter out interference signals near 13MHz and some low-frequency noises, the inductor L4 and the capacitors C5 and C6 are connected in parallel in sequence, and the two ends of the capacitor C6 are respectively connected in series with the capacitor C8, the inductor L3 and the capacitor C10, and the inductor L5, and one end of the inductor L3 and the inductor L5 is used as the output end of the first filter circuit 304, which is used to connect the first level conversion circuit 306 of the subsequent stage.

[0133] The first driving circuit 310 includes two NOT gate circuits, wherein the input end of one NOT gate circuit is connected to the 5th pin of the previous-stage two-frequency dividing circuit, and the input end of the other NOT gate circuit is connected to the 3rd pin of the two-frequency dividing circuit. The driving capability of the driving signal can be increased by the NOT gate circuit.

[0134] The first DC blocking circuit 312 includes a capacitor C7 and a capacitor C9. Figure 8 As shown, one end of the capacitor C7 is connected to the output end of a NOT gate circuit of the first driving circuit 310, and the other end is connected to the second level conversion circuit 313 of the subsequent stage as an output end of the first DC isolation circuit 312. Correspondingly, one end of the capacitor C9 is connected to the output end of another NOT gate circuit of the first driving circuit 310, and the other end is connected to the second level conversion circuit 313 of the mobile phone as another output end of the first DC isolation circuit 312. The function of the first DC isolation circuit 312 is mainly to isolate the DC component in the driving signal to ensure that the 13MHz AC signal can pass normally.

[0135] Similar to the structure of the first signal circuit, the second signal circuit includes: a third level conversion circuit 307, a second comparison circuit 309 and a second two-frequency division circuit 303. As an optional implementation, Figure 8 The second signal circuit provided in the illustrated embodiment further includes a second filtering circuit 305 and / or a second driving circuit 311 .

[0136] Specifically, the third level conversion circuit 307 is used to raise the voltage difference of the reference synchronization signal to a preset value and generate a third differential signal. Figure 8 As shown, the third level conversion circuit 307 includes resistors R14 and R15. Specifically, one end of the resistor R14 is connected to a 5V power supply, and the other end is connected to one end of the resistor R15. The other end of the resistor R15 is grounded. The resistors R14 and R15 connected in series form a voltage divider circuit, and the connection end of the two serves as the output end of the voltage divider. The function of the third level conversion circuit 307 is to increase the differential signal output from the CH1 port, that is, the relative value of the reference synchronization signal. For example, when the resistors R14 and R15 have the same resistance value, the relative value of the reference synchronization signal can be increased by 2.5V, and the voltage finally output to the second comparison circuit 309 of the subsequent stage is within the voltage input range of the second comparison circuit 309.

[0137] The second comparison circuit 309 is used to convert the third differential signal output by the third level conversion circuit 307 into a second square wave signal. Specifically, the second comparison circuit 309 includes a comparator U19, one end of the inductor L6 in the second filter circuit 305 is connected to the positive input end of the comparator U19, and one end of the inductor L7 is connected to the negative input end of the comparator U19. Further, pin 5 of the comparator U19 is connected to a 5V power supply, pin 2 is grounded, and pin 1 is used as the output end of the second comparison circuit 309. The second comparison circuit 309 can convert a sinusoidal differential signal with a frequency of 27MHz into a square wave signal with a frequency of 27MHz and an amplitude of 5V.

[0138] The second two-frequency dividing circuit 303 is used to divide the second square wave signal and output a synchronization signal with a duty cycle of 50% and a set frequency. In this embodiment, the second two-frequency dividing circuit 303 can also be implemented by a two-frequency dividing circuit in the related art. Figure 8 As shown, pin 1 of the two-frequency dividing circuit U17 is connected to the output end of the second comparison circuit 309 of the previous stage, pins 2 and 3 of the two-frequency dividing circuit U17 are connected, pin 5 is used as the output end of the second two-frequency dividing circuit 303, and is connected to the second driving circuit 311 of the subsequent stage, pin 4 of the two-frequency dividing circuit U17 is grounded, pin 8 is connected to the 5V power supply, and pins 6 and 7 have no external connection. Similar to the function of the first two-frequency dividing circuit 302, for example, a square wave signal with a frequency of 27.12MHz is divided into a frequency signal of 13.56MHz, that is, a synchronization signal.

[0139] Furthermore, the second filter circuit 305 includes: an inductor L8, a capacitor C12, a capacitor C13, a capacitor C11, a capacitor C14, an inductor L6 and an inductor L7. The connection relationship and related functions between the components in the first filter circuit 304 can be referred to. Figure 8The related contents of the first filter circuit 304 are not described in detail here. Using the previous example, the second filter circuit 305 mainly filters out the noise signal of the target frequency band in the reference synchronization signal, for example, filtering out the interference signal around 13MHz and some low-frequency noise.

[0140] The second driving circuit 311 includes a NOT gate circuit, the input end of the NOT gate circuit is connected to the 5th pin of the previous stage binary frequency division circuit, and the output end of the NOT gate circuit serves as the output end of the second signal circuit, which is used to provide a synchronization signal to the subsequent stage phase synchronization circuit. The NOT gate circuit can increase the driving capability of the synchronization signal.

[0141] To summarize, after the first signal circuit receives the reference drive signal, the interference signal is filtered out by the first filter circuit, and at the same time, a certain DC isolation effect is played. The first level conversion circuit is used to raise the zero-point level of the sinusoidal differential signal by a preset amplitude, and then the sinusoidal differential signal is converted into a square wave signal of the same frequency by the first comparison circuit, and then two square wave signals with a phase difference of 180° and a frequency of half the frequency of the previous square wave signal are generated by the first two-division circuit. The two low-frequency square wave signals are increased in driving capability by the first drive circuit composed of a NOT gate, and the DC component is isolated by the first DC isolation circuit, and finally the drive signal is output by the second level conversion circuit. Correspondingly, after the second signal circuit receives the reference synchronization signal, the interference signal is filtered out by the second filtering circuit, and at the same time, a certain DC isolation effect is played. The third level conversion circuit is used to raise the zero point level of the sinusoidal differential signal by a preset amplitude, and then the sinusoidal differential signal is converted into a square wave signal of the same frequency by the second comparison circuit, and then two square wave signals with a phase difference of 180° and a frequency of half the frequency of the previous square wave signal are generated by the second two-division circuit. The low-frequency square wave signal increases its driving capability through the second driving circuit composed of a NOT gate, thereby providing a synchronization signal to the subsequent phase synchronization circuit.

[0142] It should be noted that in Figure 8 In the illustrated embodiment, the first filter circuit and the second filter circuit both use a passive filter network composed of an inductor and a capacitor. In practical applications, an active filter network or other methods may be used to complete the filtering process. Furthermore, the first two-frequency divider circuit and the second two-frequency divider circuit are implemented according to a D-type flip-flop. In practical applications, other forms of frequency divider circuits may also be used. The above optional implementations also fall within the scope of protection of the present invention without exceeding the core concept of the present invention.

[0143] Furthermore, the present application also provides a radio frequency power supply, comprising: a plurality of radio frequency circuits and a plurality of cascaded phase synchronization circuits provided in any of the above embodiments, wherein:

[0144] Each stage of the phase synchronization circuit is correspondingly connected to a radio frequency circuit for providing a driving signal to the radio frequency circuit;

[0145] The current-stage phase synchronization circuit is used to provide a synchronization signal to the subsequent-stage phase synchronization circuit.

[0146] Furthermore, the present application also provides a semiconductor process equipment, which includes a process chamber and a radio frequency power supply as provided in the aforementioned embodiment, and the radio frequency power supply is used to provide radio frequency power to the process chamber to excite the process gas in the process chamber to generate plasma.

[0147] See also Fig. 9 As shown, in an optional embodiment, the semiconductor process equipment provided by the present application includes an upper RF power supply 10, an upper matcher 20, a process chamber 30, a lower matcher 40, and a lower RF power supply 50. Specifically, the upper RF power supply 10 provides RF power to the process chamber 30 through the upper matcher 20, and the lower RF power supply 50 provides RF power to the process chamber 30 through the lower matcher 40, and together excites the process gas in the process chamber 30 to generate plasma and controls the movement of the plasma in the process chamber 30.

[0148] The semiconductor process equipment of the embodiment of the present application may be an inductively coupled plasma (ICP) device or a capacitively coupled plasma (CCP) device. The embodiment of the present application does not limit the type of semiconductor process equipment.

[0149] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0150] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0151] Flowcharts are used in this disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or following steps are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes.

[0152] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, etc. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any particular form of combination of hardware and software.

[0153] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0154] The above is an explanation of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure are described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A phase synchronization circuit, characterized in that: include: A phase-locked loop module, a phase adjustment module and a signal output module, wherein the signal output module includes a first output port and a second output port, wherein: The phase-locked loop module is used to generate a target clock signal according to the synchronization signal of the previous stage or its own reference clock signal; The signal output module is used to provide a driving signal and a synchronization signal according to the target clock signal; The first output port is used to output the driving signal to the radio frequency circuit, so that the radio frequency circuit outputs a radio frequency signal according to the driving signal; The second output port is used to output the synchronization signal to a subsequent phase synchronization circuit; The phase adjustment module is used to determine a target phase offset according to the radio frequency power of the radio frequency signal; The signal output module is further used to adjust the phase of the driving signal according to the target phase offset so that the phase of the radio frequency signal output by the radio frequency circuit reaches the target phase.

2. The phase synchronization circuit according to claim 1, characterized in that: The phase adjustment module includes: a phase correction module and a configuration module, wherein: The phase correction module is used to provide the target phase offset corresponding to the RF power to the configuration module according to a preset mapping relationship between the RF power and the target phase offset; The configuration module is used to provide configuration information to the signal output module so that the signal output module sets the frequency and phase of the drive signal and the synchronization signal respectively according to the configuration information; the configuration module is also used to adjust the configuration information according to the target phase offset so that the signal output module adjusts the phase of the drive signal.

3. The phase synchronization circuit according to claim 1, characterized in that: The phase-locked loop module is also used to identify the current working mode of the phase synchronization circuit; If the phase synchronization circuit is in the main power mode, the phase-locked loop module is used to generate the target clock signal according to the reference clock signal; If the phase synchronization circuit is in a slave power mode, the phase-locked loop module is used to generate the target clock signal according to the synchronization signal of the previous stage.

4. The phase synchronization circuit according to claim 3, characterized in that: The phase-locked loop module comprises a first input terminal and a second input terminal, the first input terminal is used to receive the synchronization signal of the previous stage, and the second input terminal is used to receive the reference clock signal; The phase-locked loop module is used to: if the first input end does not receive the synchronization signal of the previous stage within a preset time length, determine that the phase synchronization circuit is in the main power supply mode; if the first input end receives the synchronization signal of the previous stage within the preset time length, determine that the phase synchronization circuit is in the slave power supply mode.

5. The phase synchronization circuit according to claim 1, characterized in that: The signal output module includes: a signal conversion module, a first signal circuit and a second signal circuit, wherein: The signal conversion module is connected to the first signal circuit and the second signal circuit respectively; The signal conversion module is used to provide a reference drive signal and a reference synchronization signal according to the target clock signal, and to adjust the phase of the reference drive signal according to the target phase offset so as to adjust the phase of the drive signal; The first signal circuit is used to convert the reference driving signal into the driving signal; The second signal circuit is used for converting the reference synchronization signal into the synchronization signal.

6. The phase synchronization circuit according to claim 5, characterized in that: The reference driving signal is a differential signal, and the first signal circuit includes: a first level conversion circuit, a first comparison circuit, a first two-frequency division circuit and a second level conversion circuit; The first level conversion circuit is used to raise the voltage difference of the reference driving signal to a preset value and generate a first differential signal; The first comparison circuit is used for converting the first differential signal into a first square wave signal, wherein the frequency of the first square wave signal is the same as the frequency of the first differential signal; The first two-frequency dividing circuit is used to perform frequency division processing on the first square wave signal to form a second differential signal with a duty cycle of 50% and a frequency of a set frequency; The second level conversion circuit is used for converting the second differential signal into a single-ended signal to form the driving signal.

7. The phase synchronization circuit according to claim 6, characterized in that: The first signal circuit further includes: a first filtering circuit, and / or a second driving circuit and a first DC blocking circuit, wherein: The first filtering circuit is used to filter out the noise signal of the target frequency band in the reference driving signal; The second driving circuit is used to enhance the driving capability of the driving signal; The first DC blocking circuit is used for filtering the DC component in the driving signal.

8. The phase synchronization circuit according to claim 5, characterized in that: The reference synchronization signal is a differential signal, and the second signal circuit includes: a third level conversion circuit, a second comparison circuit, and a second two-frequency division circuit; The third level conversion circuit is used to raise the voltage difference of the reference synchronization signal to a preset value and generate a third differential signal; The second voltage comparison circuit is used for converting the third differential signal into a second square wave signal, wherein the frequency of the second square wave signal is the same as the frequency of the third differential signal; The second two-frequency dividing circuit is used to perform frequency division processing on the second square wave signal, and output the synchronization signal with a duty cycle of 50% and a frequency of a set frequency.

9. The phase synchronization circuit according to claim 8, characterized in that: The second signal circuit further includes: a second filtering circuit, and / or a second driving circuit, wherein: The second filtering circuit is used to filter out the noise signal of the target frequency band in the reference synchronization signal; The second driving circuit is used to enhance the driving capability of the synchronization signal.

10. A radio frequency power supply, characterized in that: include: A plurality of radio frequency circuits and a plurality of cascaded phase synchronization circuits as claimed in any one of claims 1 to 9, wherein: Each stage of the phase synchronization circuit is connected to a corresponding radio frequency circuit, and is used to provide the driving signal to the radio frequency circuit; The phase synchronization circuit at the current stage is used to provide the synchronization signal to the phase synchronization circuit at the subsequent stage.

11. A semiconductor process equipment, characterized in that: include: A process chamber and a radio frequency power supply as claimed in claim 10.

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