On-chip network many-core architecture chip, table storage and search method

Abstract

The present invention provides a chip with a many-core network-on-chip (NOC) architecture and a table entry storage and lookup method. Based on the architecture of a NOC microcore firmware (FW) and a table lookup unit (LM), the present invention distributes table entries across multiple LMs. When a table lookup is required at the forwarding layer, multiple LMs can provide table entry lookup capabilities in parallel, thereby improving the table entry lookup and message forwarding performance of the data communication chip. Furthermore, by adaptively and dynamically adjusting the table entry storage strategy, the chip reduces table entry latency through a multiple-copy mechanism when the number of table entries is small, and increases table entry capacity by expanding the table entry storage space when the number of table entries is large. This allows the chip to more intelligently and flexibly adapt to network conditions.

Description

Technical Field

[0001] This specification relates to the field of data communication technology, and in particular to a network-on-chip (NOC) many-core architecture chip, and a table entry storage and search method. Background Art

[0002] Data communication chips (abbreviated as data communication chips), such as those used in network devices such as routers and switches, face a persistent problem, which is how to achieve higher forwarding performance at low cost.

[0003] With the accelerated development of network technology, the requirements for the processing performance of data communication chips are becoming increasingly higher. Simply improving chip performance by increasing the hardware clock frequency and scaling up is no longer able to keep up with the needs of network applications.

[0004] Static random access memory (SRAM) uses static storage technology that doesn't require periodic refreshes like dynamic random access memory (DRAM). This allows for high stability and fast read / write speeds. However, SRAM's manufacturing process is complex, consumes high power, and has a low integration density. To improve message processing performance, data communication chips typically use SRAM as built-in memory. Furthermore, to reduce power consumption and costs, the amount of built-in SRAM is kept to a minimum.

[0005] Table lookup during packet forwarding is a frequently used, fundamental function of datacom chips. Although SRAM offers fast read / write speeds, its bandwidth is limited. To forward a packet within a datacom chip, a single packet typically requires lookups in multiple tables, such as the Media Access Control (MAC) table, the Longest Prefix Match (LPM) table, and the Interface Table (INTF). Assuming basic L2 / L3 forwarding requires five table lookups per packet, and a chip forwarding capacity of 3.2TB, for a fixed-length 256B packet (276B including the interframe gap and preamble), this requires 3200GB / 8 / 276*5=7.25GB of table lookups per second. Even if one table lookup request is processed per clock cycle, a single SRAM controller cannot meet this performance requirement.

[0006] The comparative document "Tightly Coupled Adaptive Coprocessing System Supporting Multi-core Network Processing Architecture" with application publication number CN104503948A discloses: a multi-core processor chip integrates multiple CPU cores programmed in C language, and the cores interact with each other through shared memory, cache consistency bus, or dedicated switching structure (such as through a dedicated ring network cross-network, etc., to connect multiple cores, peripherals, coprocessors, etc.). Each core can be flexibly configured to perform a certain operation of network message processing, such as single operations such as message parsing, order preservation, table lookup, and flow control, to implement complex business processing. Multiple cores can also achieve concurrent processing and achieve high-throughput data forwarding.

[0007] The aforementioned comparative documents only disclose technical content that multi-core processor chips can be interconnected via shared memory or a dedicated ring cross-network, with different cores configured to perform different network message processing operations, thereby achieving multi-core concurrent processing. However, this shared memory bus approach by multi-core CPUs leads to contention for memory access, and for data communication chips requiring high-speed table lookup and message forwarding, this still fails to address the efficiency issues of table lookup. Summary of the Invention

[0008] In order to solve the technical problems existing in the prior art, the present invention provides a network-on-chip (NOC) many-core architecture chip, and a table entry storage and search method.

[0009] According to one aspect of an embodiment of the present invention, the present invention provides a chip with a many-core network-on-chip architecture, which includes a control layer network-on-chip, wherein each router of the control layer network-on-chip is connected to a firmware microkernel FW and a table lookup unit LM;

[0010] The firmware micro-core FW includes a management module, which is used to manage the table lookup unit LM. When receiving a table entry sent by an upper layer, the table entry is distributedly stored in the table lookup unit LM.

[0011] The table lookup unit LM comprises:

[0012] The storage module is used for distributed storage of table entries, and when receiving management instructions issued by the firmware micro-core, performs management operations on the table entries according to the management instructions;

[0013] The table lookup module is used to receive a table entry lookup request sent by the forwarding layer, perform table entry lookup and return the lookup result to the forwarding layer.

[0014] Furthermore, the management module of the firmware micro-core adopts a capacity priority strategy to distribute the table entry data to the table lookup unit LM mounted on the control layer on-chip network; under the capacity priority strategy, only one copy is stored for each table entry; or,

[0015] The management module of the firmware micro-core adopts a latency priority strategy to distribute and store the table entry data in the table lookup unit LM mounted on the control layer on-chip network; under the latency priority strategy, multiple copies are stored for each table entry.

[0016] Furthermore, the table lookup unit LM attached to the control layer on-chip network is divided into a plurality of LM groups;

[0017] Under the latency-first strategy, each LM group stores a copy of the table entry;

[0018] Under the capacity priority policy, only one table entry copy is stored in multiple LM groups.

[0019] Furthermore, the firmware microkernel FW also includes a policy adjustment module, which includes:

[0020] A judgment module, configured to judge whether it is necessary to adjust the table entry storage policy in the LM or in the LM group according to the switching condition of the table entry storage policy;

[0021] A switching module, configured to execute a switching operation corresponding to a switching condition of the entry storage policy;

[0022] The switching condition of the entry storage policy includes a first switching condition and a second switching condition;

[0023] The first switching condition is a condition for switching from the latency-first policy to the capacity-first policy when the total number of entries exceeds a preset first threshold. The first switching condition corresponds to a first switching operation, which is used to clear redundant entry copies from multiple LMs or multiple LM groups and switch the storage policy to the capacity-first policy.

[0024] The second switching condition, i.e., the condition for switching from the capacity priority policy to the latency priority policy, is that the total number of entries in all LMs or LM groups is lower than a preset second threshold and there is no mapping position conflict for any entry in multiple LMs or LM groups. The second switching condition corresponds to a second switching operation, which is used to copy a single entry in a single LM or a single LM group to other LMs or LM groups and switch the storage policy to the latency priority policy.

[0025] The first threshold and the second threshold are a watermark value lower than the total on-chip network entry storage space divided by the maximum number of replicas N under the latency priority policy.

[0026] Furthermore, the chip also includes a forwarding layer network on chip, in which each router is connected to a forwarding core, which is used to process and forward packets;

[0027] The scale of the forwarding layer NOC and the control layer NOC is the same, and the forwarding core has a mapping relationship with the LM or LM group;

[0028] When a table lookup is required, the forwarding core extracts the table entry keyword from the message and selects the LM or LM group closest to the forwarding core to process the table entry lookup request based on the table entry storage strategy currently used by the control layer on-chip network and the hash map storage method of the table entry.

[0029] According to another aspect of an embodiment of the present invention, the present invention further provides a table entry storage and lookup method, which is applied to a data communication chip including a control layer network-on-chip, wherein each router in the control layer network-on-chip is connected to a firmware microkernel FW and a table lookup unit LM, and the method comprises:

[0030] The firmware micro-core FW manages the table lookup unit LM; when receiving a table entry sent by an upper layer, the table entry is distributedly stored in the table lookup unit LM;

[0031] When the table lookup unit LM receives the management instruction issued by the firmware microcore, it performs a management operation on the table entry according to the management instruction;

[0032] When the table lookup unit LM receives a table entry lookup request sent by the forwarding layer, it performs a table entry lookup and returns a lookup result to the forwarding layer.

[0033] Furthermore, the firmware micro-core adopts a capacity priority strategy to distributely store the table entries in the table lookup unit LM mounted on the control layer on-chip network; or the management module of the firmware micro-core adopts a latency priority strategy to distributely store the table entries in the table lookup unit LM mounted on the control layer on-chip network;

[0034] Under the capacity-first strategy, only one copy of each entry is stored;

[0035] Under the latency priority strategy, multiple copies of each entry are stored.

[0036] Furthermore, the table lookup unit LM attached to the control layer on-chip network is divided into a plurality of LM groups;

[0037] Under the latency-first strategy, each LM group stores a copy of the table entry;

[0038] Under the capacity priority policy, only one table entry copy is stored in multiple LM groups.

[0039] Furthermore, the method for the firmware microkernel FW to manage the table lookup unit LM further includes:

[0040] Determine whether to adjust the storage policy of the entry in the LM or in the LM group based on the switching conditions of the entry storage policy;

[0041] When it is determined that the switching condition of the table entry storage policy is met, a switching operation corresponding to the switching condition of the table entry storage policy is executed;

[0042] The switching condition of the entry storage policy includes a first switching condition and a second switching condition;

[0043] The first switching condition is a condition for switching from the latency-first policy to the capacity-first policy when the total number of entries exceeds a preset first threshold. The first switching condition corresponds to a first switching operation, which is used to clear redundant entry copies from multiple LMs or multiple LM groups and switch the storage policy to the capacity-first policy.

[0044] The second switching condition, i.e., the condition for switching from the capacity priority policy to the latency priority policy, is that the total number of entries in all LMs or LM groups is lower than a preset second threshold and there is no mapping position conflict for any entry in multiple LMs or LM groups. The second switching condition corresponds to a second switching operation, which is used to copy a single entry in a single LM or a single LM group to other LMs or LM groups and switch the storage policy to the latency priority policy.

[0045] The first threshold and the second threshold are a watermark value lower than the total on-chip network entry storage space divided by the maximum number of replicas N under the latency priority policy.

[0046] Based on the embodiment of the present invention, the present invention further provides a network device, which includes the on-chip network many-core architecture chip provided in the embodiment of the present invention.

[0047] The technical solution provided by the embodiment of the present invention has the following beneficial effects:

[0048] Based on the architecture of the on-chip network-attached firmware microkernel (FW) and table lookup units (LMs), table entries are distributed and stored across multiple LMs. When the forwarding layer requires a table lookup, multiple LMs can provide table lookup capabilities in parallel, thereby improving the table lookup and message forwarding performance of the data communication chip. Furthermore, by adaptively and dynamically adjusting the table entry storage strategy, the chip reduces table lookup latency through a multi-copy mechanism when the number of table entries is small, and increases table entry capacity by expanding table entry storage space when the number of table entries is large, enabling the chip to adapt more intelligently and flexibly to network conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments of the present invention or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings of the embodiments of the present invention.

[0050] Figure 1 A schematic diagram of a many-core network-on-chip architecture according to an embodiment of the present invention;

[0051] Figure 2 A schematic diagram of location identifier-based addressing routing in one embodiment of the present invention;

[0052] Figure 3 Schematic diagram of distributed storage of table entry data in LM under the capacity priority policy in one embodiment of the present invention;

[0053] Figure 4 Schematic diagram of distributed storage of table entry data in LM under the delay priority strategy in one embodiment of the present invention;

[0054] Figure 5 This is a schematic diagram of the control layer network-on-chip structure using the LM grouping mode according to an embodiment of the present invention;

[0055] Figure 6 This is a schematic diagram of the structure of a data communication chip using a multi-layer network-on-chip (NoC) many-core architecture according to an embodiment of the present invention;

[0056] Figure 7 Schematic diagram of a flow chart of a table entry storage and search method in one embodiment of the present invention;

[0057] Figure 8 Schematic diagram of table entry change status during switching from a latency priority strategy to a capacity priority strategy in one embodiment of the present invention;

[0058] Figure 9 Schematic diagram of table entry change status during the switching process from the capacity priority strategy to the latency priority strategy in one embodiment of the present invention;

[0059] Figure 10 FIG. 1 is a schematic diagram of horizontally grouping the table lookup units LM according to an embodiment of the present invention. DETAILED DESCRIPTION

[0060] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of this specification, as detailed in the appended claims.

[0061] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this specification. As used in this specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0062] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, such information should not be limited to these terms. These terms are merely used to distinguish information of the same type from one another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information without departing from the scope of this specification. Depending on the context, the term "if" as used herein may be interpreted as "when," "when," or "in response to determining."

[0063] In the field of data communications technology, a firmware microkernel can be understood as a lightweight, highly customized software core that runs on hardware and is responsible for managing hardware resources, scheduling tasks, and other tasks. By providing services such as a hardware abstraction layer, it ensures the efficient and orderly operation of various functions in data communications equipment. From the perspective of the entire data communications system, the design and implementation of the firmware microkernel, as firmware, must consider coordinated optimization with the hardware and upper-layer software. It must not only efficiently manage hardware resources but also provide a simple and efficient interface for upper-layer software to optimize the performance, power consumption, and cost of the entire system.

[0064] A network-on-chip (NOC) is an on-chip communication architecture that builds a topology similar to a computer network within a single chip. It uses data packets as the basic transmission unit and utilizes on-chip routers (NOC routers) and communication links to enable high-speed, parallel, and scalable communication between functional modules. This network-on-chip architecture is a technical means of improving performance through horizontal expansion, which offers excellent scalability. The NOC architecture utilizes a distributed network topology, such as a two-dimensional matrix or tree structure, treating each functional module within the chip as a network node connected by network links. In a NOC architecture, different nodes can communicate in parallel. For example, in a two-dimensional matrix NOC, multiple port processing units can simultaneously transmit data to routing units in different directions, greatly increasing data processing parallelism and thereby improving overall forwarding performance.

[0065] In order to solve the problem of table entry lookup efficiency in data communication chips, the present invention proposes a network-on-chip (NOC) multi-core architecture chip and a table entry storage and lookup method implemented on the chip, which improves the table entry lookup performance and table entry management efficiency of the data communication chip by horizontally expanding and scaling out.

[0066] Example 1

[0067] Figure 1 A schematic diagram of a many-core network-on-chip architecture for an embodiment of the present invention. Based on the functions performed by the firmware microkernel, the network-on-chip (NOC) containing the firmware microkernel / processor core primarily responsible for executing control layer functions can be referred to as the control layer NOC, while the network-on-chip containing the firmware microkernel / processor core primarily responsible for executing message processing and forwarding functions can be referred to as the forwarding layer NOC. Figure 1 This example illustrates a control-layer network-on-chip (NoC) architecture, in which NoC routers form a 2x2 matrix structure. Each router in this structure is equipped with a firmware microkernel (FW) and a lookup memory (LM). This embodiment connects multiple LMs, which store table entry data, via the NoC. This allows for distributed storage of table entry data across multiple LMs, each of which can independently perform table entry lookups. Furthermore, to improve table entry data management efficiency, a local firmware microkernel (FW) is added to each LM, which manages the table entry data in the LM.

[0068] The firmware microkernel (FW) and the lookup table unit (LM) establish a network connection through the on-chip network, forming a matrix structure. The FW and LM can each connect to the on-chip network router (R) through a local port (LocalPort). Each FW can access any LM connected to the on-chip network through the on-chip network.

[0069] In order to achieve distributed routing access from FW to LM, the location identifier of the on-chip network router can be used as the address of the FW and LM attached to the router, thereby solving the routing addressing problem between FW and LM. Figure 2Consider a 4x4 NoC structure. With the router's location {0, 0} in the lower left corner as the origin, the router's location coordinates along the X-axis range from 0 to 3, and along the Y-axis range from 0 to 3. Suppose, for example, that a FW attached to the router at location {0, 1} wants to access a LM attached to the router at location {0, 3}. The FW at location {0, 1} can use location {0, 1} as its own NoC address and location {0, 3} as the destination NoC address of the LM. Messages / data packets can be routed to the destination LM using either a deterministic or adaptive routing algorithm. The NoC router performs routing based on the source and destination addresses in the message / data packet.

[0070] The functions of FW and LM in this embodiment are described in detail below.

[0071] The firmware micro-core includes at least a management module, and the management module is used to manage the table lookup unit (LM).

[0072] The management module further includes an initialization module and a maintenance module;

[0073] Initialization module, used to initialize LM;

[0074] The maintenance module is used to maintain the table data in the LM. The maintenance includes but is not limited to the maintenance operations such as issuing, deleting, updating, moving, and collecting statistics on table entries.

[0075] Table maintenance operations typically refer to operations performed on table entries by upper-layer applications or service modules as needed. For example, due to changes in network status, the upper-layer network protocol stack updates routes, requiring a refresh of routing table entries. This causes the FW to delete invalid entries from the LM and add new entries to the LM.

[0076] When the FW receives a table entry (entry) from the upper layer, it distributes the entry to each lookup table unit (LM) attached to the on-chip network. Distributed storage of table entries in the LM can be achieved using hash mapping storage. For example, the table entry keyword Key is extracted from the field of the table entry, the Key is used as the input of the hash mapping function, and the hash value calculated by the hash function is used as the mapping storage location of the table entry data. Taking a 2*2 on-chip network matrix as an example, 2 bits can be extracted from a fixed position of the hash value of the Key to determine which LM the table entry is stored in. Based on the capacity of the LM to store the table entry, a preset number of bits are extracted to determine the mapping storage location of the table entry within the LM.

[0077] The table lookup unit at least includes: a storage module and a table lookup module.

[0078] The storage module is used for distributed storage of table entries. When receiving a management instruction sent by the firmware micro-core, the storage module performs a management operation on the table entry according to the management instruction.

[0079] For example, it receives the initialization instructions issued by the firmware micro-core and initializes the parameters, algorithms, table item storage strategies, etc. used by the LM; it receives the table item maintenance instructions issued by the firmware micro-core and performs table item maintenance operations, such as writing newly issued table items, deleting, updating, moving, and counting existing table items in the LM.

[0080] The table lookup module is used to receive a table entry lookup request sent by the forwarding layer, perform table entry lookup and return the lookup result to the forwarding layer.

[0081] To improve the management and forwarding efficiency of datacom chips, a layered approach can be adopted. Based on factors such as core functions and operation frequency, the chip is divided into multiple hardware layers. The control layer's on-chip network is responsible for table entry management and control, while the forwarding layer's on-chip network is responsible for message processing and forwarding. The control layer performs management and control operations less frequently, while the forwarding layer performs message processing and forwarding at a much higher frequency. This layered approach physically separates table entry management and lookup operations, avoiding resource contention. This not only clarifies the architecture but also improves overall chip performance.

[0082] The table lookup unit LM in the embodiment of the present invention is connected to both the control layer network on chip and the forwarding layer network on chip. The LM is managed by the control layer and provides the forwarding layer with a table entry lookup capability based on distributed storage.

[0083] Each LM in this embodiment of the present invention includes an SRAM controller, providing independent table lookup capabilities to the forwarding layer. Assuming basic L2 / L3 forwarding requires five table lookups per packet, and the chip's forwarding capacity is 3.2TB, then for a fixed-length 256B packet (276B including the inter-frame gap and preamble), 3200G / 8 / 276*5 = 7.25G table lookups per second are required. If a 4x4 network-on-chip (NoC) is used, with each router node connected to a LM with an SRAM controller, a single LM only needs to provide approximately 460M table lookups per second (460M*16 = 7.36G) to meet the required table lookup performance. This can be easily achieved with a 1G hardware frequency (assuming an average of one lookup per two clock cycles). This shows that distributed storage of table entries distributes the processing load of table lookups across multiple SRAM controllers, significantly improving the table lookup performance of data communication chips.

[0084] Example 2

[0085] Figure 3The figure is a schematic diagram of the distributed storage of table item data in LM under the capacity priority strategy in one embodiment of the present invention. In this embodiment, a 2*2 scale on-chip network is adopted to hang 4 LMs, and the FW adopts a capacity priority table item storage strategy to store the table item data in the 4 LMs. Under the capacity priority strategy, each table item is stored in only one copy in all LMs hung on the on-chip network. The FW can extract 2 bits from a preset position in the hash value of the table item keyword Key as the first index to determine in which LM the table item is stored, and according to the capacity of the LM, it can further extract a preset number of bits that match the capacity as the second index to determine the mapping storage location of the table item in the LM. The advantage of the capacity priority strategy is that it can maximize the use of the storage space of the LM, and the space utilization rate is high.

[0086] Although distributed storage of table entry data through a capacity-first strategy can improve the overall table entry lookup throughput, as the scale of the on-chip network increases, the path of the forwarding core in the forwarding layer on-chip network when accessing the control layer LM will become longer, and the latency between the shortest path and the longest path will increase, which will affect the table entry lookup performance.

[0087] Example 3

[0088] Figure 4 The figure is a schematic diagram of the distributed storage of table item data in LM under the latency priority strategy in one embodiment of the present invention. In this embodiment, a 2*2 scale on-chip network is used to hang 4 LMs, and the FW adopts a latency-prioritized table item storage strategy to store the table item data in the 4 LMs. Under the latency priority strategy, each table item will have a copy in each of all LMs attached to the on-chip network, and there will be a total of 4 table item copies. Under this strategy, the FW can ignore the first index and directly store the table item mapping to each LM attached to the on-chip network according to the second index. The advantage of the latency priority strategy is that it can maximize the parallel processing performance of table item lookup. Since a copy of the table item is stored in each LM, the forwarding core of the forwarding layer can call the nearest LM to perform table item lookup, exchanging space for time, and maximizing the overall table lookup efficiency.

[0089] Under the delay priority strategy, Figure 4 The total available table entry storage space in the example NoC is only 1 / 4 of the total table entry storage space (the sum of all LM storage spaces). As the NoC scales, the ratio of total available table entry storage space to total table entry storage space decreases. For example, for a 4x4 NoC, the ratio is 1 / 16, which results in low storage space utilization efficiency.

[0090] Example 4

[0091] In order to combine the advantages of the latency priority strategy and the capacity priority strategy, the FWs and LMs attached to the on-chip network are grouped. Figure 5 The schematic diagram of the control layer NoC structure using the LM grouping mode in one embodiment of the present invention is shown in FIG. The LMs connected to the NoC form a 4*4 matrix, which is divided into four LM groups based on the X-axis coordinates, and each LM group includes four LMs.

[0092] Under the latency-first strategy, table entries are replicated in LM groups. Under the capacity-first strategy, this is logically equivalent to merging four LM groups into a larger group, combining the first and second indexes into the index of the larger group, and mapping the table entries within the larger group. Within an LM group, the storage space for all LM entries is uniformly and continuously addressed.

[0093] Assume that each LM has 1KB of table entry storage space, and an LM group contains four LMs, for a total of 4KB of table entry storage space, or 16KB for four groups. 14 bits are extracted from the hash digest of the table entry's key. Two of these bits are selected as the first index to determine which LM group the table entry is stored in. The remaining 12 bits are used as the second index to determine the mapping storage location of the table entry within the LM group. A first index of 0 corresponds to the LM group with a router location identifier of X coordinate 0 (Replica-1), a first index of 1 corresponds to the LM group with a router location identifier of X coordinate 1 (Replica-2), and so on.

[0094] In the case of the capacity-first policy, each entry stores only one copy in four LM groups.

[0095] In the case of the latency-first strategy, each table entry stores a copy in four LM groups. That is, the number of table entry copies is equal to the number of LM groups. At this time, when writing the table entry, the FW can ignore the first index and directly write the table entry data into the storage space of each LM group based on the second index.

[0096] When performing management and maintenance operations such as issuing and deleting entries, the FW firmware microkernel must correctly execute the corresponding management and maintenance operations based on the used entry storage policy. For example, under a latency-prioritized multi-copy storage policy, entries must be issued to all LM groups based on the second index. Under a capacity-prioritized single-copy policy, the first and second indexes must be combined to determine the location of the entry mapping within the LM group.

[0097] In one embodiment of the present invention, multiple types of tables are used for packet matching and lookup, such as the MAC table, LPM table, and INTF table. Each firmware micro-kernel FW is responsible only for managing various table entries in its local LM (the LM connected to the same router as the FW). When LMs are grouped, the FWs within the group can also be assigned different responsibilities. Different firmware micro-kernel FWs can be configured to manage different types of table entries within the LM group, with each FW managing one or more types of entries.

[0098] Example 5

[0099] In order to further improve the adaptability and availability of the chip under different network conditions and enable the chip to intelligently and dynamically adjust the table entry storage strategy according to the number of table entries, a policy adjustment module can be added to the control layer on-chip network. The policy adjustment module dynamically adjusts the table entry storage strategy according to the current number of table entries.

[0100] To achieve the above objectives, the firmware microkernel FW in the control layer NoC also includes:

[0101] A policy adjustment module is used to adjust the table entry storage policy in the LM or LM group according to the switching condition of the table entry storage policy and perform the corresponding switching operation, wherein the table entry storage policy includes a latency priority policy and a capacity priority policy;

[0102] The policy adjustment module further includes:

[0103] A judgment module, configured to judge whether it is necessary to adjust the table entry storage policy in the LM or in the LM group according to the switching condition of the table entry storage policy;

[0104] A switching module, configured to execute a switching operation corresponding to a switching condition of the entry storage policy;

[0105] The latency-priority strategy is a table entry storage strategy designed to reduce the latency of table entry lookups. This strategy requires that table entries be stored in multiple replicas in multiple LMs or LM groups to improve the efficiency of concurrent table entry lookups.

[0106] The capacity-first strategy aims to increase the number of table entries. This strategy requires single-copy storage of entries across multiple LMs or LM groups to increase storage capacity. This strategy maximizes network device availability when there are many concurrent connections. However, it increases table entry lookup latency and reduces lookup efficiency.

[0107] The switching condition of the entry storage policy includes a first switching condition and a second switching condition.

[0108] The first switching condition, which switches from the latency-first strategy to the capacity-first strategy, can be configured as follows: the total number of entries exceeds a preset first threshold. The first threshold can be configured to be a watermark value lower than the total entry storage space divided by the maximum number of replicas N under the latency-first strategy. The total entry storage space is the sum of the entry storage space of all LMs.

[0109] For example, a 2*2 on-chip network is connected to 4 LMs, and the table entry storage space of each LM is 1K. The total table entry storage space is the sum of the table entry storage space of the 4 LMs, which is 4K. The maximum number of replicas N under the latency priority policy is 4. Each table entry is stored in 4 LMs. The total effective table entry storage space is the total table entry storage space divided by the maximum number of replicas 4 under the latency priority policy, which is equal to 1K. The first threshold can be set to a watermark value less than or equal to the total effective table entry storage space, such as 98%, or it can be set to 100%.

[0110] When the FW determines that the first switching condition is currently met, the switching module performs a first switching operation. The purpose of the first switching operation is to clear redundant copies from multiple LMs or multiple LM groups and leave only one copy.

[0111] The second switching condition, i.e., the condition for switching from the capacity priority strategy to the delay priority strategy, can be configured as follows: the total number of entries in all LMs or LM groups is lower than a preset second threshold and there is no mapping position conflict for any entry in multiple LMs or LM groups.

[0112] The mapping location conflict means that, in all LMs or LM groups attached to the control layer on-chip network, there are more than one valid table entry at the mapping storage location indicated by the second index in the hash value of the table entry keyword Key.

[0113] The second threshold may also be set to a watermark value that is less than or equal to the total entry storage space divided by the maximum number of replicas N under the latency priority policy. The second threshold may be the same as or different from the first threshold.

[0114] When the FW determines that the second switching condition is met, the switching module executes the second switching operation. The purpose of the second switching operation is to switch table entry storage from single-copy mode to multiple-copy mode, replicating table entries stored in a single LM or LM group to other LMs or other LM groups to achieve multiple-copy storage. In scenarios particularly sensitive to packet forwarding latency, table entry replication can reduce table lookup latency.

[0115] Example 6

[0116] Figure 6This figure illustrates the structure of a datacom chip using a multi-layer network-on-chip (NoC) many-core architecture, according to one embodiment of the present invention. In this embodiment, the datacom chip employs a multi-layer NoC architecture, including a control layer NoC and a forwarding layer NoC. The router matrix of the control layer NoC can be the same size as the router matrix of the forwarding layer NoC. The location identifiers of the routers in the control layer NoC and the forwarding layer NoC correspond to each other and use the same coordinates.

[0117] Each router node in the forwarding layer on-chip network is connected to the forwarding core (FC) through a local interface (LocalPort). The forwarding core can also have programmable features like a firmware microkernel, support various types of business features, and perform various processing and forwarding on messages.

[0118] The forwarding cores in the forwarding layer's SoC map to the firmware microkernel (FW) and table lookup unit (LM) in the control layer's SoC. These cores, along with the firmware microkernel (FW) and table lookup unit (LM) in the same location, can be interconnected via local interfaces. The forwarding cores in the forwarding layer's SoC can also access any firmware microkernel and table lookup unit in the control layer's SoC via the inter-SoC interconnection mechanism.

[0119] When the forwarding core in the forwarding layer network-on-chip processes and forwards a message and needs to perform a table lookup operation, it can extract the table entry keyword Key from the message to form a table entry lookup request, and then send the table entry lookup request to the LM or LM group that stores the table entry copy in the control layer network-on-chip to perform the table entry lookup operation, thereby obtaining the table entry lookup result.

[0120] The control layer NoC and the forwarding layer NoC need to synchronize table entry storage strategies, hash mapping methods, and LM group information. Based on this synchronized information, the forwarding core in the forwarding layer NoC selects the LM or LM group with the nearest table entry replica to perform a table entry lookup.

[0121] like Figure 6For example, a mapping correspondence can be established between the LM groups of the control layer network-on-chip and the forwarding core groups of the forwarding layer network-on-chip. For example, both layers of the network-on-chip are grouped according to the X-coordinate of the router, and the groups with the same X-coordinate form one group. The control layer network-on-chip divides the four LMs with X-axis position coordinates of 0, 1, 2, and 3 into four LM groups, namely Replica-1, Replica-2, Replica-3, and Replica-4. The forwarding layer also divides the four forwarding cores with X-axis position coordinates of 0, 1, 2, and 3 into four LM groups, namely Group-1, Group-2, Group-3, and Group-4. A mapping correspondence is established between Group-1 and Replica-1, a mapping correspondence is established between Group-2 and Replica-2, and so on. It should be noted that the present invention does not limit the direction of dividing the LM groups. The groups can be divided along the X-axis or the Y-axis. The division method of the forwarding core groups is consistent with the division method of the LM groups.

[0122] When a forwarding core in Group-1 needs to perform a table lookup, if the table entry storage policy prioritizes latency, the forwarding core in Group-1 selects the LM in Replica-1 that is closest to it physically (via the number of NOC router hops) to handle the table lookup request based on the mapping relationship. If the table entry storage policy prioritizes capacity, assuming the required table entry is mapped and stored in the LM in the Replica-3 group using a hash mapping algorithm, the table lookup request is sent via the on-chip network to the LM in Replica-3's LM group for the table lookup.

[0123] By allocating control layer functions and forwarding layer functions to different on-chip networks, the management and control operations for table entries are separated from the processing and forwarding operations of messages. This can reduce the mutual impact between different types of operations and thus improve the processing performance of the entire chip.

[0124] Example 7

[0125] Figure 7 This is a flow chart of a table entry storage and lookup method according to one embodiment of the present invention. This method is applied to a data communication chip including the aforementioned control layer network-on-chip, where each router in the control layer network-on-chip is connected to a firmware microkernel FW and a table lookup unit. The method includes:

[0126] Step 701: the firmware micro-core FW manages the table lookup unit LM; when receiving a table entry sent by an upper layer, the table entry is distributedly stored in the table lookup unit LM.

[0127] Step 702: When the table lookup unit LM receives the management instruction sent by the firmware micro-core, it performs a management operation on the table entry according to the management instruction.

[0128] Step 703: When the LM receives the table entry lookup request sent by the forwarding layer, it performs a table entry lookup and returns the lookup result to the forwarding layer.

[0129] Since table entries are stored in a distributed manner, when multiple LMs each store a portion of the table entries, the forwarding layer can send table entry lookup requests to multiple LMs to process the table entry lookup requests in parallel, thereby improving table lookup efficiency.

[0130] Furthermore, the table entry lookup request is sent by the forwarding core in the forwarding layer's network-on-chip. When a message / data packet arrives at the forwarding core, it can perform preliminary processing on the message and extract the key used for the table entry lookup. For example, for IP messages, the destination IP address can be used as the lookup key; for Ethernet messages, the destination MAC address can be used as the lookup key.

[0131] The forwarding core sends a table entry lookup request, along with other information (such as the entry type), to the LM, triggering the LM to perform the entry lookup. Upon receiving the table entry lookup request from the forwarding core, the LM quickly activates its search logic. Based on the entry type and configured search algorithm, it quickly searches its stored entries. For example, if performing a longest prefix match search, it utilizes a specific data structure (such as a Trie tree) to efficiently search for the entry that longest matches the destination IP address. After obtaining the search result, the LM returns it to the forwarding core in the forwarding layer.

[0132] Example 8

[0133] In this embodiment, the NoC employs a 4x2 architecture (4 rows and 2 columns, X coordinates [0, 1], Y coordinates [0, 1, 2, 3]). The LM matrix is vertically divided into two LM groups: the four LMs at X-axis position 0 form an LM group corresponding to Replica-1, and the four LMs at X-axis position 1 form an LM group corresponding to Replica-2. The LM storage space within the LM group is uniformly addressed, and table entries are stored in the LM group. Single and dual replica modes are preconfigured. The single replica mode prioritizes capacity, while the dual replica mode prioritizes latency.

[0134] During system initialization, the firmware microkernel in the control layer's on-chip network adopts a latency-prioritized multi-replication strategy by default. When the FW writes an entry to the LM group, it writes the entry to both Replica-1 and Replica-2 LM groups.

[0135] In the multi-copy mode of the latency-first policy, as the number of entries written by the FW to the LM group increases, when the conditions for switching from the latency-first policy to the capacity-first policy (the first switching condition) are met, the corresponding switching operation (the first switching operation) is performed.

[0136] Figure 8 Schematic diagram of table entry change status during the switching process from the latency priority strategy to the capacity priority strategy in one embodiment of the present invention.

[0137] Step 801: Before publishing an entry, the firmware microkernel FW determines whether a condition for switching from a latency priority strategy to a capacity priority strategy (a first switching condition) is currently met. If the condition is met, the corresponding switching operation (a first switching operation) is triggered.

[0138] Figure 8 Part (a) shows an example of how entries are stored in two LM groups in dual-copy mode. Entry 1 to Entry 8 have two copies in both LM groups.

[0139] The FW may update the entry counter each time an entry is delivered, deleted, or invalidated, and trigger the first switching operation when the total number of entries in the LM group exceeds a preset first threshold.

[0140] In this embodiment, the on-chip network is connected to a total of 8 LMs (4*2), two LM groups, the maximum number of copies in the latency priority mode is 2, each LM group includes 4 LMs, and assuming that each LM has 1K of table entry storage space, the total on-chip network entry storage space is 8K. The first threshold can be set to a watermark value that is less than or equal to the total on-chip network entry storage space / maximum number of copies.

[0141] Step 802: Execute a first switching operation to clear redundant entry copies from multiple LM groups and switch the current entry storage strategy to a capacity priority strategy.

[0142] The FW that triggers the switchover operation notifies all FWs in the control layer's NoC. Each FW initiates a scan of the table entries in its local LM (the LM connected to the same NoC router as the FW). Whenever an entry is found, the following actions are performed:

[0143] Step 8021: Extract the key from the entry and recalculate the hash digest of the key.

[0144] Step 8022: Extract a first index from a preset position in the hash value of the Key, and determine the LM group where the entry copy is located based on the first index;

[0145] The hash value of the table entry keyword Key is used to determine the mapping storage location of the table entry. In this embodiment, there are 8 LMs. Assuming that each LM can store 1K table entries (ENTRY), the total addressing space of the 8 LMs requires 13 bits, corresponding to 8K table entry storage space. Based on this, 13 bits can be extracted from a fixed preset position in the hash value of the table entry Key, 1 bit of which is used as the first index, and the other 12 bits are used as the second index. The second index is used to determine the mapping storage location of the table entry within the LM group, corresponding to the 4K table entry storage space continuously addressed within the LM group. The first index is used to determine which LM group the table entry mapping is stored in.

[0146] Step 8023: According to the value of the chip select bit, the table entries belonging to the LM group are retained, and the table entries not belonging to the group are cleared.

[0147] In this embodiment, the four LMs at x-axis position 0 form the Replica-1 group, corresponding to the first index value 0; the four LMs at x-axis position 1 form the Replica-2 group, corresponding to the first index value 1. For the FW in Replica-1, when scanning a table entry, if the first index value in the hash value of the key of the entry is 0, it indicates that the entry belongs to the corresponding LM group, and the entry is retained in the LM group. If the first index value in the hash value of the key of the entry is 1, it indicates that the entry does not belong to Replica-1, and the entry is invalidated or deleted. The FW in the Replica-2 group performs the same operation.

[0148] Through the above scanning process, only one copy of the entry is retained in multiple LM groups, thereby clearing redundant copies of the entry.

[0149] Step 8024: After all redundant entries are cleared, the current entry storage policy is switched to a capacity priority policy.

[0150] After completing the switch from the latency-prioritized multi-copy strategy to the capacity-prioritized single-copy strategy, it is equivalent to merging two LM groups into a larger LM group. The total table storage space of the control layer on-chip network is theoretically expanded by N times, where N is the maximum number of copies. Figure 8 Example of part (b) in .

[0151] Step 803: When the FW subsequently issues new entries, it issues them according to the capacity priority policy.

[0152] Under the capacity-first strategy, the steps for mapping storage based on the hash value of the table entry key are as follows:

[0153] Step 8031: Extract 1 bit from a fixed preset position in the hash value of the entry keyword Key as the first index to determine the LM group to which the entry belongs.

[0154] Step 8032: extract 12 bits from a preset position in the hash value of the table entry keyword Key as the second index, and determine the mapping storage position of the table entry in the LM group indicated by the first index.

[0155] Step 8033: Store the table entry in the corresponding storage location in the corresponding LM group based on the first index and the second index. Only one copy of each table entry will be sent.

[0156] like Figure 8 In the example of part (c), under the capacity priority policy, the newly issued entries Entry9, Entry10, and Entry11 are mapped and stored in the storage space vacated in the LM group, allowing each group to store more entries.

[0157] Figure 9 This is a schematic diagram of the table entry changes during the switch from a capacity-first strategy to a latency-first strategy in one embodiment of the present invention. Under the capacity-first strategy, when the network load decreases, many table entries may be deleted or invalidated. As the number of table entries in the LM group decreases, when the conditions for switching from a capacity-first multi-replica strategy to a latency-first multi-replica strategy are met, the firmware microkernel FW in the control layer on-chip network can trigger the switch operation. The switching process is as follows:

[0158] Step 901: After deleting the entry in the LM group or periodically checking, the FW determines whether the conditions for switching from the capacity-first policy to the latency-first policy (second switching conditions) are met. If the conditions are met, the corresponding switching operation (second switching operation) is triggered.

[0159] Figure 9 Part (a) illustrates the storage status of entries in two LM groups in single-copy mode. Entries Entry1 to Entry8 have only one copy in both LM groups and there is no location conflict.

[0160] The position conflict means that in multiple LM groups, there are multiple valid entries at the mapping storage location indicated by the second index in the hash value of the table entry keyword Key. If the multi-copy mode of the delay priority strategy is switched, it will cause a mapping position conflict. Figure 8For example, in part (c) of the example, two valid entries, Entry 9 and Entry 3, exist at the third storage location in each LM group. In this case, duplicating the entries and switching the policy will cause a conflict, resulting in the entries being overwritten. Of course, in the event of a position conflict, you can also consider shifting the conflicting entry to a non-conflicting location to resolve the conflict.

[0161] The second switching condition in this step is: the total number of entries in all LM groups is less than a preset second threshold, and no entry has a mapping location conflict across multiple LM groups. The second threshold can be set to a watermark value that is less than or equal to the total NOC entry storage space / the maximum number of replicas under the policy priority policy. Assuming the total entry storage space for Replica-1 and Replica-2 is 8KB, and the maximum number of replicas in multi-replica mode is 2, the second threshold can be set to 4KB. When the total number of entries in the two LM groups is less than or equal to 4KB and no entry has a location conflict across multiple LM groups, the second switching condition is determined to be met.

[0162] Step 902: Execute the second switching operation to copy each table entry to other LM groups, thereby converting the table entry from a single copy to multiple copies, and switching the storage policy to a latency-priority policy.

[0163] The FW that triggers the switching operation will notify all FWs in the control layer on-chip network. Each FW will start the scanning process of the table entries in the local LM. During the scanning process, whenever a table entry is scanned, it will be copied to other LM groups.

[0164] like Figure 9 In the example in part (b) of the figure, for each entry currently existing in the local LM unit, if the current X-position coordinate of the local node is 0, the FW copies the entry to the corresponding LM unit in the other LM group with an X-position coordinate of 1. Similarly, if the X-position coordinate of the local LM is 1, the entry is copied to the corresponding LM in the other LM group with an X-position coordinate of 0. After all FW scans are completed, each entry has a copy stored in both LM groups.

[0165] Step 903: When the subsequent FW issues a new entry, it issues the entry according to the latency priority policy.

[0166] Under the latency priority policy, the steps for mapping and storing the hash value of the table entry key are as follows:

[0167] Step 9031: extract a fixed 12-bit value from a preset position in the hash value of the table entry Key as the second index to determine the mapping storage position of the table entry in the LM group.

[0168] Under the latency priority strategy, the first index does not need to be extracted to determine the LM group when the entry is downloaded, because each entry will be stored in all LM groups, and only needs to be mapped and stored according to the second index.

[0169] Step 9032: Store the entry into the corresponding hash map storage location in each LM group based on the second index.

[0170] like Figure 9 In the example in part (c), under the latency-priority policy, newly issued table entries are mapped and stored in all LM packets, allowing the forwarding core at the forwarding layer to select the closest LM packet for table entry lookup, thereby reducing latency and improving table entry lookup efficiency.

[0171] The present invention does not limit the matrix scale of the on-chip network. For example, it can also be a 4*4, 8*8, 16*16 scale on-chip network. The number of LM groups can be flexibly set according to the scale of the on-chip network and the needs of actual application. For example, it can be 2 groups, 4 groups, 8 groups, 16 groups, etc. In addition, the present invention does not limit the specific way of dividing the groups. For example, Figure 10 As shown, LM groups can also be divided according to the Y-axis position coordinate. The grouping method of the forwarding cores in the forwarding layer on-chip network should be consistent with the LM grouping method in the control layer on-chip network, which will not be repeated here.

[0172] The foregoing description of this specification describes specific embodiments. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0173] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the present invention and practicing the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this specification and include common knowledge or customary techniques in the art that are not claimed in this specification.

[0174] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A chip with a many-core network architecture, characterized in that: The chip includes a control layer on-chip network, and each router of the control layer on-chip network is connected with a firmware micro-core FW and a table lookup unit LM; The firmware micro-core FW includes a management module, which is used to manage the table lookup unit LM. When receiving a table entry sent by an upper layer, the table entry is distributedly stored in the table lookup unit LM. The table lookup unit LM comprises: The storage module is used for distributed storage of table entries, and when receiving management instructions issued by the firmware micro-core, performs management operations on the table entries according to the management instructions; The table lookup module is used to receive the table entry lookup request sent by the forwarding layer, perform the table entry lookup and return the lookup result to the forwarding layer; The chip also includes a forwarding layer network-on-chip, in which each router is connected to a forwarding core for processing and forwarding packets. The forwarding core has a mapping relationship with the firmware micro-core FW and the table lookup unit LM in the control layer network-on-chip. The firmware micro-core FW also includes a policy adjustment module, which is used to dynamically switch the table entry storage policy according to the total number of table entries.

2. The chip according to claim 1, characterized in that The management module of the firmware micro-core adopts a capacity priority strategy to distribute the table entry data to the table lookup unit LM mounted on the control layer on-chip network; under the capacity priority strategy, only one copy is stored for each table entry; or, The management module of the firmware micro-core adopts a latency priority strategy to distribute and store the table entry data in the table lookup unit LM mounted on the control layer on-chip network; under the latency priority strategy, multiple copies are stored for each table entry.

3. The chip according to claim 1, characterized in that The table lookup unit LM attached to the control layer on-chip network is divided into multiple LM groups; Under the latency-first strategy, each LM group stores a copy of the table entry; Under the capacity priority policy, only one table entry copy is stored in multiple LM groups.

4. The chip according to claim 2 or 3, characterized in that: The policy adjustment module includes: A judgment module, configured to judge whether it is necessary to adjust the table entry storage policy in the LM or in the LM group according to the switching condition of the table entry storage policy; A switching module, configured to execute a switching operation corresponding to a switching condition of the entry storage policy; The switching condition of the entry storage policy includes a first switching condition and a second switching condition; The first switching condition is a condition for switching from the latency-first policy to the capacity-first policy when the total number of entries exceeds a preset first threshold. The first switching condition corresponds to a first switching operation, which is used to clear redundant entry copies from multiple LMs or multiple LM groups and switch the storage policy to the capacity-first policy. The second switching condition, i.e., the condition for switching from the capacity priority policy to the latency priority policy, is that the total number of entries in all LMs or LM groups is lower than a preset second threshold and no mapping position conflict exists for any entry in multiple LMs or LM groups. The second switching condition corresponds to a second switching operation, which is used to copy a single entry in a single LM or a single LM group to other LMs or LM groups and switch the storage policy to the latency priority policy. The first threshold and the second threshold are a watermark value lower than the total on-chip network entry storage space divided by the maximum number of replicas N under the latency priority policy.

5. The chip according to claim 4, characterized in that When a table lookup is required, the forwarding core extracts the table entry keyword from the message and selects the LM or LM group closest to the forwarding core to process the table entry lookup request based on the table entry storage strategy currently used by the control layer on-chip network and the hash map storage method of the table entry.

6. A table entry storage and search method, characterized in that: The method is applied to a data communication chip including a control layer network on chip, wherein each router in the control layer network on chip is connected to a firmware micro-core FW and a table lookup unit LM. The method comprises: The firmware micro-core FW manages the table lookup unit LM; when receiving a table entry sent by an upper layer, the table entry is distributedly stored in the table lookup unit LM; When the table lookup unit LM receives the management instruction issued by the firmware microcore, it performs a management operation on the table entry according to the management instruction; When the table lookup unit LM receives a table entry lookup request sent by the forwarding layer, it performs a table entry lookup and returns the lookup result to the forwarding layer; The data communication chip further includes a forwarding layer network-on-chip, in which each router is connected to a forwarding core for processing and forwarding packets; the forwarding core has a mapping relationship with the firmware micro-core FW and the table lookup unit LM in the control layer network-on-chip; The firmware micro-core FW is further configured to dynamically switch the table entry storage strategy according to the total number of table entries.

7. The method according to claim 6, characterized in that The firmware micro-core adopts a capacity priority strategy to distribute and store table entries in the table lookup unit LM mounted on the control layer on-chip network; or the firmware micro-core adopts a latency priority strategy to distribute and store table entries in the table lookup unit LM mounted on the control layer on-chip network; Under the capacity-first strategy, only one copy of each entry is stored; Under the latency priority strategy, multiple copies of each entry are stored.

8. The method according to claim 7, characterized in that The table lookup unit LM attached to the control layer on-chip network is divided into multiple LM groups; Under the latency-first strategy, each LM group stores a copy of the table entry; Under the capacity priority policy, only one table entry copy is stored in multiple LM groups.

9. The method according to claim 7 or 8, characterized in that The method for the firmware micro-core FW to manage the table lookup unit LM further includes: Determine whether to adjust the storage policy of the entry in the LM or in the LM group based on the switching conditions of the entry storage policy; When it is determined that the switching condition of the table entry storage policy is met, a switching operation corresponding to the switching condition of the table entry storage policy is executed; The switching condition of the entry storage policy includes a first switching condition and a second switching condition; The first switching condition is a condition for switching from the latency-first policy to the capacity-first policy when the total number of entries exceeds a preset first threshold. The first switching condition corresponds to a first switching operation, which is used to clear redundant entry copies from multiple LMs or multiple LM groups and switch the storage policy to the capacity-first policy. The second switching condition, i.e., the condition for switching from the capacity priority policy to the latency priority policy, is that the total number of entries in all LMs or LM groups is lower than a preset second threshold and no mapping position conflict exists for any entry in multiple LMs or LM groups. The second switching condition corresponds to a second switching operation, which is used to copy a single entry in a single LM or a single LM group to other LMs or LM groups and switch the storage policy to the latency priority policy. The first threshold and the second threshold are a watermark value lower than the total on-chip network entry storage space divided by the maximum number of replicas N under the latency priority policy.

10. A network device, characterized in that: The network device includes the chip according to any one of claims 1 to 5.

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