Preparation method of nanowire-based memristor and memristor

Abstract

The invention belongs to the technical field of electronic information, and particularly relates to a preparation method based on a nanowire memristor and the memristor. The specific process of the preparation method comprises the following steps: firstly, preparing an electrode pattern on an oxidized silicon wafer through a photoetching process, and preparing a planar electrode by coating a film through a thermal evaporation method; secondly, spin-coating nanowires on the silicon oxide wafer twice by adopting a spin-coating process between the two planar electrodes, so that the nanowires are arranged in a quasi-anisotropic manner; and finally, depositing a packaging layer on the nanowire of the oxidized silicon wafer by using an atomic layer deposition process.

Description

Technical Field

[0001] The present invention belongs to the field of electronic information technology, and in particular relates to a preparation method based on a nanowire memristor and a memristor. Background Art

[0002] The rapid development of fields such as robotics, the Internet of Things, and artificial intelligence is driving changes in data processing and storage methods. For decades, the traditional von Neumann computer architecture with separation between sensing, computing, and storage units has made great contributions to the fields of science and technology. However, with the advent of the big data era, this mainstream computing architecture faces increasing challenges, such as high energy consumption and low memory bandwidth caused by serial data transmission. In the face of these problems, new computing systems need to be developed to acquire, process, and store massive amounts of data. Neuromorphic computing, which simulates the type of information processing in the human brain, can process information efficiently and energy-efficiently using sparse networks. It uses high-level abstract concepts of human cognition for special intelligent tasks, such as image / speech recognition and classification, autonomous driving, and bionic memory computing.

[0003] Most existing CMOS commercial neuromorphic chips (such as TrueNorth and Lo ihi) use digital or analog circuits to simulate neurons and static random access memory (SRAM) to simulate synapses. It still needs to load data from off-chip memory to perform computing functions, resulting in most of the system energy consumption. Memristors have sub-nanosecond switching time, ultra-low power consumption, multi-bit programmability, and highly integrable structure, and their electrical characteristics are closer to the working principles of biological neurons. Memristors provide a more attractive alternative to neuromorphic systems.

[0004] For example, Yang et al. disclosed a biomimetic cross-modal pulse sensory neuron based on vanadium dioxide (VO2) planar memristor and demonstrated a cross-modal sensor intra-encoding and computing system for wearable human-machine interface. The threshold voltage of the vanadium dioxide memristor deposited by magnetron sputtering is 1.7V and the leakage current is 0.1mA. Liu et al. disclosed a biomimetic cross-modal pulse sensory neuron based on niobium oxide (NbO x ) memristor, which integrates a pressure sensor to handle pressure and a niobium oxide memristor to detect temperature, can achieve multi-sensory perception similar to that of humans. The threshold voltage of the niobium oxide memristor deposited by magnetron sputtering is 1.3V and the leakage current is 10μA. Chen et al. disclosed a bidirectional threshold switch silver nanowire memristor, which enhances the matrix addressing of a fully integrated flexible sensing array due to the high resistance characteristics of the memristor. The threshold voltage of the silver nanowire memristor prepared by the spraying process is 0.4V and the leakage current is 0.1pA.

[0005] Disadvantages of the prior art: high threshold voltage, high leakage current and instability (unstable performance between device cycles and between devices). Summary of the invention

[0006] In view of this, the present invention provides a preparation method and a memristor based on a nanowire memristor, which can achieve a high threshold voltage without a high leakage current.

[0007] The technical solution for implementing the present invention is as follows:

[0008] In the first aspect, the present invention provides a method for preparing a nanowire memristor, the specific process of which is as follows:

[0009] First, the electrode pattern is prepared on the silicon oxide wafer by photolithography, and the planar electrode is prepared by thermal evaporation deposition;

[0010] Secondly, the nanowires were spin-coated twice on the silicon oxide wafer between the two planar electrodes using a spin coating process, so that the nanowires were arranged in a quasi-anisotropic manner;

[0011] Finally, an encapsulation layer is deposited on the nanowires of the silicon oxide wafer using an atomic layer deposition process.

[0012] Optionally, the nanowires described in the present invention are silver nanowires, titanium dioxide (TiO2) nanowires or zinc oxide (ZnO) nanowires.

[0013] Optionally, the nanowires described in the present invention are silver nanowires, and the specific process of spin coating the nanowires twice on the silicon oxide wafer using the spin coating process is: absorb an appropriate amount of silver nanowire aqueous dispersion droplets and apply them on the surface of the silicon oxide wafer, the silver nanowire aqueous dispersion has a concentration of 0.167 mg / mL, a length of 20 μm, and a diameter of 30 nm; use a coating machine to evenly cover the silver nanowires on the surface of the silicon oxide wafer, the coating machine has two speeds, speed 1 is 300 rpm, 10 s, and speed 2 is 2500 rpm, 25 s; use high-purity nitrogen to blow dry the solution on the surface of the silicon oxide wafer, and then spin coat the silver nanowire solution again to obtain a silicon oxide wafer evenly covered with silver nanowires.

[0014] Optionally, before spin coating the nanowires, the present invention may overlay patterns on the channels of the oxidized silicon wafer between the planar electrodes to obtain an oxidized silicon wafer having a channel pattern.

[0015] Optionally, the present invention uses an atomic layer deposition process to deposit an aluminum oxide encapsulation layer on the silicon oxide wafer. The specific process is: using an atomic layer deposition process to deposit a 5 nm thick aluminum oxide encapsulation layer on the silicon oxide wafer at a deposition temperature of 70°C.

[0016] Optionally, the present invention uses thermal evaporation to deposit a planar electrode: 10 nm of chromium and 50 nm of gold are deposited on a silicon oxide wafer having an electrode pattern.

[0017] In a second aspect, the present invention provides a nanowire-based memristor, prepared by the above-mentioned preparation method, comprising a silicon oxide wafer, a planar electrode, a nanowire layer and a packaging layer; wherein the planar electrodes are located at both ends of the silicon oxide wafer, the nanowire layer is spin-coated between the two planar electrodes, and the nanowires present a quasi-anisotropic arrangement, and the packaging layer covers the nanowire layer.

[0018] Optionally, the nanowires of the present invention are silver nanowires, and the materials of the planar electrodes are chromium and gold.

[0019] Optionally, the encapsulation layer of the present invention is an aluminum oxide encapsulation layer.

[0020] Optionally, the electrode line width of the silver nanowire memristor of the present invention is 50 μm, and the electrode spacing is 100 μm.

[0021] Beneficial effects:

[0022] First, the spin coating process is simple to operate, and silver nanowire memristors can be prepared on a large scale through the spin coating process, and the silver nanowires are arranged anisotropically. The prepared silver nanowire memristors have low threshold voltage, low leakage current and high stability.

[0023] Second, the aluminum oxide encapsulation layer is deposited using the atomic layer deposition process, which can effectively protect the silver nanowires from oxidation. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 Schematic diagram of the structure of silver nanowire memristor;

[0026] Figure 2 Typical threshold switching characteristics of silver nanowire memristor;

[0027] Among them, 1-silicon dioxide (SiO2); 2-gold electrode (Au); 3-silver nanowires (AgNWs); 4-aluminum oxide (Al2O3). DETAILED DESCRIPTION

[0028] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] It should be noted that the following embodiments and features in the embodiments may be combined with each other in the absence of conflict; and, based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making any creative work are within the scope of protection of the present disclosure.

[0030] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein may be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein may be implemented independently of any other aspect, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein may be used to implement this device and / or practice this method.

[0031] The present application embodiment provides a method for preparing a silver nanowire memristor, specifically: preparing a silver nanowire memristor with anisotropic arrangement on an oxide silicon wafer by photolithography-evaporation-spin coating-deposition process, the device structure diagram is shown in FIG. Figure 1 As shown. An electrode pattern is prepared on an oxidized silicon wafer 1 by photolithography, a planar gold electrode 2 is prepared by thermal evaporation, silver nanowires 3 are spin-coated twice on the oxidized silicon wafer 1 by spin coating, and finally an aluminum oxide encapsulation layer 4 is deposited on the oxidized silicon wafer by atomic layer deposition.

[0032] The silver nanowires in the electrode spacing present a quasi-anisotropic arrangement, making the conductive path of the memristor relatively fixed. Finally, aluminum oxide is deposited on the silver nanowires as an encapsulation layer, which can well prevent the silver nanowires from being oxidized, so that the device can remain stable for a long time. The silver nanowires in this embodiment can also be other nanowires, such as titanium dioxide (TiO2) nanowires, zinc oxide (ZnO) nanowires; the aluminum oxide layer can also be selected from other materials as an encapsulation layer.

[0033] The specific process of the present invention is described in detail below:

[0034] Step 1: Cut and clean the silicon oxide wafer. Cut the silicon oxide wafer into 1*1cm 2 The small square piece was then cleaned alternately with an appropriate amount of acetone and anhydrous ethanol solution for 3 minutes by ultrasonic cleaning. Finally, high-purity nitrogen was used to blow dry the solution on the surface of the silicon oxide wafer to finally obtain a silicon oxide wafer with a clean surface.

[0035] Step 2: Apply photoresist on the surface of the silicon oxide wafer. Use a dropper to absorb an appropriate amount of photoresist (AR-P5350 UV positive photoresist) and apply it on the surface of the silicon oxide wafer. Use a coating machine to evenly cover the photoresist on the surface of the silicon oxide wafer (speed 1: 500rpm, 10s; speed 2: 3000rpm, 30s). Then place the silicon oxide wafer on a heating table to dry (100℃, 210s).

[0036] Step 3: Laser direct writing of electrode patterns on the photoresist. The corresponding electrode patterns are photoetched on the photoresist using a maskless laser direct writing lithography machine (light intensity of 0.6, time of 550 ms).

[0037] Step 4: Develop and fix the electrode pattern. Soak the silicon oxide wafer with the laser-written electrode pattern in the developer (AR-P5350 developer: deionized water = 1:6), and shake the silicon oxide wafer back and forth for 8 seconds. Then soak the silicon oxide wafer in the fixer (deionized water), and shake the silicon oxide wafer back and forth for 10 seconds. Finally, use high-purity nitrogen to blow dry the surface solution of the silicon oxide wafer, and finally obtain the silicon oxide wafer with the electrode pattern.

[0038] Step 5: Evaporate an inert metal (gold) on the silicon oxide wafer with the electrode pattern. Evaporate 10 nm of chromium (rate ) and 50nm gold (rate ); the electrode line width is 50μm and the electrode spacing is 100μm.

[0039] Step 6: Remove excess photoresist from the silicon oxide wafer. Soak the evaporated silicon oxide wafer in acetone (ultrasonic for 1 minute), then soak it in anhydrous ethanol (ultrasonic for 1 minute), and finally use high-purity nitrogen to blow dry the solution on the surface of the silicon oxide wafer, and finally obtain a silicon oxide wafer with a gold electrode pattern.

[0040] Step 7: Overlay pattern on the channel of the oxidized silicon wafer with gold electrode. Repeat steps 2, 3, and 4 to finally obtain an oxidized silicon wafer with a channel pattern.

[0041] Step 8: Spin-coat silver nanowires on the silicon oxide wafer. Use a rubber-tipped dropper to draw an appropriate amount of silver nanowire aqueous dispersion (concentration: 0.167 mg / mL, length: 20 μm, diameter: 30 nm) and drop it on the surface of the silicon oxide wafer. Use a glue spreader to evenly cover the silver nanowires on the surface of the silicon oxide wafer (speed 1: 300 rpm, 10 s; speed 2: 2500 rpm, 25 s). Use high-purity nitrogen to blow dry the solution on the surface of the silicon oxide wafer and spin-coat the silver nanowire solution again to obtain a silicon oxide wafer evenly covered with silver nanowires.

[0042] The silver nanowire aqueous dispersion is spin-coated using a spin coating process. Due to the centrifugal force, the silver nanowires can be arranged in a quasi-anisotropic manner. Compared with the drop coating method and the spray coating method, the spin-coated silver nanowires are more closely combined with the silicon oxide wafer, and the arrangement direction is controllable.

[0043] Spin coating a silver nanowire dispersion with too high a concentration will cause the silver nanowires to be too concentrated, increasing the leakage current of the memristor. Using a low-concentration silver nanowire aqueous dispersion and spin coating twice can reduce the leakage current and threshold voltage of the memristor.

[0044] Step 9: Depositing an aluminum oxide layer on the silicon oxide wafer: Using an atomic layer deposition (ALD) process, a 5 nm thick aluminum oxide encapsulation layer is deposited on the silicon oxide wafer at a deposition temperature of 70°C.

[0045] The low-temperature deposited aluminum oxide layer can effectively protect the silver nanowires in the electrode channel from being affected when the photoresist is removed, and can also act as a package to prevent the silver nanowires from being oxidized.

[0046] Step 10: Remove the excess photoresist from the silicon oxide wafer. Follow step 6 to finally obtain the silver nanowire memristor.

[0047] In the second aspect, the present embodiment is a nanowire-based memristor, which is prepared by the above-mentioned preparation method, including a silicon oxide wafer, a planar electrode, a nanowire layer and a packaging layer; wherein the planar electrodes are located at both ends of the silicon oxide wafer, the nanowire layer is spin-coated between the two planar electrodes, and the nanowires present a quasi-anisotropic arrangement, and the packaging layer covers the nanowire layer.

[0048] In this embodiment, the nanowires are silver nanowires, the planar electrodes are made of chromium and gold, the encapsulation layer is an aluminum oxide encapsulation layer, the electrode line width of the silver nanowire memristor is 50 μm, and the electrode spacing is 100 μm.

[0049] The typical threshold switching characteristics of the silver nanowire memristor prepared in this embodiment are as follows: Figure 2 After 50 cycles of current-voltage (IV) scanning, there was no significant change in performance, and the threshold voltage (V th ) is about 0.15V, holding voltage (holding voltage, V hold) is about 0.07V, the current limit is 1μA, and the leakage current is about 0.1nA. When a positive scan voltage is applied, the silver clusters located on the positive polarity begin to decompose into nanoparticles due to local Joule heating under the electric field, and move toward the opposite AgNW due to the applied electric field and concentration gradient. When the scan voltage increases to the threshold voltage, the silver nanoparticles can uniformly fill the gaps between adjacent AgNWs in a fast time scale to form electrically connected filaments, and the memristor will switch from a high resistance state to a low resistance state. When the positive scan voltage is reduced to the holding voltage, the formed filaments spontaneously break and collapse into larger clusters, and the memristor will switch from a low resistance state to a high resistance state. The low threshold switching voltage of the silver nanowire memristor is due to the use of two spin coating processes in the device preparation process, which makes the silver nanowires present a quasi-anisotropic arrangement between the electrodes, and the conductive filament paths formed between the silver nanowires are relatively fixed, so that the silver nanowire memristor can maintain relatively stable performance after 50 cycles of current-voltage scans.

[0050] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a nanowire memristor, characterized in that: The specific process is: First, the electrode pattern is prepared on the silicon oxide wafer by photolithography, and the planar electrode is prepared by thermal evaporation deposition; Secondly, the nanowires are spin-coated twice on the silicon oxide wafer between the two planar electrodes using a spin coating process, so that the nanowires present a quasi-anisotropic arrangement; Finally, an encapsulation layer is deposited on the nanowires of the silicon oxide wafer using an atomic layer deposition process.

2. The method for preparing a nanowire memristor according to claim 1, characterized in that: The nanowires are silver nanowires, titanium dioxide nanowires or zinc oxide nanowires.

3. The method for preparing a nanowire memristor according to claim 1, characterized in that: The nanowires are silver nanowires, and the specific process of spin coating the nanowires twice on the silicon oxide wafer by using the spin coating process is as follows: an appropriate amount of silver nanowire water dispersion droplets are absorbed and coated on the surface of the silicon oxide wafer, wherein the concentration of the silver nanowire water dispersion is 0.167 mg / mL, the length is 20 μm, and the diameter is 30 nm; the silver nanowires are evenly covered on the surface of the silicon oxide wafer by using a coating machine, and the coating machine has two speeds, speed 1 is 300 rpm, 10 s, and speed 2 is 2500 rpm, 25 s; high-purity nitrogen is used to blow dry the solution on the surface of the silicon oxide wafer, and then the silver nanowire solution is spin coated again to obtain a silicon oxide wafer evenly covered with silver nanowires.

4. The method for preparing a nanowire memristor according to claim 3, characterized in that: Before spin coating the nanowires, patterns are overlaid on the channels of the silicon oxide wafer between the planar electrodes to obtain a silicon oxide wafer with a channel pattern.

5. The method for preparing a nanowire memristor according to claim 1, characterized in that: The method uses an atomic layer deposition process to deposit an aluminum oxide packaging layer on the silicon oxide wafer. The specific process is: using an atomic layer deposition process to deposit an aluminum oxide packaging layer with a thickness of 5 nm on the silicon oxide wafer, and the deposition temperature is 70°C.

6. The method for preparing a nanowire memristor according to claim 1, characterized in that: The planar electrode is prepared by thermal evaporation deposition: 10 nm of chromium and 50 nm of gold are evaporated on a silicon oxide wafer having an electrode pattern.

7. A nanowire memristor, prepared by any one of the methods of claims 1-6, characterized in that: It includes a silicon oxide wafer, a planar electrode, a nanowire layer and a packaging layer; wherein the planar electrodes are located at both ends of the silicon oxide wafer, the nanowire layer is spin-coated between the two planar electrodes, and the nanowires present a quasi-anisotropic arrangement, and the packaging layer covers the nanowire layer.

8. The nanowire memristor according to claim 7, characterized in that: The nanowires are silver nanowires, and the planar electrodes are made of chromium and gold.

9. The nanowire memristor according to claim 7, characterized in that: The encapsulation layer is an aluminum oxide encapsulation layer.

10. The nanowire memristor according to claim 7, characterized in that: The electrode line width of the silver nanowire memristor is 50μm and the electrode spacing is 100μm.

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