Zener diode and manufacturing method thereof

Abstract

The invention discloses a voltage stabilizing diode and a manufacturing method thereof, and the voltage stabilizing diode comprises the components of a substrate which is provided with a first doped region and is provided with an epitaxial layer; an STI structure is formed in the epitaxial layer, second doped regions are formed in the epitaxial layer at two sides of the STI structure, first heavily doped regions are formed in the second doped regions, second heavily doped regions are formed in an epitaxial layer region surrounded by the STI structure, and third doped regions are formed in the epitaxial layer below the second heavily doped regions; a fourth doped region is formed between the second heavily doped region and the third doped region; wherein the depth of the fourth doped region is smaller than that of the third doped region; the conduction types of impurities doped in the first doped region, the second doped region, the first heavily doped region and the third doped region are the same; the conduction types of impurities doped in the second heavily doped region and the fourth doped region are the same, and the conduction types of impurities doped in the second heavily doped region and the first doped region are different.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a voltage stabilizing diode and a method for manufacturing the same. Background Art

[0002] Zener diode (also known as "Zener diode") is a surface contact crystal diode that uses its avalanche breakdown effect. It is widely used in voltage stabilization power supplies as a reference voltage source or a protection diode in a cross-point protection circuit. It is also often used as a voltage regulator in a mortgage circuit. It can also be used as a surge circuit, overvoltage protection, arc suppression, and one-shot series voltage stabilization. It can be used to suppress transient interference and extremely high-speed pulse interference.

[0003] refer to Figure 1 , which shows a cross-sectional schematic diagram of a voltage regulator diode provided in the related art. For example, Figure 1 As shown, a buried layer 111 is formed in the substrate 110, an epitaxial layer 112 is formed on the substrate 110, a shallow trench isolation (STI) structure 113 is formed in the epitaxial layer 112, a well region 1011 is formed in the epitaxial layer 112 on both sides of the STI structure 113, a first heavily doped region 1012 is formed in the well region 1011, a second heavily doped region 1013 is formed in the region surrounded by the STI structure 113, and a Zener implantation region 1014 is formed below the second heavily doped region 1013.

[0004] The breakdown voltage of the zener diode is the breakdown voltage of the PN junction (positive negative junction) formed by the second heavily doped region 1013 and the Zener implant 1014. However, the zener diode provided in the related art has the problem of rapid leakage rise and large leakage current. Summary of the invention

[0005] The present application provides a voltage stabilizing diode and a manufacturing method thereof, which can solve the problem of leakage current in the voltage stabilizing diode provided in the related art.

[0006] On the one hand, an embodiment of the present application provides a method for manufacturing a voltage regulator diode, comprising:

[0007] forming a first doped region in a substrate;

[0008] forming an epitaxial layer on the substrate;

[0009] forming an STI structure in the epitaxial layer;

[0010] forming a second doped region in the epitaxial layer on both sides of the STI structure, wherein the conductivity type of the impurities doped in the second doped region is the same as the conductivity type of the impurities doped in the first doped region;

[0011] forming a first heavily doped region in the second doped region, wherein the conductivity type of the impurities doped in the first heavily doped region is the same as the conductivity type of the impurities doped in the first doped region;

[0012] forming a second heavily doped region in the epitaxial layer region surrounded by the STI structure, wherein the conductivity type of the impurities doped in the second heavily doped region is different from the conductivity type of the impurities doped in the first doped region;

[0013] A third doping region and a fourth doping region are formed in the epitaxial layer below the second heavily doped region, the fourth doping region is located between the second heavily doped region and the third doping region, the depth of the fourth doping region is less than the depth of the third doping region, the conductivity type of the impurities doped in the third doping region is the same as the conductivity type of the impurities doped in the first doping region, the conductivity type of the impurities doped in the fourth doping region is different from the conductivity type of the impurities doped in the first doping region, and the impurity concentrations doped in the first heavily doped region and the second heavily doped region are greater than the impurity concentrations doped in other doping regions.

[0014] In some embodiments, forming a first doped region in the substrate includes:

[0015] Ion implantation is performed, and the first doping region is formed in the substrate by thermal annealing.

[0016] In some embodiments, forming the STI structure in the epitaxial layer includes:

[0017] forming a groove in the epitaxial layer, wherein the groove is annular when viewed from a top view;

[0018] The groove is filled with silicon dioxide to form the STI structure.

[0019] In some embodiments, filling silicon dioxide in the groove to form the STI structure includes:

[0020] forming a first silicon dioxide layer on the surface of the epitaxial layer and the groove by a thermal oxidation process;

[0021] depositing a second silicon dioxide layer by a HDP CVD process;

[0022] A planarization process is performed to remove the first silicon dioxide layer and the second silicon dioxide layer outside the groove, and the first silicon dioxide layer and the second silicon dioxide layer inside the groove form the STI structure.

[0023] In some embodiments, forming a second doped region in the epitaxial layer on both sides of the STI structure includes:

[0024] Covering the epitaxial layer with a photoresist by a photolithography process to expose a region corresponding to the second doped region;

[0025] Ion implantation is performed, and the second doping region is formed in the epitaxial layer through an annealing push-pull process, and then the photoresist is removed.

[0026] In some embodiments, forming a third doped region and a fourth doped region in the epitaxial layer below the second heavily doped region includes:

[0027] Covering the epitaxial layer with photoresist by a photolithography process to expose the area corresponding to the third doping region;

[0028] Two ion implantations of different conductivity types are performed in sequence, and the third doping region and the fourth doping region are formed by an annealing push-pull process, and then the photoresist is removed.

[0029] On the other hand, an embodiment of the present application provides a voltage stabilizing diode, including:

[0030] A substrate, wherein a first doping region is formed in the substrate, and an epitaxial layer is formed on the substrate;

[0031] An STI structure is formed in the epitaxial layer, a second doped region is formed in the epitaxial layer on both sides of the STI structure, a first heavily doped region is formed in the second doped region, a second heavily doped region is formed in the epitaxial layer region surrounded by the STI structure, a third doped region is formed in the epitaxial layer below the second heavily doped region, and a fourth doped region is formed between the second heavily doped region and the third doped region;

[0032] Among them, the depth of the fourth doping region is less than the depth of the third doping region; the conductivity type of the impurities doped in the first doping region, the conductivity type of the impurities doped in the second doping region, the conductivity type of the impurities doped in the first heavily doped region and the conductivity type of the impurities doped in the third doping region are the same; the conductivity type of the impurities doped in the second heavily doped region is the same as the conductivity type of the impurities doped in the fourth doping region, and the conductivity type of the impurities doped in the second heavily doped region is different from the conductivity type of the impurities doped in the first doping region; the impurity concentrations doped in the first heavily doped region and the second heavily doped region are greater than the impurity concentrations doped in other doping regions.

[0033] The technical solution of this application has at least the following advantages:

[0034] By setting a doping region with the same conductivity type as the heavily doped region in the PN junction formed by the heavily doped region of the Zener diode and the Zener doped region therebelow, the leakage current problem of the Zener diode is improved, and the reliability of the device product is improved to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 is a cross-sectional schematic diagram of a voltage regulator diode provided in the related art;

[0037] Figure 2 is a flow chart of a method for manufacturing a voltage regulator diode provided by an exemplary embodiment of the present application;

[0038] Figures 3 to 7 It is a schematic diagram of the manufacturing process of a voltage regulator diode provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0039] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0041] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0042] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0043] refer to Figure 2 , which shows a flow chart of a method for manufacturing a voltage regulator diode provided by an exemplary embodiment of the present application, such as Figure 2 As shown, the method includes:

[0044] Step S1, forming a first doped region in a substrate.

[0045] refer to Figure 3 , which shows a cross-sectional schematic diagram after the first doping region is formed in the substrate. Figure 3 As shown, after ion implantation, a first doping region 211 is formed in the substrate 210 by thermal annealing. The conductivity type of the impurities doped in the first doping region 211 is different from the conductivity type of the impurities doped in the substrate 210.

[0046] Step S2, forming an epitaxial layer on the substrate.

[0047] Step S3, forming an STI structure in the epitaxial layer.

[0048] refer to Figure 4 , which shows a cross-sectional schematic diagram after the STI structure is formed in the epitaxial layer. Figure 4 As shown, an epitaxial layer 212 can be formed on a substrate 210 by an epitaxial growth process. The conductivity type of the impurities doped in the epitaxial layer 212 is different from the conductivity type of the impurities doped in the substrate 210. A groove (the depth of the groove is 2000 angstroms) can be formed in the epitaxial layer 212 by etching through a photolithography process. to 4000 angstroms) (the groove is a ring shape when viewed from a top view); and silicon dioxide is filled in the groove to form an STI structure 213.

[0049] Among them, a first silicon dioxide layer can be formed on the surface of the epitaxial layer and the groove by a thermal oxidation process, a second silicon dioxide layer can be deposited by a high-density plasma chemical vapor deposition (HDP CVD) process, and a planarization process (for example, a chemical mechanical polishing (CMP) process) can be performed to remove the first silicon dioxide layer and the second silicon dioxide layer outside the groove, and the first silicon dioxide layer and the second silicon dioxide layer in the groove form an STI structure.

[0050] Step S4, forming a second doping region in the epitaxial layer on both sides of the STI structure, wherein the conductivity type of the impurities doped in the second doping region is the same as the conductivity type of the impurities doped in the first doping region.

[0051] refer to Figure 5 , which shows a cross-sectional schematic diagram after the second doping region is formed. Figure 4 As shown, photoresist can be covered on the epitaxial layer 212 by a photolithography process to expose the area corresponding to the second doped region 212; ion implantation is performed, and the second doped region 2011 is formed in the epitaxial layer 212 by an annealing push-pull process, and then the photoresist is removed.

[0052] Step S5, forming a first heavily doped region in the second doped region, wherein the conductivity type of the impurities doped in the first heavily doped region is the same as the conductivity type of the impurities doped in the first doped region.

[0053] Step S6, forming a second heavily doped region in the epitaxial layer region surrounded by the STI structure, wherein the conductivity type of the impurities doped in the second heavily doped region is different from the conductivity type of the impurities doped in the first doped region.

[0054] refer to Figure 6 , which shows a cross-sectional schematic diagram after forming the second heavily doped region. Figure 6 As shown, photoresist can be covered on the epitaxial layer 212 through a photolithography process to expose the area corresponding to the first heavily doped region 2012; ion implantation is performed to form the first heavily doped region 2012 in the epitaxial layer 212 through an annealing push-pull process, and then the photoresist is removed; photoresist is covered on the epitaxial layer 212 through a photolithography process to expose the area corresponding to the second heavily doped region 2013; ion implantation is performed to form the second heavily doped region 2013 in the epitaxial layer 212 through an annealing push-pull process, and then the photoresist is removed.

[0055] Step S7, forming a third doping region and a fourth doping region in the epitaxial layer below the second heavily doped region, wherein the fourth doping region is located between the second heavily doped region and the third doping region.

[0056] refer to Figure 7 , which shows a cross-sectional schematic diagram after forming the third doping region and the fourth doping region. Figure 7 As shown, a photoresist can be covered on the epitaxial layer 212 by a photolithography process to expose the area corresponding to the third doping region 2014; two ion implantations of different conductivity types are performed in sequence, and the third doping region 2014 and the fourth doping region 2015 are formed by an annealing push-pull process, and then the photoresist is removed. The fourth doping region 2015 is formed using a mask template of the third doping region 2014, and no additional photolithography process is required.

[0057] Among them, the third doping region 2014 is the Zener doping region of the device, the depth of the fourth doping region 2015 is less than the depth of the third doping region 2014, the conductivity type of the impurities doped in the third doping region 2014 is the same as the conductivity type of the impurities doped in the first doping region 211, the conductivity type of the impurities doped in the fourth doping region 2015 is different from the conductivity type of the impurities doped in the first doping region 211, and the impurity concentration doped in the first heavily doped region 2012 and the second heavily doped region 2013 is greater than the impurity concentration doped in other doping regions.

[0058] To summarize, in the embodiments of the present application, in the manufacturing process of the Zener diode, after defining the Zener doping region by a photolithography process, before ion implantation is performed to form the Zener doping region, ion implantation of opposite conductivity type is performed first, and then ion implantation of the Zener doping region is performed, thereby forming a doping region with the same conductivity type as the heavily doped region between the heavily doped region of the Zener diode and the Zener doping region therebelow, thereby improving the leakage current problem of the Zener diode and improving the reliability of the device product to a certain extent.

[0059] refer to Figure 7 , which shows a cross-sectional schematic diagram of a voltage regulator diode provided by an exemplary embodiment of the present application, the voltage regulator diode can be Figure 2 The embodiment is manufactured, and the voltage stabilizing diode comprises:

[0060] The substrate 210 has a first doping region 211 formed therein and an epitaxial layer 212 formed thereon.

[0061] An STI structure 213 is formed in the epitaxial layer 212, a second doped region 2011 is formed in the epitaxial layer 212 on both sides of the STI structure 213, a first heavily doped region 2012 is formed in the second doped region 2011, a second heavily doped region 2013 is formed in the epitaxial layer 212 area surrounded by the STI structure 213, a third doped region 2014 is formed in the epitaxial layer 212 below the second heavily doped region 2013, and a fourth doped region 2015 is formed between the second heavily doped region 2013 and the third doped region 2014.

[0062] Among them, the depth of the fourth doping region 2015 is less than the depth of the third doping region 2014; the conductivity type of the impurities doped in the first doping region 211, the conductivity type of the impurities doped in the second doping region 2011, the conductivity type of the impurities doped in the first heavily doped region 2012 and the conductivity type of the impurities doped in the third doping region 2014 are the same; the conductivity type of the impurities doped in the substrate 210, the conductivity type of the impurities doped in the epitaxial layer 212, the conductivity type of the impurities doped in the second heavily doped region 2013 and the conductivity type of the impurities doped in the fourth doping region 2015 are the same, and the conductivity type of the impurities doped in the second heavily doped region 2013 is different from the conductivity type of the impurities doped in the first doping region 211; the impurity concentration doped in the first heavily doped region 2012 and the second heavily doped region 2013 is greater than the impurity concentration doped in other doping regions.

[0063] When the voltage regulator diode is working, the first heavily doped region 2012 and the first heavily doped region 2013 serve as electrodes of the device, the first doped region 211 is a buried doped region, the second doped region 2011 is a well region, and the third doped region 2014 is a Zener doped region.

[0064] When the impurities doped into the first doping region 211, the second doping region 2011, the first heavily doped region 2012 and the third doping region 2014 are N-type impurities, the impurities doped into the substrate 210, the epitaxial layer 212, the second heavily doped region 2013 and the fourth doping region 2015 are P-type impurities; when the impurities doped into the first doping region 211, the second doping region 2011, the first heavily doped region 2012 and the third doping region 2014 are P-type impurities, the impurities doped into the substrate 210, the epitaxial layer 212, the second heavily doped region 2013 and the fourth doping region 2015 are N-type impurities.

[0065] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for manufacturing a voltage regulator diode, characterized in that: include: forming a first doped region in a substrate; forming an epitaxial layer on the substrate; forming an STI structure in the epitaxial layer; forming a second doped region in the epitaxial layer on both sides of the STI structure, wherein the conductivity type of the impurities doped in the second doped region is the same as the conductivity type of the impurities doped in the first doped region; forming a first heavily doped region in the second doped region, wherein the conductivity type of the impurities doped in the first heavily doped region is the same as the conductivity type of the impurities doped in the first doped region; forming a second heavily doped region in the epitaxial layer region surrounded by the STI structure, wherein the conductivity type of the impurities doped in the second heavily doped region is different from the conductivity type of the impurities doped in the first doped region; A third doping region and a fourth doping region are formed in the epitaxial layer below the second heavily doped region, the fourth doping region is located between the second heavily doped region and the third doping region, the depth of the fourth doping region is less than the depth of the third doping region, the conductivity type of the impurities doped in the third doping region is the same as the conductivity type of the impurities doped in the first doping region, the conductivity type of the impurities doped in the fourth doping region is different from the conductivity type of the impurities doped in the first doping region, and the impurity concentrations doped in the first heavily doped region and the second heavily doped region are greater than the impurity concentrations doped in other doping regions.

2. The method according to claim 1, characterized in that The forming of a first doped region in the substrate comprises: Ion implantation is performed, and the first doping region is formed in the substrate by thermal annealing.

3. The method according to claim 1, characterized in that The forming of the STI structure in the epitaxial layer comprises: forming a groove in the epitaxial layer, wherein the groove is annular when viewed from a top view; The groove is filled with silicon dioxide to form the STI structure.

4. The method according to claim 3, characterized in that The step of filling the groove with silicon dioxide to form the STI structure comprises: forming a first silicon dioxide layer on the surface of the epitaxial layer and the groove by a thermal oxidation process; depositing a second silicon dioxide layer by a HDP CVD process; A planarization process is performed to remove the first silicon dioxide layer and the second silicon dioxide layer outside the groove, and the first silicon dioxide layer and the second silicon dioxide layer inside the groove form the STI structure.

5. The method according to claim 1, characterized in that The forming of the second doped region in the epitaxial layer on both sides of the STI structure comprises: Covering the epitaxial layer with a photoresist by a photolithography process to expose a region corresponding to the second doped region; Ion implantation is performed, and the second doping region is formed in the epitaxial layer through an annealing push-pull process, and then the photoresist is removed.

6. The method according to claim 1, characterized in that The forming of a third doped region and a fourth doped region in the epitaxial layer below the second heavily doped region comprises: Covering the epitaxial layer with photoresist by a photolithography process to expose the area corresponding to the third doping region; Two ion implantations of different conductivity types are performed in sequence, and the third doping region and the fourth doping region are formed by an annealing push-pull process, and then the photoresist is removed.

7. A voltage stabilizing diode, characterized in that: include: A substrate, wherein a first doping region is formed in the substrate, and an epitaxial layer is formed on the substrate; An STI structure is formed in the epitaxial layer, a second doped region is formed in the epitaxial layer on both sides of the STI structure, a first heavily doped region is formed in the second doped region, a second heavily doped region is formed in the epitaxial layer region surrounded by the STI structure, a third doped region is formed in the epitaxial layer below the second heavily doped region, and a fourth doped region is formed between the second heavily doped region and the third doped region; Among them, the depth of the fourth doping region is less than the depth of the third doping region; the conductivity type of the impurities doped in the first doping region, the conductivity type of the impurities doped in the second doping region, the conductivity type of the impurities doped in the first heavily doped region and the conductivity type of the impurities doped in the third doping region are the same; the conductivity type of the impurities doped in the second heavily doped region is the same as the conductivity type of the impurities doped in the fourth doping region, and the conductivity type of the impurities doped in the second heavily doped region is different from the conductivity type of the impurities doped in the first doping region; the impurity concentrations doped in the first heavily doped region and the second heavily doped region are greater than the impurity concentrations doped in other doping regions.

Images