Apparatus and method for distributing and storing write data in multiple memory regions

Abstract

A memory system includes a memory device and a memory controller. The storage device includes a first memory region to store a plurality of data entries, a second memory region to store parity entries associated with the plurality of data entries, a third memory region to store at least one partial parity entry, the at least one partial parity entry corresponding to at least one subset, each subset includes a portion of a plurality of data entries. The memory controller generates a first partial parity entry corresponding to a first sub-group among the at least one sub-group to store the first partial parity entry in a third memory region, generates a second partial parity entry corresponding to a second sub-group among the at least one sub-group, the first portion parity entry is read from the third memory region and a logical operation is performed on the first portion parity entry and the second portion parity entry to generate a parity entry.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0160999, filed on November 20, 2023, the entire disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments of the present disclosure described herein relate to a memory system or a memory device and an operation method thereof, and more particularly, to an apparatus and a method for distributing and programming write data entries in multiple regions of a memory device. Background Art

[0004] A data processing system includes a memory system or a data storage device. The data processing system can be developed to store more data in the data storage device, store data in the data storage device faster, and read data stored in the data storage device faster. The memory system or the data storage device can include non - volatile memory cells and / or volatile memory cells for storing data. To improve data security, data can be distributed and stored in multiple regions of a memory device. Summary of the Invention

[0005] Embodiments of the present disclosure can provide a memory system including a memory device, a data processing system including the memory system, and an operation process or method, which can reduce the operation complexity and performance degradation of the memory system, thereby quickly and reliably processing data into the memory device, and further improving the use efficiency of the memory device.

[0006] Embodiments of the present disclosure can provide an apparatus or a method for distributing write data entries over multiple regions of a memory device to improve the reliability or security of data stored in the memory device.

[0007] A memory system according to an embodiment of the present disclosure can reduce internal resources for generating parity check entries associated with multiple data entries distributed in multiple regions in a data programming operation for programming many write data entries in a memory device.

[0008] A memory system according to an embodiment of the present disclosure can back up partial parity check entries corresponding to smaller - unit data entries to a non - volatile memory device, thereby effectively recovering partial stored data entries in the event of, for example, a sudden power - off (SPO).

[0009] Embodiments of the present disclosure may provide a memory system, including: a memory device having a first memory area, a second memory area, and a third memory area, where the first memory area is configured to store a plurality of data entries, the second memory area is configured to store parity entries corresponding to the plurality of data entries, the third memory area is configured to store at least one partial parity entry, and the at least one partial parity entry corresponds to at least one subgroup, and each subgroup includes a part of the plurality of data entries; and a memory controller configured to generate a first partial parity entry corresponding to a first subgroup among the at least one subgroup to store the first partial parity entry in the third memory area, generate a second partial parity entry corresponding to a second subgroup among the at least one subgroup, read the first partial parity entry from the third memory area, and perform a logical operation on the first partial parity entry and the second partial parity entry to generate a parity entry.

[0010] The memory controller may be configured to invalidate at least one partial parity entry stored in the third memory area after storing the parity entry in the second memory area.

[0011] The first memory area may be distributed on a plurality of memory dies. The physical block address of the third memory area may be different from the physical block addresses of the first memory area and the second memory area.

[0012] The first memory area and the second memory area may include memory blocks having memory cells configured to store multi-bit data, while the third memory area includes memory blocks having memory cells configured to store single-bit data.

[0013] The memory controller may repeatedly perform an operation of generating and updating at least one partial parity entry for at least one subgroup in a preset unit including at least one subgroup. The size of the partial parity entry stored in the third memory area may be the same as the size of the parity entry stored in the second memory area.

[0014] When the number of the first partial parity entries is 1 / N of the total number of subgroups associated with the plurality of data entries, the memory controller may read the first partial parity entry from the third memory area, where N is a natural number of 2 or greater.

[0015] The logical operation may be an exclusive OR (XOR) operation.

[0016] The memory controller may include a parity generation circuit. The parity generation circuit may include: an operation circuit configured to perform a logical operation; and a buffer coupled to the operation circuit, and the size of the buffer corresponds to the size of the subgroup.

[0017] The third memory region may be adjacent to the first memory region.

[0018] The third memory region may be a dedicated space for storing partial parity entries.

[0019] Another embodiment of the present disclosure may provide a memory controller coupled to a memory device. The memory controller may: divide a plurality of data entries into a plurality of subgroups; generate a first partial parity entry corresponding to a first subgroup among the plurality of subgroups to store the first partial parity entry in the memory device; generate a second partial parity entry corresponding to a second subgroup among the plurality of subgroups; read the first partial parity entry stored in the memory device; perform a logical operation on the first partial parity entry and the second partial parity entry to generate a parity entry associated with the plurality of data entries, and store the parity entry in the memory device.

[0020] After storing the parity entry in the memory device, the memory controller may invalidate the first partial parity entry and the second partial parity entry.

[0021] The first partial parity entry, the second partial parity entry, and the parity entry may be generated by a parity generation circuit included in the memory controller. The parity generation circuit may include a buffer, and the size of the buffer corresponds to the size of each of the plurality of subgroups.

[0022] The size of the subgroup may correspond to K pages set in the memory device, where K is a natural number.

[0023] The memory controller may repeatedly perform operations of generating and updating partial parity entries corresponding to the plurality of subgroups in a preset unit including at least one subgroup. The size of each partial parity entry stored in the third memory region may be the same as the size of the parity entry stored in the second memory region.

[0024] When the number of the first partial parity entries is 1 / N of the total number of subgroups associated with the plurality of data entries, the memory controller may read the first partial parity entry from the third memory region, where N is a natural number greater than or equal to 2.

[0025] Another embodiment of the present disclosure may provide a memory system, including: a memory device and a memory controller. The memory device includes a plurality of memory regions, and the plurality of memory regions include a plurality of memory dies, a plurality of memory planes, or a plurality of memory blocks. A plurality of data entries and parity entries associated with the plurality of data entries are distributed and stored in the plurality of memory regions to recover uncorrectable error correction codes (UECCs). The memory controller is configured to divide the plurality of data entries into a plurality of subgroups, generate first partial parity entries corresponding to a first subgroup among the plurality of subgroups to store the first partial parity entries in the memory device, generate second partial parity entries corresponding to a second subgroup among the plurality of subgroups, read the first partial parity entries stored in the memory device, and perform a logical operation on the first partial parity entries and the second partial parity entries to generate parity entries and store the parity entries in the memory device.

[0026] The plurality of memory regions may be coupled to the memory controller via a plurality of channels.

[0027] In the memory system, each of the plurality of subgroups may include data stored in memory cells indicated by the same word line address and the same cell string address in the plurality of memory regions.

[0028] After storing the parity entries in the memory device, the memory controller may invalidate the first partial parity entries and the second partial parity entries. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The description herein refers to the accompanying drawings, in which like reference numerals denote like components throughout the drawings.

[0030] Figure 1 is a diagram showing a configuration of a data storage device according to an embodiment of the present disclosure.

[0031] Figure 2 is a diagram for describing a method of operating a memory system according to an embodiment of the present disclosure.

[0032] Figure 3 is a diagram for describing an operation of a first part in steps performed within a memory system according to another embodiment of the present disclosure.

[0033] Figure 4 is a diagram for describing an operation of a second part in steps performed within a memory system according to another embodiment of the present disclosure.

[0034] Figure 5 is a diagram for describing an operation of a third part in steps performed within a memory system according to another embodiment of the present disclosure.

[0035] Figure 6 is a diagram showing the detailed configuration of the parity generation engine as shown in Figure 1 the one shown in the above.

[0036] Figure 7 is a diagram showing the configuration of a redundant array of independent disks (RAID).

[0037] Figure 8 is a diagram for describing how multiple data entries are distributed and stored in a memory device according to an embodiment of the present disclosure.

[0038] Figure 9 is a diagram showing the configuration of a memory system according to another embodiment of the present disclosure.

[0039] Figure 10 is a diagram showing the configuration of a memory system according to another embodiment of the present disclosure. Detailed Description of the Invention

[0040] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged in different ways to form other embodiments, which may be variations of any disclosed embodiment.

[0041] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in "one embodiment", "example embodiment", "embodiment", "another embodiment", "some embodiments", "multiple embodiments", "other embodiments", "alternative embodiments", etc. are intended to mean that any such feature is included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

[0042] In the present disclosure, the terms "comprise", "comprises", "include" and "includes" are open-ended. As used in the appended claims, these terms specify the presence of the recited elements, but do not preclude the presence or addition of one or more other elements. The terms of the claims do not preclude the device from including additional components, such as interface units, circuits, etc.

[0043] In this disclosure, various units, circuits, or other components may be described or claimed as "configured to" perform one or more tasks. In such contexts, "configured to" is used to denote structure by indicating that the block / unit / circuit / component includes the structure (e.g., circuitry) that performs one or more tasks during operation. Thus, even when the block / unit / circuit / component is not currently operating, such as not being turned on or activated, it can be said that the specified block / unit / circuit / component is configured to perform the task. The block / unit / circuit / component used in conjunction with "configured to" language includes hardware, circuitry, memory storing program instructions executable to implement the operations, and the like. Additionally, "configured to" can include general structures, such as general-purpose circuitry, that are manipulated by software and / or firmware, e.g., an FPGA or a general-purpose processor that runs software in a manner capable of performing the relevant tasks. "Configured to" can also include adjusting a manufacturing process, such as a semiconductor manufacturing facility, to fabricate a device suitable for implementing or performing one or more tasks, such as an integrated circuit.

[0044] As used in this disclosure, the terms "machine", "circuit", or "logic" refer to all of the following: (a) pure hardware circuit implementations, such as implementations of only analog and / or digital circuits; and (b) combinations of circuits with software and / or firmware, such as, as applicable: (i) combinations of processors or (ii) portions of processors / software, including digital signal processors, software, and memory, that work together to enable a device such as a mobile phone or a server to perform various functions; and (c) circuits, such as a microprocessor or a portion of a microprocessor, that require software or firmware to operate, even if the software or firmware is not physically present. This definition of "machine", "circuit", or "logic" applies to all uses of the term in this application, including in any claims. As a further example, as used in this application, the terms "machine", "circuit", or "logic" also encompass implementations that include only one processor or multiple processors or portions of processors and their attendant software and / or firmware. The terms "machine", "circuit", or "logic" also encompass, for example (if applicable to a particular claim element), integrated circuits for storage devices.

[0045] As used herein, the terms "first", "second", "third", etc. are used as labels for the nouns preceding them and do not denote any type of ordering, such as spatial, temporal, logical, etc. The terms "first" and "second" do not necessarily mean that the first value must be written before the second value. Additionally, although these terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element having the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0046] In addition, the term "based on" is used to describe one or more factors that affect a determination. This term does not exclude other factors that may affect the determination. That is, the determination may be based solely on these factors, or at least in part on these factors. Consider the phrase "determine A based on B". Although in this case, B is one factor that affects the determination of A, such a phrase does not exclude the determination of A also being based on C. In other cases, A may be determined solely based on B.

[0047] Here, a data entry, an entry of data, an item of data, or a data item may be a bit sequence. For example, a data entry may include the content of a file, a part of a file, a page in a memory, an object in object-oriented programming, a digital message, a part of a digital scanned image, a video or audio signal, metadata, or any other entity that can be represented by a bit sequence. According to an embodiment, a data entry may include discrete objects. According to another embodiment, a data entry may include an information unit that is processed or disposed of for data input / output operations. According to another embodiment, a data entry may include an information unit within a transmission data packet between two different components.

[0048] Embodiments will now be described with reference to the accompanying drawings, where like reference numerals indicate like elements.

[0049] Figure 1 is a diagram showing the configuration of a data storage device according to an embodiment of the present disclosure.

[0050] Referring to Figure 1 , the data storage device may include a programming control circuit 190 and a memory device 150. The data storage device is designed for distributed storage of data and may include various components. An example of a data storage device is a memory system including volatile memory cells and non-volatile memory cells. The memory system may include a programming control circuit 190 and a memory device 150. The memory system will be described later with reference to Figure 9 and Figure 10 Description of the memory system.

[0051] The memory device 150 may include a plurality of memory regions 122, 124, 126. The first memory region 122 may include space allocated for storing data entries (or user data) WDn. The second memory region 124 may include space allocated for storing parity entries WPi generated based on the data entries WDn. The third memory region 126 is space allocated for storing partial parity entries PPk generated by the programming control circuit 190 during the process of storing the data entries (or user data) WDn in the memory device 150.

[0052] According to an embodiment, the plurality of memory regions 122, 124, 126 may be part of a cell array including non-volatile memory cells. The cell array may be formed in a two-dimensional or three-dimensional space.

[0053] According to an embodiment, each of the plurality of memory regions 122, 124, 126 may include at least one memory block. Here, a memory block may refer to a group including a plurality of memory cells, and the remaining data of these memory cells is erased by the same erase operation.

[0054] According to an embodiment, at least a portion of the first memory region 122 and the second memory region 124 among the plurality of memory regions 122, 124, 126 may be connected to the same word line. However, the third memory region 126 is provided at a different position from the first memory region 122 and the second memory region 124 (e.g., a different memory block, a different word line, or a different memory die).

[0055] According to an embodiment, the first memory region 122 and the second memory region 124 among the plurality of memory regions 122, 124, 126 may include at least one memory block that includes a plurality of memory cells, and each memory cell is controlled to store multiple bits of data. However, the third memory region 126 may include at least one memory block that includes a plurality of memory cells, and each memory cell is controlled to store single-bit data. Various embodiments of the plurality of memory regions 122, 124, 126 will be described later with reference to Figures 3 to 10 describe various embodiments of the plurality of memory regions 122, 124, 126.

[0056] The programming control circuit 190 may perform an operation of storing a data entry (or user data) WDn in the memory device 150. The data entry (or user data) WDn may be write data transmitted from an external device or data generated during an internal operation of the memory system. The programming control circuit 190 may generate a partial parity entry PPk before completely storing the data entry (or user data) WDn in the memory device 150. A parity generation engine (e.g., a parity generation circuit) 510 included in the programming control circuit 190 may generate a partial parity entry PPk corresponding to some of the data entry (or user data) WDn. The parity generation engine 510 will be described later with reference to Figure 6 be described.

[0057] The parity generation engine 510 can generate partial parity entries PPk by performing logical operations on some of the data entries (or user data) WDn. According to an embodiment, the logical operation may include an exclusive OR (XOR) operation. The data entries (or user data) WDn and the parity entries WPi can be distributed and stored in multiple memory regions, such as the first memory region 122 and the second memory region 124. If some of the multiple memory regions fail and the data stored therein cannot be read, or if some of the data entries (or user data) WDn are in error, the unobtainable data entries or the data entries in error can be recovered and restored based on the parity entries WPi. The use of the parity entries WPi will be described later with reference to Figure 7 be described.

[0058] In a typical memory system, parity entries can be generated for multiple data entries, and then the parity entries and the multiple data entries can be stored in a memory device. How many data entries are associated with one parity entry can be determined according to the characteristics of the memory device or the performance of the memory system. For example, a single parity entry can be generated for 32, 64, 128, or 256 data entries. In this case, the multiple data entries used in the process of generating a single parity entry can be temporarily stored in a buffer used or occupied by the parity generation device. As the number of data entries corresponding to one parity entry increases, the parity generation device can temporarily store more data entries.

[0059] According to an embodiment, the size of the data entries constituting the parity group can be set based on the number of cell strings. For example, the parity group can include the data entries stored in one cell string (1-String XOR scheme), and 3-bit data can be stored in the memory cells included in the first memory region 122. In this case, the size of the buffer occupied by the parity generation engine 510 can be approximately 288 KB (= 16 KB page size × 3 bits per memory cell × 3 parity groups × 2 cores). In the case where the parity group includes the data entries stored in 16 cell strings (16-String XOR scheme), the size of the parity generation engine 510 can be approximately 4.6 MB.

[0060] If the size of the buffer used by the parity generation engine 510 in the memory system is large, the size of the buffer that can be used by other components in the memory system may be reduced. Because there is not enough memory space, the size of the volatile memory (e.g., the memory used as a buffer, cache, etc.) that operates at high speed in the memory system may be limited. If most of the volatile memory is allocated for parity generation, the amount of other volatile memory allocated for other operations will be reduced. This may reduce the data input / output performance of the memory system and reduce the efficiency of resource allocation and use within the memory system.

[0061] In Figure 1 the data storage device described in, to reduce the size of the buffer occupied and used for parity generation operations in the volatile memory, the parity generation engine 510 may generate partial parity entries PPk. For example, in the process of generating one parity entry WPi for 256 data entries, the parity generation engine 510 may generate multiple partial parity entries.

[0062] The programming control circuit 190 may set or establish 256 data entries as one parity group. That is, one parity group may include 256 data entries and one parity entry corresponding to the 256 data entries. The programming control circuit 190 may divide the 256 entries belonging to one parity group into multiple subgroups and generate partial parity entries for each subgroup. For example, if the 256 entries are divided into 16 subgroups, one subgroup may include 16 data entries. The parity generation engine 510 in the programming control circuit 190 may generate 16 partial parity entries corresponding to the 16 subgroups, and then temporarily store the 16 partial parity entries in the third memory area 126 in the memory device 150. Thereafter, the parity generation engine 510 in the programming control circuit 190 may perform a logical operation on the 16 parity entries stored in the third memory area 126 to generate one parity entry for the 256 data entries.

[0063] Since the parity generation engine 510 generates partial parity entries for 16 data entries, it is not necessary to temporarily store all 256 data entries. The parity generation engine 510 may operate using a buffer that stores 16 data entries to generate partial parity entries. For example, even if the number of data entries belonging to one parity group increases to 512 or 1024, the parity generation engine 510 may only use a buffer corresponding to the size of each subgroup smaller than the parity group.

[0064] In addition, in embodiments of the present disclosure, partial parity entries are generated for each subgroup that is part of a plurality of data entries, and the partial parity entries belonging to the subgroup can be stored in the memory device 150 including non-volatile memory cells. Thus, the memory system including the memory device can easily recover the data entries belonging to the subgroup that were stored in the memory device 150 before a sudden power outage (SPO) based on the partial parity entries of the subgroup.

[0065] Next, a method in which a memory controller including a programming control circuit 190 and a parity generation engine 510 stores a plurality of data entries in a memory device will be described in more detail.

[0066] Figure 2 is a diagram for describing a method of operating a memory system according to an embodiment of the present disclosure. The memory system may include a memory controller 130 and a memory device 150. The memory controller 130 may include Figure 1 the programming control circuit 190 and the parity generation engine 510 described in. This will be described later with reference to Figure 9 and Figure 10 Other configurations and operations of the memory controller 130 and the memory device 150 will be described.

[0067] Referring to Figure 2 , the memory controller 130 may set a plurality of data entries WD[0:N] that constitute a parity group. The memory controller 130 may generate a first partial parity entry PP[0] for the first data entry WD[0], where the first data entry WD[0] is part of the plurality of data entries WD[0:N]. The first data entry WD[0] may be one of a plurality of subgroups belonging to a parity group. According to an embodiment, the first data entry WD[0] may include a plurality of data entries stored in a plurality of memory cells connected to different memory planes or different memory dies having at least one same word line address.

[0068] After generating the first partial parity entry PP[0] for the first data entry WD[0], the memory controller 130 may transmit the first data entry WD[0] and the first partial parity entry PP[0] to the memory device 150. The memory device 150 may store the first data entry WD[0] and the first partial parity entry PP[0].

[0069] The memory controller 130 and the memory device 150 may repeatedly perform operations on at least some subgroups that form a parity group (e.g., the first to the G+1 data entries WD[0:G] among the multiple data entries WD[0:N], where G is a natural number greater than 1 and less than N). For example, generate partial parity entries PP[0:G] for the first to the G+1 data entries WD[0:G], and transmit the partial parity entries PP[0:G] corresponding to the first to the G+1 data entries WD[0:G] to the memory device 150. Then, the memory device 150 may store the transmitted data entries WD[0:G] and the partial parity entries PP[0:G].

[0070] The memory controller 130 may generate other partial parity entries for other subgroups among the multiple data entries WD[0:N] that form a parity group (e.g., the G+2 to the N+1 data entries WD[G+1:N], where N is a natural number greater than G). Partial parity entries may be generated for each subgroup. For example, the memory controller 130 may generate the G+2 partial parity entry PP[G+1] for the G+2 data entry WD[G+1]. In this case, the memory controller 130 may read the first partial parity entry PP[0] previously stored in the memory device 150. The memory controller 130 may perform a logical operation on the first partial parity entry PP[0] and the G+2 data entry WD[G+1] to generate the G+2 partial parity entry PP[G+1].

[0071] After generating the G+2 partial parity entry PP[G+1] for the G+2 data entry WD[G+1] and the first partial parity entry PP[0], the memory controller 130 may transmit the G+2 data entry WD[G+1] and the G+2 partial parity entry PP[G+1] to the memory device 150. The memory device 150 may store the G+2 data entry WD[G+1] and the G+2 partial parity entry PP[G+1].

[0072] Since the first partial parity entry PP[0] has been reflected in the G+2 partial parity entry PP[G+1], the first partial parity entry PP[0] may no longer be needed. That is, after storing the G+2 partial parity entry PP[G+1], the memory controller 130 and the memory device 150 may regard the first partial parity entry PP[0] as invalid data.

[0073] In addition, the memory controller 130 and the memory device 150 may perform the above operations on other subgroups (e.g., the (G + 2)-th to (K + 1)-th data entries WD[G + 1:K] among a plurality of data entries WD[0:N] constituting a parity group). The memory controller 130 may perform operations on each subgroup of the (G + 2)-th to (K + 1)-th data entries WD[G + 1:K]. During the process of calculating partial parity entries (e.g., PP[G + 1]), the partial parity entries (e.g., PP[0]) already stored in the memory device 150 may be read. For example, after the memory controller 130 generates partial parity entries for each subgroup (e.g., the (G + 2)-th to (K + 1)-th data entries WD[G + 1:K], where K is a natural number greater than G and less than N), the partial parity entries PP[0:G] stored in the memory device 150 may be read. The memory controller 130 may perform a logical operation on the partial parity entries generated according to the data entries and the read partial parity entries obtained from the memory device 150 to generate a result of the logical operation (e.g., another partial parity entry PP[G + 1]) and store it in the memory device 150.

[0074] In addition, the memory controller 130 may read the partial parity entries (e.g., PP[G + 1]) already stored in the memory device 150 during the process of generating partial parity entries for each subgroup (e.g., the (K + 2)-th to (N + 1)-th data entries WD[K + 1:N]). For example, the memory controller 130 may perform a logical operation on the (K + 2)-th data entry WD[K + 1], and then perform a logical operation on the result of the logical operation of the (K + 2)-th data entry WD[K + 1] and the read partial parity entry (e.g., PP[G + 1]) to generate the first parity entry WP[0] included in the parity entry WP[i]. Thereafter, the memory device 150 may store the first parity entry WP[0] of the plurality of data entries WD[0:N] constituting a parity group. Subsequently, the memory controller 130 may perform a logical operation to generate partial parity entries for the remaining data entries (e.g., WD[K + 2:N]), and then read the partial parity entries previously stored in the memory device 150. The memory controller 130 may perform a logical operation on the result of the logical operation and the read partial parity entries to generate another parity entry constituting the parity entry WP[i]. After performing the logical operation to generate the parity entry WP[i], the memory controller 130 may transmit the parity entry WP[i] to the memory device 150. The memory device 150 may store the parity entry WP[i] at a preset position (e.g., Figure 1 the second memory area 124 shown).

[0075] As described above, the process of generating the parity entry WP[i] corresponding to a plurality of data entries WD[0:N] belonging to a parity group can be roughly divided into three parts. In the first part, the memory controller 130 can generate at least one partial parity entry by performing a logical operation on the data entries corresponding to each subgroup, and store the generated partial parity entry in the third memory area 126 of the memory device 150.

[0076] In the second part, the memory controller 130 can perform a logical operation on the data entries corresponding to each subgroup, and read the partial parity entry stored in the memory device 150 during the first part. Thereafter, the memory controller 130 can update the partial parity entry by performing a logical operation on the result of the logical operation and the partial parity entry read from the memory device 150. The memory controller 130 can transfer the updated partial parity entry to the memory device 150. The memory device 150 can store the updated partial parity entry in the third memory area 126 of the memory device 150.

[0077] In the third part, the memory controller 130 can perform a logical operation on the data entries corresponding to each subgroup, and read the partial parity entry stored in the memory device 150 during the second part. Thereafter, the memory controller 130 can perform a logical operation on the result of the logical operation and the partial parity entry read from the memory device 150 to update the partial parity entry and generate the parity entry WP[i]. The memory device 150 can store the parity entry WP[i] in the second memory area 124 of the memory device 150.

[0078] According to an embodiment, the size of the partial parity entries is substantially the same as the size of the parity entries. That is, the operation of generating partial parity entries for each subgroup of data entries WD[0:N] belonging to a parity group can be divided based on the size of the parity entries. If the parity group is set to include 24 data entries (e.g., WD[0:23]) and 8 parity entries (e.g., WP[0:7]), each of the first to third parts can be performed for every 8 subgroups. For example, the first part can be performed on the 1st to 8th subgroups WD[0:7], the second part can be performed on the 9th to 16th subgroups WD[8:15], and the third part can be performed on the 17th to 24th subgroups WD[16:23]. If the parity group is set to include 16 data entries, the memory controller 130 can perform only the operations of the first part and the third part without performing the operation of the second part. Additionally, when the parity group is set to include 32 data entries, the memory controller 130 can perform the operations of the first part, the second part twice, and the third part. Each time each operation is repeated, the partial parity entries can be updated. When finally updated, the updated parity entries can become the parity entries of the parity group. Through this process, even if the number of data entries increases, the size of the third memory area 126 for storing the partial parity entries and the size of the buffer for generating the parity entries can be not increased.

[0079] Through the above operations, the memory controller 130 does not need to store multiple data entries WD[0:N] corresponding to the parity entry WP[i] in the buffer. The memory controller 130 can generate partial parity entries only using a buffer having a size corresponding to each subgroup, and then store the partial parity entries in the memory device 150. Thereafter, the memory controller 130 can read the partial parity entries stored in the memory device 150, perform a logical operation on the read partial parity entries, and store the generated parity entry WP[i] in the memory device 150. During the process of storing multiple data entries WD[0:N], the additional operations of storing the partial parity entries in the memory device 150 and reading the stored partial parity entries again may cause a slight increase in the time required to store the multiple data entries WD[0:N] in the memory device 150. However, the memory controller 130 can reduce the size of the buffer for generating the parity entries. The memory controller 130 can improve the resource utilization efficiency in a restricted operating environment, such as a portable device or an ultra-small device, where it is difficult for the memory controller 130 to include a large amount of volatile memory or an interface for operating with a large-capacity volatile memory.

[0080] This will be described below with reference toFigures 3 to 5 A method of storing data entries in a memory device 150 is described. The memory device 150 may store data entries in a manner that includes data stored in 16 unit strings (16-string XOR scheme). A parity entry may be as large as the 16 unit strings. When a parity group includes data entries corresponding to the 1st to 34th word lines (e.g., WL0 to WL33) (i.e., data stored in 272 unit strings), the position where the parity entry is stored may be determined as the memory cells where the 33rd word line WL32 and the 34th word line WL33 are connected in the last memory plane (Plane3) of the last memory die (Die N).

[0081] Figure 3 It is a diagram for describing the operation of the first part executed within a memory system according to another embodiment of the present disclosure. Among them, when partial parity entries of data entries belonging to a parity group are not stored in the memory device 150, the operation of the first part may be executed.

[0082] Referring to Figures 1 to 3 , a first memory area 122 for storing data entries in the memory device 150 may be distributed over N + 1 memory dies Die 0, ……, Die N. Each memory die Die 0, ……, Die N may include four memory planes Plane0, Plane1, Plane2, Plane3. Eight unit strings String0, String1, String2, String3, String4, String5, String6, String7 may be connected to a single word line (e.g., WL0).

[0083] Referring to Figures 1 to 3 , a plurality of data entries included in one parity group may be divided into a plurality of subgroups. For example, the memory controller 130 may set each subgroup based on a page. For example, the first subgroup page0 may include data in a plurality of memory cells (i.e., (N + 1)*4 memory cells) included in the first unit string String0 connected to the first word line WL0 in the four memory planes Plane0, Plane1, Plane2, Plane3 of the N + 1 memory dies Die 0, ……, Die N.

[0084] Figure 1The parity generation engine 510 described in [description] can perform a logical operation (e.g., XOR operation) on the first subgroup page0. The first part of the parity check entries can include the result of the logical operation stored in a buffer (SRAM parity buffer) in the parity generation engine 510 and metadata (Meta). Among them, the metadata (Meta) can include information indicating that the first part of the parity check entries is associated with the first subgroup page0.

[0085] After all the data included in the first subgroup page0 is stored in the first memory area 122, the first part of the parity check entries (Parity buffer 0, Spare 0, Meta 0) can be transferred to the memory device 150. The first part of the parity check entries (Parity buffer 0, Spare 0, Meta 0) can be stored in the third memory area 126.

[0086] The memory controller 130 can generate partial parity check entries for the second subgroup page1, the third subgroup page2, and the fourth subgroup page3, and sequentially store the generated partial parity check entries in the third memory area 126.

[0087] Figure 4 is a diagram for describing the operation of the second part performed within the memory system according to another embodiment of the present disclosure. Among them, when at least some of the partial parity check entries of some data entries belonging to the parity check group have been stored in the memory device 150, the operation of the second part can be performed. For example, referring to Figure 3 , the 16 partial parity check entries of 16 subgroups page0 to page15 stored in a plurality of memory cells connected to the first word line WL0 and the second word line WL1 can be stored in the third memory area 126. Among them, the 16 partial parity check entries corresponding to the 16 subgroups can be 1 / N of the total number of subgroups associated with all data entries (e.g., the data entries WD[0:N] shown in Figure 2 ) stored in the first memory area 122, where N is a natural number of 2 or more.

[0088] Referring to Figure 4 , during the process of generating partial parity check entries for some other data entries belonging to the parity check group, the memory controller 130 can read the partial parity check entries stored in the memory device 150. After performing a logical operation on the subgroup, the memory controller 130 can generate a new partial parity check entry by performing a logical operation on the result of the logical operation and the partial parity check entry read from the memory device 150.

[0089] The memory controller 130 may perform a logical operation (e.g., XOR operation) on page 16 of the 17th subgroup belonging to the parity group (①).

[0090] Subsequently, the memory controller 130 may read the first part of the parity entries (Parity buffer 0, Spare 0, Meta 0) in the third memory area 126 stored in the memory device 150 (②).

[0091] The memory controller 130 may update the first part of the parity entries by performing a logical operation (e.g., XOR operation) on the result of the logical operation on the 17th subgroup page 16 and the first part of the parity entries to generate the 17th part of the parity entries (③).

[0092] The memory controller 130 may store the updated first part of the parity entries (Parity buffer 0, Spare 0, Meta 0), i.e., the 17th part of the parity entries, in the third memory area 126 in the memory device 150 (④).

[0093] Refer to Figure 3 and Figure 4 The memory controller 130 may generate partial parity entries, each partial parity entry for each subgroup, but the number of partial parity entries is limited to 16. The memory controller 130 generates the 17th partial parity entry by performing a logical operation on the result of the logical operation of the seventeenth data entry and the first part of the parity entries (e.g., the 17th partial parity entry is updated from the first part of the parity entries). The memory device 150 stores data entries in a manner that includes data stored in 16 unit strings (16 - string XOR scheme). The size of the partial parity entries is equal to 16 unit strings. Among them, the third memory area 126 in the memory device 150 may be used as a buffer to temporarily store the partial parity entries, so that the third memory area 126 used by the memory controller 130 can be regarded as overhead. However, due to the limited number of partial parity entries, the overhead can be reduced.

[0094] When the first part of the parity entries is updated to the 17th part of the parity entries and the 17th part of the parity entries is stored in a new location, the memory controller 130 may invalidate the previously stored first part of the parity entries. The invalidated first part of the parity can be released from the third memory area 126. That is, the size of the third memory area 126 may be substantially the same as the size of the parity entries included in the parity group. Even if more partial parity entries are generated, the size of the third memory area 126 will not change.

[0095] Figure 5 is a diagram for describing operations of a third part executed within a memory system according to another embodiment of the present disclosure. Among them, operations of the third part can be executed to perform a logical operation on a last part of data entries belonging to a parity group, update a partial parity entry to a parity entry, and store the parity entry corresponding to the parity group in the memory device 150. For example, referring to Figure 3 and Figure 4 , 16 partial parity entries of a subgroup (page0 to page239) stored in memory cells connected to the first word line WL0 to the 32nd word line WL31 can be stored in the third memory area 126. Figure 4 The operations of the second part described in

[0096] can be executed multiple times in units of two word lines. Figure 5 Referring to

[0097] , the memory controller 130 can perform a logical operation on a subgroup Page240 of data stored in memory cells included in the first unit string String0 connected to the 33rd word line WL32. Since the last memory plane Plane3 of the last memory die Die N can be allocated to the second memory area 124 for storing parity entries, the amount of data included in the subgroup Page240 can be smaller than the amount of data included in other subgroups page0 to page239 for which partial parity entries have been generated.

[0098] Subsequently, the memory controller 130 can read the updated partial parity entries (Parity buffer 0, Spare 0, Meta 0) (①) stored in the third memory area 126 in the memory device 150. Thereafter, the memory controller 130 can perform a logical operation on the logical operation result of the subgroup Page240 and the updated partial parity entries (Parity buffer 0, Spare 0, Meta 0) to generate the first parity entry Parity0 among the multiple parity entries Parity0 to Parity15 corresponding to the parity group.

[0099] The memory controller 130 can repeat the same operations of the third part for the remaining subgroups Page241 to Page255. Thus, the memory controller 130 can determine the multiple parity entries Parity0 to Parity15 of the parity group including the multiple subgroups Page0 to Page255. The memory device 150 can store the multiple parity entries Parity0 to Parity15 in the second memory area 124.

[0099] AsFigures 3 to 5 As shown, a parity group can be divided into multiple subgroups. Corresponding to the size of the parity check entries included in the parity group, the operation of generating and updating partial parity check entries for multiple subgroups can be repeatedly executed. Thus, the parity generation engine 510 that performs a logical operation to calculate parity can be operatively coupled only to a buffer whose size is smaller than the size of the data entries belonging to the parity group. In addition, the size of the third memory area 126 in the memory device 150 can be increased without corresponding to the size of the parity check entries of the parity group. Therefore, the resource utilization efficiency in the memory controller 130 and the memory device 150 can be improved or enhanced.

[0100] Figure 6 is a diagram showing Figure 1 the configuration of the parity generation engine 510 shown in

[0101] Referring to Figure 6 , the parity generation engine 510 can include a logical operation circuit 516 that performs an exclusive OR (XOR) operation and a parity operation buffer 514 that stores data entries WD[0], WD[1], WD[2], and parity check entries.

[0102] According to an embodiment, the data entries WD[0], WD[1], WD[2] sequentially transmitted to the parity generation engine 510 can be sequentially transmitted to the memory device 150 and programmed into the memory device 150. In this case, the data entries WD[0], WD[1], WD[2] can be included in a subgroup. The parity generation engine 510 can sequentially perform an exclusive OR (XOR) operation on the input data entries WD[0], WD[1], WD[2], and then store the result of the exclusive OR (XOR) operation.

[0103] The parity generation engine 510 can have a parity operation buffer 514 corresponding to the size of the subgroup. For example, one subgroup can include 9 data entries and 1 parity check entry. In this case, the parity generation engine 510 can perform a logical operation on 9 sequentially transmitted data entries (i.e., the 1st to 9th data entries) and output the result as the first parity check entry. Thereafter, the parity generation engine 510 can calculate the second parity check entry based on the other 10th to 18th data entries sequentially transmitted. Figure 1 The programming control circuit 190 described in

[0104] The programming control circuit 190 including the parity generation engine 510 can identify the physical locations of data entries that are sequentially transmitted to and programmed into the memory device 150. The parity entries output from the parity generation engine 510 can include additional information (or metadata) regarding the locations in the memory device 150 where multiple data entries are stored.

[0105] Figure 6 The parity generation engine 510 described in can generate parity entries in units of a preset number of data entries based on the programming order of the data entries or the order in which the data entries are transmitted through at least one channel to the memory device 150 for data programming operations. In addition, depending on the number of data entries constituting a parity group (or subgroup) and the size of the parity entries, the size or number of subgroups constituting the parity group can vary. According to an embodiment, the parity generation engine 510 can include a parity calculation buffer 514 corresponding to the size of the parity entries, regardless of the size or number of the subgroups.

[0106] Figure 7 FIG. is a diagram showing a configuration of an independent (or inexpensive) disk redundant array (RAID) applicable to a memory device according to another embodiment of the present disclosure. Specifically, Figure 7 An example of using five regions (Plane1, Plane2, Plane3, Plane4, Plane5) in an independent disk redundant array (RAID) or an inexpensive disk redundant array (RAID) is shown.

[0107] The five regions included in the memory device adopting the RAID scheme can have substantially the same size. According to an embodiment, each of the five regions Plane1, Plane2, Plane3, Plane4, and Plane5 included in the memory device 150 can include a memory plane, a storage block, a memory die, etc. In another embodiment, the five regions Plane1, Plane2, Plane3, Plane4, and Plane5 can be five logical regions set by a user.

[0108] The memory system 110 can adopt a RAID scheme to store 4 data entries A1, A2, A3, A4 and 1 parity entry Ap in 5 regions Plane1, Plane2, Plane3, Plane4, Plane5. Even if an error occurs in one of the 5 regions Plane1, Plane2, Plane3, Plane4, Plane5, the data stored in the error region can be recovered and restored based on the other data entries and the parity entry stored in the remaining 4 regions. For example, the parity entry Ap can be generated by performing an exclusive OR (XOR) logical operation on the 4 data entries A1, A2, A3, A4. Thereafter, when an error occurs in the second data entry A2 among the 4 data entries A1, A2, A3, A4, the second data A2 can be recovered and restored by performing an exclusive OR (XOR) operation on the first data entry A1, the third data entry A3, the fourth data entry A4, and the parity entry Ap.

[0109] In addition, since it is difficult to predict which of the five regions Plane1, Plane2, Plane3, Plane4, Plane5 will have problems, the positions of storing the four data entries and one parity entry can be changed. For example, a first parity entry Ap corresponding to the four first data entries A1, A2, A3, A4 can be stored in the fifth region Plane5, while a second parity entry Bp corresponding to the four second data entries B1, B2, B3, B4 can be stored in the fourth region Plane4.

[0110] To generate the parity entry, the memory system 110 can include a parity generation engine. Referring to Figure 4 , in the five regions Plane1, Plane2, Plane3, Plane4, Plane5 of the memory device 150, the four first data entries A1, A2, A3, A4 and a first parity entry Ap can be programmed. The parity generation engine can generate a first parity entry Ap based on the four first data entries A1, A2, A3, A4. In the memory system 110, the four first data entries A1, A2, A3, A4 can be stored in the first non-volatile cell region, and a first parity entry Ap can be stored in the second non-volatile cell region. To program multi-bit data, when the memory device 150 according to an embodiment of the present disclosure can perform a two-step programming operation, the parity entry can be generated and stored in a RAID scheme. In this case, the size of the SLC buffer described above can be reduced or effectively utilized.

[0111] Referring to Figure 7, four data entries A1, A2, A3, and A4 are used to generate a parity entry Ap. In order for the memory system 110 to generate a parity entry Ap, it must have a buffer for storing the four data entries A1, A2, A3, and A4 and a parity entry Ap. If the memory system 110 generates a parity entry based on 63 data entries, the memory system 110 should include a buffer for storing 64 entries including 63 data entries and 1 parity entry. However, referring to Figures 1 to 6 , during the process of generating a single parity entry for 63 data entries, the memory system can divide the 63 data entries into multiple subgroups, generate partial parity entries for each subgroup, and then temporarily store the partial parity entries in the memory device. Therefore, the parity generation engine (i.e., the parity generation circuit) 510 can perform a parity operation (e.g., a calculation for generating a parity entry) through a buffer having a storage space corresponding to the size of the subgroup rather than the size of the 63 data entries.

[0112] Figure 8 is a diagram for describing how multiple data entries are distributed and stored in a memory device according to an embodiment of the present disclosure. Figure 8 illustrates an embodiment in which n memory dies (Die 0, Die 1,..., Die n - 1) are assigned to a first memory area for storing data entries, and the (n + 1)th memory die (Die n) is assigned to a second memory area 124 for storing parity entries.

[0113] Referring to Figure 8 , positions indicated by the same address within the n memory dies (Die 0, Die 1,..., Die n - 1) can be set as the same parity group. For example, multiple subgroups page0 to page15 can be set in each cell string and each word line in the memory planes (Plane0, Plane1, Plane2, Plane3) of each memory die (Die 0, Die 1,..., Die n - 1). Referring to Figure 8 , a parity group can include multiple data entries and parity entries. The multiple data entries can be stored in memory cells connected to multiple word lines WL0, WL1 of each memory plane (Plane0, Plane1, Plane2, Plane3). The multiple parity entries can be stored in memory cells indicated by the same address in the (n + 1)th memory die (Die n).

[0114] For example, the memory controller 130 may generate a first partial parity entry PP[0] for the first subgroup page0 and temporarily store the first partial parity entry PP[0] in the third memory region 126. Then, the memory controller 130 may perform a logical operation on the ninth subgroup page8. The memory controller 130 performs a logical operation on the logical operation result PP[8] of the first partial parity entry PP[0] and the ninth subgroup page8 to generate a first parity entry (WP[0], parity0). After the memory controller 130 transmits the first parity entry (WP[0], parity0) to the memory device 150, the memory device 150 may store the first parity entry (WP[0], parity0) in the (Die n) n+1 memory die assigned for storing parity entries. Different from Figure 5 that, Figure 8 the following embodiment is shown: wherein the memory device 150 includes a separate memory die that stores only parity entries. Thus, all subgroups belonging to one parity group may have the same size of data.

[0115] Referring to Figures 3 to 8 , the scheme for configuring the parity group associated with the data stored in the memory device 150 may vary according to embodiments. Based on this scheme, it can be determined whether an error occurring at a certain position can be recovered. The scheme can be set differently according to the error recovery performance required by the memory device 150. Additionally, the parity group scheme can be changed according to the operating characteristics of the memory device 150. As the number of parity entries stored in the memory device 150 decreases, the number of data entries stored in the memory device 150 with the same storage capacity can increase.

[0116] Figure 9 FIG. is a diagram showing the configuration of a data processing system 100 according to an embodiment of the present disclosure.

[0117] Referring to Figure 9 , the data processing system 100 may include a host 102 and a memory system (e.g., memory system 110), and the host 102 is engaged or coupled with the memory system 110. For example, the host 102 and the memory system 110 may be interconnected via a data bus, a host cable, etc. for data communication.

[0118] The memory system 110 may include a memory device 150 and a memory controller 130. The memory device 150 and the memory controller 130 in the memory system 110 may be considered physically separate components or elements. The memory device 150 and the memory controller 130 may be connected via at least one data path. For example, the data path may include a channel and / or a way. According to an embodiment, Figure 1 the programming control circuit 190 shown coupled to the memory device 150 may be included in Figure 9 and Figure 10 the memory controllers 130, 400 shown in Figure 1 , Figure 9 and Figure 10 the memory controllers 130, 400 shown in may be implemented using a system on chip (SOC).

[0119] The memory device 150 may include a plurality of memory chips (i.e., flash memory chips) 252 coupled to the memory controller 130 via a plurality of channels CH0, CH1, ……, CHn and ways W0, ……, W_k. The memory chips 252 may include a plurality of memory planes or a plurality of memory dies. According to an embodiment, a memory plane may be considered a logical or physical partition that includes at least one storage block, a drive circuit capable of controlling an array including a plurality of non-volatile memory cells, and a buffer that can temporarily store data input to or output from the non-volatile memory cells. Each memory plane or each memory die may support an interleaved mode in which a plurality of data input / output operations are performed in parallel or simultaneously. According to an embodiment, the storage blocks included in each memory plane or each memory die included in the memory device 150 may be grouped to input / output a plurality of data entries as a super storage block. Figure 9 The internal configuration of the memory device 150 shown may change based on the operating performance of the memory system 110. Embodiments of the present disclosure may not be limited to Figure 9 the internal configuration described in.

[0120] According to an embodiment, the memory device 150 and the memory controller 130 may be components or elements divided by function. Additionally, according to an embodiment, the memory device 150 and the memory controller 130 may be implemented using a single chip or multiple chips.

[0121] The memory controller 130 may perform data input / output operations (e.g., read operations, program operations, erase operations, etc.) in response to requests or commands input from an external device such as the host 102. For example, when the memory controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the memory controller 130. In addition, the memory controller 130 may independently perform operations without requests or commands input from the host 102. Regarding the operation state of the memory device 150, the memory controller 130 may perform operations such as garbage collection (GC), wear leveling (WL), bad block management (BBM) for checking whether a storage block is bad and disposing of bad blocks.

[0122] Each memory chip 252 may include a plurality of storage blocks. A storage block may be understood as a group of non-volatile memory cells in which data is deleted together by a single erase operation. Although not shown, a storage block may further include pages, which are a group of non-volatile memory cells that store data together during a single program operation or output data together during a single read operation. For example, one storage block may include a plurality of pages. The memory device 150 may include a voltage supply circuit (not shown) capable of supplying at least one voltage to the storage block. The voltage supply circuit may supply a read voltage Vrd, a program voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the storage block.

[0123] The host 102 that interacts with the memory system 110, or the data processing system 100 that includes the memory system 110 and the host 102, is a mobile electronic device (e.g., a vehicle), a portable electronic device (e.g., a mobile phone, an MP3 player, a laptop computer, etc.), and a non-portable electronic device (e.g., a desktop computer, a game console, a television, a projector, etc.). The host 102 may provide an interaction between the host 102 and a user who uses the data processing system 100 or the memory system 110 through at least one operating system (OS). The host 102 sends a plurality of commands corresponding to user requests to the memory system 110, and the memory system 110 performs data input / output operations corresponding to the plurality of commands (e.g., operations corresponding to user requests).

[0124] Refer to Figure 9 As shown, the memory controller 130 in the memory system operates together with the host 102 and the memory device 150. As shown, the memory controller 130 may have a hierarchical structure including a host interface (HIL) 220, a flash translation layer (FTL) 240, and a memory interface layer or flash interface layer (FIL) 260.

[0125] Figure 9 The host interface layer (HIL) 220, flash translation layer (FTL) 240, and memory interface layer or flash interface layer (FIL) 260 included in the memory system 110 described in Figure 9 are shown as an example. The host interface layer (HIL) 220, flash translation layer (FTL) 240, and flash interface layer (FIL) 260 may be implemented in various forms according to the operating performance of the memory system 110. According to an embodiment, the host interface layer (HIL) 220, flash translation layer (FTL) 240, and flash interface layer (FIL) 260 may perform operations through a plurality of cores or processors having a pipeline structure included in the memory controller 130.

[0126] The host 102 and the memory system 110 may use a predetermined data communication rule or program set or preset interface to send and receive data therebetween. Examples of the data communication standards or interface rules or program sets supported by the host 102 and the memory system 110 for sending and receiving data include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Peripheral Component Interconnect Express (PCIe or PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), etc. According to an embodiment, the host 102 and the memory system 110 may be interconnected through the Universal Serial Bus (USB). The Universal Serial Bus (USB) is a highly scalable, hot-pluggable, plug-and-play serial interface that can ensure cost-effective and standard connections with peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, video conferencing cameras, etc.

[0127] The memory system 110 may support Non-Volatile Memory Express (NVMe). Non-Volatile Memory Express (NVMe) is an interface type based at least on Peripheral Component Interconnect Express (PCIe), which is designed to improve the performance and design flexibility of the host 102, server, computing device, etc. equipped with the memory system 110. PCIe may use a slot or a specific cable to connect a computing device (e.g., the host 102) and a peripheral device (e.g., the memory system 110). For example, PCIe may use a plurality of pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one wire (e.g., x1, x4, x8, or x16) to achieve high-speed data communication of hundreds of MB per second. According to an embodiment, the PCIe scheme may achieve a bandwidth of dozens to hundreds of Gbps.

[0128] The buffer manager 280 in the memory controller 130 can cooperate with the host interface layer (HIL) 220, the flash translation layer (FTL) 240, and the memory interface layer or flash interface layer (FIL) 260 to control the input / output of data or operation information. To this end, the buffer manager 280 can set up or establish various buffers, caches, or queues in the memory, and control the data input / output of the buffers, caches, or queues, or the data transfer between the buffers, caches, or queues in response to requests or commands generated by the host interface layer (HIL) 220, the flash translation layer (FTL) 240, and the memory interface layer or flash interface layer (FIL) 260. For example, the memory controller 130 can temporarily store the read data provided by the memory device 150 in response to a request from the host 102 before providing the read data to the host 102. In addition, the memory controller 130 can temporarily store the write data provided by the host 102 in the memory before storing the write data in the memory device 150. When controlling operations such as read operations, programming operations, and erase operations performed within the memory device 150, the read data or write data transmitted or generated between the memory controller 130 and the memory device 150 in the memory system 110 can be stored and managed in buffers, queues, etc. established by the buffer manager 280 in the memory. In addition to the read data or write data, the buffer manager 280 can also store signals or information (e.g., mapping data, read commands, programming commands, etc. for performing operations such as programming and reading data between the host 102 and the memory device 150) in buffers, caches, queues, etc. established in the memory. The buffer manager 280 can set up or manage command queues, program memories, data memories, write buffers / caches, read buffers / caches, data buffers / caches, mapping buffers / caches, etc.

[0129] The host interface layer (HIL) 220 may handle commands, data, etc. sent from the host 102. By way of example and not limitation, the host interface layer 220 may include a command queue manager 222 and an event queue manager 224. The command queue manager 222 may sequentially store commands, data, etc. received from the host 102 in a command queue, and output them to the event queue manager 224, for example, in the order in which they are stored in the command queue manager 222. The event queue manager 224 may sequentially transmit events for processing commands, data, etc. received from the command queue. According to an embodiment, the event queue manager 224 may classify, manage, or adjust commands, data, etc. received from the command queue. In addition, according to an embodiment, the host interface layer 220 may include an encryption manager (Encryp) 226 configured to encrypt a response or output data to be sent to the host 102, or decrypt an encrypted portion of a command or data sent from the host 102.

[0130] The host 102 may send multiple commands or data having the same characteristics, or multiple commands and data having different characteristics may be mixed or scrambled by the host 102 and then sent to the memory system 110. For example, multiple commands for reading data, i.e., read commands, may be transmitted, or a command for reading data, i.e., a read command, and a command for programming / writing data, i.e., a write command, may be alternately sent to the memory system 110. The command queue manager 222 of the host interface layer 220 may sequentially store commands, data, etc. sent from the host 102 in a command queue. Thereafter, the host interface layer 220 may estimate or predict what type of internal operation the memory controller 130 will perform based on the characteristics of the commands, data, etc. sent from the host 102. The host interface layer 220 may determine its processing order and priority based on the characteristics of the commands, data, etc. According to the characteristics of the commands, data, etc. sent from the host 102, the event queue manager 224 in the host interface layer 220 is configured to receive from the buffer manager 280 events that should be processed or handled inside the memory system 110 or the memory controller 130 according to the commands, data, etc. input by the host 102. Then, the event queue manager 224 may transmit the events including commands, data, etc. to the flash translation layer (FTL) 240.

[0131] According to an embodiment, the flash translation layer (FTL) 240 may include a host request manager (HRM) 242, a mapping manager (MM) 244, a status manager (GC / WL) 246, and a block manager (BM / BBM) 248. Further, according to an embodiment, the flash translation layer (FTL) 240 may implement a multi-threaded scheme to perform data input / output (I / O) operations. The multi-threaded FTL may be implemented by a multi-core processor using multi-threading included in the memory controller 130. For example, the host request manager (HRM) 242 may manage events transferred from an event queue. The mapping manager (MM) 244 may handle or control mapping data. The status manager 246 may perform operations such as garbage collection (GC) or wear leveling (WL) after checking the operation state of the memory device 150. The block manager 248 may run commands or instructions on blocks in the memory device 150.

[0132] The host request manager (HRM) 242 may use the mapping manager (MM) 244 and the block manager 248 to handle or process requests according to read and program commands and events passed from the host interface layer 220. The host request manager (HRM) 242 may send a query request to the mapping manager (MM) 244 to determine a physical address corresponding to a logical address input with an event. The host request manager (HRM) 242 may send a read request and the physical address to the memory interface layer 260 to process the read request, that is, to handle the event. In one embodiment, the host request manager (HRM) 242 may send a program request (or write request) to the block manager 248 to program data into a specific empty page in the memory device 150 where data is not stored, and then may transmit a mapping update request corresponding to the program request to the mapping manager (MM) 244 to update an entry related to the programmed data in the information that maps logical addresses and physical addresses to each other.

[0133] The block manager 248 may convert a program request passed from the host request manager (HRM) 242, the mapping manager (MM) 244, and / or the status manager 246 into a flash program request for the memory device 150 to manage flash blocks in the memory device 150. To maximize or enhance the programming or write performance of the memory system 110, the block manager 248 may collect program requests and send flash program requests for multi-plane and single-programming operations to the memory interface layer 260. In an embodiment, the block manager 248 sends multiple flash program requests to the memory interface layer 260 to enhance or maximize parallel processing of a multi-channel and multi-direction flash controller.

[0134] In an embodiment, the block manager 248 may manage the blocks in the memory device 150 according to the number of valid pages, select and erase blocks without valid pages when free blocks are needed, and select the blocks including the least number of valid pages when it is determined to perform garbage collection. The state manager 246 may perform garbage collection to move the valid data stored in the selected blocks to empty blocks and erase the data stored in the selected blocks, so that the memory device 150 may have sufficient free blocks (i.e., empty blocks without data).

[0135] When the block manager 248 provides the information of the block to be erased to the state manager 246, the state manager 246 may check all the flash pages of the block to be erased to determine whether each page of the block is valid. For example, to determine the validity of each page, the state manager 246 may identify the logical address recorded in the out-of-band (OOB) area of each page. To determine whether each page is valid, the state manager 246 may compare the physical address of the page with the physical address mapped to the logical address obtained from the query request. The state manager 246 sends a programming request for each valid page to the block manager 248. When the programming operation is completed, the mapping manager 244 may update the mapping table.

[0136] The mapping manager 244 may manage mapping data, such as a logical-physical mapping table. The mapping manager 244 may process various requests generated by the host request manager (HRM) 242 or the state manager 246, such as queries, updates, etc. The mapping manager 244 may store the entire mapping table in the memory device 150, for example, stored in the flash / non-volatile memory, and cache mapping entries according to the storage capacity of the memory 144. When a mapping cache miss occurs during the processing of a query or update request, the mapping manager 244 may send a read request to the memory interface layer 260 to load the relevant mapping table stored in the memory device 150. When the number of dirty cache blocks in the mapping manager 244 exceeds a certain threshold, a programming request may be sent to the block manager 246, so that clean cache blocks can be generated and the dirty mapping table can be stored in the memory device 150.

[0137] When garbage collection is performed, the status manager 246 copies valid pages into free blocks, and the host request manager (HRM) 242 can program the latest version of data for the same logical address of the page and issue an update request simultaneously. When the status manager 246 requests a mapping update while the copy of the valid page is not completed properly, the mapping manager 244 may not perform the mapping table update. This is because when the status manager 246 requests a mapping update and later completes the copy of the valid page, the mapping request is issued using the old physical information. The mapping manager 244 may perform the mapping update operation to ensure accuracy when or only when the latest mapping table still points to the old physical address.

[0138] The memory interface layer or flash interface layer (FIL) 260 may exchange data, commands, status information, etc. with a plurality of memory chips 252 in the memory device 150 through a data communication method. According to an embodiment, the memory interface layer 260 may include a status check scheduling manager (SM / SC) 262 and a data path manager (DPC) 264. The status check scheduling manager 262 may check and determine the operation status of the plurality of memory chips 252 coupled to the memory controller 130, the operation status of the plurality of channels CH0, CH1, ……, CHn, and the operation status of the plurality of paths W0, ……, W_k, etc. The transmission and reception of data or commands may be scheduled in response to the operation status of the plurality of memory chips 252 and the plurality of channels CH0, CH1, ……, CHn. The data path manager 264 may control the transmission and reception of data, commands, etc. through the plurality of channels CH0, CH1, ……, CHn and paths W0, ……, W_k based on the information transmitted by the status check scheduling manager 262. According to an embodiment, the data path manager 264 may include a plurality of transceivers, each corresponding to each of the plurality of channels CH0, CH1, ……, CHn. In addition, according to an embodiment, the status check scheduling manager 262 and the data path manager 264 included in the memory interface layer 260 may be implemented as or in conjunction with a memory control sequence generator.

[0139] According to an embodiment, the memory interface layer 260 may further include an ECC (error correction code) circuit 266, which is configured to perform error checking and correction on data transmitted between the memory controller 130 and the memory device 150. The ECC circuit 266 may be implemented as a separate module, circuit, or firmware in the memory controller 130, but according to an embodiment, it may also be implemented in each memory chip 252 included in the memory device 150. The ECC circuit 266 may include a program, circuit, module, system, or device for detecting and correcting error bits of data processed by the memory device 150.

[0140] To find and correct any errors in the data transferred from the memory device 150, the ECC circuit 266 may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder may perform error correction encoding on the data to be programmed into the memory device 150 to generate encoded data with parity bits added and store the encoded data in the memory device 150. When the memory controller 130 reads the data stored in the memory device 150, the ECC decoder may detect and correct the error bits included in the data read from the memory device 150. For example, after performing error correction decoding on the data read from the memory device 150, the ECC circuit 266 may determine whether the error correction decoding is successful and output an indication signal based on the result of the error correction decoding, such as a correction success signal or a correction failure signal. The ECC circuit 266 may use the parity bits generated during the ECC encoding process of the data stored in the memory device 150 to correct the error bits of the read data entry. When the number of error bits is greater than or equal to the number of correctable error bits, the ECC circuit 266 may not correct the error bits but instead output a correction failure signal indicating a failure to correct the error bits.

[0141] According to an embodiment, the ECC circuit 266 may perform error correction operations based on coding modulation such as: low density parity check (LDPC) code, Bose-Chaudhri-Hocquenghem (BCH) code, turbo code, Reed-Solomon (RS) code, convolutional code, recursive systematic code (RSC), trellis coded modulation (TCM), block coded modulation (BCM), etc. The ECC circuit 266 may include all circuits, modules, systems, and / or devices that perform error correction operations based on at least one of the above codes.

[0142] For example, an encoder in the ECC circuit 266 may generate a codeword that is a unit of ECC application data. A codeword of length n bits may include k bits of user data and (n - k) bits of parity. The code rate may be calculated as (k / n). The higher the code rate, the more user data can be stored in a given codeword. When the length of the codeword is long and the code rate is small, the error correction ability of the ECC circuit 266 can be improved. In addition, the ECC circuit 266 performs decoding using information read from channels CH0, CH1, ……, CHn. The decoder in the ECC circuit 266 can be classified into a hard decision decoder and a soft decision decoder according to how many bits represent the information to be decoded. The hard decision decoder performs decoding using the output information of a memory cell represented by 1 bit, and the 1-bit information used in this case is called hard decision information. The soft decision decoder uses more accurate output information of a memory cell composed of 2 bits or more bits, and this information is called soft decision information. The ECC circuit 266 can use hard decision information or soft decision information to correct errors included in the data.

[0143] According to an embodiment, in order to improve the error correction ability, the ECC circuit 266 may use a concatenated code that employs two or more codes. In addition, the ECC circuit 266 may use a product code that divides a codeword into several rows and columns and applies different relatively short ECCs to each row and each column.

[0144] According to an embodiment, managers included in the host interface layer 220, the flash translation layer (FTL) 240, and the memory interface layer or flash interface layer (FIL) 260 may be implemented using a general-purpose processor, an accelerator, a dedicated processor, a coprocessor, a multi-core processor, and the like. According to an embodiment, the manager may be implemented with firmware that works in cooperation with the processor.

[0145] According to an embodiment, the memory device 150 is implemented as a non-volatile memory, such as a flash memory, such as a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable ROM (EPROM), an electrically erasable ROM (EEPROM), a magnetic RAM (MRAM), a NAND flash memory, a NOR flash memory, and the like. In another embodiment, the memory device 150 may be implemented by at least one of a phase change random access memory (PCRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), and a spin transfer torque magnetic random access memory (STT-MRAM).

[0146] Figure 10 is a diagram showing the configuration of a data storage system according to an embodiment of the present disclosure. Figure 10A memory system including multiple cores or multiple processors is shown, which is an example of a data storage system. The memory system may support the Non-Volatile Memory Express (NVMe) protocol.

[0147] NVMe is a transport protocol designed specifically for solid-state memory and can operate much faster than traditional hard drives. NVMe can support higher Input / Output Operations Per Second (IOPS) and lower latency, thus increasing data transfer speed and improving the overall performance of the data storage system. Different from SATA designed for hard disk drives, NVMe can utilize the parallelism of solid-state storage to more effectively use multiple queues and processors (e.g., CPUs). NVMe is designed to allow the host to use multiple threads to achieve higher bandwidth. NVMe can fully utilize all the parallelism provided by the SSD. However, due to limited firmware scalability, limited computing power, and severe hardware contention in the SSD, the memory system may not be able to process a large number of I / O requests in parallel.

[0148] Referring to Figure 10 , a host, as an external device, can be connected to the memory system through multiple PCIe Gen 3.0 lanes, a PCIe Physical Layer (PCIe PHY) 412, and a PCIe Core 414. The memory controller 400 may include three embedded processors 432A, 432B, 432C, and each embedded processor uses two cores 302A, 302B. According to an embodiment, the multiple cores 302A, 302B or the multiple embedded processors 432A, 432B, 432C may be implemented using a microprocessor such as a Tensor Processing Unit (TPU).

[0149] The multiple embedded processors 432A, 432B, 432C may be connected to an internal DRAM controller 434 through a processor interconnect. The memory controller 400 further includes a Low-Density Parity-Check (LDPC) sequencer 460, a Direct Memory Access (DMA) engine 420, a scratch pad memory for metadata management 450, and an NVMe controller 410. Components within the memory controller 400 may be connected to multiple channels connected to multiple memory packages 152 through a NAND Flash Physical Layer (NAND Flash PHY) 440. The multiple memory packages 152 may correspond to Figure 9 the multiple memory chips 252 described in

[0150] According to an embodiment, the NVMe controller 410 included in the memory controller 400 is a storage controller designed to be used with a solid-state drive (SSD) using the NVMe interface. The NVMe controller 410 can manage data transfer between the SSD and the computer CPU, as well as other functions such as error correction, wear leveling, and power management. The NVMe controller 410 can support fast data transfer rates using a simplified low-overhead protocol.

[0151] According to an embodiment, the staging memory 450 can be a storage area set by the NVMe controller 410 for temporarily storing data. The staging memory 450 can be used to store data waiting to be written to multiple memory packages (i.e., Flash) 152. The staging memory 450 can also be used as a buffer to accelerate the write process, typically using a small amount of dynamic random access memory (DRAM) or static random access memory (SRAM). When a write command is executed, the data can first be written to the staging memory 450 and then transferred to the multiple memory packages 152 in larger blocks. The staging memory 450 can be used as a temporary storage buffer to help optimize the write performance of the multiple memory packages 152. The staging memory 450 can be used as an intermediate data storage device before the data is written to the non-volatile memory cells.

[0152] The DMA engine 420 included in the memory controller 400 is a component that transfers data between the NVMe controller 410 in the host system and the host memory without the intervention of the host processor. The DMA engine 420 can support the NVMe controller 410 to directly read data from or write data to the host memory without the intervention of the host processor. According to an embodiment, the DMA engine 420 can use DMA descriptors including information related to data transfer, such as buffer addresses, transfer lengths, and other control information, to implement or support high-speed data transfer between the host and the NVMe device.

[0153] The low-density parity-check (LDPC) sequencer 460 in the memory controller 400 is a component that performs error correction on data stored in multiple memory packages 152. Here, the LDPC code is a commonly used error correction code in NAND flash memories for reducing the bit error rate. The LDPC sequencer 460 can be designed to immediately process the encoding and decoding of the LDPC code when reading data from the NAND flash memory and writing data to the NAND flash memory. According to an embodiment, the LDPC sequencer 460 can divide the data into multiple blocks, encode each block using the LDPC code, and store the encoded data in the multiple memory packages 152. Thereafter, when reading the encoded data from the multiple memory packages 152, the LDPC sequencer 460 can decode the encoded data based on the LDPC code and correct errors that may occur during the write or read operation. The LDPC sequencer 460 can correspond to Figure 9 the ECC circuit 266 described in

[0154] In addition, although Figure 9 and Figure 10 show examples of a memory system including a memory device 150 or multiple memory packages 152 capable of storing data, the data storage system according to an embodiment of the present disclosure may not be limited to Figure 9 and Figure 10 the memory systems described therein. For example, the memory device 150, the multiple memory packages 152, or the data storage device controlled by the memory controllers 130, 400 may include volatile or non-volatile memory devices. In Figure 10 it is described that the memory controller 400 can communicate data with a host 102 (refer to Figure 9 ) placed outside the memory system through a high-speed NVM (NVMe) interface and a high-speed PCI (PCIe). In an embodiment, the memory controller 400 can communicate data with at least one host through a protocol such as a high-speed Compute Express Link (CXL).

[0155] In addition, the devices and methods for distributed processing or allocation / reallocation for executing multiple instructions in a controller including multiple processors with a pipeline structure according to an embodiment of the present disclosure can be applied to a data processing system including multiple memory systems or multiple data storage devices. For example, a Memory Pool System (MPS) is a very general, adaptable, flexible, reliable, and efficient memory management system, where a memory pool, e.g., a logical partition of the main memory or storage device reserved for a processing task or a group of tasks, can be used to control or manage the storage devices coupled to the controller. A controller including multiple processors with a pipeline structure can control the transfer of data and programs to the memory pool controlled or managed by the Memory Pool System (MPS).

[0156] As described above, a memory system according to an embodiment of the present disclosure can reduce the overhead that occurs during the process of distributing and storing a large number of data entries.

[0157] In addition, a memory controller in a memory system according to an embodiment of the present disclosure can reduce the usage amount of a buffer memory or a cache during an operation of generating parity entries for data entries distributed and stored in a memory device. Therefore, during the process of performing a data programming operation in a memory controller implemented in a system on chip (SoC) that does not include a large volatile memory but has a small volatile memory, the resource usage efficiency within the memory system can be improved.

[0158] The methods, processes, and / or operations described herein can be executed by code or instructions run by a computer, a processor, a controller, or other signal processing device. The computer, the processor, the controller, or other signal processing device can be a device described herein or a device other than the elements described herein. Since the algorithms that form the basis of the methods or the operations of the computer, the processor, the controller, or other signal processing device are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, the processor, the controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0159] In addition, another embodiment can include a computer-readable medium, such as a non-transitory computer-readable medium, for storing the above code or instructions. The computer-readable medium can be a volatile or non-volatile memory or other storage device that is removably or fixedly coupled to the computer, the processor, the controller, or other signal processing device to run the code or instructions for performing the operations of the method embodiments or device embodiments herein.

[0160] The controller, processor, control circuit, device, module, unit, multiplexer, logic, interface, decoder, driver, generator, and other signal generation and signal processing components of the embodiments disclosed herein can be implemented, for example, as non-transitory logic, and the non-transitory logic can include hardware, software, or both. When implemented at least partially as hardware, the controller, processor, control circuit, device, module, unit, multiplexer, logic, interface, decoder, driver, generator, and other signal generation and signal processing components can be any of various integrated circuits, including but not limited to application-specific integrated circuits, field-programmable gate arrays, combinations of logic gates, systems on chip, microprocessors, or other types of processing or control circuits.

[0161] When implemented at least in part in software, a controller, processor, control circuit, apparatus, module, unit, multiplexer, generator, logic, interface, decoder, driver, and other signal generation and signal processing components may include, for example, a memory or other storage device for storing code or instructions to be run by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be a device described herein or a device other than the elements described herein. Since algorithms underlying the methods or the operation of the computer, processor, microprocessor, controller, or other signal processing device have been described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.

[0162] Although the present teachings have been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made in accordance with the present disclosure without departing from the spirit and scope of the present disclosure as defined by the appended claims. Additionally, embodiments may be combined to form other embodiments.

Claims

1. A memory system, comprising: A memory device, comprising a first memory area, a second memory area, and a third memory area, wherein the first memory area stores a plurality of data entries, the second memory area stores parity entries corresponding to the plurality of data entries, and the third memory area stores at least one partial parity entry, the at least one partial parity entry corresponds to at least one subgroup, each subgroup including a portion of the plurality of data entries; as well as A memory controller generates a first partial parity entry corresponding to a first subgroup among the at least one subgroup to store the first partial parity entry in the third memory area, generates a second partial parity entry corresponding to a second subgroup among the at least one subgroup, reads the first partial parity entry from the third memory area, and performs a logic operation on the first partial parity entry and the second partial parity entry to generate the parity entry.

2. The memory system according to claim 1, wherein: The memory controller invalidates at least one partial parity entry stored in the third memory area after storing the parity entry in the second memory area.

3. The memory system according to claim 1, wherein: The first memory region is distributed across a plurality of memory dies, and A physical block address of the third memory area is different from a physical block address of the first memory area and a physical block address of the second memory area.

4. The memory system according to claim 3, wherein: Each of the first memory area and the second memory area includes a memory block having memory cells storing multi-bit data, and the third memory area includes a memory block having memory cells storing single-bit data.

5. The memory system according to claim 1, wherein: The memory controller repeatedly performs the operation of generating and updating the at least one partial parity entry for the at least one subgroup in a preset unit including the at least one subgroup, and The size of the partial parity entries stored in the third memory area is the same as the size of the parity entries stored in the second memory area.

6. The memory system according to claim 1, wherein: The memory controller reads the first partial parity entries from the third memory area when the number of the first partial parity entries is 1 / N of the total number of subgroups associated with the plurality of data entries, where N is a natural number of 2 or greater.

7. The memory system according to claim 1, wherein: The logic operation is an exclusive OR operation, namely, an XOR operation.

8. The memory system according to claim 1, wherein: The memory controller includes a parity generation circuit, the parity generation circuit including: an operation circuit for performing the logic operation; and A buffer is connected to the operation circuit, and the size of the buffer corresponds to the size of the subgroup.

9. The memory system according to claim 1, wherein: The third memory area is adjacent to the first memory area.

10. The memory system according to claim 1, wherein: The third memory area is a dedicated space for storing the partial parity entries.

11. A memory controller coupled to a memory device, wherein: The memory controller: Divide multiple data items into multiple subgroups; generating a first partial parity entry corresponding to a first subgroup among the plurality of subgroups to store the first partial parity entry in the memory device; generating a second partial parity entry corresponding to a second subgroup among the plurality of subgroups; reading a first portion of parity entries stored in the memory device; performing a logical operation on the first portion of parity entries and the second portion of parity entries to generate parity entries associated with the plurality of data entries; and The parity entry is stored in the memory device.

12. The memory controller according to claim 11, wherein: The memory controller invalidates the first partial parity entry and the second partial parity entry after storing the parity entry in the memory device.

13. The memory controller according to claim 11, wherein: The first partial parity entry, the second partial parity entry, and the parity entry are generated by a parity generation circuit included in the memory controller, and The parity generation circuit includes a buffer having a size corresponding to a size of each of the plurality of subgroups.

14. The memory controller according to claim 13, wherein: The size of the bank corresponds to K pages provided in the memory device, where K is a natural number.

15. The memory controller according to claim 11, wherein: The memory controller repeatedly performs the operation of generating and updating partial parity entries corresponding to the plurality of subgroups in preset units including at least one subgroup, and The size of each partial parity entry stored in the third memory area is the same as the size of the parity entry stored in the second memory area.

16. The memory controller according to claim 11, wherein: The memory controller reads the first partial parity entries from the third memory area when the number of the first partial parity entries is 1 / N of the total number of subgroups associated with the plurality of data entries, where N is a natural number of 2 or greater.

17. A memory system comprising: A memory device comprising a plurality of memory regions, the plurality of memory regions comprising a plurality of memory dies, a plurality of memory planes or a plurality of memory blocks, wherein a plurality of data entries and parity entries associated with the plurality of data entries are distributed and stored in the plurality of memory regions to recover an uncorrectable error correction code, i.e., a UECC; as well as A memory controller divides the plurality of data entries into a plurality of sub-groups, generates a first partial parity entry corresponding to a first sub-group among the plurality of sub-groups to store the first partial parity entry in the memory device, generates a second partial parity entry corresponding to a second sub-group among the plurality of sub-groups, reads the first partial parity entry stored in the memory device, performs a logic operation on the first partial parity entry and the second partial parity entry to generate the parity entry, and stores the parity entry in the memory device.

18. The memory system of claim 17, wherein: The plurality of memory regions are coupled to the memory controller via a plurality of channels.

19. The memory system of claim 17, wherein: Each of the plurality of subsets includes data stored in memory cells indicated by the same word line address and the same cell string address in the plurality of memory regions.

20. The memory system of claim 17, wherein: The memory controller invalidates the first partial parity entry and the second partial parity entry after storing the parity entry in the memory device.

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