Memory device, memory system, and operating method of memory device

Abstract

A memory device includes a plurality of memory cells configured to store at least one bit, the memory device including a first word line and a second word line. The memory device is configured to perform a first program operation on a first word line on a plurality of memory cells in a higher state, the higher state being a state in which the plurality of memory cells have a threshold voltage above a specific voltage; performing a second program operation on the second word line; and when the second program operation is performed after the first program operation is performed, performing a third program operation at a voltage lower than a voltage of the first program operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0161437 filed in the Korean Intellectual Property Office on November 20, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a memory device, a memory system, and an operating method of the memory device, and more particularly, to a memory device, a memory system, and an operating method of the memory device that improve interference to a victim word line affected by a voltage distribution of an aggressor word line. Background Art

[0004] Recently developed memory devices include multiple word lines. Multiple word lines are individually programmed to affect the voltage distribution of adjacent word lines. For example, if a disturber word line is programmed after a victim word line is programmed, the voltage distribution of the victim word line is affected by the programming of the disturber word line.

[0005] To improve this, a reprogramming operation has been proposed that performs a program operation on a victim word line at a voltage lower than a threshold voltage and then performs a correction operation on the victim word line again after performing a program operation on a disturber word line.

[0006] However, the related art method cannot sufficiently eliminate the disturbance caused by the program voltage of the disturbing square word line. Summary of the invention

[0007] Aspects of the inventive concept provide a memory device and a memory system that eliminate disturbance caused by a program voltage of a disturbing square word line.

[0008] Aspects of the inventive concept also provide a memory device and a memory system that eliminate disturbance caused by a program voltage of a disturber word line by using a voltage higher than a threshold voltage when performing a program operation on the victim word line even without a disturbance correction operation on the victim word line.

[0009] According to an example embodiment, a memory device includes a plurality of memory cells configured to store at least one bit, the memory device including a first word line and a second word line. The memory device is configured to perform a first programming operation on the first word line on the plurality of memory cells in a higher state, the higher state being a state in which the plurality of memory cells have a threshold voltage above a specific voltage; perform a second programming operation on the second word line; and when the second programming operation is performed after the first programming operation is performed, perform a third programming operation at a voltage lower than the voltage of the first programming operation.

[0010] According to an example embodiment, an operating method of a memory device including a plurality of memory cells each storing at least one bit includes performing a first programming operation on a memory cell connected to a first word line, including applying a first voltage to the first word line; and performing a second programming operation on a memory cell connected to a second word line adjacent to the first word line, including applying a second voltage to the second word line. When performing the first programming operation, the first programming operation is performed on a memory cell in a higher state, the higher state being a state in which the memory cell has a threshold voltage above a specific voltage. When performing the second programming operation after performing the first programming operation, a third programming operation is performed on the memory cell connected to the first word line, including applying a third voltage lower than the first voltage to the first word line.

[0011] According to an example embodiment, a memory system includes: a host configured to generate a reprogramming command for a word line; and a memory device configured to receive the reprogramming command, the memory device including a plurality of memory cells each storing at least one bit and configured to perform a reprogramming operation. The memory device includes a first word line and a second word line, a first programming operation is configured to be performed on the first word line, and a second programming operation is configured to be performed on the second word line. The memory device is configured to perform a first programming operation on a memory cell in a higher state, the higher state refers to a state in which the memory cell has a threshold voltage above a specific voltage, and when the second programming operation is performed after the first programming operation is performed, a third programming operation is performed at a voltage lower than the voltage of the first programming operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram of a memory system according to an embodiment;

[0014] Figure 2 is a block diagram of a memory device according to an embodiment;

[0015] Figure 3 is a conceptual diagram showing a word line of a memory device according to an embodiment;

[0016] Figure 4 is a conceptual diagram illustrating programming of a word line according to an embodiment;

[0017] Figure 5A is a conceptual diagram illustrating a programming process of a word line when a first word line is in a lower state and a second word line is in a lower state according to an embodiment;

[0018] Figure 5Bis a conceptual diagram illustrating a programming process of a word line when a first word line is in a lower state and a second word line is in a higher state according to an embodiment;

[0019] Figure 5C is a conceptual diagram illustrating a programming process of a word line when a first word line is in a higher state and a second word line is in a lower state according to an embodiment;

[0020] Figure 5D is a conceptual diagram illustrating a programming process of a word line when a first word line is in a higher state and a second word line is in a higher state according to an embodiment;

[0021] Figure 5E shows a voltage distribution diagram after programming a word line according to an embodiment;

[0022] Figure 6 is a flow chart of a method of programming a memory device according to an embodiment;

[0023] Figure 7 is a flow chart illustrating a programming process for a memory device when a first word line is in a lower state and a second word line is in a lower state according to an embodiment;

[0024] Figure 8 is a flow chart illustrating a programming process for a memory device when a first word line is in a lower state and a second word line is in a higher state according to an embodiment;

[0025] Fig. 9 is a conceptual diagram illustrating a programming process for a memory device when a first word line is in a higher state according to an embodiment; and

[0026] Figures 10 to 12 is a diagram illustrating a three-dimensional V-NAND structure that may be applied to a memory device according to an embodiment. DETAILED DESCRIPTION

[0027] In the following, together with the attached Figure 1 Hereinafter, details such as detailed configuration and structure are provided to help understand the embodiments. Therefore, the embodiments described herein may be changed or modified in various ways without departing from the present invention.

[0028] Figure 1 is a block diagram of a memory system 10 according to an embodiment.

[0029] refer to Figure 1, the memory system 10 according to the embodiment includes a memory device 100 and a host 200. The memory device 100 according to the embodiment may receive a reprogramming command RePGM_CMD generated by the host 200 and perform a reprogramming operation on a plurality of word lines included in the memory device 100. Hereinafter, the reprogramming operation used in this specification is an operation of performing a programming operation on a first word line among a plurality of word lines included in the memory device 100, performing a programming operation on a second word line adjacent to the first word line after the programming operation performed on the first word line, and then performing a programming operation again on the first word line affected by the programming operation on the second word line. Here, the first word line may be a victim word line, and the second word line may be an interfering word line. For example, the reprogramming operation may be an operation of correcting the voltage distribution of a cell connected to the victim word line affected by the programming operation on the interfering word line.

[0030] The memory device 100 according to the embodiment may store at least one bit in each of a plurality of cells and perform a reprogramming operation. For example, the memory device 100 may include a plurality of word lines and store at least one bit in each of a plurality of memory cells connected to each word line. The memory device 100 according to the embodiment may include a first word line on which a first programming operation is performed and a second word line on which a second programming operation is performed. The first programming operation according to the embodiment may be performed before the second programming operation in time. For example, after performing a first programming operation on a first word line (e.g., on a cell connected to the first word line), a second programming operation may be performed on a second word line (e.g., on a cell connected to the second word line), thereby changing the voltage distribution of the cell connected to the first word line.

[0031] The first word line of the memory device 100 according to the embodiment may be configured to perform a first programming operation on the cell to place the cell in a higher state (e.g., a data state), and when a second programming operation is performed after the first programming operation is performed, the first word line may be configured to perform a third programming operation at a voltage lower than the voltage of the first programming operation. The third programming operation according to the embodiment may be a reprogramming operation for the first word line. For example, the first programming operation may place the cell in a state having a threshold voltage above a certain level, which places the cell in a first higher data state.

[0032] According to an embodiment, the voltage used in the third programming operation may be set to be lower than the voltage of the first programming operation, and therefore, when the cells of the first word line have a higher state from among a group of states representing different values ​​(e.g., from among the states of a multi-level cell), the memory device 100 may have an effect as if the third programming operation is omitted for those cells. For example, because the first programming operation is performed at a higher voltage than the third programming operation, when the first programming operation is performed, the memory device 100 may form a voltage distribution that takes into account the reprogramming operation of the first word line. However, when the cells of the first word line have a threshold voltage corresponding to a lower state from among a group of states representing different values ​​(e.g., from among the states of a multi-level cell), the memory device 100 may perform the third programming operation with a voltage higher than the voltage applied in the first programming operation. The higher state according to an embodiment may be a state among a group of possible states of a memory cell programmed to have a voltage distribution at a level higher than a specific threshold voltage, and the lower state may be a state among a group of possible states of a memory cell programmed to have a voltage distribution at a level lower than a specific threshold voltage.

[0033] The host 200 according to an embodiment may include a memory controller 210, and may generate a reprogram command RePGM_CMD for the memory device 100. For example, the memory controller 210 may generate a reprogram command RePGM_CMD for the memory device 100 and transmit the generated reprogram command RePGM_CMD to the memory device 100. The memory device 100 may receive the reprogram command RePGM_CMD and perform a reprogram operation on a word line.

[0034] Figure 2 is a block diagram of a memory device 100 according to an embodiment.

[0035] Reference Figure 2 , the memory device 100 according to the embodiment may include a first word line 110, a second word line 120, and a third word line 130. However, as Figure 2As shown, the memory device 100 may further include a plurality of word lines, including an (N-2)th word line 1[N-2]0, an (N-1)th word line 1[N-1]0, or an Nth word line 1[N]0. However, in the present specification, for the sake of convenience, the description will focus on the first word line 110, the second word line 120, and the third word line 130. The first word line 110 according to the embodiment may be a victim word line of the second word line 120. In addition, the second word line 120 may be a victim word line of the third word line 130. For example, in the case where a programming operation is performed on the second word line 120 after a programming operation is performed on the first word line 110, the first word line 110 having a voltage distribution change when the programming operation is performed on the second word line 120 may be a victim word line of the second word line 120, and the second word line 120 may be a disturber word line of the first word line 110. Similarly, in the case where a programming operation is performed on the third word line 130 after a programming operation is performed on the second word line 120, the second word line 120 having a voltage distribution change during the programming operation on the third word line 130 may be a victim word line of the third word line 130, and the third word line 130 may be a disturber word line of the second word line 120. Each of the first word line 110, the second word line 120, and the third word line 130 according to an embodiment may include a plurality of memory cells (e.g., may be connected to gates of the plurality of memory cells).

[0036] The first word line 110 according to the embodiment may perform a first programming operation on a cell in a higher state. After performing the first programming operation, the second word line 120 according to the embodiment may perform a second programming operation. After performing the second programming operation, the first word line 110 according to the embodiment may perform a third programming operation. The third programming operation according to the embodiment may be a reprogramming operation of the first word line 110. The voltage of the third programming operation according to the embodiment may be at a level lower than the voltage of the first programming operation.

[0037] For example, the first word line 110 performs a first programming operation on cells in a higher state, and when a second programming operation is performed after the first programming operation is performed, the first word line 110 may perform a third programming with a voltage lower than that of the first programming operation. According to an embodiment, the voltage of the third programming operation is set to be lower than that of the first programming operation, and therefore, when cells connected to the first word line 110 have a higher state and thus have a higher threshold voltage, the third programming operation on the first word line 110 may have an effect as if the third programming operation is omitted. For example, because the first programming operation is performed with a higher voltage than the third programming operation, when the first programming operation is performed, the cells connected to the first word line 110 may form a voltage distribution that takes into account the reprogramming operation on the first word line 110.

[0038] The first word line 110 according to the embodiment can perform a first programming operation using a voltage higher than the threshold voltage of a plurality of memory cells. For example, the first word line 110 can perform a first programming operation using a voltage higher than the threshold voltage of a memory cell to form a voltage distribution of memory cells having a higher state.

[0039] According to an embodiment, when cells connected to the first word line 110 are programmed to have a lower state, and then a voltage is provided to the second word line 120 to place the cells connected to the second word line 120 in a higher state, the first word line 110 may be configured to stop further programming operations performed after performing a third programming operation. For example, the first word line 110 having a voltage distribution affected by the second programming operation may correct the voltage distribution by performing the third programming operation, and an additional reprogramming operation may not be performed thereafter.

[0040] According to an embodiment, when the cells connected to the first word line 110 are programmed to have a higher state, the first word line 110 may be configured to omit the third programming operation. For example, when the first programming operation of the first word line 110 is performed to cause all cells intended to be programmed to have a high voltage threshold voltage distribution exceeding a specific threshold voltage, the first word line 110 may omit the third programming operation. When the cells connected to the first word line 110 according to an embodiment have recently been programmed to be in a higher state and the cells connected to the second word line 120 have recently been programmed to be in a lower state, or when the cells connected to the first word line 110 according to an embodiment have recently been programmed to be in a higher state and the cells connected to the second word line 120 have recently been programmed to be in a higher state, the first word line 110 may omit the third programming operation.

[0041] The second word line 120 according to the embodiment may be a word line adjacent to the first word line 110. For example, the second word line 120 may be disposed adjacent to the first word line 110, and voltage distribution of cells connected to the first word line 110 may be affected due to the second programming operation performed on the second word line 120. When the voltage distribution of cells connected to the first word line 110 is affected due to the second programming operation of the second word line 120, the first word line 110 according to the embodiment may perform a third programming operation depending on the state.

[0042] The second word line 120 according to the embodiment may perform a fifth programming operation according to the fourth programming operation of the third word line 130. For example, when the cells connected to the first word line 110 have been recently programmed to be in a lower state and the cells connected to the second word line 120 have been recently programmed to be in a lower state, when the fourth programming operation is performed on the third word line 130 adjacent to the second word line 120, the second word line 120 may be configured to perform the fifth programming operation. The fourth programming operation according to the embodiment may be a programming operation performed on the third word line 130 after the reprogramming operation performed on the first word line 110. The fifth programming operation according to the embodiment may be a reprogramming operation of the second word line 120.

[0043] The voltage for the fifth programming operation according to an embodiment may be at a level lower than the voltage of the second programming operation. For example, in the case where the second word line 120 has recently programmed the cell connected to the second word line 120 to be in a higher state, when the fourth programming operation is performed after the second programming operation is performed, the second word line 120 may be configured to perform the fifth programming operation at a voltage lower than the voltage of the second programming operation. According to an embodiment, the voltage of the fifth programming operation may be set to be lower than the voltage of the second programming operation, and therefore, when the cell connected to the second word line 120 has been programmed to a higher state, the second word line 120 may have an effect as if the fifth programming operation is omitted. Because the second programming operation is performed at a higher voltage than the fourth programming operation, when the second programming operation is performed, the second word line 120 may form a voltage distribution that takes into account the reprogramming operation of the second word line 120.

[0044] The first word line 110 and the second word line 120 according to the embodiment may be configured to include a four-level cell (QLC) or a three-level cell (TLC). However, this embodiment is not limited to the first word line 110 and the second word line 120, and another word line included in the memory device 100 may be configured to include a four-level cell or a three-level cell. In order for the memory to include a four-level cell or a three-level cell, the word line according to the embodiment may store at least two bits in one memory cell.

[0045] Figure 3 is a conceptual diagram illustrating a word line of the memory device 100 according to an embodiment.

[0046] Reference Figure 3 , the memory device 100 according to the embodiment may include a plurality of word lines. For example, the memory device 100 may include a first word line 110, a second word line 120, and a third word line 130. However, as Figure 3As shown, the memory device 100 may further include an (N-2)th word line 1[N-2]0, an (N-1)th word line 1[N-1]0, or an Nth word line 1[N]0. The word lines may be positioned adjacent to each other. In an embodiment, because different word lines are arranged adjacent to each other, each word line may be affected by a voltage distribution according to a programming operation of an adjacent word line. For example, a voltage distribution of a first word line 110 may be affected by a programming operation on a second word line 120. However, by performing a first programming operation on the first word line 110 using a voltage exceeding a threshold voltage of all cells being programmed, thereby causing the programmed cells to all have a higher state, the first word line 110 may not be affected by the second programming operation. For example, by setting the first programming operation so that all cells of the first word line 110 intended to be programmed to a higher state actually have a higher state, the memory device 100 may omit a reprogramming operation on the first word line 110, or may perform a reprogramming operation on the first word line 110 with a voltage lower than the first programming voltage.

[0047] Figure 4 is a conceptual diagram illustrating programming of a word line according to an embodiment.

[0048] Reference Figure 4 , the memory device 100 according to the embodiment may include a first word line 110, a second word line 120, or a third word line 130, and a program operation may be performed on each word line.

[0049] The first word line 110 of the memory device 100 according to the embodiment may perform the first programming operation 1PGM or the third programming operation 3PGM. The second word line 120 of the memory device 100 according to the embodiment may perform the second programming operation 2PGM or the fifth programming operation 5PGM. The third word line 130 of the memory device 100 according to the embodiment may perform the fourth programming operation. When describing the first to fifth programming operations according to the embodiment, the term "first to fifth" may be determined according to the programming order. For example, the memory device 100 according to the embodiment may perform the second programming operation on the second word line 120 after performing the first programming operation on the first word line 110. When performing the second programming operation, the memory device 100 according to the embodiment may then perform the third programming operation on the first word line 110. The third programming operation may be a reprogramming operation of the first word line 110. When the third programming operation is completed, the memory device 100 according to the embodiment may perform the fourth programming operation on the third word line 130. When performing the fourth programming operation, the memory device 100 according to the embodiment may then perform the fifth programming operation on the second word line 120. The fifth program operation according to an embodiment may be a reprogram operation of the second word line 120 .

[0050] According to an embodiment, when the first word line 110 initially programs all memory cells to be programmed to a higher state to a higher state, and the memory cells remain in the higher state after a second programming operation on the second word line 120, the first word line 110 may be configured to omit the third programming operation. For example, when the first programming operation is performed on the first word line 110 so that all cells connected to the first word line 110 and programmed to a higher state have a voltage threshold distribution that exceeds a specific threshold voltage by a sufficient amount so that any change in the threshold voltage due to programming of the second word line 120 does not lower the threshold voltage of any cell below the specific threshold voltage, then the first word line 110 may omit the third programming operation, or may perform the third programming operation at a voltage lower than that of the first programming operation to have an effect as if the third programming operation were omitted.

[0051] According to an embodiment, when the second word line 120 is in a higher state, the second word line 120 may be configured to omit the fifth programming operation. For example, when the second programming operation is performed on the second word line 120 so that all cells connected to the second word line 120 and programmed to a higher state have a voltage threshold distribution that exceeds a specific threshold voltage by a sufficient amount so that any change in the threshold voltage due to programming of the third word line 130 does not reduce the threshold voltage of any cell below the specific threshold voltage, then the second word line 120 may omit the fifth programming operation or perform the fifth programming operation at a voltage lower than the voltage of the second programming operation to have an effect as if the fifth programming operation is omitted.

[0052] Figure 5A is a conceptual diagram showing a programming process of a word line when a cell connected to a first word line is programmed to be in a lower state and a cell connected to a second word line is programmed to be in a lower state according to an embodiment. The lower state in this example refers to one or more lower states among a set of states representing all bit values ​​of a memory cell. For example, the lower state may refer to any one of the P0 and P1 states in a multi-level cell. The higher state in this example refers to one or more higher states among a set of states representing all bit values ​​of a memory cell. For example, the higher state may refer to any one of the P2 to P7 states in a multi-level cell (TLC).

[0053] exist Figure 5A In an embodiment of the present invention, the horizontal axis may be a voltage level N WL Vth of the N-th word line. The N-th word line according to the embodiment may have a first threshold voltage first verification and a second threshold voltage second verification. The higher state according to the embodiment may be a state having a voltage threshold distribution higher than the second threshold voltage second verification, and the lower state may be a state having a voltage threshold distribution lower than the second threshold voltage second verification. In the following, the voltage threshold distribution of the first word line is described based on the voltage threshold distribution of the first word line. Figure 5A Embodiment of the invention.

[0054] Reference Figure 2 and Figure 5A , when the first word line 110 is in a lower state and the second word line 120 is in a lower state, the memory device 100 according to the embodiment may perform a second programming operation on the second word line 120 after the first programming operation on the first word line 110. When performing the second programming operation, the memory device 100 according to the embodiment may perform a third programming operation on the first word line 110. The third programming operation may be a reprogramming operation of the first word line 110, and it may be performed after performing the second programming operation. When the third programming operation is completed, the memory device 100 according to the embodiment may perform a fourth programming operation on the third word line 130. When performing the fourth programming operation, the memory device 100 according to the embodiment may perform a fifth programming operation on the second word line 120. The fifth programming operation according to the embodiment may be a reprogramming operation of the second word line 120. As a result of the reprogramming operation on the first word line 110 and the second word line 120, the programmed cells connected to the first word line 110 may have a voltage threshold distribution labeled as a first PGM after the first programming operation, as a second PGM after the second programming operation, as a third PGM after the third programming operation, and as a fifth PGM after the fifth programming operation. Therefore, after both the fourth and fifth programming operations, the programmed cells connected to the first word line 110 have a voltage distribution above the second verification voltage, which may correspond to a higher state (e.g., a P2 state) among a plurality of states that the cells may be in. Therefore, in Figure 5A , the final state (above the second verification voltage) labeled as the 5th PGM may be the P2 state among the states P0-P7 in the multi-level cell memory.

[0055] When memory cells connected to the first word line 110 are programmed to be in a lower state and memory cells connected to the second word line 120 are programmed to be in a lower state, the memory device 100 according to an embodiment can perform a reprogramming operation on the first word line 110 and the second word line 120 to correct the voltage threshold distribution of the first word line 110 and the second word line 120.

[0056] Figure 5B is a conceptual diagram illustrating a programming process of word lines when programmed cells connected to a first word line are programmed to be in a lower state and programmed cells connected to a second word line are programmed to be in a higher state according to an embodiment.

[0057] exist Figure 5BIn an embodiment of the present invention, the horizontal axis may be a voltage level N WL Vth of the N-th word line. The N-th word line according to the embodiment may have a first threshold voltage first verification and a second threshold voltage second verification. The higher state according to the embodiment may be a state of a voltage threshold distribution having a voltage threshold distribution higher than the second threshold voltage second verification, and the lower state may be a state of a voltage threshold distribution having a voltage threshold distribution lower than the second threshold voltage second verification. In the following, the description based on the voltage distribution of the first word line is Figure 5B In the embodiment of Figure 5B In the example, the first state shown (e.g., the state between the first verification and the second verification) can be a lower state among multiple states in the MLC memory (e.g., states P0 and P1), and the second state shown (e.g., the state above the second verification) can be a higher state among multiple states in the MLC memory (e.g., states P2-P7).

[0058] refer to Figure 2 and Figure 5B According to an embodiment, when the programmed cells connected to the first word line 110 are in a lower state and the programmed cells connected to the second word line 120 are in a higher state, the first word line 110 may be configured to stop the program operation performed after the third program operation. For example, the first word line 110 connected to the programmed cells having the voltage distribution affected by the second program operation may perform the third program operation to correct the voltage distribution, and may not perform any additional reprogramming operation.

[0059] Figure 5C is a conceptual diagram illustrating a programming process of a word line when a programmed cell connected to a first word line is in a higher state and a programmed cell connected to a second word line is in a lower state according to an embodiment, and Figure 5D is a conceptual diagram illustrating a programming process of a word line when a programming cell connected to a first word line is in a higher state and a programming cell connected to a second word line is in a higher state according to an embodiment. Figure 5C and Figure 5D In the example, the first state shown (e.g., the state between the first verification and the second verification) can be a lower state among multiple states in the MLC memory (e.g., states P0 and P1), and the second state shown (e.g., the state above the second verification) can be a higher state among multiple states in the MLC memory (e.g., states P2-P7).

[0060] exist Figure 5C and Figure 5DIn an embodiment of the present invention, the horizontal axis may be a voltage level N WL Vth of the N-th word line. The N-th word line according to the embodiment may have a first threshold voltage first verification and a second threshold voltage second verification. The higher state according to the embodiment may be a state of a voltage distribution of memory cells having a voltage distribution higher than the second threshold voltage second verification, and the lower state may be a state of a voltage distribution of memory cells having a voltage distribution lower than the second threshold voltage second verification. In the following, the description based on the voltage distribution of the first word line is described. Figure 5C and Figure 5D Embodiment of the invention.

[0061] refer to Figure 2 , Figure 5C and Figure 5D , when the programmed cells connected to the first word line 110 according to an embodiment are in a higher state, the first word line 110 may be configured to omit the third program operation regardless of the states of the cells of the second word line 120.

[0062] For example, when the first programming operation of the first word line 110 is performed so that the voltage distribution of the memory cell has a high voltage exceeding the threshold voltage, the first word line 110 may omit the third programming operation. When the programmed cell connected to the first word line 110 according to the embodiment is in a higher state and the programmed cell connected to the second word line 120 is in a lower state, or when the programmed cell connected to the first word line 110 according to the embodiment is in a higher state and the programmed cell connected to the second word line 120 is in a higher state, the first word line 110 may omit the third programming operation. For example, when the first programming operation of the first word line 110 is performed to cause the programmed cell of the first word line 110 to exceed the second threshold voltage second verification, the programmed cell connected to the first word line 110 may not be affected by the second programming operation, and the memory device 100 may omit the reprogramming operation. By omitting the reprogramming operation, the memory device 100 may have reduced power consumption.

[0063] Figure 5E 2 shows a voltage distribution diagram after programming a word line according to an embodiment. Figure 5E In the embodiment of FIG. 5 , the horizontal axis represents the voltage level N WL Vth of the N-th word line.

[0064] refer to Figure 2 and Figure 5E, when the programmed cells connected to the first word line according to the embodiment have a voltage in a lower state, the memory device 100 may perform a third programming operation using a third programming voltage third PGM Vth having a level higher than that of the first programming operation voltage first PGM Vth. For example, when the programmed cells connected to the first word line 110 are in a lower state, the memory device 100 may perform a reprogramming operation on the first word line 110 after performing the second programming operation on the second word line 120. The third programming operation according to the embodiment may be a reprogramming operation of the first word line 110. When the programmed cells connected to the first word line 110 according to the embodiment are in a lower state, the third programming operation voltage third PGM Vth may have a level higher than that of the first programming operation voltage first PGM Vth. The higher state according to the embodiment may be a state in which the memory cell is programmed to have a voltage distribution with a level higher than the threshold voltage, and the lower state may be a state in which the memory cell is programmed to have a voltage distribution with a level lower than the threshold voltage.

[0065] Reference again Figure 2 and Figure 5E , the first word line of the memory device 100 according to the embodiment may perform a first programming operation on a cell in a higher state, and when a second programming operation is performed after the first programming operation is performed, the first word line may perform a third programming operation using a third programming voltage third PGM Vth, and the third programming voltage third PGM Vth has a level lower than that of the first programming operation voltage first PGM Vth. The third programming operation according to the embodiment may be a reprogramming operation of the first word line. According to the embodiment, the voltage of the third programming operation may be set to be lower than the voltage of the first programming operation, so that when the first word line has a higher state voltage, the memory device 100 may have an effect as if the third programming operation is omitted. For example, because the first programming operation is performed at a higher voltage than the third programming operation, when the first programming operation is performed, the memory device 100 may form a voltage distribution that takes the reprogramming operation of the first word line into account.

[0066] Figure 6 is a flowchart of a method of programming the memory device 100 according to an embodiment.

[0067] refer to Figure 2 and Figure 6 , the memory device 100 according to the embodiment may start a reprogramming operation ( S610 ).

[0068] The reprogramming operation according to the embodiment may be an operation of performing a programming operation on a first word line 110 among word lines included in the memory device 100, performing a programming operation on a second word line 120 adjacent to the first word line 110 after performing the programming operation on the first word line 110, and then performing a programming operation again on the first word line 110 affected by the programming performed on the second word line 120. Here, the first word line 110 may be a victim word line, and the second word line 120 may be a disturber word line. The reprogramming operation may be an operation of correcting voltage distribution of programmed cells of the victim word line affected by the programming operation of the disturber word line.

[0069] When the reprogramming operation starts, the memory device 100 according to the embodiment may perform a first program operation on the first word line 110 ( S620 ). The first program operation according to the embodiment may be an operation of performing a write operation on the first word line 110 .

[0070] After performing the first program operation on the first word line 110 , the memory device 100 according to the embodiment may perform a second program operation on the second word line 120 ( S630 ). The second program operation according to the embodiment may perform a write operation on the second word line 120 .

[0071] After performing the second programming operation on the second word line 120, the memory device 100 according to the embodiment may perform a third programming operation on the first word line 110 (S640). The third programming operation according to the embodiment may be a reprogramming operation of the first word line 110. The voltage of the third programming operation according to the embodiment may have a lower level than the voltage of the first programming operation.

[0072] For example, the memory device 100 may perform a first programming operation on the first word line 110, and when the second programming operation is performed after the first programming operation is performed, the memory device 100 may perform a third programming operation at a voltage lower than that of the first programming operation. According to an embodiment, the voltage of the third programming operation may be set to be lower than that of the first programming operation, so that when the programmed cells connected to the first word line 110 have a higher state voltage distribution, the first word line 110 may have an effect as if the third programming operation is omitted. Therefore, since the first programming operation is performed at a higher voltage than the third programming operation, when the first programming operation is performed, the first word line 110 may form a voltage distribution that takes into account the reprogramming operation in the first word line 110.

[0073] Figure 7 is a flow chart illustrating a programming process for a memory device when a first word line is in a lower state and a second word line is in a lower state according to an embodiment.

[0074] refer to Figure 2 and Figure 7 , the memory device 100 according to the embodiment may start a reprogramming operation ( S710 ).

[0075] The reprogramming operation according to the embodiment may be an operation of performing a programming operation on a first word line 110 among word lines included in the memory device 100, performing a programming operation on a second word line 120 adjacent to the first word line 110 after performing the programming operation on the first word line 110, and then performing a programming operation again on the first word line 110 that is not affected by the programming performed on the second word line 120. Here, the first word line 110 may be a victim word line, and the second word line 120 may be a disturber word line. For example, the reprogramming operation may be an operation of correcting a voltage distribution of a victim word line affected by a programming operation on a disturber word line.

[0076] When the reprogramming operation starts, the memory device 100 according to the embodiment may determine the state of the programming cell connected to the word line (S720). The word line of the memory device 100 according to the embodiment may include a programmed cell in a higher state or a lower state. The higher state according to the embodiment may be a state programmed to a voltage distribution having a level higher than the threshold voltage, and the lower state may be a state programmed to a voltage distribution having a level lower than the threshold voltage.

[0077] The memory device 100 according to the embodiment may determine whether the first word line 110 is in a lower state and whether the second word line 120 is in a lower state (S730). However, when it is determined that the first word line 110 is not in a lower state or the second word line 120 is not in a lower state, the memory device 100 according to the embodiment may determine the state of the word line again.

[0078] If it is determined that the first word line 110 is in a lower state and the second word line 120 is in a lower state, the memory device 100 according to an embodiment may determine whether to perform a fourth program operation on the third word line 130 adjacent to the second word line 120 ( S740 ).

[0079] For example, the memory device 100 according to the embodiment may perform a second programming operation on the second word line 120 after performing a first programming operation on the first word line 110. While performing the second programming operation, the memory device 100 according to the embodiment may perform a third programming operation on the first word line 110. The third programming operation may be a reprogramming operation of the first word line 110. When the third programming operation is completed, the memory device 100 according to the embodiment may perform a fourth programming operation on the third word line 130.

[0080] If it is determined that the fourth program operation has been performed on the third word line 130 , the memory device 100 according to an embodiment may perform a fifth program operation on the second word line 120 ( S750 ). The fifth program operation according to an embodiment may be a reprogramming operation of the second word line 120 .

[0081] However, if it is determined that the fourth programming operation has not been performed on the third word line 130, the memory device 100 according to the embodiment may perform the fourth programming operation on the third word line 130 adjacent to the second word line 120 (S760). The memory device 100 according to the embodiment may perform the fifth programming operation on the second word line 120 after performing the fourth programming operation on the third word line 130.

[0082] Figure 8 is a flow chart illustrating a programming process for a memory device when programmed cells connected to a first word line are in a lower state and programmed cells connected to a second word line are in an upper state according to an embodiment.

[0083] refer to Figure 2 and Figure 8 , the memory device 100 according to the embodiment may start a reprogramming operation ( S810 ).

[0084] The reprogramming operation according to the embodiment may be an operation of performing a programming operation on a first word line 110 among word lines included in the memory device 100, performing a programming operation on a second word line 120 adjacent to the first word line 110 after performing the programming operation on the first word line 110, and then performing a programming operation again on the first word line 110 affected by the programming performed on the second word line 120. Here, the first word line 110 may be a victim word line, and the second word line 120 may be a disturber word line. The reprogramming operation may be an operation of correcting a voltage distribution of a victim word line affected by the programming operation of the disturber word line.

[0085] When the reprogram operation starts, the memory device 100 according to the embodiment may determine the state of a word line ( S820 ).

[0086] The word line of the memory device 100 according to the embodiment may be in a higher state or a lower state. The higher state according to the embodiment may be a state programmed to a voltage distribution having a level higher than a threshold voltage, and the lower state may be a state programmed to a voltage distribution having a level lower than a threshold voltage.

[0087] The memory device 100 according to the embodiment may determine whether the first word line 110 is in a lower state and whether the second word line 110 is in a higher state ( S830 ).

[0088] If it is determined that the first word line 110 is in the lower state and the second word line 110 is in the higher state, the memory device 100 according to the embodiment may stop the program operation performed after the third program operation ( S840 ).

[0089] According to an embodiment, when the first word line 110 is in a lower state and the second word line 120 is in a higher state, the first word line 110 may be configured to stop the program operation performed after the third program operation. For example, the first word line 110 having a voltage distribution affected by the second program operation may perform the third program operation to correct the voltage distribution, and may not perform any additional reprogramming operation.

[0090] However, when it is determined that the first word line 110 is not in the lower state or the second word line 110 is not in the higher state, the memory device 100 according to an embodiment may determine the states of the word lines again.

[0091] Fig. 9 is a conceptual diagram illustrating a programming process for the memory device 100 when the first word line is in a higher state according to an embodiment.

[0092] refer to Figure 2 and Fig. 9 , the memory device 100 according to the embodiment may start a reprogramming operation ( S910 ).

[0093] The reprogramming operation according to the embodiment may be an operation of performing a programming operation on a first word line 110 among word lines included in the memory device 100, performing a programming operation on a second word line 120 adjacent to the first word line 110 after performing the programming operation on the first word line 110, and then performing a programming operation again on the first word line 110 affected by the programming performed on the second word line 120. Here, the first word line 110 may be a victim word line, and the second word line 120 may be a disturber word line. That is, the reprogramming operation may be an operation of correcting a voltage distribution of a victim word line affected by the programming operation of the disturber word line.

[0094] When the reprogramming operation starts, the memory device 100 according to the embodiment may determine the state of a word line ( S920 ).

[0095] The word lines of the memory device 100 according to the embodiment may be in a higher state or a lower state (for example, the programmed cells of each word line may be in a higher state, or may be in a lower state). The higher state according to the embodiment may be a state in which the cells are programmed to a voltage distribution having a level higher than the threshold voltage, and the lower state may be a state in which the cells are programmed to a voltage distribution having a level lower than the threshold voltage.

[0096] The memory device 100 according to the embodiment may determine whether the first word line 110 is in a higher state ( S930 ).

[0097] If it is determined that the first word line 110 is in the higher state, the memory device 100 according to an embodiment may omit the third program operation ( S940 ).

[0098] According to an embodiment, when the first word line 110 is in a higher state, the first word line 110 may be configured to omit the third program operation regardless of the state of the second word line 120 .

[0099] For example, when the first programming operation for the first word line 110 is performed using a voltage distribution having a high voltage exceeding a threshold voltage, the first word line 110 may omit the third programming operation. When the first word line 110 according to an embodiment is in a higher state and the second word line 120 is in a lower state, or when the first word line 110 according to an embodiment is in a higher state and the second word line 120 is in a higher state, the first word line 110 may omit the third programming operation. When the first programming operation of the first word line 110 is performed to exceed the threshold voltage, the first word line 110 may not be affected by the second programming operation, and the memory device 100 may omit the reprogramming operation. By omitting the reprogramming operation, the memory device 100 may have reduced power consumption.

[0100] However, if it is determined that the first word line 110 is not in the higher state, the memory device 100 according to an embodiment may determine the state of the word line again.

[0101] Figures 10 to 12 is a diagram illustrating a three-dimensional V-NAND structure that may be applied to the memory device 100 according to an embodiment.

[0102] Applicable to the memory device 100 ( Figure 1 )'s first nonvolatile memory 1000 may include a plurality of memory blocks. Fig.10 and Fig.11 shows the structure of a storage block BLKi among multiple storage blocks, Fig.12 An implementation example of a non-volatile memory 1000 is shown.

[0103] refer to Fig.10 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the memory NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. For the sake of simplicity of the drawings, Fig.10It is shown that each of the memory NAND strings NS11 to NS33 includes eight memory cells MC1 to MC8, but is not limited thereto.

[0104] The string selection transistor SST may be connected to a corresponding string selection line among the string selection lines SSL1, SSL2, and SSL3. The memory cells MC1 to MC8 may be connected to corresponding gate lines GTL1 to GTL8, respectively. The gate lines GTL1 to GTL8 may correspond to word lines, and some of the gate lines GTL1 to GTL8 may correspond to dummy word lines. The ground selection transistor GST may be connected to a corresponding ground selection line among the ground selection lines GSL1, GSL2, and GSL3. The string selection transistor SST may be connected to corresponding bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to a common source line CSL.

[0105] Gate lines (eg, GTL1) of the same height may be connected in common, and ground selection lines GSL1, GSL2, and GSL3 and string selection lines SSL1, SSL2, and SSL3 may be separated from each other. Fig.10 , the memory block BLKi is illustrated as being connected to eight gate lines GTL1 to GTL8 and three bit lines BL1 , BL2 , and BL3 , but is not limited thereto.

[0106] Further references Fig.11 , the memory block BLKi is formed in a vertical direction with respect to the substrate SUB. The memory cells constituting the memory NAND strings NS11 to NS33 are formed to be stacked on a plurality of semiconductor layers.

[0107] On the substrate SUB, a common source line CSL extending in a first direction (Y direction) is provided. In the region of the substrate SUB between two adjacent common source lines CSL, a plurality of insulating films IL extending in the first direction (Y direction) are sequentially provided in a third direction (Z direction), and the plurality of insulating films IL may be separated from each other by a certain distance in the third direction (Z direction). A plurality of pillars P are provided to pass through the insulating film IL in the third direction (Z direction), and the insulating film IL is sequentially arranged in the first direction (Y direction) in the region of the substrate SUB between two adjacent common source lines CSL. The pillars P may pass through the insulating film IL to contact the substrate SUB. The surface layer S of each pillar P may include a silicon material doped with a first conductivity type, and may be used as a channel region.

[0108] The inner layer I of each pillar P may include an insulating material (such as silicon oxide) or an air gap. In the region between two adjacent common source lines CSL, a charge storage layer CS is provided along the exposed surfaces of the insulating film IL, the pillar P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (also referred to as a "tunneling insulating layer"), a charge trapping layer, and a blocking insulating layer. In addition, in the region between two adjacent common source lines CSL, a gate electrode GE is provided on the exposed surface of the charge storage layer CS, such as selection lines GSL and SSL and word lines WL1 to WL8. Drains or drain pads DR may be provided on the pillars P, respectively. Bit lines BL1 to BL3 may be provided on the drain pads DR, extending in the second direction (X direction), and separated from each other by a certain distance in the first direction (Y direction).

[0109] like Fig.11 As shown, each of the memory NAND strings NS11 to NS33 can be implemented in a structure in which a first memory stack ST1 and a second memory stack ST2 are stacked. The first memory stack ST1 is connected to a common source line CSL, the second memory stack ST2 is connected to bit lines BL1 to BL3, and the first memory stack ST1 and the second memory stack ST2 are stacked to share a channel hole with each other.

[0110] Fig.12 is a diagram illustrating a memory device 400 according to another example embodiment.

[0111] refer to Fig.12 , the memory device 400 may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a cell area CELL on a first wafer, manufacturing a lower chip including a peripheral circuit area PERI on a second wafer separated from the first wafer, and then bonding the upper chip and the lower chip to each other. Here, the bonding process may include a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal may include copper (Cu), Cu-Cu bonding is used. However, example embodiments may not be limited thereto. For example, the bonding metal may also be aluminum (Al) or tungsten (W).

[0112] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 400 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0113] The peripheral circuit region PERI may include a first substrate 210, an interlayer insulating layer 215, a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210, first metal layers 230a, 230b, and 230c respectively connected to the plurality of circuit elements 220a, 220b, and 220c, and second metal layers 240a, 240b, and 240c respectively formed on the first metal layers 230a, 230b, and 230c. In example embodiments, the first metal layers 230a, 230b, and 230c may be formed of tungsten having a relatively high resistivity, and the second metal layers 240a, 240b, and 240c may be formed of copper having a relatively low resistivity.

[0114] exist Fig.12 In the illustrated example embodiment, although only the first metal layers 230a, 230b, and 230c and the second metal layers 240a, 240b, and 240c are illustrated and described, example embodiments are not limited thereto, and one or more additional metal layers may be further formed on the second metal layers 240a, 240b, and 240c. At least a portion of the one or more additional metal layers formed on the second metal layers 240a, 240b, and 240c may be formed of aluminum or the like having a higher resistivity than the resistivity of copper forming the second metal layers 240a, 240b, and 240c.

[0115] The interlayer insulating layer 215 may be disposed on the first substrate 210 and cover the plurality of circuit elements 220a, 220b, and 220c, the first metal layers 230a, 230b, and 230c, and the second metal layers 240a, 240b, and 240c. The interlayer insulating layer 215 may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0116] The lower bonding metals 271b and 272b may be formed on the second metal layer 240b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 271b and 272b in the peripheral circuit area PERI may be electrically bonded to the upper bonding metals 371b and 372b of the cell area CELL. The lower bonding metals 271b, 272b and the upper bonding metals 371b, 372b may be formed of aluminum, copper, tungsten, or the like. In addition, the upper bonding metals 371b and 372b in the cell area CELL may be referred to as first metal pads, and the lower bonding metals 271b and 272b in the peripheral circuit area PERI may be referred to as second metal pads.

[0117] The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate 310 and a common source line 320. On the second substrate 310, a plurality of word lines 331 to 338 (i.e., 330) may be stacked in a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 310. At least one string selection line and at least one ground selection line may be arranged above and below the plurality of word lines 330, respectively, and the plurality of word lines 330 may be arranged between the at least one string selection line and the at least one ground selection line.

[0118] In the bit line bonding area BLBA, the channel structure CH may extend in a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 310 and pass through a plurality of word lines 330, at least one string selection line, and at least one ground selection line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c may be a bit line pad, and the second metal layer 360c may be a bit line. In example embodiments, the bit line 360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310.

[0119] exist Fig.12 In the example embodiment shown, a region in which a channel structure CH, a bit line 360c, etc. are disposed may be defined as a bit line bonding region BLBA. In the bit line bonding region BLBA, the bit line 360c may be electrically connected to a circuit element 220c providing a page buffer 393 in the peripheral circuit region PERI. The bit line 360c may be connected to upper bonding metals 371c and 372c in the cell region CELL, and the upper bonding metals 371c and 372c may be connected to lower bonding metals 271c and 272c connected to the circuit element 220c of the page buffer 393.

[0120] In the word line bonding area WLBA, a plurality of word lines 330 may extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 310 and perpendicular to the first direction, and may be connected to a plurality of cell pad plugs 341 to 347 (i.e., 340). A plurality of word lines 330 and a plurality of cell pad plugs 340 may be connected to each other in pads provided by at least a portion of a plurality of word lines 330 extending in different lengths in the second direction. A first metal layer 350b and a second metal layer 360b may be sequentially connected to upper portions of a plurality of cell pad plugs 340 connected to a plurality of word lines 330. A plurality of cell pad plugs 340 may be connected to the peripheral circuit region PERI through upper bonding metals 371b and 372b of the cell region CELL in the word line bonding area WLBA and lower bonding metals 271b and 272b of the peripheral circuit region PERI.

[0121] The plurality of cell pad plugs 340 may be electrically connected to the circuit elements 220 b, thereby forming a row decoder 394 in the peripheral circuit region PERI. In example embodiments, the operation voltage of the circuit elements 220 b of the row decoder 394 may be different from the operation voltage of the circuit elements 220 c forming the page buffer 393. For example, the operation voltage of the circuit elements 220 c forming the page buffer 393 may be greater than the operation voltage of the circuit elements 220 b forming the row decoder 394.

[0122] The common source line pad plug 380 may be disposed in the external pad bonding area PA. The common source line pad plug 380 may be formed of a conductive material such as a metal, a metal compound, polysilicon, etc., and may be electrically connected to the common source line 320. The first metal layer 350a and the second metal layer 360a may be sequentially stacked on the upper portion of the common source line pad plug 380. For example, a region in which the common source line pad plug 380, the first metal layer 350a, and the second metal layer 360a are disposed may be defined as the external pad bonding area PA.

[0123] The input-output pads 205 and 305 may be disposed in the external pad bonding area PA. Fig.12, a lower insulating film 201 covering the lower surface of the first substrate 210 may be formed under the first substrate 210, and first input-output pads 205 may be formed on the lower insulating film 201. The first input-output pads 205 may be connected to at least one of a plurality of circuit elements 220a, 220b, and 220c provided in the peripheral circuit region PERI through the first input-output pad plug 203, and may be separated from the first substrate 210 by the lower insulating film 201. In addition, a side insulating film may be provided between the first input-output pad plug 203 and the first substrate 210 to electrically separate the first input-output pad plug 203 and the first substrate 210.

[0124] refer to Fig.12 , an upper insulating film 301 of an upper surface of a second substrate 310 may be formed to cover the second substrate 310, and a second input-output pad 305 may be disposed on the upper insulating layer 301. The second input-output pad 305 may be connected to at least one of a plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit region PERI through a second input-output pad plug 303. In example embodiments, the second input-output pad 305 is electrically connected to the circuit element 220a.

[0125] According to an embodiment, the second substrate 310 and the common source line 320 may not be disposed in the region where the second input-output pad plug 303 is disposed. In addition, the second input-output pad 305 may not overlap the word line 330 in the third direction (Z-axis direction). Fig.12 The second input-output pad plug 303 may be separated from the second substrate 310 in a direction parallel to the upper surface of the second substrate 310 , and may pass through the interlayer insulating layer 315 of the cell region CELL to be connected to the second input-output pad 305 .

[0126] According to an embodiment, the first input-output pad 205 and the second input-output pad 305 may be selectively formed. For example, the memory device 400 may include only the first input-output pad 205 disposed on the first substrate 210 or the second input-output pad 305 disposed on the second substrate 310. Alternatively, the memory device 400 may include both the first input-output pad 205 and the second input-output pad 305.

[0127] The metal pattern provided on the uppermost metal layer may be provided as a dummy pattern, or the uppermost metal layer may not exist in each of the external pad bonding area PA and the bit line bonding area BLBA respectively included in the cell region CELL and the peripheral circuit region PERI.

[0128] In the external pad bonding area PA, the memory device 400 may include a lower metal pattern 273a in the uppermost metal layer of the peripheral circuit area PERI, the lower metal pattern 273a corresponding to the upper metal pattern 372a formed in the uppermost metal layer of the cell area CELL, and having the same cross-sectional shape as the upper metal pattern 372a of the cell area CELL so as to be connected to each other. In the peripheral circuit area PERI, the lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit area PERI may not be connected to the pad. Similarly, in the external pad bonding area PA, an upper metal pattern 372a corresponding to the lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit area PERI and having the same shape as the lower metal pattern 273a of the peripheral circuit area PERI may be formed in the uppermost metal layer of the cell area CELL.

[0129] The lower bonding metals 271b and 272b may be formed on the second metal layer 240b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 271b and 272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 371b and 372b of the cell area CELL by Cu-to-Cu bonding.

[0130] Furthermore, in the bit line bonding area BLBA, an upper metal pattern 392 corresponding to the lower metal pattern 252 formed in the uppermost metal layer of the peripheral circuit area PERI and having the same cross-sectional shape as the lower metal pattern 252 of the peripheral circuit area PERI may be formed in the uppermost metal layer of the cell area CELL. A pad may not be formed on the upper metal pattern 392 formed in the uppermost metal layer of the cell area CELL.

[0131] In an exemplary embodiment, corresponding to the metal pattern formed in the uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI, a reinforcement metal pattern having the same cross-sectional shape as the metal pattern may be formed in the uppermost metal layer in the other of the cell region CELL and the peripheral circuit region PERI. The pad may not be formed on the reinforcement metal pattern.

[0132] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device, comprising a plurality of memory cells configured to store at least one bit, the memory device comprising a first word line and a second word line, and configured to: performing a first programming operation on the first word line on a plurality of memory cells in a higher state, the higher state being a state in which the plurality of memory cells have a threshold voltage above a second threshold voltage; performing a second programming operation on the second word line; as well as When the second program operation is performed after the first program operation is performed, a third program operation is performed at a voltage lower than that of the first program operation.

2. The memory device according to claim 1, wherein: The first word line is a victim word line, and the second word line is a disturber word line.

3. The memory device according to claim 1, wherein: When the plurality of memory cells of the first word line are in a lower state and the plurality of memory cells of the second word line are in a lower state, the lower state being a state in which the plurality of memory cells have a threshold voltage below the second threshold voltage, the memory device is configured to perform a fifth programming operation on the second word line when a fourth programming operation is performed on a third word line adjacent to the second word line.

4. The memory device according to claim 1, wherein: When the plurality of memory cells of the first word line are in a lower state and the plurality of memory cells of the second word line are in a higher state, the lower state referring to a state in which the plurality of memory cells have a threshold voltage below the second threshold voltage and the higher state referring to a state in which the plurality of memory cells have a threshold voltage above the second threshold voltage, the memory device is configured to stop additional programming operations performed on the first word line after the third programming operation.

5. The memory device according to claim 1, wherein: When the plurality of memory cells of the first word line are in a higher state, the higher state being a state in which the plurality of memory cells have a threshold voltage above the second threshold voltage, the memory device is configured to omit the third programming operation on the first word line.

6. The memory device according to claim 1, wherein: The first word line and the second word line are configured to include a four-level cell or a three-level cell.

7. The memory device according to claim 1, wherein: The first word line is configured to perform the first program operation using a voltage higher than a threshold voltage of a memory cell.

8. A method for operating a memory device, the memory device comprising a plurality of memory cells each storing at least one bit, the method comprising: performing a first programming operation on a memory cell connected to a first word line, including applying a first voltage to the first word line; as well as performing a second programming operation on memory cells connected to a second word line adjacent to the first word line, including applying a second voltage to the second word line, wherein, when performing the first programming operation, the first programming operation is performed on a memory cell in a higher state, the higher state being a state in which the memory cell has a threshold voltage above a second threshold voltage, and Wherein, when the second programming operation is performed after the first programming operation is performed, a third programming operation is performed on the memory cells connected to the first word line, including applying a third voltage lower than the first voltage to the first word line.

9. The operating method according to claim 8, further comprising: When the memory cell connected to the first word line is in a lower state and the memory cell connected to the second word line is in a lower state, After performing a fourth programming operation on a third word line adjacent to the second word line, a fifth programming operation is performed on the second word line, the lower state refers to a state in which the memory cell has a threshold voltage below a second threshold voltage.

10. The operating method according to claim 8, further comprising: When the memory cell connected to the first word line is in a lower state, the lower state refers to a state in which the memory cell has a threshold voltage below a second threshold voltage, and the memory cell connected to the second word line is in the higher state, Program operations performed after the third program operation are stopped.

11. The operating method according to claim 8, further comprising: When the second program operation is not performed after the first program operation is performed, the third program operation is omitted.

12. The operating method according to claim 8, wherein: The performing the first program operation and the performing the second program operation include performing a predefined program operation on a four-level cell or a three-level cell.

13. The operating method according to claim 8, wherein: In the performing the first program operation, the first program operation is performed using a voltage higher than a threshold voltage of a memory cell.

14. A memory system comprising: a host configured to generate a reprogramming command for a word line; as well as a memory device configured to receive the reprogram command, the memory device comprising a plurality of memory cells each storing at least one bit and configured to perform a reprogram operation, Wherein, the memory device comprises: a first word line, a first programming operation being configured to be performed on the first word line; and a second word line, a second programming operation being configured to be performed on the second word line, Wherein, the memory device is configured as: performing the first programming operation on a memory cell in a higher state, the higher state being a state in which the memory cell has a threshold voltage above a second threshold voltage, and When the second program operation is performed after the first program operation is performed, a third program operation is performed at a voltage lower than a voltage used for the first program operation.

15. The memory system of claim 14, wherein: The first word line is a victim word line, and the second word line is a disturber word line.

16. The memory system of claim 14, wherein: When a group of programmed memory cells of the first word line is in a lower state and a group of programmed memory cells of the second word line is in a lower state, the lower state being a state in which the group of programmed memory cells has a threshold voltage below the second threshold voltage, the memory device is configured to perform a fifth programming operation when a fourth programming operation is performed on a third word line adjacent to the second word line.

17. The memory system of claim 14, wherein: When a group of programmed memory cells of the first word line are in a lower state, wherein the lower state refers to a state in which the group of programmed memory cells have a threshold voltage below the second threshold voltage, and a group of programmed memory cells of the second word line are in the higher state, the memory device is configured to stop the programming operation performed after the third programming operation.

18. The memory system of claim 14, wherein: The memory device is configured to omit the third programming operation when a set of programmed memory cells of the first word line are in the higher state.

19. The memory system of claim 14, wherein: The memory device is configured to include a four-level cell or a three-level cell.

20. The memory system of claim 14, wherein: The memory device is configured to perform the first program operation using a voltage higher than a threshold voltage of a memory cell.

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