Integrated circuit (IC) structure and manufacturing method thereof

Abstract

Embodiments of the present disclosure provide an integrated circuit (IC) structure. The IC structure includes an optical interposer having an optical waveguide; a plurality of chip stacks disposed over the optical interposer, each of the plurality of chip stacks including a first photonic IC chip and a memory chip over the first photonic IC wafer; and a plurality of first laser source chips disposed adjacent to the plurality of chip stacks, respectively, in which an optical waveguide in the optical interposer is configured as an optical interconnect structure to couple with the memory chip through the first photonic IC chip. Embodiments of the present disclosure also provide a method of fabricating an integrated circuit (IC) structure.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of semiconductors, and more particularly, to integrated circuit structures and methods for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each smaller and more complex than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] This reduction has also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advances. For example, memory macros require many input / output (I / O) ports because different memory macros have different I / O ports. The increase in the number of I / Os may hinder the expansion of memory capacity. Therefore, although existing memory macro structures are generally sufficient for their intended purposes, they are not completely satisfactory in all aspects. Summary of the invention

[0004] One embodiment of the present invention provides an integrated circuit (IC) structure, comprising: an optical interposer having an optical waveguide; a plurality of chip stacks arranged above the optical interposer, each of the plurality of chip stacks comprising a first photonic integrated circuit chip and a memory chip located above the first photonic integrated circuit chip; and a plurality of first laser source chips arranged adjacent to the plurality of chip stacks, respectively, wherein the optical waveguide in the optical interposer is configured as an optical interconnect structure to be coupled with the memory chip through the first photonic integrated circuit chip.

[0005] Another embodiment of the present invention provides an integrated circuit (IC) structure, comprising: an optical interposer having an optical waveguide; a plurality of memory chip stacks disposed above the optical interposer, each of the plurality of memory chip stacks comprising a first photonic integrated circuit chip and a memory chip disposed above the first photonic integrated circuit wafer and bonded to the first photonic integrated circuit wafer; a plurality of first laser source chips disposed adjacent to the plurality of memory chip stacks, respectively; a memory input / output (I / O) chip stack disposed above the optical interposer, wherein the memory input / output chip stack comprises a second photonic integrated circuit chip and a memory input / output chip disposed above the second photonic integrated circuit chip and bonded to the second photonic integrated circuit chip; and a second laser source chip disposed adjacent to the memory input / output chip stack, wherein the optical waveguide in the optical interposer is configured to couple the memory chip with the memory input / output chip through the first photonic integrated circuit chip and the second photonic integrated circuit chip.

[0006] Another embodiment of the present invention provides a method for manufacturing an integrated circuit (IC) structure, comprising: forming a photonic integrated circuit (IC) structure on a first substrate; bonding a memory chip to the photonic integrated circuit structure formed on the first substrate; sawing the first substrate to obtain memory chip stacks, each memory chip stack comprising one of the photonic integrated circuit structures and one of the memory chips; forming an optical interposer; and adopting a configuration of bonding the memory chip stacks and a laser source chip on the optical interposer so that one of the laser source chips is adjacent to one of the memory chip stacks. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A A partially simplified schematic diagram of a memory device structure or system according to an embodiment of the present disclosure is shown.

[0009] Figure 1B A simplified cross-sectional view of a portion of a memory device structure or system with an optical interposer according to an embodiment of the present disclosure is shown.

[0010] Figure 2A and Figure 2C A partially simplified schematic diagram of a memory device structure or system according to an embodiment of the present disclosure is shown.

[0011] Figure 2BA simplified cross-sectional view of a portion of a memory device structure or system according to an embodiment of the present disclosure is shown.

[0012] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F and Figure 3G Simplified cross-sectional views of portions of a memory device structure or system at various stages of fabrication are shown according to an embodiment of the present disclosure.

[0013] Figure 4 A flow chart of a method for manufacturing a memory device structure or system according to an embodiment of the present disclosure is shown.

[0014] Figure 5 A simplified cross-sectional view of a portion of a memory device structure or system according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0015] The present invention provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] In addition, when a number or series of numbers is described using the term "about," "approximately," etc., the term is intended to include numbers within a reasonable range, taking into account variations inherent in manufacturing processes as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features associated with the number, the number or range includes a reasonable range that includes the described number, such as within + / - 10% of the described number. For example, a material layer having a thickness of "about 5 nm" may include a size range of 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing the material layer is known to be + / - 15%.

[0018] The present disclosure relates generally to optoelectronic systems, and more particularly to semiconductor structures or optoelectronic systems having a memory device and an optical interposer configured with efficient control and data communication and methods thereof.

[0019] Optical data communication systems encode digital data patterns by modulating laser light. The modulated laser light is transmitted from a sending node (e.g., an optical transmitter) to a receiving node (e.g., an optical receiver) through an optical data network. The modulated laser light arriving at the receiving node is demodulated to obtain the original digital data pattern. The implementation and operation of optical data communication systems depends on having reliable and efficient mechanisms for transmitting laser light and detecting laser light at different nodes within the optical data network, and also depends on the structure of integrated circuits, photonic circuits, and memory devices.

[0020] The present disclosure provides an integrated circuit (IC) structure having a storage device and an optical link and a method for manufacturing the same. In particular, the sending and receiving nodes in an optical data network can be interconnected through an interposer, and the optical signal is transmitted through the interposer. Such an interposer can be referred to as an optical interposer. Using an optical interposer can shorten the length of the optical path and improve the integrity of the optical signal.

[0021] In addition, the memory device structure includes a plurality of memory macros, each memory macro having a set of memory cells, which are configured in an array form and formed in an IC chip (or die), and the IC chip is referred to as a memory macro chip (or simply a memory chip). Each memory chip is stacked on a photonic IC chip, which is also stacked on an optical interposer. Memory input / output (I / O) modules are formed in a similar configuration in an independent chip (referred to as a memory I / O chip). In particular, the memory I / O chip is stacked on a photonic IC chip, which is also stacked on an optical interposer. In the disclosed embodiment, all memory macro chips are of the same type, such as a static random access memory (SRAM), a dynamic random access memory (DRAM), a floating gate memory device, or other appropriate type of memory device. Therefore, all memory chips can share a single memory I / O chip in a cost-effective manner.

[0022] The memory device structure may include other chip stacks formed on the optical interposer. For example, the memory device structure includes one or more electrical IC chips (EIC chips) in a chip stack configuration. Specifically, each EIC chip is stacked on a photonic IC chip, which is also stacked on the optical interposer.

[0023] In the disclosed memory device structure, all functional chips, such as memory chips, memory I / O chips, and EIC chips, have similar chip stacking configurations and are coupled together through an optical interposer, which provides a universal optical interface with high coupling speed and higher efficiency for integrating different memories. The signal is transmitted through the optical interposer in an optical mode, converted into an electrical signal by the corresponding PIC chip, and further coupled to the overlying chip (such as a memory chip, a memory I / O chip, or an EIC chip) in the form of an electrical signal. The disclosed structure provides a memory macro-embedded silicon-photonics integration (COUPE) system on the optical interposer. The disclosed memory device structure is capable of expanding memory capacity beyond I / O requirements to take into account different I / O requirements, such as double data rate memory (DDR) and low power double data rate memory (LPDDR). The disclosed memory device structure also realizes high performance computing (HPC) or large language models (LLM) in artificial intelligence (AI), which requires high capacity and bandwidth memory within a rack or data center. In some alternative embodiments, the optical signal in the optical interposer may be converted into an electrical signal in the optical interposer and then electrically coupled to a chip covering the optical interposer.

[0024] Figure 1A is a partially simplified schematic diagram of a memory device structure 100 constructed according to some embodiments, Figure 1B FIG. 1 is a simplified cross-sectional view of a portion of a memory device structure (or IC structure) 100. Figure 1A and Figure 1B , the memory device structure 100 includes an optical interposer 102 to provide communication between various IC modules, including receiving, transmitting, and sending signals in optical mode.

[0025] The optical interposer 102 includes an integrated optical interconnect (structure) 104, which also includes various waveguides for transmitting optical signals; and may also include optical microlenses, optical couplers (such as grating couplers), other optical couplers, or a combination thereof, to receive and send optical signals. In some embodiments, the waveguides formed in the optical interposer 102 include horizontal waveguides that are arranged parallel (or substantially parallel) to each other and extend laterally, and vertical waveguides that are arranged parallel (or substantially parallel) to each other and extend vertically to form an interconnect structure that transmits optical signals from one location to another and is also coupled to the overlying chip stack. In particular, the waveguides are designed to transmit broadband optical signals, so that different optical signals of different wavelengths can be transmitted in parallel.

[0026] In some embodiments, the optical interposer 102 may also include an electrical interconnect structure 106 to electrically couple the chip stack to other structures, such as a printed circuit board (PCB) bonded to the back side of the optical interposer 102, thereby providing some low-frequency signals, such as a power line Vdd and a ground line Vss from the PCB.

[0027] The integrated optical interconnect 104 is similar to the electrical interconnect structure 106, but is designed to carry and transmit optical signals instead of electrical signals, while the electrical interconnect structure 106 carries and transmits electrical signals. The electrical interconnect structure 106 includes metal lines for horizontal wiring and metal vias for vertical wiring. These metal lines and metal vias are embedded in one or more dielectric materials to achieve appropriate isolation. The integrated optical interconnect 104 includes waveguides made of optically transparent materials (such as silicon oxide). These waveguides are formed on a substrate and embedded in one or more appropriate materials, such as materials with a higher refractive index, to achieve complete reflection and reduce signal loss. The electrical interconnect structure 106 and the integrated optical interconnect 104 are interwoven in the optical interposer 102, but are independent of each other and are designed to provide dual signal paths for electrical and optical signals.

[0028] The memory device structure 100 also includes various chip stacks 110 formed on the optical interposer 102. Each chip stack 110 includes two or more chips stacked vertically on the optical interposer 102. The chip stacks 110 include a memory chip stack 110M and a memory I / O chip stack 110I coupled to the integrated optical interconnect 104 of the optical interposer 102. The memory device structure 100 may also include one or more electrical IC chip stacks 110E coupled to the integrated optical interconnect 104. All of these IC chip stacks 110M, 110I, 110E (collectively referred to as chip stacks 110) are coupled together through the integrated optical interconnect 104 of the optical interposer 102. Although Figure 1AOnly two memory chip stacks 110M are shown for illustration, but it is understandable that the number of memory chip stacks 110M can be any appropriate number, such as 3, 4 or 5. Similarly, it is understandable that the number of EIC chip stacks 110E can be any appropriate number, such as 2, 3 or 4, each of which is designed for its intended purpose, such as data processing, in-memory computing, imaging processing, other appropriate functional modules or combinations thereof.

[0029] Various IC chip stacks 110M, 110I, 110E are disposed on the optical interposer 102 and are arranged adjacent to each other at appropriate intervals to optimize isolation and packaging density. Each IC module includes Figure 1B The chip stack shown. For example, each chip stack includes a photonic IC (PIC) chip 114 stacked on an optical interposer 102 and a functional IC chip 112 (e.g., a memory chip 112M, a memory I / O chip 112I, or an EIC chip 112E, collectively referred to as numeral 112) stacked on the PIC chip 114. As described above, the memory chip 112M includes a memory body (or memory macro) 113 having a plurality of memory cells configured in an array and formed in a single substrate (such as a silicon substrate). The memory I / O chip 112I includes an I / O circuit formed in a substrate, which is designed to perform input / output functions on these memory chips 112M. In some embodiments, the I / O circuit of the memory I / O chip 112.I includes various I / O functional circuit blocks, such as a bit line decoder, a word line decoder, a bit line multiplexer, other suitable circuit blocks, or combinations thereof. Note that the memory I / O chip 112I is not directly connected to the memory chip 112M, but is connected via the EIC chip 112E and the optical interposer 102, which will be further described later. Figure 1B The device (not shown in the figure but will be described in other figures) includes an integrated circuit formed on a substrate, which is designed for data processing, storage computing functions, imaging sensing modules, other appropriate functional modules or combinations thereof.

[0030] In each chip stack, a functional IC chip 112 (such as a memory chip 112M, a memory I / O chip 112I, or an EIC chip 112E) is stacked on a photonic IC chip 114 and bonded to the photonic IC chip 114 through electrical communication therebetween. In some embodiments, the bonding between the functional IC chip 112 and the underlying PIC chip 114 includes a bonding interface 116 having an appropriate bonding structure (such as a hybrid bonding structure). In the hybrid bonding structure, the bonding interface 116 includes a dielectric dielectric bonding surface and a metal metal bonding surface. In particular, the metal metal bonding surface provides a conductive trace to provide electrical coupling between the PIC chip 114 and the corresponding functional IC chip 112.

[0031] As for the PIC chips 114, each PIC chip 114 includes an optoelectronic structure, such as a microlens, a grating coupler, an optical modulator, a photodetector (such as a photodiode or PD) and other components, a transimpedance amplifier (TIA) or a combination thereof, to receive an optical signal from the underlying optical interposer 102; convert the optical signal into an electrical signal, and send the electrical signal to the overlying functional chip 112; receive an electrical signal from the overlying functional chip 112; and convert the electrical signal into an optical signal, and send the optical signal to the underlying optical interposer 102. In particular, the PIC chip 114 includes a plurality of microring resonators (also referred to as optical ring resonators or ORS) 120 with different ring sizes (such as radii) to select optical signals of a specific wavelength λ (such as λ1, λ2, ..., λi, ...λn) using different resonant wavelengths λ (or frequencies). These microring resonators 120 are configured to be associated with corresponding bit lines (or word lines). In some embodiments, each type of microring resonator 120 having a particular size may include two or more identical microring resonators configured in series to enhance signal selection and signal strength. Thus, some of the PIC chips 114 include arrays of microring resonators 120 having different characteristics (e.g., different sizes, different materials) configured in an array and used as an address decoder. Different microring resonators 120 in each PIC chip 114 may be formed with different characteristics (e.g., different sizes and / or materials) to work with different light of various wavelengths. Since different light of different wavelengths can be transmitted / processed simultaneously without interference, the storage bandwidth can be further improved.

[0032] The communication between the various functional IC chips 112 is also described. The electrical signal from the functional IC chip 112 is sent to the PIC chip 114 below; the electrical signal is converted into an optical signal by the corresponding PIC chip 114; the optical signal is transmitted to another PIC chip 114 through the waveguide of the optical interposer 102; the optical signal is converted back into an electrical signal; and the electrical signal is sent to the overlying functional IC chip 112. The communication between the memory chip 112M and the memory I / O chip 112I is used as an example for explanation. When the memory I / O chip 112I generates an electrical signal and addresses it to a specific bit line (such as bit line i), the electrical signal is converted into an optical signal carried in light with a specific wavelength λi, which matches the resonant wavelength λi of the microring resonator 120 associated with the bit line. The optical signal is then sent to the memory chip stack 110M through the waveguide of the optical interposer 102. The PIC chip 114 of the memory chip stack 110M uses an array of microring resonators 120 to select an optical signal that sends an expected path associated with the microring resonant cavity 120 having a resonant wavelength λi. The PIC chip 114 also converts the optical signal into an electrical signal through a suitable optical-to-electrical (OE) converter 122 (e.g., a photodiode, other suitable OE converters, or a combination thereof). The electrical signal can be further processed, such as amplified using a suitable amplifier 124 (e.g., a transimpedance amplifier (TIA)). The electrical signal is also sent to a target bit line (or word line) 126, such as through a multiplexer 128. Power signals such as high power Vdd and low power Vss can be provided to the memory cells of the memory macro 113 through appropriate circuits such as drivers 130. The communication between the various functional IC chips 112 and the PIC chip 114 can include any appropriate coupling and communication structures and technologies (such as Serdes) to achieve high-speed effects. Serdes technology is used to transmit high-speed data between memory, processors, and network interfaces, and it is designed for data centers, telecommunications, and high-performance computing.

[0033] In one embodiment, a multiplexer in the memory chip can match the operating speed between the optical modulator and the memory macro. For example, the data from the multiplexer of the memory macro has a lower data rate, while the optical modulator has a higher data rate. The multiplexer or additional circuitry can be designed to transmit more data in parallel and send this data to the optical modulator at the same time at a matching speed.

[0034] Reference FIG. 2A to FIG. 2C The memory device structure 100 is described in further detail. Figure 2A is a partially simplified schematic diagram of a memory device structure 100 constructed according to some embodiments, Figure 2B is a simplified cross-sectional view of a portion of a memory device structure 200, Figure 2Cis a partially simplified schematic diagram of the memory device structure 100. In particular, Figure 2C Only one memory chip stack 110M is included. FIG. 2A to FIG. 2C The memory device structure 100 in FIG. Figure 1A and Figure 2B For simplicity, similar descriptions are not repeated here.

[0035] refer to FIG. 2A to FIG. 2C , the memory device structure 100 includes an optical interposer 102 for providing communication between various IC modules, including receiving, transmitting and sending signals in optical mode. As described above, the memory device structure 100 also includes various chip stacks 110, such as a memory chip stack 110M, a memory I / O chip stack 110I and an EIC chip stack 110E disposed on the optical interposer 102, bonded to the optical interposer 102 and optically coupled. The memory device structure 100 also includes a laser source chip 132 disposed near the PIC chip 114. The laser source chip 132 is designed to be a laser source that generates broadband laser light, and is coupled to an adjacent PIC chip 114 to provide light thereto. In some embodiments, the laser source chip 132 includes one or more light generating devices (such as light emitting diodes or LEDs) to generate laser light of different wavelengths. For example, when an electrical signal is sent to the PIC chip 114, the PIC chip 114 receives light from an adjacent laser source chip 132, and modulates the light to carry a signal in the electrical signal, thereby forming an optical signal. Thereafter, the optical signal is sent to the optical interposer 102, and is further transmitted to other chip stacks 110, such as the memory chip stack 110M. In some embodiments, the laser source chip 132 is coupled to the adjacent PIC chip 114 through the optical interposer 102. Therefore, the interface 134 between the laser source chip 132 and the optical interposer 102 provides a mechanism for optical coupling (optical communication). For example, the interface 134 includes a portion made of a transparent material (such as silicon oxide) to transmit light to or from the waveguide of the optical interposer 102. Figure 2C As shown, the same interface 134 is formed between the PIC chip 114 and the optical interposer 102. In some embodiments, the laser source chip 132 and the PIC chip 114 are in lateral contact to form an interface with direct optical coupling.

[0036] The storage device structure 100 includes one or more fiber array units (FAUs) 136 that serve as input / output ports 138 of the storage device structure 100. The FAUs 136 include a plurality of optical fibers configured in an array and connected to input / output signals in an optical mode. The FAUs 136 are attached to one or more chip stacks 110, such as an EIC chip stack 110E (e.g., Figure 2B), attached to the memory I / O chip stack 110I (as shown in Figure 2B ), attached to other chip stacks, or a combination thereof. Figure 2A In some embodiments shown, four fiber array units 136 are attached to the memory I / O chip stack 112I. Figure 2B In some embodiments shown, one or more fiber array units 136 are attached to the EIC chip 112E.

[0037] The memory device structure 100 includes a dielectric component 140 having one or more dielectric materials (eg, silicon oxide). In some embodiments, the dielectric component 140 fills the gap between the chip stacks 110, such as Figure 3G As shown. In some embodiments, FAU 136 is disposed on dielectric component 140 so that dielectric component 140 serves as an optical path for optical signals starting from and reaching FAU 136. To further implement these embodiments, dielectric component 140 includes a curved top portion to serve as a microlens for the optical signal. An optical device, such as a grating coupler or a reflector, is formed below the dielectric component, for example, on a portion of PIC chip 114 below dielectric structure 140.

[0038] The memory device structure 100 is also sealed in an IC package 142 such as a 3DIC package. In some embodiments, the memory device structure 100 is sealed in a single package to surround various chip stacks 110. In some embodiments, various chip stacks 110 are sealed in two or more package structures in consideration of design requirements, stress and sealing effects and / or other relevant factors. In various embodiments, the sealed package structure 142 includes various sealing components, such as a metal cover, a metal frame, a metal housing, a bottom filling material, glue, a thermal interface material, a heat sink, other sealing components, or a combination thereof, which are configured to form one or more appropriate sealing structures, such as a hermetic sealing structure.

[0039] The memory device structure 100 is also attached to a printed circuit board (PCB) 144, another 3DIC structure, a substrate, an interposer, other suitable structures, or a combination thereof. The memory device structure 100 is bonded and electrically coupled to the PCB 144. For example, the bonding surface therebetween includes a controlled collapse chip connection (C4) structure, a microbump, a hybrid bonding structure, other suitable bonding features, or a combination thereof.

[0040] As described above, the optical interposer 102 may additionally include an electrical interconnect structure 106 to provide a mechanism to electrically connect the PCB 144 to the chip stack 110. To further implement this embodiment, high frequency signals are optically coupled to the memory device structure at high speed through the FAU 136, while low frequency signals (such as power lines Vss and Vdd) are electrically coupled to the memory device structure through the PCB 144 without affecting the overall system performance.

[0041] The memory device structure 100 may have other suitable structures and may include additional components, such as additional chip stacks or chips. The memory device structure 100 is formed by suitable methods, such as the following reference Figures 3A to 3G Describe the method.

[0042] Figures 3A to 3G are partial, simplified, cross-sectional views of a memory device structure 100 constructed in accordance with some embodiments at various stages of fabrication. Figure 4 is a flow chart of a method 200 of manufacturing a memory device structure 100 according to some embodiments. According to some embodiments, reference is made to Figures 3A to 3G and Figure 4 The memory device structure 100 and the method 200 for manufacturing the same are described in further detail.

[0043] refer to Figure 3A and Figure 4 , in operation 202, various memory macros 112M are formed on a first substrate, such as a silicon substrate or other suitable substrate. The memory macros 112M include the same type of memory structure, such as SRAM, DRAM, NAND, non-volatile memory devices, magnetic memory devices, resistive memory devices, or other types of memory devices, so that all memory macros 112M can be controlled by the same memory I / O chip 112I through the integrated optical interconnect 104 of the optical interposer 102. Each memory macro 112M includes a plurality of memory cells configured in an array, and may additionally include other circuit components, such as drive circuits, amplifiers, multiplexers, or combinations thereof. Operation 202 includes forming the memory macros 112M through various manufacturing steps, including various front-end process (FEOL) processing steps and back-end process (BEOL) processing steps, such as deposition, etching, photolithography processes, and ion implantation. Operation 202 also includes a chemical mechanical polishing (CMP) process to flatten the top surface and cut (sawing) into individual memory chips (also referred to as 112M).

[0044] Reference Figure 3B and Figure 4, in operation 204, various PIC structures 114 are formed on the second substrate. The PIC structure 114 includes a second substrate, such as a silicon substrate, various dielectric layers, and a plurality of optical structures in the dielectric layers. For example, the plurality of optical structures may include the above-mentioned grating couplers, modulators, photodetectors, and waveguides. Operation 204 includes FEOL and BEOL processing steps. Each PIC structure 114 is a single PIC chip after later dicing.

[0045] Still refer to Figure 3B and Figure 4 , in operation 206, the memory macro chip 114M is bonded to the second substrate above the PIC structure 114. The bonding structure and bonding method may include any suitable bonding structure and method. In the disclosed embodiment, the bonding method includes a chip-on-wafer (CoW) bonding method. For example, each memory chip 112M is picked up and placed on the PIC structure 114 on the second substrate and bonded to the PIC structure 114. In some embodiments, the bonding structure includes a hybrid bonding structure having a dielectric-dielectric bonding interface and a metal-metal bonding interface, providing conductive wiring for electrical coupling between the memory chip 112M and the PIC chip 114. In some embodiments, other functional IC structures 112, such as memory I / O chips 112I and EIC chips 112E, are formed on the same substrate or separately formed on other substrates, and are disposed on the PIC structure 114 and bonded to the second substrate.

[0046] refer to Figure 3C and Figure 4 , at operation 208, one or more dielectric materials are filled into the gaps between the memory chips 112M, thereby forming a dielectric filling component (or dielectric component) 140. In some embodiments, the dielectric component 140 includes silicon oxide, is transparent and can be used as an optical path as described above. Operation 208 includes deposition and subsequent CMP, and may also include other processing steps. Deposition may include chemical vapor deposition (CVD), flowable CVD (FCVD), other suitable deposition techniques, or combinations thereof.

[0047] Still refer to Figure 3C and Figure 4 At operation 210, the second substrate is cut into a plurality of chip stacks 110 along the scribe lines 152, each chip stack 110 having a PIC chip 114 and a memory macro chip 114M stacked and bonded together. Other functional IC chips 112I and 112E are also bonded to the PIC structure 114 and cut into corresponding chip stacks, such as 110I and 110E.

[0048] Reference Figure 3D and Figure 4, at operation 212, various laser source chips 132 are formed. Operation 212 includes forming a laser source structure (also indicated by numeral 132) on a third substrate (e.g., a silicon substrate or other suitable substrate). Operation 212 includes FEOL and BEOL processing steps to form the laser source structure 132. Operation 212 also includes cutting the laser source structure 132 into laser source chips 132.

[0049] Reference Figure 3E and Figure 4 , at operation 214, an optical interposer 102 is formed on a fourth substrate. As described above, the optical interposer 102 includes an integrated optical interconnect 104 having a waveguide, and may include other optical components, such as grating couplers, mirrors, microlenses, amplifiers, or combinations thereof. The optical interposer 102 includes silicon, silicon oxide, silicon nitride, other suitable dielectric materials, or combinations thereof to form waveguides and other optical elements. Operation 214 includes deposition, photolithography, etching, CMP, or combinations thereof. In some examples, the waveguide includes a dielectric material component surrounded by another dielectric material of a lower refractive index, such as amorphous silicon or silicon nitride surrounded by silicon oxide; or silicon nitride surrounded by silicon. In the last case, the waveguide can be formed as a silicon nitride component in a silicon substrate. The waveguide includes horizontal waveguides and vertical waveguides to form an optical interconnect structure. In some embodiments, the optical interposer 102 also includes an electrical interconnect structure 106 having various metal lines and vias to provide additional electrical communications, such as communications between a PCB and a chip stack 110. The formation of the electrical interconnect structure 106 includes any suitable method, such as damascene processing, deposition and patterning (also including photolithography and etching), or a combination thereof. The optical interposer 102 and operation 214 will be described in further detail later.

[0050] Reference Figure 3F and Figure 4 , in operation 216, the chip stack 110 and the laser source chip 132 are bonded to the optical interposer 102. The bonding structure and bonding method may include any suitable bonding structure and method. In the disclosed embodiment, the bonding method includes a chip-on-wafer (CoW) bonding method. For example, the chip stack 110 and the laser source chip 132 are picked up and placed on the optical interposer 102. In some embodiments, the bonding structure includes a hybrid bonding structure having a dielectric-dielectric bonding interface and a metal-metal bonding interface. The dielectric-dielectric bonding interface or portions thereof provide an optical path, and the metal-metal bonding interface provides conductive wiring for electrical coupling between the optical interposer 102 and the PIC chip 114. In addition, other chip stacks 110, such as 110I and 110E, are also bonded to the optical interposer 102 in a similar manner.

[0051] refer to Figure 3G and Figure 4 At operation 218, one or more dielectric materials are filled in the gap between the chip stack 110 and the laser source chip 132 to form a dielectric filling member (or dielectric member), and is represented by the same numeral 140. In some embodiments, the dielectric member 140 includes silicon oxide, which is transparent and can be used as an optical path as described above. Operation 208 includes deposition and subsequent CMP, and may also include other processing steps. Deposition may include CVD, FCVD, other suitable deposition techniques, or combinations thereof.

[0052] Still refer to Figure 3G and Figure 4 At operation 220, the optical fiber array unit 136 is attached to the storage device structure 100, for example, to the dielectric component 140, so that the dielectric component 140 can serve as an optical path to the optical fiber array unit 36. The optical fiber array unit 136 is connected to the optical fiber 138, which serves as an input / output port of the storage device structure 100 in the optical mode. The optical fiber array unit 136 is bonded to the storage device structure 100 by a suitable technique (such as glue or other bonding methods). Operation 220 may also include other processing steps, such as sealing the storage device structure 100 to form a sealed packaging structure 142, such as Figure 2B shown.

[0053] Figure 5 is a simplified cross-sectional view of a portion of a memory device structure 100 according to some embodiments. In particular, Figure 5 The optical interposer 102 , the chip stack 110 , and various bonding interfaces are shown in greater detail and will be described in further detail.

[0054] exist Figure 5 In the embodiment, the memory device structure 100 includes an optical interposer 102 formed on a substrate 302. In an embodiment, the substrate 302 is a semiconductor substrate, such as a silicon substrate (e.g., a silicon wafer or a portion thereof). In addition, or alternatively, the substrate 302 may include other semiconductor materials, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used as the substrate 302. In some embodiments, the substrate 302 may include a glass substrate or a ceramic substrate.

[0055] In the illustrated embodiment, the optical interposer 102 includes a dielectric layer 304 formed on a substrate 302. In an embodiment, the dielectric layer 304 includes silicon dioxide, and various optical structures 312, 314, and 316 are formed in the dielectric layer 304 and include optical structures based on silicon nitride. In other words, the optical structures 312, 314, and 316 can use the difference between the refractive index of silicon nitride and silicon dioxide to confine and transmit light. For example, the optical structures 312, 314, and 316 may include a dielectric material with a higher refractive index to achieve total reflection. The dielectric layer 304 may include other suitable dielectric materials to achieve the same confinement effect in alternative embodiments. In various embodiments, the optical interposer 102 may include a silicon-based photonic device embedded in the silicon oxide dielectric layer 304 or a silicon nitride-based photonic device embedded in the silicon oxide dielectric layer 304.

[0056] In an embodiment, the optical structures 312 and 314 include waveguides for sending optical signals to and receiving optical signals from optical structures in the dielectric layer 304. In some embodiments, the optical structures 312 and 314 are disposed at different vertical levels in the dielectric layer 304. In an embodiment, the optical structure 316 may include an edge coupler for coupling the optical structure 314 (e.g., a waveguide) with the optical fiber array unit 136, which may be disposed on the side or top of the optical interposer 102. In an embodiment, the edge coupler 315 includes multi-layer optical paths that provide a high tolerance for alignment with the optical fiber array unit 136. The optical fiber array unit 136 may also be coupled with an optical fiber 138 for connecting with another structure or system (not shown) for inputting / outputting signals.

[0057] The formation of the optical interposer 102 may include any suitable method, such as deposition, etching, and photolithography processes, to form optical structures of different levels layer by layer. In some embodiments, the method may include forming each layer separately and then bonding them together, which increases the flexibility of integrating different types of photonic devices into the optical interposer.

[0058] The optical interposer 102 and the overlying bonded chip stack 110 can be further bonded to another substrate 144. In some embodiments, the substrate 144 is a printed circuit board (PCB), such as a FR4 PCB. FR4 is a type of PCB substrate made of a flame retardant epoxy resin and glass fiber composite material. In some embodiments, the substrate 144 may include an organic dielectric material, such as a polymer, which may include polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), other suitable polymer-based materials, or combinations thereof. The substrate 144 also includes a metallization pattern 306 (such as metal traces, metal pads, and metal vias) on or in the organic material. The metallization pattern 306 may include a metal or metal alloy, such as copper, titanium, tungsten, aluminum, etc., or a combination thereof, and may be formed using a deposition and patterning process.

[0059] The substrate 302 and the substrate 144 are electrically and mechanically coupled or connected by a conductive connector 308. The conductive connector 308 can be a ball grid array (BGA) connector, a solder ball, a metal pillar, a C4 bump, a micro bump, a bump formed by electroless nickel-electroless palladium immersion gold technology (ENEPIG), etc. The conductive connector 308 can be formed of a metal or a metal alloy, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 308 is formed using methods such as evaporation, sputtering, electroplating, electroless plating, printing, solder transfer, ball placement, reflow, etc. The conductive connector 308 is connected to a conductive pad (or under bump metal) 310 on the bottom surface of the substrate 302 and to a metallization pattern 306 on the top surface of the substrate 144.

[0060] Various chip stacks 110 are bonded to the optical interposer 102. Each chip stack 110 includes a PIC chip 114 and a functional IC chip 112, such as a memory chip 112M, a memory I / O chip 112I, an EIC chip 112E, or a combination thereof. In some embodiments, the functional IC chip 112 of the memory device structure 100 includes a plurality of memory chips 112M, a single memory I / O chip 112I, and one or more EIC chips 112E.

[0061] The PIC chip 114 includes a substrate, various optical structures and electrical structures formed thereon. The optical structure includes an optical processing structure for receiving, transmitting, and modulating optical signals; and an optoelectronic structure for converting optical signals into electrical signals or vice versa. These structures are also collectively referred to as optical structures. The electrical structure includes various structures for processing electrical signals, such as various devices (including transistors, capacitors, diodes, etc.) and interconnect structures for coupling these devices. Figure 5 , optical structures 312, 314, 316, 318 are shown for illustration purposes according to some embodiments.

[0062] In one embodiment, the optical structure or a subset thereof is formed in one or more dielectric layers 311 including silicon dioxide. In alternative embodiments, the dielectric layer 311 may include other dielectric materials. In an embodiment, the optical structure 312 may include a grating coupler 312. In an embodiment, the grating coupler 312 includes several segments configured periodically to implement a grating mechanism. The grating coupler 312 may be coupled to a laser generator, such as from a laser source chip 132 (e.g., Figure 3F ), and is configured to convert a laser signal into a modulated optical signal, and vice versa. In some embodiments, the grating coupler 312 may include a metal or dielectric material having a dielectric constant higher than that of silicon dioxide or the dielectric layer 311.

[0063] In an embodiment, optical structure 314 may include a photonic modulator and is referred to as modulator 314. In some embodiments, modulator 314 may include silicon, germanium, tin, a group III element such as aluminum, indium, or gallium, and / or a group V element such as arsenic, phosphorus, antimony. In an embodiment, modulator 314 may be configured to convert a laser signal into a modulated optical signal that includes or carries a high-speed data signal. Modulator 314 may be electrically coupled to die 402 and / or controlled by die 402, as will be discussed further below.

[0064] In an embodiment, the optical structure 316 may include a photodetector and is referred to as a photodetector 316. In an embodiment, the photodetector 316 may include a photodiode (or photo-controlled diode), a phototransistor, or other types of photodetectors. The photodetector 316 is configured to convert an optical signal into an electrical signal. In some embodiments, the photodetector 316 may include silicon, germanium, tin, a group III element such as aluminum, indium, or gallium, and / or a group V element such as arsenic, phosphorus, or antimony.

[0065] In an embodiment, optical structure 318 may include a waveguide, and is referred to as waveguide 318. In an embodiment, waveguide 318 includes a silicon waveguide that uses the difference between the refractive index of silicon and dielectric layer 311 (e.g., silicon dioxide) to confine and transmit light. In alternative embodiments, waveguide 318 may include a dielectric waveguide or a plasma waveguide. The dielectric waveguide may include patterned silicon nitride, amorphous silicon, or a high dielectric material surrounded by a low dielectric constant material (e.g., silicon dioxide) of dielectric layer 311. Plasma waveguides may include patterned metal nanowires surrounded by a dielectric material of dielectric layer 311.

[0066] The PIC chip 114 is bonded to the optical interposer 102 through the bonding interface 134 to be optically coupled to each other and communicate through optical signals. The optical structure in the optical interposer 102 and the optical structure in the PIC chip 114 are designed and configured to have such communication. For example, the waveguides in the optical interposer 102 and the PIC chip 114 have vertical waveguides that are aligned and in direct contact with each other.

[0067] The PIC chip 114 also includes an electrical interconnect structure 322, which also includes metal lines and through-holes. The functional IC chip 112 is bonded to the PIC chip 114 through a bonding interface 116 to electrically communicate between them, for example, through a conductive connector 324. In some embodiments, the bonding interface 116 between the functional IC chip 112 and the following PIC chip 114 includes a suitable bonding structure, such as a hybrid bonding structure. In the hybrid bonding structure, the bonding interface 116 includes a dielectric-dielectric bonding surface and a metal-metal bonding surface. In particular, the metal-metal bonding surface provides a conductive trace to provide electrical coupling between the PIC chip 114 and the corresponding functional IC chip 112.

[0068] In some embodiments, the optical interposer 102 further includes an electrical interconnect structure 106 to provide electrical communication between the PCB 144 and the PIC chip 114. In an embodiment, the optical interposer 102 includes through-substrate via (TSV) features 326, metal lines 328, and vias 330 to form the electrical interconnect structure 106 to provide electrical connection between the PIC chip 114 (and the functional IC chip 112) and the PCB 144 through the bonding interface between the PCB 144 and the optical interposer 102 and the bonding interface 134 between the PIC chip 114 and the optical interposer 102.

[0069] Other components and processes may also be included in the above embodiments. For example, the memory device structure may include other optical structures and electrical structures, such as back reflectors, optical amplifiers, digital devices (such as bipolar transistors), passive devices (such as capacitors and inductors), other suitable devices, or combinations thereof. In another example, a test structure may be included to assist in verification testing of the memory device structure 100. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that incorporates intermediate verification of known good dies (or known good device layers) to increase yield and reduce costs.

[0070] The present disclosure provides an integrated circuit (IC) structure with a memory device and an optical link and a manufacturing method thereof. In particular, the sending and receiving nodes in the optical data network can be interconnected through an interposer, and the optical signal is transmitted through the interposer. In addition, the memory device structure includes a plurality of memory macros, each of which has a memory cell body configured in an array and formed in an IC chip. Each memory chip is stacked on a photonic IC chip, and the photonic IC chip is further stacked on an optical interposer, thereby forming a chip stack above the optical interposer in a 3DIC packaging structure. Multiple memory chip stacks, memory I / O chip stacks, and one or more EIC chip stacks are coupled to the optical interposer and communicate with each other in an optical mode through the optical interposer. All functional chips, such as memory chips, memory I / O chips, and EIC chips, have similar chip stacking configurations and are coupled together through an optical interposer, which provides a universal optical interface for integrating different memories, while having high coupling speed and higher efficiency. The signal is transmitted through the optical interposer in an optical mode, converted into an electrical signal by the corresponding PIC chip, and further coupled to the overlying chip (such as a memory chip, a memory I / O chip, or an EIC chip) in the form of an electrical signal.

[0071] The disclosed structure provides a memory macro embedded COUPE system on an optical interposer. The disclosed memory device structure is capable of expanding memory capacity beyond I / O requirements to consider different I / O requirements, such as double data rate memory (DDR) and low power double data rate memory (LPDDR). The disclosed memory device structure also enables high performance computing (HPC) or large language models (LLM) in artificial intelligence (AI), which require high capacity and bandwidth memory within a rack or data center.

[0072] Although not limiting, one or more embodiments of the present disclosure provide many benefits to semiconductor devices and manufacturing, such as three-dimensional integrated circuits or systems with optical devices. For example, multiple memory macros are directly optically linked to a memory I / O module, and the memory capacity is greatly increased. Multiple memory chips are able to share a single memory I / O chip. The data of these memory chips can be transmitted to the memory I / O chip through optical communication implemented by the PIC chip and the waveguide in the optical interposer. The multiplexer in the memory chip can match the operating speed between the optical modulator and the memory macro. Different microring resonators in each PIC chip can form microring resonators with different characteristics (e.g., different sizes and / or materials) to work with different light of various wavelengths. Since different light of different wavelengths can be transmitted / processed simultaneously without interference, the storage bandwidth can be further improved.

[0073] The disclosed structure is also applicable to in-memory computing (CIM) or near-memory computing (NMC). In another example, an embodiment of the present disclosure provides an optical interposer that can be used in a three-dimensional integrated circuit or system. The optical interposer provides optoelectronic devices and waveguides. In various embodiments, the interface between the optical interposer and the PIC chip is optically coupled, which enables high-speed and efficient communication between memory macros, memory I / O chips, and EIC chips. Various bonding interfaces and bonding structures can use existing or future developed bonding methods. The disclosed structures and methods can be easily integrated into existing semiconductor (such as CMOS) manufacturing processes.

[0074] In one exemplary aspect, the present disclosure provides an integrated circuit (IC) structure. The IC structure includes an optical interposer having an optical waveguide; a plurality of chip stacks disposed on the optical interposer, each of the plurality of chip stacks including a first photonic IC chip and a memory chip located on the first photonic IC wafer; and a plurality of first laser source chips disposed adjacent to the plurality of chip stacks, respectively, wherein the optical waveguide in the optical interposer is configured as an optical interconnect structure to couple with the memory chip through the first photonic IC chip.

[0075] In some embodiments, the optical interposer further includes a conductive component configured as an electrical interconnect structure to electrically couple with the memory chip.

[0076] In some embodiments, the optical interposer includes a substrate; the optical waveguide is formed on the substrate and is made of silicon or silicon nitride; and the conductive component is formed on the substrate and is made of metal, metal alloy, or a combination thereof, wherein the optical waveguide and the conductive component are interwoven and independently coupled to the memory chip.

[0077] In some embodiments, the optical waveguide includes a lateral waveguide and a horizontal waveguide configured to guide light to the first photonic integrated circuit chip.

[0078] In some embodiments, the integrated circuit structure also includes: a memory input / output (I / O) chip stack disposed above the optical interposer, wherein the memory input / output chip stack includes a second photonic integrated circuit chip; a memory input / output chip located on the second photonic integrated circuit chip; and a second laser source chip disposed adjacent to the memory input / output chip, wherein the optical waveguide in the optical interposer is configured to optically couple the memory input / output chip through the second photonic integrated circuit chip.

[0079] In some embodiments, the integrated circuit structure further comprises: an electrical chip stack disposed above the optical interposer, wherein the electrical chip stack comprises a third photonic integrated circuit chip;

[0080] an electrical integrated circuit chip located above a third photonic integrated circuit chip; and a third laser source chip disposed adjacent to the electrical integrated circuit chip, wherein the optical waveguide in the optical interposer is configured to optically couple the electrical integrated circuit chip through the third photonic integrated circuit chip.

[0081] In some embodiments, the integrated circuit structure further includes: an optical fiber array unit attached to the memory input / output chip and configured to provide input and output signals in an optical mode.

[0082] In some embodiments, each of the first laser source chips is configured to provide light to the first photonic chip in a corresponding one of the chip stacks.

[0083] In some embodiments, the optical interposer, the chip stack, and the first laser source chip are sealed in the same package.

[0084] In some embodiments, each of the first photonic integrated circuit chips includes a plurality of microring resonators having different sizes, the microring resonators being designed to have different resonant wavelengths.

[0085] In some embodiments, the first photonic integrated circuit chip and the chips in the corresponding stack of each of the chip stacks are bonded together by hybrid bonding and are electrically coupled by bonding metal features in a bonding interface.

[0086] In another example aspect, the present disclosure provides an integrated circuit (IC) structure. The IC structure includes an optical interposer having an optical waveguide; a plurality of memory chip stacks disposed on the optical interposer, each of the plurality of memory chip stacks including a first photonic IC chip and a memory chip disposed on and bonded to the first photonic IC wafer; a plurality of first laser source chips disposed adjacent to the plurality of memory chip stacks, respectively; a memory input / output (I / O) chip stack disposed on the optical interposer, wherein the memory I / O chip stack includes a second photonic IC chip and a memory I / O chip disposed on and bonded to the second photonic IC chip; and a second laser source chip disposed adjacent to the memory I / O chip stack, wherein the optical waveguide in the optical interposer is configured to couple the memory chip to the memory I / O chip through the first and second photonic IC chips.

[0087] In some embodiments, the optical waveguide in the optical interposer is configured as an optical interconnect structure to optically couple the waveguide with the first photonic integrated circuit chip; and the first photonic integrated circuit chip is electrically coupled to the memory chip.

[0088] In some embodiments, the optical interposer further includes a conductive component configured as an electrical interconnect structure to electrically couple with the memory chip and the first photonic integrated circuit chip to provide power to the memory chip and the first photonic integrated circuit chip.

[0089] In some embodiments, the integrated circuit structure further includes: an optical fiber array unit attached to the memory input / output chip and configured to provide input and output signals in an optical mode.

[0090] In some embodiments, each of the first laser source chips is configured to provide light to the first photonic chip in a corresponding one of the chip stacks.

[0091] In some embodiments, each of the first photonic integrated circuit chips includes a plurality of microring resonators having different sizes, the microring resonators being designed to have different resonant wavelengths.

[0092] In some embodiments, the first photonic integrated circuit chip and the chips in each corresponding chip stack in the chip stack are bonded together by hybrid bonding and are electrically coupled by bonding metal features in a bonding interface; and the optical interposer, the chip stack and the first laser source chip are sealed in the same package.

[0093] In another example aspect, the present disclosure provides a method. The method includes forming a photonic integrated circuit (IC) structure on a first substrate; bonding a memory chip to the photonic IC structure formed on the first substrate; sawing the first substrate to obtain memory chip stacks each including a photonic IC structure and a memory chip; forming an optical interposer; and bonding the memory chip stack and the laser source chip on the optical interposer in a configuration where one of the laser source chips is adjacent to one of the memory chip stacks.

[0094] In some embodiments, the method further includes: bonding a memory input / output (I / O) chip stack and a second laser source chip on the optical interposer so that the second laser source chip is adjacent to the memory input / output chip stack, the memory input / output chip stack comprising a second photonic integrated circuit chip and a memory input / output chip bonded to the second photonic integrated circuit chip; filling gaps between the memory chips before sawing the first substrate; and attaching a fiber array unit to the memory input / output chip stack.

[0095] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit (IC) structure, comprising: an optical intermediary layer having an optical waveguide; a plurality of chip stacks disposed above the optical interposer, each of the plurality of chip stacks comprising a first photonic integrated circuit chip and a memory chip located above the first photonic integrated circuit chip; and A plurality of first laser source chips are respectively arranged adjacent to the plurality of chip stacks, wherein the optical waveguide in the optical interposer is configured as an optical interconnect structure to be coupled with the memory chip through the first photonic integrated circuit chip.

2. The integrated circuit structure according to claim 1, wherein: The optical interposer also includes a conductive component configured as an electrical interconnect structure to electrically couple with the memory chip.

3. The integrated circuit structure according to claim 2, wherein: The optical interposer includes a substrate; The optical waveguide is formed on the substrate and is made of silicon or silicon nitride; and The conductive component is formed on the substrate and is made of metal, metal alloy or a combination thereof, wherein the optical waveguide and the conductive component are interwoven and independently coupled to the memory chip.

4. The integrated circuit structure according to claim 3, wherein: The optical waveguide includes a lateral waveguide and a horizontal waveguide configured to guide light to the first photonic integrated circuit chip.

5. An integrated circuit (IC) structure comprising: an optical intermediary layer having an optical waveguide; a plurality of memory chip stacks disposed above the optical interposer, each of the plurality of memory chip stacks comprising a first photonic integrated circuit chip and a memory chip disposed above and bonded to the first photonic integrated circuit wafer; A plurality of first laser source chips are respectively arranged adjacent to the plurality of memory chip stacks; a memory input / output (I / O) chip stack disposed above the optical interposer, wherein the memory input / output chip stack includes a second photonic integrated circuit chip and a memory input / output chip disposed above and bonded to the second photonic integrated circuit chip; and A second laser source chip is disposed adjacent to the memory input / output chip stack, wherein the optical waveguide in the optical interposer is configured to couple the memory chip to the memory input / output chip through the first photonic integrated circuit chip and the second photonic integrated circuit chip.

6. The integrated circuit structure according to claim 5, wherein: The optical waveguide in the optical interposer is configured as an optical interconnect structure to optically couple the waveguide with the first photonic integrated circuit chip; and The first photonic integrated circuit chip is electrically coupled to the memory chip.

7. The integrated circuit structure according to claim 5, wherein: The optical interposer further includes a conductive component configured as an electrical interconnect structure to electrically couple with the memory chip and the first photonic integrated circuit chip to provide power to the memory chip and the first photonic integrated circuit chip.

8. The integrated circuit structure according to claim 5, further comprising: A fiber array unit is attached to the memory input / output chip and is configured to provide input and output signals in an optical mode.

9. A method of manufacturing an integrated circuit (IC) structure, comprising: forming a photonic integrated circuit (IC) structure on a first substrate; bonding a memory chip to the photonic integrated circuit structure formed on the first substrate; Sawing the first substrate to obtain memory chip stacks, each memory chip stack comprising one of the photonic integrated circuit structures and one of the memory chips; forming an optical intermediary layer; as well as A configuration is adopted in which the memory chip stack and the laser source chip are bonded on the optical interposer so that one of the laser source chips is adjacent to one of the memory chip stack.

10. The method according to claim 9, further comprising: Bonding a memory input / output (I / O) chip stack and a second laser source chip on the optical interposer so that the second laser source chip is adjacent to the memory input / output chip stack, the memory input / output chip stack comprising a second photonic integrated circuit chip and a memory input / output chip bonded to the second photonic integrated circuit chip; filling the gaps between the memory chips before sawing the first substrate; as well as A fiber array unit is attached to the memory input / output chip stack.

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