Preparation method of semiconductor device structure
The wet etching technology uses HNA acid to form grooves, and control the groove depth to reduce the gate oxygen layer height difference in the devices in high-voltage and low-voltage areas, solving the problems of increased process difficulty and reduced device performance, and achieving planarization and height uniformity of the gate oxygen layer surface.
Patent Information
- Application Number
- CN202311568062.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-22
- Publication Date
- 2025-05-23
AI Technical Summary
The height difference between the high-voltage gate oxygen layer and the low-voltage gate oxygen layer leads to increased process difficulty and reduced device performance.
The isotropic characteristics of the silicon by wet etching, and the depth of the groove is changed by controlling the amount of HNA acid to reduce the gate oxygen layer height difference in the device in the high- and low-voltage area.
The surface planarization of the gate oxygen layer in different device areas is achieved, the uniformity of the surface height of the gate oxygen layer is improved, and the difficulty of subsequent polysilicon etching and contact hole etching is reduced.
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Figure CN120033147A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of semiconductor integrated circuit design and manufacture, and in particular relates to a method for preparing a semiconductor device structure. Background Art
[0002] For high voltage (HV) devices, in order to enable the devices to withstand higher voltages while ensuring that the gate is not broken down and meets reliability test standards under high voltage operation, the thickness of the gate oxide layer of high voltage devices is usually much thicker than that of traditional low voltage devices; for example, in some devices, the gate oxide layer thicknesses of high voltage, medium voltage and low voltage regions are different due to different pressures; so for high voltage products, when the three devices are integrated together, the difference in gate oxide thickness of high voltage / medium voltage / low voltage devices will form a height difference at the intersection of the three MOS tubes, resulting in the surface morphology of the gate after the polysilicon is deposited. The surface morphology is ups and downs, which will increase the difficulty of subsequent polysilicon etching, and may lead to a reduction in polysilicon formed at the interface and affect the critical size of polysilicon. In addition, due to the difference in gate height during subsequent contact hole etching, the required etching depth of the contact hole is inconsistent, which also brings great difficulty to the contact hole etching process.
[0003] The current method for improving the height difference at the junction of the three MOS tubes in high-voltage products is to use a furnace tube to grow a sacrificial silicon oxide layer at high temperature to consume silicon at the corresponding position, and then grow a high-voltage gate oxide layer after the sacrificial silicon oxide layer is corroded, thereby reducing the height difference between the high-voltage gate oxide layer and the low-voltage gate oxide layer; this method will increase more furnace tube processes and introduce more thermal processes. At the same time, this sacrificial silicon oxide layer will not only oxidize the active area of the high-voltage device, but also this furnace tube high-temperature oxidation process will penetrate the silicon oxide layer of the shallow trench isolation structure, and oxidize and consume the active area at the bottom and sidewall of the shallow trench isolation structure, thereby deepening the depth of the shallow trench isolation structure, locally increasing the oxide layer in the shallow trench isolation structure, and consuming the silicon in the active area, resulting in a reduction in the size of the active area, thereby affecting the device performance. Figure 1 shown.
[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for preparing a semiconductor device structure, which is used to solve the problem of increased process difficulty and reduced device performance caused by the height difference between the high-voltage gate oxide layer and the low-voltage gate oxide layer in the prior art.
[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for preparing a semiconductor device structure, the preparation method comprising: providing a semiconductor substrate, defining a high-voltage region and a low-voltage region on the semiconductor substrate; forming a first isolation layer on the semiconductor substrate; removing the first isolation layer on the high-voltage region to form a first window, etching the semiconductor substrate in the first window with a first wet etching solution to form a first groove; forming a first oxide layer in the first groove; removing the first isolation layer, and forming a second oxide layer on the semiconductor substrate in the low-voltage region, wherein the thickness of the second oxide layer is less than the thickness of the first oxide layer.
[0007] Optionally, the step of defining a medium-voltage area on the semiconductor substrate is also included. After the first oxide layer is formed, the preparation method also includes: forming a second isolation layer on the semiconductor substrate; removing the second isolation layer on the medium-voltage area to form a second window, etching the semiconductor substrate in the second window with a second wet etching solution to form a second groove, the depth of the second groove is less than the depth of the first groove; forming a third oxide layer in the second groove, the thickness of the third oxide layer is less than the thickness of the first oxide layer and greater than the thickness of the second oxide layer.
[0008] Optionally, the first wet etching solution and / or the second wet etching solution is an HNA solution formed by mixing hydrofluoric acid, nitric acid and acetic acid, and the etching depth of the first groove and / or the second groove is controlled by controlling the amount of the HNA solution introduced.
[0009] Optionally, the volume ratio of hydrofluoric acid, nitric acid and acetic acid in the HNA solution is 1-3:1-6:4-15, wherein the mass percentage concentration range of hydrofluoric acid is 35-45%, the mass percentage concentration range of nitric acid is 55-65%, and the mass percentage concentration range of acetic acid is 85-95%.
[0010] Optionally, the thickness of the first oxide layer is 10 to 100 times the thickness of the second oxide layer, and the thickness of the third oxide layer is 2 to 10 times the thickness of the second oxide layer.
[0011] Optionally, the thickness of the first oxide layer is 800 angstroms to 1200 angstroms, the thickness of the third oxide layer is 150 angstroms to 300 angstroms, and the thickness of the second oxide layer is 15 angstroms to 50 angstroms.
[0012] Optionally, a high-voltage device is formed in the high-voltage area based on the first oxide layer, a medium-voltage device is formed in the medium-voltage area based on the third oxide layer, and a low-voltage device is formed in the low-voltage area based on the second oxide layer. The operating voltage of the low-voltage device is 1V~5V, the operating voltage of the medium-voltage device is 5V~15V, and the operating voltage of the high-voltage device is greater than 15V.
[0013] Optionally, the first isolation layer and the second isolation layer are made of silicon nitride.
[0014] Optionally, the first oxide layer, the second oxide layer and the third oxide layer are formed by a chemical vapor deposition process or a thermal oxidation process.
[0015] Optionally, before forming the first oxide layer and the third oxide layer, the method further includes forming an oxide liner layer on the inner walls of the first groove and the second groove respectively by a thermal oxidation process and removing the oxide liner layer.
[0016] Optionally, a shallow trench isolation structure is formed in the semiconductor substrate to separate a high voltage region, a medium voltage region and a low voltage region on the semiconductor substrate.
[0017] As described above, the method for preparing a semiconductor device structure of the present invention has the following beneficial effects:
[0018] The present invention forms a groove by utilizing the isotropic property of HNA acid on silicon through wet etching, and changes the depth of the silicon groove by controlling the amount of HNA acid introduced, thereby effectively reducing the height difference between the gate oxide layers of the devices in the high-voltage region and the low-voltage region, achieving the purpose of flattening the surface of the gate oxide layer in different device regions, improving the uniformity of the surface height of the gate oxide layer, and thus reducing the process difficulty of subsequent polysilicon etching and contact hole etching. The present invention forms a groove by utilizing the isotropic property of HNA acid on silicon through wet etching, and changes the depth of the silicon groove by controlling the amount of HNA acid introduced, and has strong adjustment ability and controllability. The present invention proposes a new high-voltage product gate oxide layer formation architecture, which can effectively reduce the high-temperature furnace control process, and uses wet etching to flatten the gate oxide layer surfaces in the high-voltage region, the medium-voltage region and the low-voltage region, thereby reducing the process difficulty of subsequent polysilicon etching and contact hole etching.
[0019] The present invention solves the problem that when silicon is consumed through a sacrificial layer in the traditional method, the sacrificial silicon oxide layer not only oxidizes the active area of the high-voltage device, but also the furnace tube high-temperature oxidation process penetrates the silicon oxide layer of the shallow trench isolation structure, oxidizes and consumes the active area at the bottom and sidewall of the shallow trench isolation structure, thereby causing the depth of the shallow trench isolation structure to deepen, the oxide layer in the shallow trench isolation structure to increase locally, the silicon in the active area is consumed, resulting in a reduction in the size of the active area, thereby affecting the device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.
[0021] Figure 1 Schematic diagram showing that silicon in the active area is consumed, resulting in a reduction in the size of the active area.
[0022] Figure 2 to Figure 12It is a schematic structural diagram showing the steps of a method for preparing a semiconductor device structure according to an embodiment of the present invention.
[0023] Component number description
[0024] 100 Semiconductor substrate
[0025] 101 Shallow Trench Isolation Structure
[0026] 102 First isolation layer
[0027] 103 High Pressure Area
[0028] 104 Medium Pressure Area
[0029] 105 Low Pressure Area
[0030] 106 First Window
[0031] 107 First Groove
[0032] 108 First Oxide Layer
[0033] 109 Sacrificial Oxide Layer
[0034] 110 Second isolation layer
[0035] 111 Second Window
[0036] 112 Initial groove
[0037] 113 Second groove
[0038] 114 Third Oxide Layer
[0039] 115 Second Oxide Layer
[0040] 116 Polysilicon Gate Layer DETAILED DESCRIPTION
[0041] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0042] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.
[0043] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0044] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.
[0045] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
[0046] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0047] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0048] like Figure 2 to Figure 12 As shown, this embodiment provides a method for preparing a semiconductor device structure, and the preparation method comprises the following steps:
[0049] like Figure 2 As shown, step 1) is first performed to provide a semiconductor substrate 100 , and a high voltage region 103 , a medium voltage region 104 and a low voltage region 105 are defined on the semiconductor substrate 100 .
[0050] The semiconductor substrate 100 may be, for example, a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, etc., but is not limited to the examples listed here. Various doping regions, such as a P-type doping region and an N-type doping region, may be pre-formed in the semiconductor substrate 100 .
[0051] like Figure 2As shown, in one embodiment, a shallow trench isolation structure (STI) 101 can be formed in the semiconductor substrate 100 to separate a high voltage region 103, a medium voltage region 104, and a low voltage region 105 on the semiconductor substrate 100. The shallow trench isolation structure (STI) 101 includes a trench structure disposed in the semiconductor substrate 100 and an insulating oxide filled in the trench structure, such as silicon dioxide. The interval of the shallow trench isolation structure (STI) 101 is set according to the required size of the high voltage region 103, the medium voltage region 104, and the low voltage region 105.
[0052] like Figure 3 Then, step 2) is performed to form a first isolation layer 102 on the semiconductor substrate 100 .
[0053] In one embodiment, a first isolation layer 102 can be formed on the semiconductor substrate 100 by a process such as plasma enhanced chemical vapor deposition (PECVD). The material of the first isolation layer 102 has a higher etching selectivity with silicon in a subsequent wet etching process, such as an etching selectivity greater than 50:1 or greater than 100:1, to ensure that silicon in other areas will not be corroded and consumed during the wet etching process. The first isolation layer 102 can be, for example, a silicon nitride layer.
[0054] like Figure 4-5 As shown, step 3) is then performed to remove the first isolation layer 102 on the high voltage region 103 to form a first window 106 , and the semiconductor substrate 100 in the first window 106 is etched by a first wet etching solution to form a first groove 107 .
[0055] In one embodiment, the first isolation layer 102 on the high voltage region 103 may be removed by a photolithography-etching process to form the first window 106 .
[0056] In one embodiment, the first wet etching solution is hydrofluoric acid (HF), nitric acid (HNO 3 ), acetic acid (CH 3 The etching depth of the first groove 107 is controlled by controlling the amount of the HNA solution introduced.
[0057] In one embodiment, the volume ratio of hydrofluoric acid, nitric acid and acetic acid in the HNA solution is 1-3:1-6:4-15, wherein the mass percentage concentration range of hydrofluoric acid is 35-45%, the mass percentage concentration range of nitric acid is 55-65%, and the mass percentage concentration range of acetic acid is 85-95%. In a preferred example, the volume ratio of hydrofluoric acid, nitric acid and acetic acid in the HNA solution is 1:3:9.
[0058] In this embodiment, silicon is etched by HNA solution. On the one hand, the silicon surface after being etched by HNA solution has fewer defects, and a high-quality silicon surface can be obtained. On the other hand, the HNA solution etches silicon, and the consumption of silicon can be precisely controlled by the amount of HNA solution passing through, thereby precisely controlling the depth of the first groove 107.
[0059] like Figure 6 As shown, step 4) is then performed to form a first oxide layer 108 in the first groove 107 .
[0060] In one embodiment, before forming the first oxide layer 108 and the second oxide layer 115, the steps of forming an oxide liner layer on the inner wall of the first groove 107 by a thermal oxidation process and removing the oxide liner layer are also included to repair silicon surface defects introduced by HNA solution corrosion, thereby further improving the quality and thickness uniformity of the first oxide layer 108.
[0061] In one embodiment, the first oxide layer 108 may be formed by a chemical vapor deposition process or a thermal oxidation process. The thickness of the first oxide layer 108 may be controlled to be equal to or slightly higher than the semiconductor substrate 100, and the height above the semiconductor substrate 100 may be controlled to be less than 10 angstroms, for example.
[0062] like Figure 7 As shown, in one embodiment, a step of forming a sacrificial oxide layer 109 in the medium voltage region 104 by a thermal oxidation process may also be included.
[0063] like Figure 8 As shown, step 5) is then performed to form a second isolation layer 110 on the semiconductor substrate 100 .
[0064] In one embodiment, a second isolation layer 110 can be formed on the semiconductor substrate 100 by a process such as plasma enhanced chemical vapor deposition (PECVD). The material of the second isolation layer 110 has a higher etching selectivity with silicon in a subsequent wet etching process, such as an etching selectivity greater than 50:1 or greater than 100:1, to ensure that silicon in other areas will not be corroded and consumed during the wet etching process. The second isolation layer 110 can be, for example, a silicon nitride layer.
[0065] like Figure 8-Figure 9 As shown, step 6 is then performed to remove the second isolation layer 110 on the medium voltage area 104 to form a second window 111, and the semiconductor substrate 100 in the second window 111 is etched by a second wet etching solution to form a second groove 113, the depth of the second groove 113 is less than the depth of the first groove 107.
[0066] In one embodiment, the second isolation layer 110 on the high voltage region 103 may be removed by a photolithography-etching process to form a second window 111 .
[0067] In one embodiment, the second wet etching solution is hydrofluoric acid (HF), nitric acid (HNO 3 ), acetic acid (CH 3 The etching depth of the first groove 107 is controlled by controlling the amount of the HNA solution introduced.
[0068] In one embodiment, the volume ratio of hydrofluoric acid, nitric acid and acetic acid in the HNA solution is 1-3:1-6:4-15, wherein the mass percentage concentration range of hydrofluoric acid is 35-45%, the mass percentage concentration range of nitric acid is 55-65%, and the mass percentage concentration range of acetic acid is 85-95%. In a preferred example, the volume ratio of hydrofluoric acid, nitric acid and acetic acid in the HNA solution is 1:3:9.
[0069] In this embodiment, silicon is etched by HNA solution. On the one hand, the silicon surface after being etched by HNA solution has fewer defects, and a high-quality silicon surface can be obtained. On the other hand, the HNA solution etches silicon, and the consumption of silicon can be precisely controlled by the amount of HNA solution passing through, thereby precisely controlling the depth of the second groove 113.
[0070] In one embodiment, when step 4) first forms a sacrificial oxide layer 109 in the medium voltage region 104 by a thermal oxidation process, before etching the semiconductor substrate 100 by a second wet etching solution, a step of removing the sacrificial oxide layer 109 on the surface of the medium voltage region 104 by a wet etching process is also included to form an initial groove 112, which can effectively reduce the subsequent etching time of the semiconductor substrate 100. Figure 8 Then, the semiconductor substrate 100 in the second window 111 is etched by a second wet etching solution to form a second groove 113 on the basis of the initial groove 112. The depth of the second groove 113 is less than the depth of the first groove 107. Fig. 9 shown.
[0071] like Fig.10 As shown, step 7) is then performed to form a third oxide layer 114 in the second groove 113, wherein the thickness of the third oxide layer 114 is less than the thickness of the first oxide layer 108 and greater than the thickness of the second oxide layer 115 formed subsequently.
[0072] In one embodiment, before forming the third oxide layer 114, the steps of forming an oxide liner layer on the inner wall of the second groove 107 by a thermal oxidation process and removing the oxide liner layer are also included to repair silicon surface defects introduced by HNA solution corrosion, thereby further improving the quality and thickness uniformity of the third oxide layer 114.
[0073] In one embodiment, the third oxide layer 114 may be formed by a chemical vapor deposition process or a thermal oxidation process.
[0074] like Fig.11 As shown, step 8 is then performed to remove the second isolation layer 110 and form a second oxide layer 115 on the semiconductor substrate 100 in the low voltage region 105 , wherein the thickness of the second oxide layer 115 is less than the thickness of the first oxide layer 108 .
[0075] In one embodiment, the second oxide layer 115 may be formed by a chemical vapor deposition process or a thermal oxidation process.
[0076] In one embodiment, the thickness of the first oxide layer 108 is 10 to 100 times the thickness of the second oxide layer 115, and the thickness of the third oxide layer 114 is 2 to 10 times the thickness of the second oxide layer 115. In a specific implementation, the thickness of the first oxide layer 108 is 800 to 1200 angstroms, for example, 1100 angstroms, the thickness of the third oxide layer 114 is 150 to 300 angstroms, for example, 200 angstroms, and the thickness of the second oxide layer 115 is 15 to 50 angstroms, for example, 25 angstroms.
[0077] like Fig.12 As shown, step 9) is finally performed. After forming the second oxide layer 115 on the semiconductor substrate 100 in the low voltage region 105 , the following steps are further included: forming a polysilicon gate layer 116 on the first oxide layer 108 , the second oxide layer 115 and the third oxide layer 114 .
[0078] In one embodiment, the method further includes the steps of forming a high-voltage device in the high-voltage region 103 based on the first oxide layer 108, forming a medium-voltage device in the medium-voltage region 104 based on the third oxide layer 114, and forming a low-voltage device in the low-voltage region 105 based on the second oxide layer 115, wherein the operating voltage of the low-voltage device is 1V to 5V, the operating voltage of the medium-voltage device is 5V to 15V, and the operating voltage of the high-voltage device is greater than 15V. For example, the high-voltage device may be a high-voltage MOS tube, the medium-voltage device may be a medium-voltage MOS tube, and the low-voltage device may be a low-voltage MOS tube.
[0079] As described above, the method for preparing a semiconductor device structure of the present invention has the following beneficial effects:
[0080] The present invention forms a groove by utilizing the isotropic property of HNA acid on silicon through wet etching, and changes the depth of the silicon groove by controlling the amount of HNA acid introduced, thereby effectively reducing the height difference between the gate oxide layer of the high-voltage region 103 domain and the low-voltage region 105 domain device, achieving the purpose of flattening the surface of the gate oxide layer in different device regions, improving the uniformity of the surface height of the gate oxide layer, thereby reducing the process difficulty of subsequent polysilicon etching and contact hole etching. The present invention forms a groove by utilizing the isotropic property of HNA acid on silicon through wet etching, and changes the depth of the silicon groove by controlling the amount of HNA acid introduced, and has strong adjustment ability and controllability. The present invention proposes a new high-voltage product gate oxide layer formation architecture, which can effectively reduce the high-temperature furnace control process, and uses wet etching to flatten the gate oxide layer surface of the high-voltage region 103 domain, the medium-voltage region 104 domain and the low-voltage region 105 domain, thereby reducing the process difficulty of subsequent polysilicon etching and contact hole etching.
[0081] The present invention solves the problem that when silicon is consumed through a sacrificial layer in the traditional method, the sacrificial silicon oxide layer not only oxidizes the active area of the high-voltage device, but also the furnace tube high-temperature oxidation process penetrates the silicon oxide layer of the shallow trench isolation structure, oxidizes and consumes the active area at the bottom and sidewall of the shallow trench isolation structure, thereby causing the depth of the shallow trench isolation structure to deepen, the oxide layer in the shallow trench isolation structure to increase locally, the silicon in the active area is consumed, resulting in a reduction in the size of the active area, thereby affecting the device performance.
[0082] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
[0083] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for preparing a semiconductor device structure, It is characterized in that The preparation method comprises: Providing a semiconductor substrate, on which a high-voltage region and a low-voltage region are defined; forming a first isolation layer on the semiconductor substrate; Removing the first isolation layer on the high voltage region to form a first window, and etching the semiconductor substrate in the first window by using a first wet etching solution to form a first groove; forming a first oxide layer in the first groove; The first isolation layer is removed, and a second oxide layer is formed on the semiconductor substrate in the low-voltage region, wherein the thickness of the second oxide layer is less than the thickness of the first oxide layer.
2. The method for preparing a semiconductor device structure according to claim 1, Features: The method further includes the step of defining a medium voltage region on the semiconductor substrate. After the first oxide layer is formed, the method further includes: forming a second isolation layer on the semiconductor substrate; Removing the second isolation layer on the medium voltage region to form a second window, etching the semiconductor substrate in the second window with a second wet etching solution to form a second groove, wherein the depth of the second groove is less than the depth of the first groove; A third oxide layer is formed in the second groove, wherein a thickness of the third oxide layer is smaller than a thickness of the first oxide layer and larger than a thickness of the second oxide layer.
3. The method for preparing a semiconductor device structure according to claim 1 or 2, Features: The first wet etching solution and / or the second wet etching solution is an HNA solution formed by mixing hydrofluoric acid, nitric acid and acetic acid, and the etching depth of the first groove and / or the second groove is controlled by controlling the amount of the HNA solution introduced.
4. The method for preparing a semiconductor device structure according to claim 3, Features: The volume ratio of hydrofluoric acid, nitric acid and acetic acid in the HNA solution is 1-3:1-6:4-15, wherein the mass percentage concentration range of the hydrofluoric acid is 35-45%, the mass percentage concentration range of the nitric acid is 55-65%, and the mass percentage concentration range of the acetic acid is 85-95%.
5. The method for preparing a semiconductor device structure according to claim 2, Features: The thickness of the first oxide layer is 10 to 100 times the thickness of the second oxide layer, and the thickness of the third oxide layer is 2 to 10 times the thickness of the second oxide layer.
6. The method for preparing a semiconductor device structure according to claim 5, Features: The thickness of the first oxide layer is 800 angstroms to 1200 angstroms, the thickness of the third oxide layer is 150 angstroms to 300 angstroms, and the thickness of the second oxide layer is 15 angstroms to 50 angstroms.
7. The method for preparing a semiconductor device structure according to claim 2, Features: A high-voltage device is formed in the high-voltage area based on the first oxide layer, a medium-voltage device is formed in the medium-voltage area based on the third oxide layer, and a low-voltage device is formed in the low-voltage area based on the second oxide layer. The operating voltage of the low-voltage device is 1V to 5V, the operating voltage of the medium-voltage device is 5V to 15V, and the operating voltage of the high-voltage device is greater than 15V.
8. The method for preparing a semiconductor device structure according to claim 2, Features: The first isolation layer and the second isolation layer are made of silicon nitride.
9. The method for preparing a semiconductor device structure according to claim 2, Features: The first oxide layer, the second oxide layer and the third oxide layer are formed by a chemical vapor deposition process or a thermal oxidation process.
10. The method for preparing a semiconductor device structure according to claim 9, Features: Before forming the first oxide layer and the third oxide layer, the method further includes forming an oxide liner layer on the inner walls of the first groove and the second groove respectively through a thermal oxidation process and removing the oxide liner layer.
11. The method for preparing a semiconductor device structure according to claim 2, Features: A shallow trench isolation structure is formed in the semiconductor substrate to separate a high voltage region, a medium voltage region and a low voltage region on the semiconductor substrate.