GaN power amplifier tube bias control circuit and method thereof

Abstract

The invention relates to a GaN power amplifier tube bias control circuit and a method thereof. The GaN power amplifier tube bias control circuit comprises a power supply unit, a drain voltage control unit, a reference power supply chip D5 and a grid voltage control unit, the power supply unit is connected to a power supply circuit; the drain electrode voltage control unit is electrically connected to the power supply unit and the drain electrode of the GaN power amplifier tube, and the drain electrode voltage control unit is used for being connected to a power supply circuit; the reference power supply chip D5 is electrically connected to the power supply unit and the grid voltage control unit; and the grid voltage control unit is electrically connected to the power supply unit and the grid of the GaN power amplifier tube. The low-noise reference voltage is provided based on the reference power supply chip D5, interference of lower bias noise can be provided, and the signal-to-noise ratio of the grid voltage control unit to the grid of the GaN power amplifier tube is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of GaN power amplifier tubes, and in particular to a GaN power amplifier tube bias control circuit and method thereof. Background Art

[0002] GaN power amplifier tubes are suitable for high-frequency, high-power RF signal amplification scenarios. GaN power amplifier tubes are a depletion-type transistor. This type of power amplifier tube requires the gate to be in a negative voltage state when operating in the amplification or shutdown state. If the gate voltage is not biased at a suitable negative voltage when powering on or off, the drain stage will be powered, which will cause the chip to heat up instantly and burn out. In addition, in other application scenarios, the frequency and power of GaN power amplifier tubes not only have specific requirements, but also need to minimize the additional noise introduced during the amplification process to reduce later interference.

[0003] In the related art, a patent document with publication number CN107528553A discloses a GaN power amplifier tube bias protection circuit, which includes a GaN power amplifier tube, a gate voltage stabilizing circuit A, a gate voltage adjustment circuit B, a voltage follower circuit C, and a gate drain power-on timing protection circuit D. The gate voltage stabilizing circuit includes a voltage stabilizing chip U1, the chip U1 is connected to a +5V power supply, the REG pin of the chip U1 is connected to the input end of the gate drain power-on timing protection circuit D, the output end of the gate drain power-on timing protection circuit D is connected to the drain of the GaN power amplifier tube, the OUT pin of the chip U1 is connected to the input end of the gate voltage adjustment circuit B, the OUT pin of the chip U1 is also connected to the input end of the voltage follower circuit C, the output end of the voltage follower circuit C is connected to the gate of the GaN power amplifier tube, and the gate drain power-on timing protection circuit D is also connected to the system drain power supply Vd_IN, which can well realize the power amplifier bias power-on timing protection and the rapid switching of the power amplifier switch and the controllable power amplifier gain. Although the bias protection circuit can provide protection for the power on and off of the GaN power amplifier tube, the bias voltage itself still has high ripple noise, thereby reducing the signal-to-noise ratio of the bias voltage. Summary of the invention

[0004] Based on the above description, the present invention provides a GaN power amplifier tube bias control circuit and method thereof, aiming to solve the problem of low signal-to-noise ratio of the existing bias protection circuit.

[0005] The technical solution of the present invention to solve the above technical problems is as follows: In a first aspect, a GaN power amplifier tube bias control circuit and method thereof include a power supply unit, a drain voltage control unit, a reference power chip D5 and a gate voltage control unit; The power supply unit is used to access the power supply circuit; The drain voltage control unit is electrically connected to the power supply unit and the drain of the GaN power amplifier tube, and the drain voltage control unit is used to access the power supply circuit; The reference power chip D5 is electrically connected to the power supply unit and the gate voltage control unit; The gate voltage control unit is electrically connected to the power supply unit and the gate of the GaN power amplifier tube.

[0006] Based on the above technical solution, the present invention can also be improved as follows.

[0007] Furthermore, the first pin of the power chip D1 and the first pin of the power chip D3 are used to access the power supply circuit, and the second pin of the reference power chip D5 is electrically connected to the 12th pin of the power chip D1.

[0008] Further, the drain voltage control unit includes an inverter D4, a transistor U2 and a MOS tube U1, the 4th pin and the 5th pin of the inverter D4 are electrically connected to the 5th pin of the power chip D1 and the 5th pin of the power chip D3 one by one, the 5th pin of the transistor U2 is electrically connected to the 3rd pin of the inverter D4, the 1st pin, the 2nd pin and the 3rd pin of the MOS tube U1 are used to access the power supply circuit, the 4th pin of the MOS tube U1 is electrically connected to the 2nd pin and the 3rd pin of the transistor U2, the 5th pin, the 6th pin, the 7th pin and the 8th pin of the MOS tube U1 are all electrically connected to the drain of the GaN power amplifier tube, and the gate voltage control unit is connected in parallel between the 5th pin, the 6th pin, the 7th pin and the 8th pin of the MOS tube U1 and the drain of the GaN power amplifier tube.

[0009] Furthermore, the drain voltage control unit includes a resistor R5, and the fifth pin of the transistor U2 is electrically connected to the third pin of the inverter D4 via the resistor R5.

[0010] Furthermore, the drain voltage control unit includes a resistor R6 and a resistor R7, the 4th pin of the MOS tube U1 is electrically connected to the 2nd pin of the transistor U2 via the resistor R6, and the 4th pin of the MOS tube U1 is electrically connected to the 3rd pin of the transistor U2 via the resistor R7.

[0011] Furthermore, the drain voltage control unit includes a resistor R2 and a voltage stabilizing diode D2, and the third pin and the second pin of the resistor R2 and the voltage stabilizing diode D2 are connected in parallel between the power supply circuit and the fourth pin of the MOS tube U1.

[0012] Furthermore, the gate voltage control unit includes a transistor D6, a second voltage divider sub-circuit, a resistor R10 and an operational amplifier N1, the second pin of the transistor D6 is electrically connected to the fifth pin, the sixth pin, the seventh pin and the eighth pin of the MOS tube U1, the second voltage divider sub-circuit is electrically connected to the sixth pin of the transistor D6 and the sixth pin of the reference power supply chip D5, the resistor R10 is electrically connected between the second voltage divider sub-circuit and the sixth pin of the operational amplifier N1, and the first pin of the operational amplifier N1 is electrically connected to the gate of the GaN power amplifier tube.

[0013] Furthermore, the drain voltage control unit includes a first voltage divider sub-circuit, which is connected in parallel between the 5th, 6th, 7th and 8th pins of the MOS tube U1 and the drain of the GaN power amplifier tube, and the 2nd pin of the transistor D6 is electrically connected to the first voltage divider sub-circuit.

[0014] Furthermore, the gate voltage control unit includes a resistor R15, and the second pin of the transistor D6 is electrically connected to the first voltage dividing sub-circuit via the resistor R15.

[0015] In a second aspect, a GaN power amplifier tube bias control method is provided, wherein the bias control method is applicable to a GaN power amplifier tube bias control circuit as described in the first aspect, and comprises: The power supply unit sends a state indication signal to the drain voltage control unit, and the reference power chip D5 sends a reference voltage to the gate voltage control unit. The gate voltage control unit converts the reference voltage ratio and then sends it to the gate of the GaN power amplifier tube. The drain voltage control unit controls the power supply circuit and the drain of the GaN power amplifier tube to be turned on according to the state indication signal, and sends a turn-on voltage to the gate voltage control unit when the voltage of the drain of the GaN power amplifier tube is higher than a preset voltage threshold; The gate voltage control unit changes the voltage division ratio when receiving the on-voltage, divides the reference voltage based on the changed voltage division ratio and then converts the voltage to obtain an amplified bias voltage, and then sends the amplified bias voltage to the gate of the GaN power amplifier tube for power-on.

[0016] Compared with the prior art, the technical solution of the present application has the following beneficial technical effects: the present application provides a low-noise reference voltage based on the reference power chip D5, can provide lower bias noise interference, and improve the signal-to-noise ratio of the gate voltage control unit to the gate of the GaN power amplifier tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A circuit schematic diagram of a GaN power amplifier tube bias control circuit provided in an embodiment of the present invention; Figure 2 The present invention provides a flowchart of a GaN power amplifier tube bias control method according to an embodiment of the present invention.

[0018] Description of reference numerals: 1. Power supply unit; 2. Drain voltage control unit; 21. First voltage divider circuit; 3. Gate voltage control unit; 31. Second voltage divider circuit. DETAILED DESCRIPTION

[0019] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0021] It will be appreciated that spatial relationship terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It will be appreciated that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0022] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0023] Reference Figure 1 As shown, the present invention provides a technical solution: a GaN power amplifier tube bias control circuit, comprising a power supply unit 1, a drain voltage control unit 2, a reference power supply chip D5 and a gate voltage control unit 3; the power supply unit 1 is used to access the power supply circuit; the drain voltage control unit 2 is electrically connected to the power supply unit 1 and the drain of the GaN power amplifier tube, and the drain voltage control unit 2 is used to access the power supply circuit; the reference power supply chip D5 is electrically connected to the power supply unit 1 and the gate voltage control unit 3; the gate voltage control unit 3 is electrically connected to the power supply unit 1 and the gate of the GaN power amplifier tube.

[0024] Exemplarily, the model of the reference power chip D5 may be ADR4550 or the like.

[0025] In this embodiment, the reference power chip D5 and the gate voltage control unit 3 are powered by the power supply unit 1, and the power supply unit 1 sends a state indication signal to the drain voltage control unit 2, so that the power supply circuit is connected to the drain of the GaN power amplifier tube, and the drain of the GaN power amplifier tube is powered on. At the same time, the reference power chip D5 sends a reference voltage to the gate voltage control unit 3, and after the gate voltage control unit 3 performs a proportional conversion, it is sent to the gate of the GaN power amplifier tube, so that the gate of the GaN power amplifier tube remains in the off state. After the drain voltage control unit 2 sends the on-voltage to the gate voltage control unit 3, the gate voltage control unit 3 changes the voltage division ratio, so that the reference voltage is first divided and then proportionally converted, and finally the amplified bias voltage enters the gate of the GaN power amplifier tube, so that the GaN power amplifier tube can work normally. In this way, a low-noise reference voltage is provided based on the reference power chip D5, which can provide lower bias noise interference and improve the signal-to-noise ratio of the gate voltage control unit 3 to the gate of the GaN power amplifier tube.

[0026] Reference Figure 1 As shown, in some embodiments, the first pin of the power chip D1 and the first pin of the power chip D3 are used to access the power supply circuit, and the second pin of the reference power chip D5 is electrically connected to the twelfth pin of the power chip D1.

[0027] In this embodiment, when the GaN power amplifier tube is powered on, the power chip D1 and the power chip D3 cooperate to send a state indication signal to the drain voltage control unit 2, and supply power to the drain voltage control unit 2 and the gate voltage control unit 3. Thus, the drain voltage control unit 2, the reference power chip D5 and the gate voltage control unit 3 perform their respective operations, and finally the GaN power amplifier tube starts to work.

[0028] Reference Figure 1As shown, in some embodiments, the drain voltage control unit 2 includes an inverter D4, a transistor U2 and a MOS tube U1, the 4th pin and the 5th pin of the inverter D4 are electrically connected to the 5th pin of the power chip D1 and the 5th pin of the power chip D3 one by one, the 5th pin of the transistor U2 is electrically connected to the 3rd pin of the inverter D4, the 1st pin, the 2nd pin and the 3rd pin of the MOS tube U1 are used to access the power supply circuit, the 4th pin of the MOS tube U1 is electrically connected to the 2nd pin and the 3rd pin of the transistor U2, the 5th pin, the 6th pin, the 7th pin and the 8th pin of the MOS tube U1 are all electrically connected to the drain of the GaN power amplifier tube, and the gate voltage control unit 3 is connected in parallel between the 5th pin, the 6th pin, the 7th pin and the 8th pin of the MOS tube U1 and the drain of the GaN power amplifier tube.

[0029] Exemplarily, the model of the inverter D4 may be SN74AUC1G08 or the like.

[0030] In this embodiment, when the GaN power amplifier tube is powered on, the power chip D1 and the power chip D3 supply power to the MOS tube U1. After the inverter D4 receives the status indication signal, if the voltage of the status indication signal is lower than the preset output voltage, the status indication signal is regarded as a low-level status indication signal, and the status indication signal sent by the 5th pin of the power chip D1 and the 5th pin of the power chip D3 to the drain voltage control unit 2 is continuously waited for to be gradually increased; if the voltage of the status indication signal is higher than the preset output voltage, the status indication signal is regarded as a high-level status indication signal, and the transistor U2 and the MOS tube are driven to be turned on, and the drain of the MOS tube U1 generates a bias voltage, so that the power supply circuit and the drain of the GaN power amplifier tube are turned on, and the drain of the GaN power amplifier tube starts to be powered on. When the GaN power amplifier tube is powered off, after the inverter D4 receives the status indication signal, if the voltage of the status indication signal is higher than the preset output voltage, the status indication signal is regarded as a high-level status indication signal, and the status indication signal sent by the 5th pin of the power chip D1 and the 5th pin of the power chip D3 to the drain voltage control unit 2 is gradually reduced in voltage, and the transistor U2 and the MOS tube are still turned on, the drain of the MOS tube U1 still generates a bias voltage, and the power supply circuit and the drain of the GaN power amplifier tube are still turned on; if the voltage of the status indication signal is lower than the preset output voltage, the status indication signal is regarded as a low-level status indication signal, then the inverter D4 is turned off, and the transistor U2 and the MOS tube U1 are turned off at the same time, so that the power supply circuit and the drain of the GaN power amplifier tube are also turned off, and the drain of the GaN power amplifier tube is powered off.

[0031] Reference Figure 1 As shown, in some embodiments, the drain voltage control unit 2 includes a resistor R5, and the fifth pin of the transistor U2 is electrically connected to the third pin of the inverter D4 via the resistor R5.

[0032] In this embodiment, when the inverter D4 drives the transistor U2 to turn on, the resistor R5 can play a role in current limiting, thereby preventing the transistor U2 from being damaged due to excessive current.

[0033] Reference Figure 1 As shown, in some embodiments, the drain voltage control unit 2 includes a resistor R6 and a resistor R7, the 4th pin of the MOS tube U1 is electrically connected to the 2nd pin of the transistor U2 via the resistor R6, and the 4th pin of the MOS tube U1 is electrically connected to the 3rd pin of the transistor U2 via the resistor R7.

[0034] In this embodiment, when the transistor U2 drives the MOS tube U1 to turn on, the resistor R6 and the resistor R7 both play a role of current limiting, thereby preventing the MOS tube U1 from being damaged due to excessive current.

[0035] Reference Figure 1 As shown, in some embodiments, the drain voltage control unit 2 includes a resistor R2 and a Zener diode D2, and the third pin and the second pin of the resistor R2 and the Zener diode D2 are connected in parallel between the power supply circuit and the fourth pin of the MOS tube U1.

[0036] In this embodiment, when the power supply circuit supplies power to the MOS tube, the resistor R2 and the voltage stabilizing diode D2 play a role in stabilizing the voltage, thereby ensuring the stability of the voltage and preventing the MOS tube U1 from being damaged.

[0037] Reference Figure 1 As shown, in some embodiments, the gate voltage control unit 3 includes a transistor D6, a second voltage divider sub-circuit 31, a resistor R10 and an operational amplifier N1, the second pin of the transistor D6 is electrically connected to the 5th pin, the 6th pin, the 7th pin and the 8th pin of the MOS tube U1, the second voltage divider sub-circuit 31 is electrically connected to the 6th pin of the transistor D6 and the 6th pin of the reference power supply chip D5, the resistor R10 is electrically connected between the second voltage divider sub-circuit 31 and the 6th pin of the operational amplifier N1, and the 1st pin of the operational amplifier N1 is electrically connected to the gate of the GaN power amplifier tube.

[0038] Exemplarily, the second voltage divider sub-circuit 31 includes resistors R13 and R14 connected in series in sequence, one end of the resistor R13 away from the resistor R14 is electrically connected to the 6th pin of the reference power supply chip D5, one end of the resistor R13 away from the resistor R14 is electrically connected to the 6th pin of the transistor D6, and one end of the resistor R10 away from the 6th pin of the operational amplifier N1 is connected in parallel between the resistor R13 and the resistor R14.

[0039] In this embodiment, when the GaN power amplifier tube is powered on, before the drain of the GaN power amplifier tube is turned on, the reference power chip D5 directly sends the reference voltage to the operational amplifier N1 via the resistor R10, and the reference voltage is proportionally converted by the operational amplifier N1 to obtain a negative voltage and sent to the gate of the GaN power amplifier tube. Ensure that the gate of the GaN power amplifier tube has entered the off state and is safe to power on before the drain of the GaN power amplifier tube is powered on. After the drain of the GaN power amplifier tube is turned on, the on-voltage drives the triode D6 to turn on, and at the same time, the on-voltage changes the voltage division ratio of the second voltage divider sub-circuit 31, so that the reference voltage enters the operational amplifier N1 after the second voltage divider sub-circuit 31 that changes the voltage division ratio is divided, and then the operational amplifier N1 performs proportional conversion to obtain a bias voltage and sends it to the gate of the GaN power amplifier tube. At this time, the gate of the GaN power amplifier tube is amplified by the bias voltage, so that the GaN power amplifier tube enters a normal working state. When the GaN power amplifier tube is powered off, vice versa.

[0040] Reference Figure 1 As shown, in some embodiments, the drain voltage control unit 2 includes a first voltage divider sub-circuit 21, which is connected in parallel between the 5th pin, the 6th pin, the 7th pin and the 8th pin of the MOS tube U1 and the drain of the GaN power amplifier tube, and the 2nd pin of the transistor D6 is electrically connected to the first voltage divider sub-circuit 21.

[0041] Exemplarily, the first voltage divider sub-circuit 21 includes a resistor R1 and a resistor R2 connected in series in sequence, an end of the resistor R1 facing away from the resistor R2 is connected in parallel between the 5th, 6th, 7th and 8th pins of the MOS tube U1 and the drain of the GaN power amplifier tube, an end of the resistor R2 facing away from the resistor R1 is grounded, and the second pin of the transistor D6 is connected in parallel to the resistor R1 and the resistor R2.

[0042] In this embodiment, when the MOS tube U1 sends the conduction voltage to the transistor D6, the first voltage dividing sub-circuit 21 divides the conduction voltage, thereby preventing the voltage entering the transistor D6 from being too high, thereby preventing the transistor D6 from being damaged.

[0043] Reference Figure 1 As shown, in some embodiments, the gate voltage control unit 3 includes a resistor R15 , and the second pin of the transistor D6 is electrically connected to the first voltage dividing sub-circuit 21 via the resistor R15 .

[0044] In this embodiment, before the on-voltage enters the transistor D6 , the resistor R15 pulls up the on-voltage to a high level to ensure that the on-voltage can turn on the transistor D6 .

[0045] Reference Figure 2As shown, the present invention provides a technical solution: a GaN power amplifier tube bias control method, the bias control method is applicable to the above-mentioned GaN power amplifier tube bias control circuit, comprising the following steps: S1, the power supply unit 1 sends a status indication signal to the drain voltage control unit 2, and at the same time, the reference power chip D5 sends a reference voltage to the gate voltage control unit 3, and the gate voltage control unit 3 converts the reference voltage ratio and then sends it to the gate of the GaN power amplifier tube; S2, the drain voltage control unit 2 controls the power supply circuit and the drain of the GaN power amplifier tube to be turned on according to the state indication signal, and sends a turn-on voltage to the gate voltage control unit 3 when the voltage of the drain of the GaN power amplifier tube is higher than a preset voltage threshold; S3, the gate voltage control unit 3 changes the voltage division ratio when receiving the on-voltage, and divides the reference voltage based on the changed voltage division ratio and then converts the voltage ratio to obtain an amplified bias voltage, and then sends the amplified bias voltage to the gate of the GaN power amplifier tube to power on.

[0046] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A GaN power amplifier tube bias control circuit, characterized in that: It comprises a power supply unit (1), a drain voltage control unit (2), a reference power chip D5 and a gate voltage control unit (3); The power supply unit (1) is used to connect to a power supply circuit; The drain voltage control unit (2) is electrically connected to the power supply unit (1) and the drain of the GaN power amplifier tube, and the drain voltage control unit (2) is used to be connected to the power supply circuit; The reference power chip D5 is electrically connected to the power supply unit (1) and the gate voltage control unit (3); The gate voltage control unit (3) is electrically connected to the power supply unit (1) and the gate of the GaN power amplifier tube.

2. A GaN power amplifier tube bias control circuit according to claim 1, characterized in that: The power supply unit (1) comprises a power chip D1 and a power chip D3, wherein the first pin of the power chip D1 and the first pin of the power chip D3 are used to access the power supply circuit, and the second pin of the reference power chip D5 is electrically connected to the twelfth pin of the power chip D1.

3. A GaN power amplifier tube bias control circuit according to claim 2, characterized in that: The drain voltage control unit (2) comprises an inverter D4, a transistor U2 and a MOS tube U1. The 4th pin and the 5th pin of the inverter D4 are electrically connected to the 5th pin of the power chip D1 and the 5th pin of the power chip D3 in a one-to-one correspondence. The 5th pin of the transistor U2 is electrically connected to the 3rd pin of the inverter D4. The 1st pin, the 2nd pin and the 3rd pin of the MOS tube U1 are used to access the power supply circuit. The 4th pin of the MOS tube U1 is electrically connected to the 2nd pin and the 3rd pin of the transistor U2. The 5th pin, the 6th pin, the 7th pin and the 8th pin of the MOS tube U1 are all electrically connected to the drain of the GaN power amplifier tube. The gate voltage control unit (3) is connected in parallel between the 5th pin, the 6th pin, the 7th pin and the 8th pin of the MOS tube U1 and the drain of the GaN power amplifier tube.

4. A GaN power amplifier tube bias control circuit according to claim 3, characterized in that: The drain voltage control unit (2) comprises a resistor R5, and the fifth pin of the transistor U2 is electrically connected to the third pin of the inverter D4 via the resistor R5.

5. The GaN power amplifier tube bias control circuit according to claim 3, characterized in that: The drain voltage control unit (2) comprises a resistor R6 and a resistor R7, the fourth pin of the MOS tube U1 is electrically connected to the second pin of the transistor U2 via the resistor R6, and the fourth pin of the MOS tube U1 is electrically connected to the third pin of the transistor U2 via the resistor R7.

6. A GaN power amplifier tube bias control circuit according to claim 3, characterized in that: The drain voltage control unit (2) comprises a resistor R2 and a voltage stabilizing diode D2, wherein the third pin and the second pin of the resistor R2 and the voltage stabilizing diode D2 are connected in parallel between the power supply circuit and the fourth pin of the MOS tube U1.

7. A GaN power amplifier tube bias control circuit according to any one of claims 3 to 5, characterized in that: The gate voltage control unit (3) comprises a transistor D6, a second voltage dividing sub-circuit (31), a resistor R10 and an operational amplifier N1, the second pin of the transistor D6 is electrically connected to the fifth pin, the sixth pin, the seventh pin and the eighth pin of the MOS tube U1, the second voltage dividing sub-circuit (31) is electrically connected to the sixth pin of the transistor D6 and the sixth pin of the reference power supply chip D5, the resistor R10 is electrically connected between the second voltage dividing sub-circuit (31) and the sixth pin of the operational amplifier N1, and the first pin of the operational amplifier N1 is electrically connected to the gate of the GaN power amplifier tube.

8. A GaN power amplifier tube bias control circuit according to claim 7, characterized in that: The drain voltage control unit (2) comprises a first voltage dividing sub-circuit (21), the first voltage dividing sub-circuit (21) being connected in parallel between the 5th pin, the 6th pin, the 7th pin and the 8th pin of the MOS tube U1 and the drain of the GaN power amplifier tube, and the 2nd pin of the transistor D6 being electrically connected to the first voltage dividing sub-circuit (21).

9. A GaN power amplifier tube bias control circuit according to claim 8, characterized in that: The gate voltage control unit (3) comprises a resistor R15, and the second pin of the transistor D6 is electrically connected to the first voltage dividing sub-circuit (21) via the resistor R15.

10. A GaN power amplifier tube bias control method, characterized in that: The bias control method is applicable to a GaN power amplifier tube bias control circuit according to any one of claims 1 to 9, comprising: The power supply unit (1) sends a state indication signal to the drain voltage control unit (2), and at the same time the reference power chip D5 sends a reference voltage to the gate voltage control unit (3), and the gate voltage control unit (3) converts the reference voltage ratio and then sends it to the gate of the GaN power amplifier tube; The drain voltage control unit (2) controls the power supply circuit and the drain of the GaN power amplifier tube to be turned on according to the state indication signal, and sends a turn-on voltage to the gate voltage control unit (3) when the voltage of the drain of the GaN power amplifier tube is higher than a preset voltage threshold; The gate voltage control unit (3) changes the voltage division ratio when receiving the conduction voltage, divides the reference voltage based on the changed voltage division ratio and then converts the voltage into an amplified bias voltage, and then sends the amplified bias voltage to the gate of the GaN power amplifier tube for powering on.

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