Digital calibration method and system for a multi-phase clock

Abstract

The present invention discloses a digital calibration method and system for a multi-phase clock, which relates to the technical fields of digital communication systems and digital signal processing technologies. The method includes: selecting a training sequence type and configuring a sampling circuit; fixing the PI Code, sampling the input data according to the set training sequence, recovering the corresponding clock phase of the initialized PI Code through a curve fitting algorithm, and sequentially fixing multiple PI Codes; analyzing the deviation between the clock phases of each phase obtained by actual measurement and the ideal phase, and quantifying the systematic deviation by plotting a curve; calculating a pre-distortion function according to the difference between the actual phase curve and the ideal phase curve; storing the calculated pre-distortion function in the non-volatile storage space of the chip; when the chip is working normally, reading the stored pre-distortion function and performing real-time compensation through a digital logic circuit to generate a calibrated clock phase index. The present invention realizes high-efficiency clock recovery and data sampling alignment through the digital calibration method and the pre-distortion function.

Description

Technical Field

[0001] The present invention relates to the technical fields of digital communication systems and digital signal processing, and particularly to a digital calibration method and system for multi-phase clocks. Background Art

[0002] Clock signals play a fundamental and crucial role in digital communication systems and digital signal processing. With the continuous increase in communication rates, multi-phase clock technology has become an indispensable part of high-speed data transmission systems. As the core component for generating multi-phase clocks, the Phase Interpolator (PI) generates multiple clock signals with different phases based on a reference clock signal, ensuring that data bits can be sampled at the optimal phase points, thereby maximizing the Signal-to-Noise Ratio (SNR) and improving the overall performance of the system. With the increase in the number of phases, systematic deviations in the phase delay module are inevitably introduced in the actual circuit implementation, resulting in a significant deviation between the actual phase curve and the ideal phase curve. Such deviations not only reduce the accuracy of clock recovery but also have a negative impact on the data sampling accuracy and system SNR of digital communication systems.

[0003] Although existing multi-phase clock recovery technologies reduce phase deviations to a certain extent through dynamic phase adjustment, there are still many deficiencies. First, traditional methods rely heavily on the precise design and process matching of analog circuits and are difficult to achieve high-precision phase control in a digital environment. Especially when the number of phases is large, the complexity and cost of system design increase significantly. Second, with the increase in the number of phases, the power consumption and chip area of the system also increase linearly or even non-linearly, restricting its application in large-scale integrated circuits. In addition, since systematic deviations are difficult to completely eliminate through traditional methods, errors still exist between the actual phase curve and the ideal phase curve, thereby affecting the accuracy of data sampling and the stability of communication systems. Summary of the Invention

[0004] In view of the above existing problems, the present invention is proposed.

[0005] Therefore, the present invention provides a digital calibration method and system for multi-phase clocks to solve the phase error problem caused by systematic deviations in the actual circuit implementation of multi-phase clocks.

[0006] To solve the above technical problems, the present invention provides the following technical solutions:

[0007] In a first aspect, an embodiment of the present invention provides a digital calibration method for a multi-phase clock, which includes selecting a training sequence type and configuring a sampling circuit; fixing the PI Code, sampling the input data according to the set training sequence, recovering the corresponding clock phase of the initialized PI Code through a curve fitting algorithm, and sequentially fixing multiple PI Codes; analyzing the deviation between the clock phases of each phase obtained by actual measurement and the ideal phase, and quantifying the systematic deviation by plotting a curve; calculating a pre-distortion function according to the difference between the actual phase curve and the ideal phase curve; storing the calculated pre-distortion function in the non-volatile storage space of the chip; when the chip is operating normally, reading the stored pre-distortion function and compensating it in real time through a digital logic circuit to generate a calibrated clock phase index.

[0008] As a preferred solution of the digital calibration method for the multi-phase clock according to the present invention, the training sequence type includes a sine wave, a triangular wave, and a sawtooth wave.

[0009] As a preferred solution of the digital calibration method for the multi-phase clock according to the present invention, fixing the PI Code, sampling the input data according to the set training sequence, recovering the corresponding clock phase of the initialized PI Code through a curve fitting algorithm, and sequentially fixing multiple PI Codes includes the following steps:

[0010] Set the PI Code to 0 through a control interface, and confirm that the clock signal output by the phase interpolator has a phase corresponding to the predetermined phase of PI Code 0;

[0011] Use an oscilloscope or a logic analyzer to monitor the output of the clock signal, and confirm that the frequency of the clock signal is consistent with the reference clock source and the phase meets the expectations;

[0012] According to the set training sequence, the receiving end samples the input data using the clock signal to obtain a digital signal sequence;

[0013] Collect the known training sequence parameters and the acquired digital signal sequence;

[0014] Use the least mean square error algorithm Fit the collected data to calculate the optimal clock phase , taking the sine training sequence as an example, its expression is,

[0015] ;

[0016] Where, is the clock phase parameter to be obtained, is the number of sampling times, is the time interval of the th sampling, is the digital signal value obtained by the th subsampling, is the signal amplitude, is the signal frequency;

[0017] Set the initial phase estimate value, and according to the optimization objective, iteratively adjust the value until it converges to the optimal solution ;

[0018] When the phase adjustment amount is less than the predetermined threshold ϵ, stop the iteration and accept the current as the recovery result;

[0019] Repeat the above steps, traverse the PI Code, and obtain the optimal phase as the clock phase corresponding to the PI Code ;

[0020] As a preferred solution of the digital calibration method of the multi-phase clock according to the present invention, wherein: analyze the deviation between the phase of each phase clock obtained by actual measurement and the ideal phase, and quantify the systematic deviation by plotting a curve, including the following steps,

[0021] Determine the clock period and the number of phases;

[0022] For each PI Code , calculate its corresponding ideal clock phase;

[0023] Obtain the actual clock phase corresponding to each recovered PI Code ;

[0024] For each PI Code , calculate the deviation between its actual phase and the ideal phase;

[0025] Taking the PI Code as the horizontal axis and the calculated phase deviation as the vertical axis, plot a curve of the phase deviation changing with the PI Code;

[0026] Observe the plotted phase deviation curve and identify whether there is an obvious pattern;

[0027] Through statistical analysis methods, further quantify the characteristics of the deviation pattern;

[0028] According to the identified deviation pattern, determine the main components and characteristics of the deviation;

[0029] If the deviation curve is close to a straight line, it is considered a linear deviation. If the deviation curve presents a curve or other complex shapes, it is considered a nonlinear deviation. If the deviation curve shows periodic fluctuations, the frequency and amplitude of the periodic deviation are analyzed.

[0030] For linear deviations, the slope and intercept are quantified; for nonlinear deviations, the high-order coefficients and low-order coefficients are quantified; for periodic deviations, the frequency and amplitude are quantified.

[0031] As a preferred solution of the digital calibration method of the multi-phase clock of the present invention, the pre-distortion function is calculated according to the difference between the actual phase curve and the ideal phase curve, including the following steps:

[0032] The actual phase Forming an actual phase curve;

[0033] Based on the calculated ideal phase, an ideal phase curve is defined;

[0034] Define the objective function of the PI Code error after calibration;

[0035] For each PI Code , corresponding to an actual phase ;

[0036] Using numerical methods to Perform an approximate inverse operation and calculate the predistortion function based on the error minimization objective. The expression is:

[0037] ;

[0038] in, As the pre-distortion function, PI Code Mapped to new PI Code index , is the approximate inverse function of the actual phase curve, is the clock period, is the number of phases;

[0039] Collect all actual phases , and the corresponding PI Code index ;

[0040] According to the characteristics of the actual phase curve, select the interpolation method, perform interpolation operation on the actual phase curve, and calculate The approximate value of

[0041] The calculated pre-distortion function values are organized into a discrete mapping table.

[0042] As a preferred embodiment of the digital calibration method for the multi-phase clock of the present invention, the method includes the following steps of storing the calculated pre-distortion function in the non-volatile storage space of the chip:

[0043] Determine the storage capacity required for the pre-distortion function, evaluate the access speed requirements for the pre-distortion function during normal chip operation, and consider the write frequency of the pre-distortion function;

[0044] Select the type of non-volatile memory according to the storage requirements;

[0045] Determine the address range and data width of the memory according to the number of phases;

[0046] Construct a pre-distortion mapping table according to the calculated pre-distortion function;

[0047] Convert the data of the pre-distortion mapping table into a format recognizable by the memory, ensuring that the encoded bit width of each mapping value conforms to the storage specification of the memory;

[0048] Organize the pre-distortion mapping table data into the programming format of the memory according to the memory requirements, ensuring that the arrangement order of the data is consistent with the address correspondence relationship of the memory;

[0049] Write the pre-distortion mapping table into the selected non-volatile memory through the programming interface.

[0050] As a preferred embodiment of the digital calibration method for the multi-phase clock of the present invention, the method includes the following steps of reading the stored pre-distortion function during normal chip operation and generating a calibrated clock phase index through real-time compensation by a digital logic circuit:

[0051] During normal chip operation, read the pre-distortion mapping table from the non-volatile memory;

[0052] Monitor and obtain the PI Code input by the current phase interpolator , and find the corresponding pre-distortion value in the loaded pre-distortion mapping table;

[0053] Assign the found pre-distortion mapping value to a new PI Code index ;

[0054] Transfer the new PI Code index to the phase interpolator to update the clock signal output.

[0055] In a second aspect, the present invention provides a digital calibration system for a multi-phase clock, including a training sequence generation module responsible for selecting the type of training sequence and configuring a sampling circuit; a clock phase recovery module responsible for fixing the PI Code, sampling the input data according to the set training sequence, recovering the corresponding clock phase of the initialized PI Code through a curve fitting algorithm, and sequentially fixing multiple PI Codes; a phase deviation analysis module responsible for analyzing the deviation between the phase clocks actually measured and the ideal phase, and quantifying the systematic deviation by drawing a curve; a pre-distortion function calculation module responsible for calculating a pre-distortion function according to the difference between the actual phase curve and the ideal phase curve; a non-volatile storage module responsible for storing the calculated pre-distortion function in the non-volatile storage space of the chip; and a pre-distortion application module responsible for reading the stored pre-distortion function during normal operation of the chip, compensating in real time through a digital logic circuit, and generating a calibrated clock phase index.

[0056] In a third aspect, an embodiment of the present invention provides a computer device, including a memory and a processor, where the memory stores a computer program, and: when the computer program is executed by the processor, any step of the digital calibration method for a multi-phase clock as described in the first aspect of the present invention is implemented.

[0057] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, and: when the computer program is executed by the processor, any step of the digital calibration method for a multi-phase clock as described in the first aspect of the present invention is implemented.

[0058] The beneficial effects of the present invention are as follows: by generating pre-distortion parameters for real-time compensation, it is ensured that the multi-phase clock system can dynamically adjust the PI Code during actual operation, achieve precise alignment of phases. Based on efficient and accurate calculation of the pre-distortion function, the systematic phase deviation is significantly reduced, the alignment accuracy of the clock signal and the signal-to-noise ratio of the overall system are improved, thereby enhancing the performance of the high-speed digital communication system and the reliability of data transmission. Description of the Drawings

[0059] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0060] Figure 1 It is a flowchart of the digital calibration method for a multi-phase clock in Embodiment 1.

[0061] Figure 2 It is a flowchart of the digital calibration system for a multi-phase clock in Embodiment 1. Detailed implementation manners

[0062] To make the above objects, features and advantages of the present invention more obvious and understandable, the following detailed description of the specific implementation manners of the present invention will be made with reference to the accompanying drawings of the specification.

[0063] In the following description, many specific details are set forth to fully understand the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0064] Secondly, the so-called "one embodiment" or "embodiment" herein refers to a specific feature, structure or characteristic that may be included in at least one implementation manner of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments.

[0065] Embodiment 1, referring to Figure 1 and Figure 2 , is the first embodiment of the present invention. This embodiment provides a digital calibration method for a multi-phase clock, including the following steps:

[0066] S1. Select the type of training sequence and configure the sampling circuit;

[0067] S1.1. According to the selected type of training sequence (sine wave, triangular wave, and sawtooth wave), switch the signal generator to the corresponding working mode;

[0068] For a sine wave, select a known and stable frequency, set a definite amplitude, ensure that the signal is within the linear range of the sampling circuit, and set the frequency and amplitude to predetermined values, ensuring that the phase is set to 0 or other predetermined values to simplify the measurement; for a triangular wave, set a known period and the slopes of the signal rise and fall, ensuring that the rising and falling phases of the signal are smooth and meet expectations; for a sawtooth wave, set a known period and the slopes of the signal rise and fall, ensuring that the sharp change part of the signal meets the measurement requirements;

[0069] Use measuring instruments such as an oscilloscope to verify whether the parameters of the generated training sequence signal meet expectations. According to the actual measurement results, fine-tune the parameters of the signal generator to ensure the accuracy and stability of the signal;

[0070] Check the noise level and distortion of the training sequence signal to ensure the transmission quality of the signal in the sampling circuit. If necessary, add a filter or other signal processing modules to optimize the signal quality.

[0071] S1.2. Use high-quality connection lines or interfaces to firmly connect the output end of the signal generator to the input end of the sampling circuit, ensure impedance matching of the connection path, and avoid signal reflection and distortion;

[0072] According to the input requirements of the sampling circuit, adjust the level of the training sequence signal to make it within the optimal working range of the circuit. If necessary, use an amplifier or attenuator to adjust the signal amplitude;

[0073] Ensure that the transmission of the training sequence signal is synchronized with the system clock, avoid phase drift during signal transmission, use a low-delay and high-stability transmission path, and reduce the phase error during signal transmission;

[0074] Use an oscilloscope or logic analyzer to detect the signal status at the input end of the sampling circuit, confirm the correct signal transmission, check whether the signal waveform is consistent with the output of the training sequence generator, and ensure the integrity of the signal;

[0075] After confirming the error-free signal transmission, set the sampling trigger condition of the sampling circuit and prepare for the subsequent data acquisition process.

[0076] S2. Fix the PI Code, sample the input data according to the set training sequence, recover the corresponding clock phase of the initialized PI Code through a curve fitting algorithm, and fix multiple PI Codes in sequence, including the following steps,

[0077] S2.1. Set the PI Code to 0 through the control interface, that is, set the input PI Code of the phase interpolator to 0, and confirm the output clock signal CLK[0] of the phase interpolator. Its phase should correspond to the predetermined phase of PI Code 0;

[0078] Use an oscilloscope or logic analyzer to monitor the output of the clock signal, ensure the signal is stable and has no obvious distortion, confirm that the frequency of the clock signal is consistent with the reference clock source, and the phase meets the expectations.

[0079] S2.2. According to the set training sequence, the receiving end samples the input data using the clock signal to obtain a digital signal sequence;

[0080] Specifically, activate the sampling circuit to start sampling the input training sequence according to the rising edge or falling edge of CLK[0], ensure that the sampling clock is synchronized with the training sequence, and avoid sampling errors caused by clock drift; under the control of the clock CLK[0], the receiving end samples the input training sequence M times, records the digital signal values of each sampling point, and obtains a digital signal sequence.

[0081] S2.3. Collect the known training sequence parameters (amplitude, frequency) and the acquired digital signal sequence;

[0082] Use the least mean square error algorithm to fit the collected data and calculate the optimal clock phase , so that the fitting error is minimized. When the training sequence is a sine wave, its expression is

[0083] ;

[0084] where is the clock phase parameter to be solved is the number of sampling times is the time interval of the -th sampling is the digital signal value obtained from the -th sampling is the signal amplitude is the signal frequency;

[0085] Set the initial phase estimate value and iteratively adjust the value according to the optimization objective of until it converges to the optimal solution ;

[0086] When the phase adjustment amount is less than the predetermined threshold ϵ, stop the iteration and accept the current as the recovery result

[0087] S2.4. Repeat the above steps S2.1, S2.2, and S2.3, and use the obtained optimal phase as the clock phase corresponding to the PI Code

[0088] S3. Analyze the deviation between the clock phases of each phase obtained from the actual measurement and the ideal phase, and quantify the systematic deviation by plotting a curve, including the following steps

[0089] S3.1. Determine the clock period, that is, the duration of a single clock signal and the number of phases, that is, the number of different phases included in the multi-phase clock

[0090] For each PI Code ( ), calculate its corresponding ideal clock phase, and the expression is

[0091] ;

[0092] where is the ideal clock phase at PI Code , is the clock period is the number of phases​ It is the current PI Code index;

[0093] Get each PI Code recovered The actual clock phase corresponding to ;

[0094] For each PI Code , calculate the deviation between its actual phase and the ideal phase;

[0095] S3.2, with PI Code The horizontal axis is the calculated phase deviation, and the vertical axis is the phase deviation curve.

[0096] Observe the plotted phase deviation curve to identify whether there is an obvious pattern, such as linear deviation, nonlinear deviation or periodic deviation; Linear deviation: the deviation changes with Linear increase or decrease may be caused by systematic errors; nonlinear deviation: the deviation increases or decreases with It changes nonlinearly, which may be caused by nonlinear components or other complex factors. Periodic deviation: The deviation changes with It fluctuates periodically and may be caused by jitter or high-frequency interference of the clock signal.

[0097] Further quantify the characteristics of the deviation pattern through statistical analysis methods, such as regression analysis and Fourier transform; for example, fit the linear component of the deviation curve to determine the deviation growth rate, use Fourier transform to detect the frequency component in the deviation curve, and identify periodic interference;

[0098] Prepare a phase deviation analysis report that describes in detail the identified deviation patterns and characteristics, providing supporting graphs and statistical data.

[0099] S3.3. Based on the identified deviation patterns, determine the main components and characteristics of the deviation;

[0100] If the deviation curve is close to a straight line, it is considered as a linear deviation, which can be described by a first-order polynomial model. If the deviation curve is a curve or other complex shape, it is considered as a nonlinear deviation, which may require a higher-order polynomial model or other nonlinear model to describe. If the deviation curve shows periodic fluctuations, analyze the frequency and amplitude of the periodic deviation. The periodic deviation may be caused by high-frequency noise or clock jitter, and filtering or noise suppression measures need to be considered.

[0101] For linear deviations, the slope and intercept are quantified; for nonlinear deviations, the high-order coefficients and low-order coefficients are quantified; for periodic deviations, the frequency and amplitude are quantified.

[0102] S4. Calculate the predistortion function based on the difference between the actual phase curve and the ideal phase curve, including the following steps:

[0103] S4.1. Take the actual phase to form the actual phase curve, expressed as:

[0104] ;

[0105] where is the actual phase at PI Code , is the actual clock phase at PI Code ;

[0106] Based on the calculated ideal phase, define the ideal phase curve, expressed as:

[0107] ;

[0108] where is the ideal phase at PI Code ;

[0109] Define the objective function for the calibrated PI Code error to be minimized, expressed as:

[0110] ;

[0111] where is the actual phase mapped by the predistortion function ;

[0112] S4.2. For each PI Code , there corresponds an actual phase ;

[0113] Since usually does not have an analytical inverse function, numerical methods need to be used to approximately invert . Commonly used numerical methods include interpolation and inverse interpolation;

[0114] Based on the error minimization objective, calculate the predistortion function, and the expression is:

[0115] ;

[0116] where is the predistortion function that maps PI Code to the new PI Code index , is the approximate inverse function of the actual phase curve that maps the ideal phase back to the actual phase, is the clock cycle, is the number of phases.

[0117] S4.3. Collect all actual phases , and the corresponding PI Code indices ;

[0118] According to the characteristics of the actual phase curve, select the interpolation method: Linear interpolation: simple and with low computational complexity, suitable for cases where the phase change is relatively linear; Spline interpolation: suitable for cases where there is a non-linear trend in the phase change, providing a smoother fitting effect; Polynomial interpolation: suitable for complex phase change models, but may introduce high-order oscillations;

[0119] Perform interpolation operations on the actual phase curve using the selected interpolation method to calculate the approximate value; for example (linear interpolation):

[0120] For each ideal phase , find the two closest points and on the actual phase curve; calculate the corresponding PI Code index through linear interpolation, and the expression is

[0121] ;

[0122] where ;

[0123] Organize the calculated pre-distortion function values into a pre-distortion mapping table to ensure the integrity and accuracy of the mapping table, which closely corresponds to the actual phase curve .

[0124] S5. Store the calculated pre-distortion function in the non-volatile storage space of the chip, including the following steps

[0125] S5.1. Determine the storage capacity required for the pre-distortion function. For N-phase, the pre-distortion function is usually stored in the form of a Lookup Table (LUT), where each PI Code corresponds to an integer mapping value. Evaluate the access speed requirements for the pre-distortion function during normal chip operation to ensure that the memory can meet the needs of real-time compensation, and consider the write frequency of the pre-distortion function. During the foreground calibration phase, usually only one write is required, which is suitable for one-time programmable or low-write-count memories;

[0126] According to the storage requirements, select the non-volatile memory type, including but not limited to E-Fuse, one-time programmable memory, and electrically erasable programmable read-only memory;

[0127] Determine the address range and data width of the memory according to the number of phases. For example, if N = 8, 8 memory addresses are required, and each address stores a pre-distortion function mapping value to ensure that the selected memory can cover the storage requirements of all N PI Codes;

[0128] S5.2. Construct a pre-distortion mapping table according to the calculated pre-distortion function;

[0129] Convert the data of the pre-distortion mapping table into a format recognizable by the memory. For example, convert each value into binary representation to ensure that the coding bit width of each mapping value meets the storage specifications of the memory. For example, if the value range is from 0 to 15, each mapping value can be represented by 4-bit binary;

[0130] Organize the data of the pre-distortion mapping table into the programming format of the memory according to the memory requirements. For example, for EEPROM, the data can be formatted into page programming format to ensure that the arrangement order of the data is consistent with the address correspondence relationship of the memory and avoid data storage errors;

[0131] Write the pre-distortion mapping table into the selected non-volatile memory through the programming interface.

[0132] S6. When the chip is working normally, read the stored pre-distortion function and perform real-time compensation through digital logic circuits to generate a calibrated clock phase index, including the following steps:

[0133] When the chip is working normally, read the pre-distortion mapping table from the non-volatile memory;

[0134] Read the pre-distortion mapping table from the non-volatile memory one by one through the programming interface (such as I²C, SPI or other protocols), perform preliminary verification on the read data to ensure data integrity and correctness, and load the valid pre-distortion function into the digital logic circuit for real-time compensation use;

[0135] Monitor and obtain the PI Code input by the current phase interpolator , and find the corresponding pre-distortion value in the loaded pre-distortion mapping table;

[0136] Assign the found pre-distortion mapping value to a new PI Code index ;

[0137] Transfer the new PI Code index to the phase interpolator to update the clock signal output;

[0138] Transfer the calibrated PI Code index Input to the phase interpolator, output a calibrated clock signal to ensure the best alignment of the clock signal phase with the data bits.

[0139] This embodiment also provides a digital calibration system for a multi-phase clock, including: a training sequence generation module, responsible for selecting the type of training sequence and configuring the sampling circuit; a clock phase recovery module, responsible for fixing the PI Code, sampling the input data according to the set training sequence, recovering the corresponding clock phase of the initialized PI Code through a curve fitting algorithm, and sequentially fixing multiple PI Codes; a phase deviation analysis module, responsible for analyzing the deviation between the phase of each phase clock obtained by actual measurement and the ideal phase, and quantifying the systematic deviation by drawing a curve; a pre-distortion function calculation module, responsible for calculating the pre-distortion function according to the difference between the actual phase curve and the ideal phase curve; a non-volatile storage module, responsible for storing the calculated pre-distortion function in the non-volatile storage space of the chip; a pre-distortion application module, responsible for reading the stored pre-distortion function during normal operation of the chip, compensating in real time through digital logic circuits, and generating a calibrated clock phase index.

[0140] This embodiment also provides a computer device applicable to the case of the digital calibration method for a multi-phase clock, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the digital calibration method for a multi-phase clock as proposed in the above embodiment.

[0141] This computer device can be a terminal. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected through a system bus. Among them, the processor of this computer device is used to provide computing and control capabilities. The memory of this computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of this computer device is used to communicate with an external terminal in a wired or wireless manner. The wireless manner can be achieved through WIFI, a carrier network, NFC (Near Field Communication), or other technologies. The display screen of this computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of this computer device can be a touch layer covered on the display screen, or a button, a trackball, or a touchpad set on the shell of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0142] This embodiment also provides a storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the digital calibration method for implementing a multi-phase clock as proposed in the above embodiment; the storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (Static Random Access Memory, abbreviated as SRAM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, abbreviated as EEPROM), erasable programmable read-only memory (Erasable Programmable Read Only Memory, abbreviated as EPROM), programmable read-only memory (Programmable Red-Only Memory, abbreviated as PROM), read-only memory (Read-Only Memory, abbreviated as ROM), magnetic memory, flash memory, magnetic disk or optical disc.

[0143] In summary, the present invention achieves the following: By selecting an appropriate training sequence type and precisely configuring the sampling circuit, it realizes the generation and capture of a reference signal with known characteristics, ensures that the training sequence signal has a stable frequency and amplitude, completes the acquisition of accurate and consistent phase reference data, and provides a reliable reference signal for subsequent phase measurement; by systematically obtaining the clock phase information at each phase, it ensures the high precision and consistency of phase recovery, realizes comprehensive phase mapping and precise clock phase recovery, provides detailed data support for subsequent phase deviation analysis and pre-distortion function calculation, and improves the calibration accuracy of the multi-phase clock system; by identifying the specific pattern of the deviation, clarifying the nature and characteristics of the systematic deviation, it realizes precise deviation quantitative analysis, enables the design of the pre-distortion function to be optimized according to the specific deviation characteristics, and ensures the effectiveness of the calibration effect and the improvement of system performance; by generating pre-distortion parameters for real-time compensation, it ensures that the multi-phase clock system can dynamically adjust the PI Code during actual operation, realizes precise phase alignment, and based on efficient and accurate pre-distortion function calculation, significantly reduces systematic phase deviation, improves the alignment accuracy of the clock signal and the signal-to-noise ratio of the overall system, thereby enhancing the performance of the high-speed digital communication system and the reliability of data transmission.

[0144] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A digital calibration method for a multi-phase clock, characterized in that: including Select a training sequence type and configure the sampling circuit; Fix the PI Code, sample the input data according to the set training sequence, recover the corresponding clock phase of the initialized PI Code through a curve fitting algorithm, and sequentially fix multiple PI Codes; Analyze the deviation between the clock phases of each phase obtained from actual measurement and the ideal phase, and quantify the systematic deviation by plotting a curve; Calculate the pre-distortion function according to the difference between the actual phase curve and the ideal phase curve; Store the calculated pre-distortion function in the non-volatile storage space of the chip; When the chip is working normally, read the stored pre-distortion function, perform real-time compensation through digital logic circuits, and generate a calibrated clock phase index; Fix the PI Code, sample the input data according to the set training sequence, recover the corresponding clock phase of the initialized PI Code through a curve fitting algorithm, and sequentially fix multiple PI Codes, including the following steps Set the PI Code to 0 through the control interface, and confirm that the clock signal output by the phase interpolator has a phase corresponding to the predetermined phase of PICode 0; Use an oscilloscope or logic analyzer to monitor the output of the clock signal, and confirm that the frequency of the clock signal is consistent with the reference clock source and the phase meets the expectation; According to the set training sequence, the receiving end samples the input data using the clock signal to obtain a digital signal sequence; Collect the known training sequence parameters and the collected digital signal sequence; Using the least mean square error algorithm Fit the collected data and calculate the optimal clock phase , when the training sequence is a sine wave, its expression is ； wherein, is the clock phase parameter to be obtained, is the number of sampling times, is the time interval of the th sampling, is the digital signal value obtained from the th sampling, is the signal amplitude, is the signal frequency; Set the initial phase estimation value, and iteratively adjust the value according to the optimization objective until convergence to the optimal solution ; ; When the phase adjustment amount is less than a predetermined threshold ϵ, stop the iteration and accept the current as the recovery result; Repeat the above steps to traverse the PI Code and obtain the optimal phase as the PI Code and the corresponding clock phase 2. The digital calibration method for a multi-phase clock according to claim 1, characterized in that: Analyze the deviation between the clock phases of each phase obtained from actual measurement and the ideal phase, and quantify the systematic deviation by plotting a curve, including the following steps Determine the clock period and the number of phases; For each PI Code , calculate its corresponding ideal clock phase; Obtain the actual clock phase corresponding to each restored PI Code when For each PI Code , calculate the deviation between its actual phase and the ideal phase; With the PI Code as the horizontal axis and the calculated phase deviation as the vertical axis, plot a curve graph showing the variation of the phase deviation with the PI Code; Observe the plotted phase deviation curve and identify whether there is an obvious pattern; Further quantify the characteristics of the deviation pattern through statistical analysis methods; According to the identified deviation pattern, determine the main components and characteristics of the deviation; If the deviation curve is approximately a straight line, it is judged as a linear deviation. If the deviation curve shows a curve or other complex shape, it is judged as a non-linear deviation. If the deviation curve exhibits periodic fluctuations, analyze the frequency and amplitude of the periodic deviation; For linear deviation, quantify its slope and intercept. For non-linear deviation, quantify its high-order coefficient and low-order coefficient. For periodic deviation, quantify its frequency and amplitude.

3. The digital calibration method of the multi-phase clock according to claim 2, characterized in that: Calculate the pre-distortion function according to the difference between the actual phase curve and the ideal phase curve, including the following steps actual phase form an actual phase curve; Based on the calculated ideal phase, define the ideal phase curve; Define the objective function of the calibrated PI Code error; For each PI Code , there corresponds an actual phase ; A numerical method is used to perform an approximate inverse operation. Based on the objective of minimizing the error, a predistortion function is calculated, and the expression is ； Among them, is the predistortion function that maps the PI Code to a new PI Code index , is the approximate inverse function of the actual phase curve, is the clock period, is the number of phases; Collect all actual phases , and the corresponding PI Code index ; According to the characteristics of the actual phase curve, select an interpolation method and perform an interpolation operation on the actual phase curve to calculate the approximate value; Organize the calculated pre-distortion function values into a discrete mapping table.

4. The digital calibration method of the multi-phase clock according to claim 3, characterized in that: Store the calculated pre-distortion function in the non-volatile storage space of the chip, including the following steps Determine the storage capacity required for the pre-distortion function, evaluate the access speed requirements for the pre-distortion function when the chip is working normally, and consider the write frequency of the pre-distortion function; Select the non-volatile memory type according to the storage requirements; Determine the address range and data width of the memory according to the number of phases; Construct a pre-distortion mapping table according to the calculated pre-distortion function; Convert the data of the predistortion mapping table into a format recognizable by the memory, ensuring that the encoded bit width of each mapping value complies with the storage specifications of the memory; Organize the predistortion mapping table data into the programming format of the memory according to the memory requirements, ensuring that the arrangement order of the data is consistent with the address correspondence of the memory; Write the predistortion mapping table into the selected non-volatile memory through the programming interface.

5. The digital calibration method of the multi-phase clock according to claim 4, characterized in that: When the chip is working normally, read the stored predistortion function and perform real-time compensation through the digital logic circuit to generate a calibrated clock phase index, including the following steps When the chip is working normally, read the predistortion mapping table from the non-volatile memory; Monitor and obtain the PI Code input by the current phase interpolator , and look up the corresponding predistortion value in the loaded predistortion mapping table; Assign the found pre-distortion mapping value to the new PI Code index ; Transfer the new PI Code index to the phase interpolator to update the clock signal output.

6. A digital calibration system for a multi-phase clock, based on the digital calibration method of the multi-phase clock according to any one of claims 1 to 5, characterized in that: including The training sequence generation module is responsible for selecting the training sequence type and configuring the sampling circuit; The clock phase recovery module is responsible for fixing the PI Code, sampling the input data according to the set training sequence, recovering the corresponding clock phase of the initialized PI Code through the curve fitting algorithm, and fixing multiple PI Codes in sequence; The phase deviation analysis module is responsible for analyzing the deviation between the actually measured clock phases of each phase and the ideal phase, and quantifying the systematic deviation by drawing a curve; The predistortion function calculation module is responsible for calculating the predistortion function according to the difference between the actual phase curve and the ideal phase curve; The non-volatile storage module is responsible for storing the calculated predistortion function in the non-volatile storage space of the chip; The predistortion application module is responsible for reading the stored predistortion function when the chip is working normally, and generating a calibrated clock phase index through real-time compensation by the digital logic circuit.

7. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the digital calibration method of the multi-phase clock according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the digital calibration method of the multi-phase clock according to any one of claims 1 to 5.

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