Phase-locked loop control circuit, phase-locked loop circuit and control method thereof

Abstract

The invention discloses a phase-locked loop circuit. The device comprises a reference current generating circuit for generating a reference current, a frequency calibration circuit for generating a current adjusting signal according to a target frequency, a multiplying power adjusting circuit for adjusting the reference current to the target frequency current according to the current adjusting signal, an oscillating circuit for generating an output clock signal according to the target frequency current, and a front-end circuit. The front-end circuit detects a phase and a frequency difference between an output clock signal and a reference clock signal to generate a first control signal. The oscillation circuit adjusts the output frequency of the output clock signal to be consistent with the target frequency based on the first control signal and the target frequency current. When the first control signal deviates, the front-end circuit generates a second control signal to enable the multiplying power adjusting circuit to adjust the target frequency current according to the sum of the reference current and the second control signal.

Description

Technical Field

[0001] The present invention relates to a phase-locked loop circuit, a phase-locked loop control circuit for controlling an oscillating circuit, and a control method for the phase-locked loop, and in particular to a phase-locked loop circuit with a frequency band calibration mechanism and a temperature tracking lock function, a phase-locked loop control circuit for controlling an oscillating circuit, and a control method for the phase-locked loop. Background Art

[0002] In a conventional phase-locked loop circuit, the oscillator itself may produce an output frequency deviation due to process or temperature changes. When the output frequency of the oscillator changes beyond the adjustment range of the phase-locked loop, the phase-locked loop circuit will be out of lock and unable to generate a stable output clock signal.

[0003] In the past, in order to overcome the problem of output frequency deviation caused by process or temperature changes, the oscillator's voltage-frequency gain parameter (K) was usually increased. VCO ) to enable the oscillator to cover a wider range of process and temperature variations. However, this approach amplifies the periodic spike noise generated when the charge pump (CP) charges the filter circuit, which in turn causes the oscillator's output frequency to generate more phase noise. Summary of the invention

[0004] Therefore, the purpose of the present invention is to provide a phase-locked loop circuit, a phase-locked loop control circuit and a phase-locked loop control method, adding an additional tracking loop, a multiplier adjustment circuit and a frequency calibration circuit to provide a fine-tuning control signal when the frequency of the oscillator is offset, so as to adjust the output frequency of the oscillator to be consistent with the target frequency.

[0005] According to the above-mentioned purpose of the present disclosure, a phase-locked loop circuit is provided, comprising a reference current generating circuit, a frequency calibration circuit, a multiplier adjustment circuit, an oscillation circuit and a front-end circuit. The reference current generating circuit is configured to generate a reference current. The frequency calibration circuit is configured to generate a current adjustment signal according to a target frequency. The multiplier adjustment circuit is configured to adjust the reference current to a target frequency current according to the current adjustment signal. The oscillation circuit is configured to receive a target frequency current and generate an output clock signal according to the target frequency current. The front-end circuit is configured to detect the phase and frequency difference between the output clock signal and the reference clock signal to generate a first control signal to the oscillation circuit, so that the oscillation circuit adjusts the output frequency of the output clock signal based on the first control signal and the target frequency current to be consistent with the target frequency. Wherein, when the first control signal is offset, the front-end circuit is also configured to generate a second control signal so that the multiplier adjustment circuit adjusts the target frequency current according to the sum of the reference current and the second control signal.

[0006] According to an embodiment of the present disclosure, the front-end circuit includes a phase frequency detection circuit, a charge pump, and a filter circuit. The phase frequency detection circuit is configured to detect the phase and frequency difference between the output clock signal and the reference clock signal to generate an error signal. The charge pump is electrically connected to the phase frequency detection circuit and configured to convert the error signal into an error current signal. The filter circuit is electrically connected to the charge pump and configured to generate a first control signal and a second control signal according to the error current signal.

[0007] According to an embodiment of the present disclosure, the filter circuit includes a first capacitor, a resistor, and a second capacitor. The first capacitor is electrically connected to a reference voltage terminal. The resistor is connected between a charge pump and the first capacitor. The second capacitor is electrically connected between the charge pump and the reference voltage terminal. The voltage across the first capacitor is used as a sampling voltage, and the voltage across the second capacitor is used as a first control signal.

[0008] According to an embodiment of the present disclosure, the front-end circuit further includes an operational transconductance amplifier (OTA) configured to convert a difference between the sampled voltage and a reference voltage into a second control signal, wherein the reference voltage corresponds to a target frequency.

[0009] According to an embodiment of the present disclosure, the front-end circuit further includes a comparator circuit. The comparator circuit is configured to generate an upper limit control signal and a lower limit control signal to the frequency calibration circuit when the sampled voltage exceeds the reference voltage range, so that the frequency calibration circuit generates a corresponding current adjustment signal according to the target frequency, the upper limit control signal and the lower limit control signal.

[0010] According to an embodiment of the present disclosure, the oscillation circuit is a current-controlled oscillation circuit, and a voltage-current conversion circuit is included between the front-end circuit and the current-controlled oscillation circuit. The voltage-current conversion circuit is configured to convert the first control signal into a current signal.

[0011] According to an embodiment of the present disclosure, the multiplier adjustment circuit includes a plurality of multiplier gears, so that the multiplier adjustment circuit selects one of the multiplier gears based on the current adjustment signal to adjust the reference current to the target frequency current according to the one of the multiplier gears.

[0012] According to an embodiment of the present disclosure, when the first control signal is offset, the multiplier adjustment circuit adjusts the sum of the reference current and the second control signal to a correction current according to one of the multipliers of the multiplier levels to serve as the target frequency current.

[0013] According to another object of the present disclosure, a phase-locked loop control circuit is provided for controlling the output clock signal of an oscillating circuit, wherein the phase-locked loop control circuit includes a reference current generating circuit, a frequency calibration circuit, a multiplier adjustment circuit and a front-end circuit. The reference current generating circuit is configured to generate a reference current. The frequency calibration circuit is configured to generate a current adjustment signal according to a target frequency. The multiplier adjustment circuit is configured to adjust the reference current to a target frequency current according to the current adjustment signal, so that the oscillating circuit generates an output clock signal according to the target frequency current. The front-end circuit is configured to detect the phase and frequency difference between the output clock signal and the reference clock signal to generate a first control signal to the oscillating circuit, so that the oscillating circuit adjusts the output frequency of the output clock signal based on the first control signal and the target frequency current to be consistent with the target frequency. When the first control signal is offset, the front-end circuit is also configured to generate a second control signal, so that the multiplier adjustment circuit adjusts the target frequency current according to the sum of the reference current and the second control signal; when the first control signal is offset beyond the control range of the second control signal, the front-end circuit is also configured to generate an upper limit control signal and a lower limit control signal to the frequency calibration circuit, so that the frequency calibration circuit generates a corresponding current adjustment signal according to the target frequency, the upper limit control signal and the lower limit control signal.

[0014] According to another object of the present disclosure, a control method of a phase-locked loop is provided for controlling an oscillating circuit, wherein the method includes performing a frequency calibration operation and a phase-locked loop operation. Performing a frequency calibration operation includes: generating a corresponding current adjustment signal to a multiplier adjustment circuit according to a target frequency of the oscillating circuit; providing a reference current to the multiplier adjustment circuit; and adjusting the reference current to a target frequency current according to the current adjustment signal, so that the oscillating circuit generates an output clock signal according to the target frequency current. Performing a phase-locked loop operation includes: using a front-end circuit to detect the phase and frequency difference between the output clock signal and the reference clock signal; generating a first control signal to the oscillating circuit, so that the oscillating circuit adjusts the output frequency of the output clock signal based on the first control signal and the target frequency current to be consistent with the target frequency; wherein, when the first control signal is offset, the front-end circuit is also used to generate a second control signal, so that the multiplier adjustment circuit adjusts the target frequency current according to the sum of the reference current and the second control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to make the above and other objects, features, advantages and embodiments of the present invention more understandable, the accompanying drawings are described as follows:

[0016] Figure 1 A schematic diagram of a phase-locked loop circuit according to an embodiment of the present invention;

[0017] Figure 2 is a schematic diagram of a front-end circuit according to an embodiment of the present invention;

[0018] Figure 3 is a schematic diagram of a front-end circuit according to another embodiment of the present invention; and

[0019] Figure 4 and Figure 5 4 is a flow chart of a phase-locked loop control method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] Figure 1 1 is a schematic diagram of a phase-locked loop circuit 100 according to an embodiment of the present invention. The phase-locked loop circuit 100 includes a reference current generating circuit 110 , a frequency calibration circuit 120 , a multiplier adjusting circuit 130 , an oscillating circuit 140 and a front-end circuit 150 .

[0021] The reference current generating circuit 110 is configured to generate a reference current I BIAS This reference current I BIAS The frequency calibration circuit 120 is configured to generate a constant current which is stable and not affected by temperature, frequency and process. T Generate a current adjustment signal S CA For example, if the target frequency f required by the oscillation circuit 140 is T If the frequency is 10 GHz, the frequency calibration circuit 120 will generate a current adjustment signal S corresponding to 10 GHz. CA Thus, the oscillating circuit 140 can adjust the target frequency f according to the desired target frequency f. T Instead, switch to a different target frequency band.

[0022] The multiplier adjustment circuit 130 is electrically connected to the reference current generation circuit 110 and the frequency calibration circuit 120, and is configured to receive the reference current I BIAS and current adjustment signal S CA , to adjust the signal S according to the current CA The reference current I BIAS Adjust to the target frequency current I TF In some embodiments, the rate adjustment circuit 130 includes a plurality of rate levels. When the rate adjustment circuit 130 receives the current adjustment signal S CA When the power is on, it will automatically select the appropriate power level from these power levels, and use the appropriate power level to adjust the reference current I BIAS Adjust to the target frequency current I TF For example, if the target frequency f of the oscillator circuit 140 is T For 10GHz, the target frequency current I TF is 1mA, and the reference current I BIAS The multiplier setting of the multiplier adjustment circuit 130 needs to be 20 times to adjust the reference current IBIAS Adjust to 1mA to get a target frequency f of 10GHz T In the embodiment of the present invention, the multiplier adjustment circuit 130 includes 256 multiplier positions for adjusting the multiplier according to the desired target frequency f T The reference current I BIAS The magnification is adjusted to 256 different values ​​of the target frequency current I TF .

[0023] The oscillation circuit 140 is electrically connected to the multiplication factor adjustment circuit 130 and the front-end circuit 150 and is configured to generate a current I TF Generate output clock signal S 0 , so that the output clock signal S 0 The output frequency f 0 Close to or equal to the target frequency f T In other words, before the PLL operation is performed, the PLL circuit 100 can be configured to generate a current according to the target frequency I TF The output clock signal S of the oscillation circuit 140 is set in advance. 0 The output frequency f 0 Adjust to close to the target frequency f T (For example, at the target frequency f T During the phase-locked loop operation, since the output clock signal S 0 The output frequency f 0 It has been initially adjusted to be close to the target frequency f T , so the phase-locked loop circuit 100 can quickly convert the output clock signal S of the oscillation circuit 140 0 The output frequency f 0 Adjust to the target frequency f T In this way, the time for the phase-locked loop circuit 100 to complete phase locking and reach a stable state can be shortened.

[0024] The phase-locked loop circuit 100 includes a control loop L 1 , L 2 In the control loop L 1 In the process, the front-end circuit 150 detects the output clock signal S 0 With the reference clock signal S REF The phase and frequency difference between them is used to generate a first control signal S C1 to the oscillation circuit 140, and the oscillation circuit 140 is based on the first control signal S C1 The output clock signal S 0 The output frequency f 0 Adjust to the target frequency f T When the first control signal S C1When the output frequency f0 of the oscillator circuit 140 deviates, the control loop L is triggered. 2 , so that the front-end circuit 150 generates a second control signal S C2 to the rate adjustment circuit 130, and the rate adjustment circuit 130 adjusts the current according to the reference current I BIAS and the second control signal S C2 The sum of the target frequency current I TF In this way, the oscillation circuit 140 can be based on the first control signal S C1 And the adjusted target frequency current I TF To compensate the output frequency f 0 The offset of the adjusted output clock signal S 0 The output frequency f 0 With the target frequency f T Specifically, the multiplier adjustment circuit 130 includes an adding circuit configured to add the reference current I BIAS and the second control signal S C2 Therefore, the multiplier adjustment circuit 130 can adjust the current signal S according to the current adjustment signal S provided by the frequency calibration circuit 120. CA Select the appropriate magnification level and set the reference current I BIAS and the second control signal S C2 The sum of the current and frequency is multiplied by the appropriate multiplication factor to obtain the adjusted target frequency current I TF .

[0025] In an embodiment of the present invention, the oscillation circuit 140 is a current-controlled oscillation circuit, which is configured to receive a current control signal and a target frequency current I TF Converted into output clock signal S 0 , and a voltage-current conversion circuit (not shown) is further included between the front-end circuit 150 and the oscillation circuit 140. The voltage-current conversion circuit is used to receive the first control signal S output by the front-end circuit 150 C1 , and converts it into a current control signal. In some embodiments, the voltage-to-current conversion circuit includes a transistor, such as a metal oxide semiconductor field effect transistor (MOSFET). Specifically, the transistor can obtain a corresponding source current by inputting a gate voltage to the gate terminal to achieve conversion between voltage and current. In some embodiments, the oscillation circuit 140 is a voltage-controlled oscillation circuit, which can directly receive the first control signal S as a voltage control signal. C1 , to control the output clock signal S of the oscillation circuit 140 0 , but the present invention is not limited to this.

[0026] Figure 2 1 is an internal schematic diagram of a front-end circuit 150 according to an embodiment of the present invention. The front-end circuit 150 includes a phase frequency detection circuit 151, a charge pump 152, a filter circuit 153 and an operational transconductance amplifier 154. The supply path of the control signal includes a first path P 1 and the second path P 2 The phase frequency detection circuit 151 includes two input terminals, one of which receives a reference clock signal S REF , and the other input end is connected to the output end of the oscillation circuit 140 and is used to receive the output clock signal S 0 When the phase-locked loop mechanism is performed, the phase frequency detection circuit 151 detects the output clock signal S 0 With the reference clock signal S REF and generates an error signal S at the output end of the phase frequency detection circuit 151. e The charge pump 152 is electrically connected to the phase frequency detection circuit 151 and is configured to convert the error signal S e Converted into error current signal I e The filter circuit 153 is electrically connected to the charge pump 152 and is configured to generate a filter based on the error current signal I e The output terminal of the front-end circuit 150 generates a first control signal S C1 and the second control signal S C2 The first control signal S C1 Via the first path P 1 is supplied to the output terminal of the front-end circuit 150, and the second control signal S C2 Via the second path P 2 to be supplied to the output end of the front-end circuit 150 .

[0027] The filter circuit 153 is a second-order low-pass filter circuit, which includes a first capacitor C 1 , resistor R and second capacitor C 2 The first capacitor C 1 The resistor R is electrically connected to the output terminal of the charge pump 152 and the first capacitor C 1 The second capacitor C 2 The reference voltage terminal can be a power supply voltage (eg, a common power supply potential VDD) or a ground voltage (eg, Figure 2 The potential of the ground terminal G shown in FIG. 1 is not limited to this. The first capacitor C 1 The voltage across the circuit is used as the sampling voltage V provided to the operational transconductance amplifier 154. S , and the second capacitor C 2 The voltage across the oscillation circuit 140 is used as the first control signal S C1The oscillating circuit 140 can be controlled by the first control signal S of the filtering circuit 153. C1 Change the output frequency f 0 , and in the first control signal S C1 When the filter circuit 153 is offset, the second control signal S C2 Compensated output frequency f 0 The offset is to maintain the reference clock signal S REF and the output clock signal S 0 In an embodiment including an operational transconductance amplifier 154, the second control signal S C2 is the current control signal.

[0028] Specifically, the charge pump 152 is based on the error signal S e Generates forward or reverse error current signal I e , and the first capacitor C in the filter circuit 153 1 And the second capacitor C 2 The first control signal S generated by the filter circuit 153 is charged or discharged to change C1 And the sampling voltage V S。 The operational transconductance amplifier 154 is configured to receive the sampled voltage V S And reference voltage V ref , and the sample voltage V S With reference voltage V ref The difference between them is converted into a second control signal S C2 Since the reference voltage V ref Corresponding to the desired target frequency f T , when the first control signal S after the phase-locked loop circuit 100 is phase-locked C1 When an offset occurs, the sampling voltage V S will be related to the reference voltage V ref The difference is generated, thereby triggering the operational transconductance amplifier 154 to generate a second control signal S at the output terminal. C2 In this way, the phase-locked loop circuit 100 can convert the first control signal S C1 Adjusted to the reference voltage V ref Consistent, and then the output frequency f 0 Compensation correction back to the target frequency f T .

[0029] Figure 3 FIG. 1 is a schematic diagram of a front-end circuit 150 according to another embodiment of the present invention. In this embodiment, the front-end circuit 150 includes a phase frequency detection circuit 151, a charge pump 152, a filter circuit 153, an operational transconductance amplifier 154, and a comparator circuit 155. The supply path of the control signal includes a first path P 1 , the second path P2 and the third path P 3 Since the working principles of the phase frequency detection circuit 151, the charge pump 152 and the filter circuit 153 have been Figure 2 The embodiment shown in FIG. 1 is described in detail, so it is not repeated here. The following only describes the working principle of the comparator circuit 155. The first control signal S C1 Via the first path P 1 to the output terminal of the front-end circuit 150, the second control signal S C2 Via the second path P 2 is supplied to the output terminal of the front-end circuit 150, and the upper limit control signal S H And the lower limit control signal S L Via the third path P 3 to be supplied to the output end of the front-end circuit 150 .

[0030] The comparator circuit 155 is electrically connected to the filter circuit 153 and the frequency calibration circuit 120 ( Figure 3 Not shown) and is configured to receive a sampling voltage V S (That is, the first capacitor C 1 The cross voltage), upper limit reference voltage V ref_H And the lower limit reference voltage V ref_L . Upper limit reference voltage V ref_H And the lower limit reference voltage V ref_L The interval between is the reference voltage V ref The controllable range. When the sampling voltage V S Exceeds the reference voltage V ref When the controllable range is C1 The deviation degree has exceeded the second path P 2 The second control signal S C2 The output frequency f that can be compensated 0 The offset leads to the second path P 2 Out of lock. At this time, the sampling voltage V S The comparator circuit 155 is triggered to generate an upper limit control signal S H And the lower limit control signal S L To the frequency calibration circuit 120. In this way, the frequency calibration circuit 120 can adjust the target frequency f T , upper limit control signal S H And the lower limit control signal S L Generates the corresponding current adjustment signal S CA and target frequency current I TF , so that the output clock signal S of the oscillation circuit 140 0 The output frequency f 0 Re-adjust to the target frequency f TConsistent.

[0031] For example, the target frequency f of the oscillator circuit 140 is T is 10 GHz, corresponding to a target frequency f of 10 GHz T The reference voltage V ref is 0.55 volts (V), the reference voltage V ref The controllable range of V is between 0.45V and 0.65V. Therefore, the upper limit reference voltage V ref_H Set to 0.65V, the lower limit reference voltage V ref_L is set to 0.45V. When the first control signal S C1 When the offset is between 0.45V and 0.65V, it means that the reference voltage V ref At this time, the front-end circuit 150 will not trigger the third path P 3 , but through the second path P 2 The operational transconductance amplifier 154 outputs the second control signal S C2 , thus shifting the output frequency f of the oscillation circuit 140 0 Adjust back to the target frequency f T On the contrary, if the first control signal S C1 The offset is higher than the upper reference voltage V ref_H (0.65V) or lower than the lower reference voltage V ref_L (0.45V), it means that the reference voltage V ref At this time, the front-end circuit 150 triggers the third path P 3 , so that the comparator circuit 155 outputs an upper limit control signal S H Or lower limit control signal S L to the frequency calibration circuit 120, thereby adjusting the output frequency f of the oscillation circuit 140 0 Recalibrate to a frequency close to the target frequency f T In some embodiments, the use of the operational transconductance amplifier 154 to generate the second control signal S may be omitted. C2 The second path P 2 , but directly uses the comparator circuit 155 to generate the upper limit control signal S H And the lower limit control signal S L To compensate the offset output frequency f 0 .

[0032] In an embodiment of the present invention, the phase-locked loop circuit 100 further includes a frequency divider (not shown). The frequency divider is electrically connected between the oscillating circuit 140 and the front-end circuit 150 and is configured to convert the output frequency f of the oscillating circuit 140 into 0 After frequency division, the output frequency f0 is output to the front-end circuit 150. Therefore, in the embodiment including the frequency divider, the reference clock signal S REF In fact, it is the output clock signal S after frequency division. 0 are compared with each other to complete the phase-locked loop operation.

[0033] Figure 4 4 is a schematic diagram of a phase-locked loop control method 400 according to an embodiment of the present invention. The phase-locked loop control method 400 includes a frequency calibration operation 410 and a phase-locked loop operation 420. The frequency calibration operation 410 includes steps 411 to 413. The phase-locked loop operation 420 includes steps 421 to 422; when the oscillation circuit 140 changes due to process or temperature, the output frequency f 0 When offset, the PLL operation 420 further includes steps 423 to 425 .

[0034] Before performing the phase-locked loop operation 420, a frequency calibration operation 410 is first performed to adjust the output clock signal S of the oscillator circuit 140 to 0 The output frequency f 0 Adjust to close to the target frequency f T (For example, at the target frequency f T In step 411 and step 412, the frequency calibration circuit 120 performs the frequency calibration according to the target frequency f of the oscillation circuit 140. T Generates the corresponding current adjustment signal S CA , and the reference current generating circuit 110 provides a reference current I BIAS To the rate adjustment circuit 130. In step 413, the rate adjustment circuit 130 adjusts the current signal S CA Select the appropriate ratio gear, and then set the reference current I BIAS The magnification is adjusted to correspond to the target frequency f T Target frequency current I TF Therefore, the oscillation circuit 140 generates a current I TF The generated output frequency f 0 will be close to the target frequency f T , thereby completing the frequency calibration operation 410 of the phase-locked loop circuit 100.

[0035] After the frequency calibration operation 410 is completed, the phase-locked loop operation 420 is performed. In the phase-locked loop operation 420, steps 421 and 422 (such as Figure 2 The first path P shown 1 In step 421, the phase frequency detection circuit 151 detects the output clock signal S 0 With the reference clock signal S REFThe phase and frequency difference between them enables the front-end circuit 150 to generate a first control signal S C1 Next, in step 422, the oscillation circuit 140 generates a first control signal S C1 With the target frequency current I TF Adjust the output clock signal S 0 The output frequency is f 0 With the target frequency f T Specifically, the phase-locked loop operation 420 repeats step 421 and step 422 until the output clock signal S of the oscillator circuit 140 is 0 The output frequency is f 0 With the target frequency f T The phase-locked loop operation 420 is completed. At this time, the output clock signal S of the oscillation circuit 140 is 0 With the reference clock signal S REF The phase difference between them is locked, and the output frequency is f 0 With the target frequency f T same.

[0036] When the environment changes (for example, the ambient temperature rises from -40°C to 125°C), the output frequency f of the oscillator circuit 140 0 At this time, the phase-locked loop operation 420 triggers Figure 2 The second path P shown 2 , to perform steps 423 to 425. In step 423, when the first control signal S C1 When an offset occurs, the sampling voltage V S With reference voltage V ref A difference is generated between the two, driving the operational transconductance amplifier 154 to convert the difference into a current control signal (ie, the second control signal S C2 ), and outputs it to the multiplier adjustment circuit 130. In step 424, the multiplier adjustment circuit 130 uses an adding circuit to add the reference current I BIAS and the second control signal S C2 Then, the current is adjusted according to the current signal S provided by the frequency calibration circuit 120. CA The sum current is amplified according to the appropriate magnification level to serve as the adjusted target frequency current I TF Specifically, when the output frequency f of the oscillator circuit 140 is 0 When the second path P 2 Provides additional boost current (second control signal S C2 ) to increase the total current, thereby increasing the output frequency f of the oscillation circuit 140 0 On the contrary, when the output frequency f of the oscillation circuit 140 is0 When the second path P 2 Generates an additional negative current (the second control signal S C2 ), so as to reduce the total current, thereby reducing the output frequency f of the oscillation circuit 140 0 Thus, in step 425, the oscillation circuit 140 can be controlled based on the first control signal S C1 And the adjusted target frequency current I TF To compensate the first control signal S C1 The offset (also equivalent to compensating the output frequency f 0 The offset of the output clock signal S 0 The output frequency f 0 With the target frequency f T Consistent.

[0037] For example, the target frequency f of the oscillator circuit 140 is T For 10GHz, the target frequency current I TF The reference current I BIAS is 50μA, and the required magnification level of the magnification adjustment circuit 130 is 20 times. When the ambient temperature changes, the output frequency f of the oscillation circuit 140 0 The offset is about 500MHz, resulting in the required target frequency current I TF The output frequency f of the oscillator circuit 140 needs to be adjusted to 1.2 mA. 0 In this case, the front-end circuit 150 is triggered to generate a second control signal S of about 10 μA. C2 The summed second control signal S C2 And reference current I BIAS It is about 60μA, and after amplification by the multiplier, the target frequency current I of about 1.2mA can be obtained. TF , and finally according to the adjusted target frequency current I TF The output frequency f 0 In the embodiment of the present invention, compared with the reference current I BIAS , the current control signal (the second control signal S C2 ) has a smaller current value. After the phase-locked loop circuit 100 completes locking, if the first control signal S C1 When an offset occurs, only a small amount of the second control signal S C2 For output frequency f 0 Therefore, it can not only ensure that the addition of the operational transconductance amplifier 154 does not generate excessive noise, but also solve the problem of output frequency deviation caused by process or temperature changes of the oscillator itself.

[0038] like Figure 5 As shown, in some embodiments of the present invention, the phase-locked loop operation 420 further includes steps 426 to 428. In step 426, when the first control signal S C1 The offset exceeds the second path P 2 The second control signal S C2 The controllable range (i.e., the first control signal S C1 With a preset upper and lower limit controlled range), it represents the second path P 2 At this time, the comparator circuit 155 is subjected to the upper limit reference voltage V ref_H Or lower limit reference voltage V ref_L The trigger generates the upper limit control signal S H And the lower limit control signal S L To the frequency calibration circuit 120. In step 427, the frequency calibration circuit 120 performs the calibration according to the desired target frequency f T , upper limit control signal S H And the lower limit control signal S L Generate an adjusted current adjustment signal S CA Next, in step 428, the rate adjustment circuit 130 adjusts the current signal S according to the adjusted current. CA Reselect the appropriate ratio to set the reference current I BIAS The re-multiplication factor is the adjusted target frequency current. In this way, the oscillation circuit 140 can re-multiply the output clock signal S according to the adjusted target frequency current. 0 The output frequency f 0 Corrected to target frequency f T In some embodiments, the phase-locked loop operation 420 omits the second path P 2 The following lock steps 423 to 425 only include the first path P 1 and the third path P 3 .

[0039] According to the phase-locked loop control circuit, phase-locked loop circuit and control method of the present invention, combined with an additional tracking loop, a multiplier adjustment circuit and a frequency calibration circuit, when the output frequency of the oscillator is offset, a control signal can be provided to compensate for the offset of the output frequency. In this way, the oscillator can control the output frequency to be consistent with the target frequency in different environments in response to the phenomenon of output frequency offset caused by process and temperature changes, thereby improving the stability of the phase-locked loop.

[0040] Although the present invention has disclosed various embodiments as above, the present invention is not limited thereto. Any ordinary technician in the field can make some modifications and changes without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the claims.

[0041] Description of Reference Numerals

[0042] 100: Phase-locked loop circuit

[0043] 110: Reference current generating circuit

[0044] 120: Frequency calibration circuit

[0045] 130: Ratio adjustment circuit

[0046] 140: Oscillator circuit

[0047] 150:Front-end circuit

[0048] 151: Phase frequency detection circuit

[0049] 152: Charge Pump

[0050] 153:Filter circuit

[0051] 154: Operational Transconductance Amplifier

[0052] 155: Comparator circuit

[0053] 400: Phase-locked loop control method

[0054] 410: Frequency calibration operation

[0055] 420: Phase-locked loop operation

[0056] 411, 412, 413: Steps

[0057] 421, 422, 423, 424, 425: Steps

[0058] 426, 427, 428: Steps

[0059] I BIAS : Reference current

[0060] S CA : Current adjustment signal

[0061] S REF :Reference clock signal

[0062] S 0 : Output clock signal

[0063] S e :Error signal

[0064] S C1 :First control signal

[0065] S C2 : Second control signal

[0066] S H :Upper limit control signal

[0067] S L :Lower limit control signal

[0068] I TF : Target frequency current

[0069] I e : Error current signal

[0070] L 1 , L 2 :Control loop

[0071] V S : Sampling voltage

[0072] V ref :Reference voltage

[0073] V ref_H :Upper limit reference voltage

[0074] V ref_L :Lower reference voltage

[0075] P 1 :First Path

[0076] P 2 : Second Path

[0077] P 3 : The Third Path

[0078] C 1 :First capacitor

[0079] C 2 : Second capacitor

[0080] G: Ground terminal

[0081] R: Resistance

Claims

1. A phase-locked loop circuit, comprising: a reference current generating circuit configured to generate a reference current; a frequency calibration circuit configured to generate a current adjustment signal according to a target frequency; A multiplier adjustment circuit configured to adjust the reference current to a target frequency current according to the current adjustment signal; an oscillator circuit configured to receive the target frequency current and generate an output clock signal according to the target frequency current; as well as A front-end circuit configured to detect a phase and frequency difference between the output clock signal and a reference clock signal to generate a first control signal to the oscillation circuit, so that the oscillation circuit adjusts the output frequency of the output clock signal to be consistent with the target frequency based on the first control signal and the target frequency current; When the first control signal is offset, the front-end circuit is further configured to generate a second control signal so that the multiplier adjustment circuit adjusts the target frequency current according to the sum of the reference current and the second control signal.

2. The phase-locked loop circuit according to claim 1, wherein the front-end circuit comprises: a phase frequency detection circuit configured to detect a phase and frequency difference between the output clock signal and the reference clock signal to generate an error signal; a charge pump, electrically connected to the phase frequency detection circuit, configured to convert the error signal into an error current signal; and The filter circuit is electrically connected to the charge pump and configured to generate the first control signal and the second control signal according to the error current signal.

3. The phase-locked loop circuit according to claim 2, wherein the filter circuit comprises: A first capacitor, electrically connected to the reference voltage terminal; a resistor electrically connected between the charge pump and the first capacitor; and A second capacitor, electrically connected between the charge pump and the reference voltage terminal; The voltage across the first capacitor is used as the sampling voltage, and the voltage across the second capacitor is used as the first control signal.

4. The phase-locked loop circuit according to claim 3, wherein the front-end circuit further comprises: An operational transconductance amplifier is configured to convert a difference between the sampled voltage and a reference voltage into the second control signal, wherein the reference voltage corresponds to the target frequency.

5. The phase-locked loop circuit according to claim 3, wherein the front-end circuit further comprises: The comparator circuit is configured to generate an upper limit control signal and a lower limit control signal to the frequency calibration circuit when the sampling voltage exceeds the reference voltage range, so that the frequency calibration circuit generates the corresponding current adjustment signal according to the target frequency, the upper limit control signal and the lower limit control signal.

6. The phase-locked loop circuit according to claim 1, wherein the oscillation circuit is a current-controlled oscillation circuit, and the front-end circuit and the current-controlled oscillation circuit further comprise: The voltage-to-current conversion circuit is configured to convert the first control signal into a current signal.

7. The phase-locked loop circuit according to claim 1, wherein the multiplier adjustment circuit includes a plurality of multiplier gears, so that the multiplier adjustment circuit selects one of the plurality of multiplier gears based on the current adjustment signal to adjust the reference current to the target frequency current according to the one of the multipliers of the plurality of multiplier gears.

8. The phase-locked loop circuit according to claim 7, wherein when the first control signal is offset, the multiplier adjustment circuit adjusts the sum of the reference current and the second control signal to a correction current according to one of the multipliers of the plurality of multiplier gears to serve as the target frequency current.

9. A phase-locked loop control circuit for controlling an output clock signal of an oscillator circuit, wherein the phase-locked loop control circuit comprises: a reference current generating circuit configured to generate a reference current; a frequency calibration circuit configured to generate a current adjustment signal according to a target frequency; a multiplication factor adjustment circuit configured to adjust the reference current to a target frequency current according to the current adjustment signal, so that the oscillation circuit generates an output clock signal according to the target frequency current; and a front-end circuit configured to detect a phase and frequency difference between the output clock signal and a reference clock signal to generate a first control signal to the oscillation circuit, so that the oscillation circuit adjusts the output frequency of the output clock signal to be consistent with the target frequency based on the first control signal and the target frequency current; in, When the first control signal is offset, the front-end circuit is further configured to generate a second control signal so that the multiplier adjustment circuit adjusts the target frequency current according to the sum of the reference current and the second control signal; When the first control signal offset exceeds the control range of the second control signal, the front-end circuit is also configured to generate an upper limit control signal and a lower limit control signal to the frequency calibration circuit, so that the frequency calibration circuit generates the corresponding current adjustment signal according to the target frequency, the upper limit control signal and the lower limit control signal.

10. A control method of a phase-locked loop for controlling an oscillating circuit, wherein the method comprises: Perform frequency calibration operations, including: Generating a corresponding current adjustment signal to a multiplier adjustment circuit according to a target frequency of the oscillation circuit; Providing a reference current to the rate adjustment circuit; as well as adjusting the reference current to a target frequency current according to the current adjustment signal, so that the oscillation circuit generates an output clock signal according to the target frequency current; as well as Perform phase-locked loop operations, including: Using a front-end circuit to detect the phase and frequency difference between the output clock signal and a reference clock signal; as well as generating a first control signal to the oscillation circuit, so that the oscillation circuit adjusts the output frequency of the output clock signal to be consistent with the target frequency based on the first control signal and the target frequency current; When the first control signal is offset, the front-end circuit is further used to generate a second control signal, so that the multiplier adjustment circuit adjusts the target frequency current according to the sum of the reference current and the second control signal.

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