Digital-to-analog converter

Abstract

The invention relates to a method of controlling a digital-to-analog converter (DAC) system. The DAC system includes a plurality of DAC cores connected in parallel with the outputs of the coupled DAC cores to provide a combined analog output. Each DAC core receives a digital signal that is a modified version of a digital input provided to the DAC system. The monotonicity of the DAC system can be improved by providing the modified digital signal to the DAC cores and using multiple DAC cores.

Description

Technical Field

[0001] The present disclosure relates to a digital-to-analog converter, and more particularly to a digital-to-analog conversion method. Background Art

[0002] Digital-to-analog converters (DACs) can be susceptible to various errors that can cause the relationship between input and output to be non-monotonic. Such a DAC can be considered non-monotonic because a change in the input does not result in a similar change in the output. Non-monotonicity can be problematic because it indicates that the analog output represents the digital input with reduced accuracy.

[0003] It would therefore be desirable to provide a DAC with improved monotonicity such that more bits of the DAC are monotonic and the analog output can be obtained with better resolution. Summary of the invention

[0004] This invention proposes a method for achieving monotonicity in a high resolution DAC. Multiple identical DAC cores can be connected in parallel, provided with appropriate digital inputs, to achieve better monotonicity than a single core can achieve. Methods for deriving the inputs to a single core based on the digital inputs from the user are presented. Also, techniques for handling full scale overflow are discussed.

[0005] In particular, the system can provide a different digital signal to each of a plurality of identical DAC cores such that the output has increased monotonicity compared to a system in which all DAC cores receive the same input digital signal.

[0006] According to a first aspect of the present invention, a digital-to-analog conversion method is provided, the method comprising: receiving a digital input at an input of a digital-to-analog converter DAC system, the DAC system being configured to provide a P-bit monotonic; converting the digital input into an analog output, wherein converting the digital input into the analog output comprises: providing a corresponding digital signal to each corresponding DAC core of a plurality of DAC cores based on the digital input, wherein each DAC core of the plurality of DAC cores is an N-bit DAC core and has an M-bit monotonicity, wherein the plurality of DAC cores comprises 2 P-M DAC cores, and wherein when the corresponding digital signal has more than N bits, the corresponding DAC core is configured to receive an input having more than N bits; the corresponding digital signal is converted into a corresponding analog signal using each of the plurality of DAC cores; and the corresponding analog signals output by each of the plurality of DAC cores are combined to provide the analog output.

[0007] According to a second aspect of the present invention, a digital-to-analog converter DAC system is provided, which is configured to implement the method, including receiving a digital input and outputting an analog output, the DAC system is configured to provide P-bit monotonicity, and the DAC system includes: multiple DAC cores.

[0008] According to a third aspect of the present invention, a digital-to-analog conversion method is provided, the method comprising: receiving a digital input at an input of a digital-to-analog converter DAC system, the DAC system being configured to provide a P-bit monotonic; converting the digital input into an analog output, wherein converting the digital input into the analog output comprises: providing a corresponding digital signal to each corresponding DAC core of a plurality of DAC cores based on the digital input, wherein each DAC core of the plurality of DAC cores is an N-bit DAC core and has an M-bit monotonicity, wherein the plurality of DAC cores comprises 2 P-M DAC cores, and all of the DAC cores are configured to support over-range, wherein supporting over-range includes receiving an input with more bits than the bits that the DAC core is configured to accept; converting the corresponding digital signal into a corresponding analog signal using each of the multiple DAC cores; and combining the corresponding analog signals output by each of the multiple DAC cores to provide the analog output.

[0009] According to a fourth aspect of the present invention, a digital-to-analog conversion method is provided, the method comprising: receiving a digital input at an input of a digital-to-analog converter DAC system, the DAC system being configured to provide a P-bit monotonic; converting the digital input into an analog output, wherein converting the digital input into the analog output comprises: providing a corresponding digital signal to each corresponding DAC core of a plurality of DAC cores based on the digital input, wherein each DAC core of the plurality of DAC cores is an N-bit DAC core and has an M-bit monotonicity, wherein the plurality of DAC cores comprises 2 P-M a DAC core; converting the corresponding digital signal into a corresponding analog signal using each of the multiple DAC cores; combining the corresponding analog signals output by each of the multiple DAC cores to provide the analog output; and changing the connection of the termination branch of the corresponding DAC core from a first reference voltage to a second reference voltage if the corresponding DAC core would overflow when provided with the corresponding digital signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Aspects of the present disclosure will now be described, by way of example only, with reference to the accompanying drawings, wherein like reference numerals represent like parts, and wherein:

[0011] Figure 1 The DAC core is shown;

[0012] Figure 2 Two DAC cores coupled in parallel are shown;

[0013] Figure 3 Two DAC cores coupled in parallel are shown, the inputs to the DAC cores being provided by a control system according to an example of the present disclosure;

[0014] Figure 4 shows a plurality of DAC cores coupled in parallel according to an example of the present disclosure;

[0015] Figure 5 A control system according to an example of the present disclosure is shown;

[0016] Figure 6 shows a modeled representation of a plurality of DAC cores according to examples of the present disclosure;

[0017] Figure 7 A digital-to-analog conversion method according to an example of the present disclosure is shown;

[0018] Figure 8 An R-2R DAC with terminated branches is shown;

[0019] Fig. 9 An R-2R DAC with a modified termination branch according to an example of the present disclosure is shown. DETAILED DESCRIPTION

[0020] A digital-to-analog converter (DAC) is a system that takes a digital input and converts it into an analog signal. Ensuring that the analog output accurately represents the digital input is critical to ensuring that downstream systems and components operate correctly and predictably.

[0021] The DAC can receive an N-bit word as digital input. If the word is binary, then the N-bit word represents 2 N The DAC should therefore provide one of two possible states or values. N possible outputs. Ideally, the relationship between the input and output of a DAC should be monotonic, so that the analog output increases as the digital input increases. This ensures that the analog output is a true representation of the digital input.

[0022] However, DACs can be susceptible to many errors that result in a relationship between input and output that is not monotonic. Such DACs can be considered non-monotonic because a change in the input does not result in a similar change in the output. Non-monotonicity can be problematic because it limits the minimum amount that the analog output can be changed by changing the digital input. The greater the monotonicity of the system, the higher the resolution of the analog output.

[0023] A DAC can be specified to provide multiple monotonic bits. For example, a 24-bit DAC can provide 21 bits of monotonicity, which means that changes in the 21 most significant bits of the DAC input are monotonic, while the three least significant bits of the DAC input are not monotonic. This means that the DAC accurately converts the 21 most significant bits of the digital input so that changing the 21MSBs of the digital input causes the analog output to change in the same direction. Changing the three least significant bits of the input may not cause the output to change in the expected direction.

[0024] Providing a DAC with more monotonic bits can achieve more accurate analog-to-digital conversion. However, increasing the monotonicity of the DAC may result in a complex circuit architecture with higher silicon area or higher test costs due to trimming or calibration.

[0025] The inventors have recognized that in order to improve the monotonicity of the digital-to-analog conversion, the outputs of multiple DACs can be combined in parallel. This provides higher monotonicity, lower noise, and lower glitch energy. Each DAC can receive the same digital input signal, or can receive a modified version of the digital input signal. In addition, the input provided to the DAC can be modified relative to the input provided to other DACs.

[0026] Figure 1 A digital to analog converter DAC 100 is shown. DAC 100 receives a digital input at an input node 102, converts the digital input to an analog signal, and outputs the analog signal to an output node 104.

[0027] DAC 100 can be specified or configured to convert a digital input or word up to N bits long. In the case where DAC 100 is a binary DAC, the N-bit digital signal can represent 2 N The analog output signal can have 2 possible values. N The DAC can be expressed as a different magnitude, such as a voltage or a current, depending on whether the DAC is a voltage DAC or a current DAC.

[0028] DAC 100 is capable of providing M bits of monotonicity. If DAC 100 is completely monotonic, then M and N are the same number, and the output of the DAC is monotonically related to the input. If DAC 100 is not completely monotonic, then M is less than N.

[0029] For example, where the DAC 100 is a 24-bit DAC (N=24) and the DAC provides 21-bit monotonicity (M=21), the DAC may convert the 21 most significant bits (MSBs) of the input in a monotonic manner. Changes in the 3 least significant bits (LSBs) of the DAC input may result in non-monotonic changes in the DAC output. This may mean that when the value of the 3 LSBs of the DAC input increases, the value of the output may not increase, but may decrease.

[0030] To improve monotonicity, multiple DAC cores can be configured in parallel.

[0031] Figure 2A DAC 200 is shown that includes a first DAC core 206 and a second DAC core 208. The first DAC core 206 and the second DAC core 208 can be the same type of DAC core. For example, they can be built using the same technology or process and specified to be the same monotonicity level. The first DAC core 206 and the second DAC core 208 are both coupled to the same input 202 and therefore receive the same digital input. In addition, the outputs of the first DAC core 206 and the second DAC core 208 are coupled together and output through the same analog output node 204. Therefore, the first DAC core 206 and the second DAC core 208 can be considered to be coupled in parallel.

[0032] Due to process variations and manufacturing tolerances, the errors generated by the first DAC core 206 and the second DAC core 208 may be different. Coupling the outputs of the DAC cores together results in the analog output signal being the average of the corresponding outputs of the two DAC cores. This allows the errors of the first DAC core 206 and the second DAC core 208 to be averaged, thereby reducing the errors contained in the analog output and the effects of process variations in the DAC cores.

[0033] Although two DAC cores are shown in DAC 200, other DAC cores may be connected to input 202 and output 204, such as 4, 8, 16, 32, etc. The number of DAC cores may be any power of 2. The DAC cores may be coupled in parallel between the input and output of DAC system 200. The greater the number of DAC cores coupled in parallel in DAC 200, the greater the reduction in error contained in the analog output, and the better the performance of DAC 200.

[0034] The inventors have discovered that the monotonicity of a combined DAC on a single core can be improved by generating a suitable digital signal for each core based on an input digital code.Each digital signal provided to each DAC core may be a modified version of a digital signal.

[0035] Figure 3 A digital-to-analog converter system 300 is shown that includes two DAC cores 306, 308 connected in parallel. The DAC system receives a digital input at an input node 302. The digital input is provided to a DAC control system 310. The DAC control system 310 is configured to provide a corresponding digital signal to each DAC core 306, 308 based on the received digital input. The first DAC core 306 receives a first digital signal from a first output 312 of the control system 310, and the second DAC core 308 receives a second digital signal from a second output 314 of the control system.

[0036] The first DAC core 306 converts the first digital signal into a first analog signal. The second DAC core 308 converts the second digital signal into a second analog signal. The outputs of the first DAC core 306 and the second DAC core 308 are coupled together so that the first analog signal and the second analog signal are combined to provide an analog output signal at the output node 304. The output impedance of the DAC cores 306 and 308 can be such that by connecting the outputs of multiple DAC cores, the analog output of the DAC converter system is the average of the outputs of the multiple DAC cores. For example, all DAC cores can have the same output impedance. The DAC cores can operate individually. For example, the DAC cores may be able to receive different input signals.

[0037] The digital signal provided to each DAC core can be selected based on knowledge of the number of monotonic bits provided by each DAC core, the desired number of monotonic bits for the system, and the number of DAC cores.

[0038] Although Figure 3 Two DAC cores 306, 308 are included, but other DAC cores may be used.

[0039] Figure 4 A DAC system 400 including a plurality of DAC cores is shown. Figure 4 Four DAC cores are shown, but there may be more or fewer DAC cores. The number of DAC cores in the system may be selected based on the desired number of monotonic bits of the DAC system 400. In cases where the desired improvement in monotonicity is greater, a greater number of DAC cores may be used. Thus, the system may include i DAC cores.

[0040] The DAC core may be an R-2R DAC core, a capacitive DAC core, or a current-controlled DAC core. Other types of DAC cores may also be used.

[0041] Figure 5 A view of a control system 410 is shown. The control system 410 may include one or more processors 502. The processor 502 is configured to receive an input at an input node 402. The input includes a digital input provided to the DAC system 400. The control system may include a memory or storage 504. The control system 410 includes a plurality of outputs 530-534, each configured to provide a corresponding digital signal to an input of a DAC core in the plurality of DAC cores.

[0042] exist Figure 4, the control system 410 receives a digital input at an input node 402 and provides a corresponding digital signal to each DAC core. The control system 410 provides i digital signals, each of which is determined based on the digital input, the monotonicity of the DAC core. The first DAC core 420 receives a first digital signal 412 from the control system 410. The second DAC core 422 receives a second digital signal 414 from the control system 410. The third DAC core 424 receives a third digital signal 416 from the control system 410. The fourth DAC core 426 receives a fourth digital signal 418 from the control system 410. Each digital signal is provided at a corresponding output of the control system 410 and provided to an input of a corresponding one of the i DAC cores.

[0043] The DAC cores 420-426 included in the DAC system 400 may be the same type of DAC cores. For example, they may be built using the same technology and additionally or alternatively specified to the same level of accuracy or monotonicity.

[0044] All DAC cores 420-426 have the same number of monotonic bits. In the case where each DAC core is an N-bit DAC core (configured to receive an N-bit input), the DAC core may have M-bit monotonicity, where M≤N. For a completely monotonic DAC core, M=N.

[0045] M = number of monotonic bits of DAC core

[0046] N = number of bits of DAC core

[0047] It is desirable to have a DAC system with more monotonic bits than a single DAC core. For example, DAC system 400 provides P monotonic bits, where P>M and P≤N.

[0048] P = the expected number of monotonic bits of the DAC system

[0049] This is accomplished by using multiple DAC cores, each configured to provide digital-to-analog conversion, rather than a single DAC core. Additionally, each DAC core can receive its own digital signal, rather than providing the same digital input signal to each DAC core. The DAC cores used in DAC system 400 are related to the desired number of monotonic bits for the system, as compared to the number of monotonic bits provided by a single DAC core, as follows:

[0050] DAC core quantity = 2 P-M

[0051] Figure 6 Shows Figure 46. A version of the DAC core shown. Each of the DAC cores 420-426 can be modeled as a voltage source in series with a resistor. For example, the DAC core 420 is modeled using a resistor 602 and a voltage source 604. The voltage source 604 can generate a voltage Vdac. The resistor 602 represents the output resistance of the DAC core 602, having a resistance Rout.

[0052] The voltage source 604 generates a voltage Vdac=Vref*c / N, where Vref is the reference voltage of the DAC core 602 (not shown), c is the digital input signal of the DAC core, and N=2 n , where n is the number of bits of the digital signal.

[0053] Each DAC core 420-426 is monotonic to some extent, for example, each DAC core has M monotonic bits. Therefore, a small change in the input code may not result in a monotonic change in the DAC core output. For example, each DAC core may monotonically increase by 4Δc. A 4Δc change in the DAC core input code may cause the analog output of the DAC system to change by ΔVdac. Any change of less than 4Δc in the input signal provided to each DAC core may result in a non-monotonic change in the DAC core output.

[0054] Assuming the digital input of the DAC system changes by Δc, the input signal of each DAC core 420-426 will generally change by Δc (if the DAC core is Figure 2 However, in this case, the output of each DAC core may not change monotonically because the minimum increment for a DAC core to be monotonic is 4Δc.

[0055] Therefore, instead of increasing the input signals of all channels by Δc, the input signals of three of the four DAC cores (such as DAC cores 420-424) can remain unchanged, and the input of one of the four DAC cores (such as DAC 426) can be increased by 4Δc. This change in the input of DAC core 426 results in a monotonic change in the output of DAC core 426. When the outputs of DAC cores 420-426 are added at output node 404, due to the average value provided by the output connections of the DAC cores, 4Δc in the input of one DAC core has the same effect on the output at node 404 as Δc in the input of all DAC cores, while providing monotonicity for these changing bits.

[0056] Thus, providing four DAC cores 420-426 in parallel in this manner, while varying the digital signal provided to each DAC core, allows the system to operate with greater monotonicity.

[0057] PM can be thought of as the number of extra bits that a DAC system has to be monotonic compared to a single DAC core. Therefore, if a DAC system is designed to add 1 bit of monotonicity, 2 1 = 2 DAC cores. If the DAC system is designed to add 2 bits of monotonicity, 2 2 = 4 DAC cores. For ease of understanding, the DAC cores can be numbered as i = 0 to 2 P-M -1.

[0058] The digital signal supplied to each DAC core is modified so that the signal increments by a value that the DAC core can monotonically transition to, and the average change in the digital signal is the same as the change in the digital input. In other words, the average value of the digital signal supplied to the DAC core is the same as the digital input to the DAC system. The adjustment value—the minimum value by which the digital signal of the DAC core increments—is chosen to be 2. N -M , because 2 N-M is the smallest input that the DAC core can convert monotonically, since they are M-bit monotonic DAC cores.

[0059] Figure 7 Outlines the Figure 4 The method 700 is performed by the DAC system 400 of the embodiment of the present invention, or a method for controlling the DAC system 400. In step 710, the DAC system 400 receives a digital input at an input 402 of the DAC system 400. The digital input is provided to the control system 410 at the input 402 of the control system 410.

[0060] In step 720, the control system 410 determines a plurality of digital signals, generates these digital signals and provides each digital signal to a corresponding DAC core in a plurality of DAC cores. The control system 410 generates a plurality of digital signals. Each digital signal is generated based on a digital input of the DAC system and provided to a corresponding DAC core in a plurality of DAC cores. The digital signals are generated so that each digital signal includes a bit that can be monotonically converted by the DAC core and so that the average value of the digital signal is the same as the value of the digital input. In other words, each DAC core has an adjustment value, and the adjustment value of the DAC core has an average value equal to [(N-1-M): (NP)] bits of the digital input.

[0061] The digital input to the DAC system is N bits long, and the bits of the digital input are numbered bits [N-1:0].

[0062] Digital input = [N-1N-2…2 1 0]

[0063] The corresponding digital signal provided to each DAC core may include two parts, a first binary signal and an adjustment value.

[0064] A single DAC core will accurately convert the M most significant bits of the digital input to a monotonic analog output because each DAC core is monotonic to the M MSBs of the digital input. Therefore, the first binary signal consists of the M most significant bits of the input concatenated with the PM bits, where the PM bits are 0. These PM bits are the digital input bits that the system wishes to make monotonic. Based on the knowledge that all DAC cores can accurately or monotonically convert these M most significant bits, the first binary signal is the same for all DAC cores.

[0065] If the purpose of the DAC system is to provide a non-completely monotonic output, such that N-1-P ≥ 0, the first binary signal also comprises the concatenation of bits [N-1-P:0] of the digital input.

[0066] In other words, the first binary signal is a digital input where the first NP non-monotonic MSB is set to zero.

[0067] The adjustment value is different for each DAC core, so the average output has better resolution. Therefore, the adjustment value provided in each digital signal varies depending on the DAC provided. The adjustment value is different for each DAC core and can be 0 or 2. N-M As mentioned above, the DAC cores are numbered as i=[2 P-M -1:0]. If the value of the digital input [(N-1-M):(NP)] bits is greater than i, the adjustment value of the i-th DAC core is 2 N-M If the value of the [(N-1-M):(NP)] bits of the digital input is less than or equal to i, the adjustment value of the i-th DAC core is 0.

[0068] The adjustment value is selected as 2 N-M , because 2 N-M is the minimum input that the DAC core can convert monotonically, since they are M-bit monotonic DAC cores. For example, suppose the input to the combined DAC system changes by 2 N-M-1 , then the input of half of the DAC cores changes by 2 N-M , while the output of the other DAC cores remains unchanged (in fact, an adjustment value of 0 is added). The average analog output then corresponds to 2 N-M-1 In this way, the combined DAC system can change its output monotonically by half.

[0069] To form the digital signal for each respective DAC core, the adjustment value is added to the first binary signal.

[0070] Once the control system 410 generates the plurality of digital signals, they are provided to the plurality of DAC cores.

[0071] In step 730 , each of the plurality of DAC cores converts the respective received digital signal into a respective analog signal.

[0072] In step 740 , the analog signals output by each DAC core are combined to provide an analog output at the output node 404 of the DAC system.

[0073] As an example of how to generate a digital signal, the DAC core can be a 10-bit DAC core (N=10), with each DAC core (M=6) having 6 bits of monotonicity. Therefore, the four least significant bits (NM) of the DAC core are non-monotonic. It may be desirable to provide a DAC system with 8 bits of monotonicity (P=8) instead of the 6 bits of monotonicity provided by a single DAC core. This is a 2-bit increase in monotonicity (PM).

[0074] The DAC system may include multiple DAC cores that are related to the number of monotonic bits added to the DAC system compared to the number of monotonic bits of a single DAC core. Since 2 bits of monotonicity need to be added to the DAC system 400, the system requires 4 (2 P-M )DAC cores - DAC cores 420-426. The DAC cores are parallel, the outputs of the DAC cores are coupled together, and each DAC core receives its own digital signal. The DAC cores can be labeled as DAC core 0, DAC core 1, DAC core 2, and DAC core 3.

[0075] The digital input of the DAC system 400 provided to the input node 402 is a 10-bit digital input signal. For example, the digital input may be: 1101011001

[0077] The bits of the digital input are labeled as bits [N-1:0]. In this case, bits [9:0]:

[0078]

[0079] The first binary signal is the same for all DAC cores:

[0080] The M most significant bits of the digital input are bits [N-1:NM], or bits [9:4] of the digital input: 110101

[0081] This value is concatenated with the PM bit, where the bits are set to zero - 00.

[0082] The intention is not to make the DAC system completely monotonic, but to make the first 8 most significant bits monotonic - so N-1-P ≥ 0, i.e. 10-1-8 = 1. Therefore, the first binary signal also includes the concatenation with bits [N-1-P:0] of the digital input or bits [1:0] of the digital input -01.

[0083] This provides a first binary signal which is a concatenation of 110101, 00 and 01. Therefore, the first binary signal is 1101010001. This binary signal is the same for all DAC cores.

[0084] First binary signal = 1101010001

[0085] The adjustment value of each DAC core is different. There are four DAC cores, marked as i=0, i=1, i=2 and i=3. The adjustment value is 0 or 2 N-M , for this example, the adjustment value is therefore 0 or 2 4 =16.

[0086] The [(N-1-M):(NP)] bits of the digital input, the [3:2] bits of the digital input, are 10 in binary and 2 in decimal. The values ​​of these bits are used to determine the adjustment value of each DAC core.

[0087] For the i=0 DAC core, bits [3:2] of the digital input are greater than i=0 because 2>0, so the adjustment value is decimal 16. Therefore, the digital signal of the i=0 DAC core is the first binary signal +16.

[0088] Digital signal of DAC core 0 = 1101010001 + 16 = 1101100001

[0089] For the i=1 DAC core, 2>1, so the adjustment value is decimal 16. Therefore, the digital signal of the i=1 DAC core is the first binary signal+16.

[0090] Digital signal of DAC core 1 = 1101010001 + 16 = 1101100001

[0091] For i=2 DAC cores, 2≤2, so the adjustment value is decimal 0. Therefore, the digital signal of i=2 DAC cores is a first binary signal.

[0092] Digital signal of DAC core 2 = 1101010001

[0093] For i=3 DAC cores, 2≤3, so the adjustment value is decimal 0. Therefore, the digital signal of i=3 DAC cores is a first binary signal.

[0094] Digital signal of DAC core 3 = 1101010001

[0095] These digital signals are provided to the input terminals of the respective DAC cores.

[0096] By doing this, the system can monotonically convert the first 8 bits of the digital signal.

[0097] In the above example, no overflow occurred because the DAC cores were able to convert the N bits supplied to them. However, in some cases, using an adjustment value may cause the digital signal supplied to the DAC to overflow. For example, when the digital input is all "1s", the adjustment value may cause an overflow. N-M code, this happens.

[0098] For example, take 2 N Numeric input of -1:

[0099] Digital input = 1111111111

[0100] Assuming each DAC core is a 10-bit DAC core (N=10), each DAC core (M=6) has 6-bit monotonicity, and the required DAC system monotonicity is set to 8-bit monotonicity (P=8), the first binary signal is:

[0101] First binary signal = 1111110011

[0102] The [(N-1-M):(NP)] bits of the digital input (the [3:2] bits of the digital input) are 11 bits in binary, or 3 bits in decimal. In this case, the adjustment value for DAC i=0 is 2 4 =16.

[0103] This results in the digital signal of DAC i=0 being 1111110011+16=

[0104] Digital signal = 10000000011

[0105] This digital signal provided to the DAC core i has overflowed because it is longer than N bits or longer than the digital input. Therefore, the output of the DAC may not represent the true transition of the digital signal provided to the DAC core.

[0106] In the event that the combination of the first binary signal and the adjustment value would result in a digital signal longer than N bits, an alternative adjustment value and binary signal may be used.

[0107] The first binary signal is set to the M most significant bits of the digital input, where NM bits are set to zero. Taking the above example, when the digital input = 1111111111, the first binary signal is:

[0108] First binary signal = 1111110000

[0109] In addition, the adjustment value is not 2 N-M , but set it to 2 N-M An alternative adjustment value of -1.

[0110] In the above example, the alternative adjustment value is 2 4 -1=15. This results in the digital signal of DAC i being 1111110000+15=

[0111] Digital signal = 11111111111

[0112] This prevents the digital signal from overflowing and keeps it N bits long. To compensate for changes in the value of the digital signal, the DAC core can be modified.

[0113] Figure 8 An example of a typical R-2R DAC core is shown, including a switch branch 802 and a termination branch 804. This DAC core can be used to replace the DAC core in the previous figures. The termination branch is coupled or directly connected to the reference voltage. In a typical R-2R topology, the termination branch 804 is always connected to a low reference voltage, sometimes called Ref-N or ground. A plurality of switches 806 are controlled by a control signal and switchably coupled to two different reference voltages - at Figure 8 In the embodiment of the present invention, the control signal is represented as RefN and RefP. According to the input digital signal of the DAC core, the control signal will change the coupling between RefN and RefP of the switch branch of the main part 802 of the DAC core. This causes the output voltage at the output node to change. The operation of the R-2R DAC core will be understood by those skilled in the art, so it will not be described in detail here.

[0114] Fig. 9 An example of a modified R-2R DAC core 900 is shown that is capable of receiving or configured to receive an input equal to N+1. Figure 8 The typical DAC core configuration or design shown is for received digital word lengths. Fig. 9 The termination branch 804 shown is not directly coupled to the low reference voltage, but is coupled to the low reference voltage RefN and the high reference voltage RefP through a switch 902. The switch 902 can be controlled by a termination branch control signal. Therefore, according to the terminal branch control signal, the terminal branch is configured to be coupled to the low reference voltage or the high reference voltage. The high reference voltage can be a voltage supply rail or a positive voltage.

[0115] Fig. 9 The illustrated R-2R DAC 900 may be used to replace each DAC core of a DAC system.

[0116] When the DAC core overflows, the termination branch 804 coupling switches from a low reference voltage to a high reference voltage. This termination branch 804 can be considered to have a value equal to one bit or any other bit value, so modifying its connection results in a larger value at the output Vout.

[0117] By switching the termination branch of the DAC when overflow occurs, the DAC core can be configured to mitigate full-scale overflow without losing monotonicity. When the combination of the adjustment value and the first binary signal would result in a digital signal longer than N bits, use 2 N-M -1 and use an alternative first binary signal. In addition, the termination legs of the individual DAC cores are connected to a high reference voltage or Ref-P. We change the adjustment value to 2 N-M -1, since the terminating branch can be considered to have a weight or value equal to 1. The DAC can be implemented so that the terminating branch is considered to have a different value. In this case, if the DAC is implemented so that the weight of the terminating branch is considered to be a higher power of 2, such as 2 t , then the adjustment value will be 2 N-M -2 t .

[0118] So, as an example, to achieve a digital input of 1111111100, we have 3 DAC cores with inputs of 1111111111. The termination branches of these DACs are connected to the first reference voltage (Ref-P). The input of the fourth DAC is 1111110000 and its termination branch is connected to the second reference voltage (Ref-N).

[0119] Using an alternative first binary signal means that due to changes in the way the binary signal is created, the last two bits of the digital input ("11" in the example above) can also be optionally considered in the second stage. The last two bits in this example represent the bits that remain non-monotonic in the DAC system. In some cases, when the goal is to create a completely monotonic DAC system, there will not be any other bits to consider, so this stage may be optional. Alternatively, since these bits may have a non-monotonic effect on the output, they can be ignored. Consideration of the additional bits in the second stage can be taken in a variety of ways since the DAC is not expected to be monotonic with respect to these bit transitions. For example, the input of one of the DACs receiving an adjustment value of 0 could be increased by 2 P-M Multiply the value of the final bit not included in the adjusted binary signal.

[0120] and Fig. 9 The DAC of FIG. 1 shows an R-2R DAC core. Other DAC cores may be used, such as a capacitive DAC core or a current-controlled DAC core. The DAC cores may be selected so that they can support over-range or overflow of the input of the DAC core, so that the DAC core can receive or convert more than N bits.

[0121] Various modifications may be made to the above-described examples, whether by adding, deleting, or substituting features, to provide further examples, any and all of which should be encompassed by the following claims.

[0122] Various aspects

[0123] As non-limiting examples, some aspects of the disclosure are listed in the following numbered clauses.

[0124] 1. A digital-to-analog conversion method, the method comprising:

[0125] receiving a digital input at an input of a digital-to-analog converter DAC system, the DAC system being configured to provide P-bit monotonicity;

[0126] Converting the digital input into an analog output, wherein converting the digital input into the analog output comprises:

[0127] Based on the digital input, a corresponding digital signal is provided to each corresponding DAC core of a plurality of DAC cores, wherein each DAC core of the plurality of DAC cores is an N-bit DAC core and has M-bit monotonicity, wherein the plurality of DAC cores include 2 P-M a DAC core, and wherein when the corresponding digital signal has more than N bits, the corresponding DAC core is configured to receive an input having more than N bits;

[0128] converting the respective digital signal into a respective analog signal using each of the plurality of DAC cores;

[0129] The respective analog signals output by each of the plurality of DAC cores are combined to provide the analog output.

[0130] 2. The method of clause 1, wherein each DAC core of the plurality of DAC cores is configured to receive an input having more bits than the DAC core is programmed to accept.

[0131] 3. The method according to aspect 1 or 2, wherein the corresponding digital signal provided to each DAC core of the plurality of DAC cores is formed by adding a first binary signal based on the digital input and an adjustment value.

[0132] 4. A method according to clause 3, wherein the first binary signal comprises the M most significant bits of the digital input.

[0133] 5. A method according to aspect 4, wherein the first binary signal comprises the M most significant bits of the digital input, the remaining bits of the digital input being set to zero.

[0134] 6. The method according to any one of aspects 3-5, wherein the system adds PM bits monotonically.

[0135] 7. The method of clause 6, wherein the average of the respective adjusted values ​​of the respective digital signals is the same as the value of the PM bit to which monotonicity is added.

[0136] 8. A method according to any one of clauses 3 to 7, wherein the bits of the digital input are numbered bits [N-1:0], and wherein the first binary signal is obtained by concatenating the following bits:

[0137] The bits of the digital input [N-1:NM];

[0138] PM bit, where the bit is set to zero.

[0139] 9. The method of clause 8, wherein if N-1-P ≥ 0, the first binary signal further comprises a concatenation of bits [N-1-P: 0] of the digital input.

[0140] 10. The method according to any one of aspects 3 to 9, wherein the method further comprises obtaining the adjustment value, wherein the adjustment value is 0 or 2. N-M .

[0141] 11. The method according to any one of aspects 3 to 10, wherein the plurality of DAC cores are numbered as i=[2 P-M -1:0], and wherein if the value of the [(N-1-M):(NP)] bits of the digital input is greater than i, then the adjustment value of the i-th DAC core is 2 N-M .

[0142] 12. The method of clause 11, wherein if the value of [(N-1-M):(NP)] bits of the digital input is less than or equal to i, the adjustment value of the i-th DAC core is 0.

[0143] 13. A method according to any preceding aspect, further comprising configuring the DAC core or each respective DAC core so that it can receive 2 N +1 input code.

[0144] 14. The method of clause 13, wherein the method further comprises connecting a termination branch of the DAC core to a reference voltage when the DAC overflows.

[0145] 15. The method of clause 13, wherein if the corresponding DAC core would overflow when provided with the corresponding digital signal, the method further comprises changing the connection of the termination branch of the corresponding DAC core from the first reference voltage to the second reference voltage.

[0146] 16. A method according to any one of clauses 3 to 15, wherein if the addition of the first binary signal and the adjustment value would result in a value greater than 2 N -1, the method further comprises:

[0147] modifying the first binary signal to be a concatenation of the M most significant bits of the digital input and NM bits set to zero;

[0148] Change the adjustment value to 2 N-M -1, and

[0149] The connection of the termination branch of the corresponding DAC core is changed from a first reference voltage to a second reference voltage.

[0150] 17. A method according to any preceding aspect, wherein combining the respective analog signals output by each of the plurality of DAC cores to provide the analog output comprises combining the analog signals such that each analog signal has equal weight in the analog output.

[0151] 18. A method according to any preceding aspect, wherein the adjustment value of the DAC core has an average value equal to [(N-1-M):(NP)] bits of the digital input.

[0152] 19. A digital-to-analog converter (DAC) system configured to implement the method according to any preceding aspect, receiving a digital input and outputting an analog output, the DAC system being configured to provide P-bit monotonicity, the DAC system comprising: a plurality of DAC cores.

[0153] 20. A DAC system according to aspect 19, wherein each of the plurality of DAC cores has an output impedance, and the output impedance is configured such that by connecting the outputs of the plurality of DAC cores, an analog output of the DAC converter system is an average of the outputs of the plurality of DAC cores.

[0154] 21. A DAC system according to any one of aspects 19 or 20, wherein the plurality of DAC cores are of the same type.

[0155] 22. The DAC system of any one of aspects 19-21, wherein the plurality of DAC cores are R-2R DAC cores.

[0156] 23. A DAC system according to any one of aspects 19-21, wherein the plurality of DAC cores are capacitive DAC cores.

[0157] 24. A DAC system according to any one of aspects 19-21, wherein the plurality of DAC cores are current controlled DAC cores.

[0158] 25. A DAC system according to any one of aspects 19-24, wherein each DAC core is configured to operate independently.

[0159] 26. A digital-to-analog conversion method, the method comprising:

[0160] receiving a digital input at an input of a digital-to-analog converter DAC system, the DAC system being configured to provide P-bit monotonicity;

[0161] Converting the digital input into an analog output, wherein converting the digital input into the analog output comprises:

[0162] Based on the digital input, a corresponding digital signal is provided to each corresponding DAC core of a plurality of DAC cores, wherein each DAC core of the plurality of DAC cores is an N-bit DAC core and has M-bit monotonicity, wherein the plurality of DAC cores include 2 P-M a plurality of DAC cores, and all of the DAC cores in the plurality of DAC cores are configured to support over-range, wherein supporting over-range includes receiving an input with more bits than the DAC cores are configured to accept;

[0163] converting the respective digital signal into a respective analog signal using each of the plurality of DAC cores;

[0164] The respective analog signals output by each of the plurality of DAC cores are combined to provide the analog output.

[0165] 27. A digital-to-analog conversion method, the method comprising:

[0166] receiving a digital input at an input of a digital-to-analog converter DAC system, the DAC system being configured to provide P-bit monotonicity;

[0167] Converting the digital input into an analog output, wherein converting the digital input into the analog output comprises:

[0168] Based on the digital input, a corresponding digital signal is provided to each corresponding DAC core of a plurality of DAC cores, wherein each DAC core of the plurality of DAC cores is an N-bit DAC core and has M-bit monotonicity, wherein the plurality of DAC cores include 2 P-M A DAC core;

[0169] converting the respective digital signal into a respective analog signal using each of the plurality of DAC cores;

[0170] combining the respective analog signals output by each of the plurality of DAC cores to provide the analog output; and

[0171] If the corresponding DAC core would overflow when provided with the corresponding digital signal, the connection of the termination branch of the corresponding DAC core is changed from the first reference voltage to the second reference voltage.

Claims

1. A digital-to-analog conversion method, the method comprising: receiving a digital input at an input of a digital-to-analog converter DAC system, the DAC system being configured to provide P-bit monotonicity; and Converting the digital input into an analog output, wherein converting the digital input into the analog output comprises: Based on the digital input, a corresponding digital signal is provided to each corresponding DAC core of a plurality of DAC cores, wherein each DAC core of the plurality of DAC cores is an N-bit DAC core and has M-bit monotonicity, wherein the plurality of DAC cores include 2 P-M a DAC core, and wherein when the corresponding digital signal has more than N bits, the corresponding DAC core is configured to receive an input having more than N bits; converting the respective digital signal into a respective analog signal using each of the plurality of DAC cores; and The respective analog signals output by each of the plurality of DAC cores are combined to provide the analog output. 2 . The method of claim 1 , wherein each DAC core of the plurality of DAC cores is configured to receive an input having more bits than the DAC core is programmed to accept. 3 . The method of claim 1 , wherein the corresponding digital signal provided to each of the plurality of DAC cores is formed by adding a first binary signal based on the digital input and an adjustment value.

4. The method of claim 3, wherein the adjustment value of the DAC core has an average value equal to [(N-1-M):(NP)] bits of the digital input. The method of claim 3 , wherein the first binary signal comprises the M most significant bits of the digital input.

6. The method of claim 5, wherein the first binary signal comprises the M most significant bits of the digital input, wherein the remaining bits of the digital input are set to zero.

7. The method of claim 3, wherein the system adds PM bits monotonically.

8. The method of claim 7, wherein the average of the respective adjusted values ​​of the respective digital signals is the same as the value of the PM bit to which monotonicity is added.

9. The method according to claim 3, wherein the bits of the digital input are numbered bits [N-1:0], and wherein the first binary signal is obtained by concatenating the following bits: bits [N-1:NM] of the digital input; and PM bit, where the bit is set to zero.

10. The method of claim 9, wherein if N-1-P ≥ 0, the first binary signal further comprises a concatenation of bits [N-1-P: 0] of the digital input.

11. The method according to claim 3, wherein the method further comprises obtaining the adjustment value, wherein the adjustment value is 0 or 2. N-M .

12. The method according to claim 3, wherein the plurality of DAC cores are numbered as i=[2 P-M -1:0], and wherein if the value of the [(N-1-M):(NP)] bits of the digital input is greater than i, then the adjustment value of the i-th DAC core is 2 N-M .

13. The method of claim 12, wherein if the value of [(N-1-M):(NP)] bits of the digital input is less than or equal to i, the adjustment value of the i-th DAC core is 0.

14. The method according to claim 1, further comprising configuring each corresponding DAC core so that it can receive 2 N +1 input code.

15. The method of claim 14, wherein the method further comprises connecting a termination branch of a corresponding DAC core to a reference voltage when the DAC overflows.

16. The method of claim 14, wherein if the corresponding DAC core would overflow when provided with the corresponding digital signal, the method further comprises changing a connection of a termination branch of the corresponding DAC core from a first reference voltage to a second reference voltage.

17. The method of claim 3, wherein if the addition of the first binary signal and the adjustment value results in a signal having a value greater than 2 N If the corresponding digital signal has a value of -1, the method further comprises: modifying the first binary signal to be a concatenation of the M most significant bits of the digital input and NM bits set to zero; Modify the adjustment value to 2 N-M -1, and The connection of the termination branch of the corresponding DAC core is changed from a first reference voltage to a second reference voltage.

18. A digital-to-analog converter (DAC) system, configured to implement the method of claim 1, receiving a digital input and outputting an analog output, the DAC system being configured to provide P-bit monotonicity, the DAC system comprising: Multiple DAC cores.

19. A digital-to-analog conversion method, the method comprising: receiving a digital input at an input of a digital-to-analog converter DAC system, the DAC system being configured to provide P-bit monotonicity; and Converting the digital input into an analog output, wherein converting the digital input into the analog output comprises: Based on the digital input, a corresponding digital signal is provided to each corresponding DAC core of a plurality of DAC cores, wherein each DAC core of the plurality of DAC cores is an N-bit DAC core and has M-bit monotonicity, wherein the plurality of DAC cores include 2 P-M a plurality of DAC cores, and all of the DAC cores in the plurality of DAC cores are configured to support over-range, wherein supporting over-range includes receiving an input with more bits than the DAC cores are configured to accept; converting the respective digital signal into a respective analog signal using each of the plurality of DAC cores; and The respective analog signals output by each of the plurality of DAC cores are combined to provide the analog output.

20. A digital-to-analog conversion method, the method comprising: receiving a digital input at an input of a digital-to-analog converter DAC system, the DAC system being configured to provide P-bit monotonicity; and Converting the digital input into an analog output, wherein converting the digital input into the analog output comprises: Based on the digital input, a corresponding digital signal is provided to each corresponding DAC core of a plurality of DAC cores, wherein each DAC core of the plurality of DAC cores is an N-bit DAC core and has M-bit monotonicity, wherein the plurality of DAC cores include 2 P-M A DAC core; converting the respective digital signal into a respective analog signal using each of the plurality of DAC cores; combining the respective analog signals output by each of the plurality of DAC cores to provide the analog output; and If the corresponding DAC core would overflow when provided with the corresponding digital signal, the connection of the termination branch of the corresponding DAC core is changed from the first reference voltage to the second reference voltage.

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