Circuit board, communication equipment and chip

Abstract

The embodiment of the invention provides a circuit board, communication equipment and a chip, the circuit board is used for connecting an electronic device, the circuit board is used for inhibiting thermal expansion coefficient mismatch between the circuit board and the electronic device, and the insertion loss of the circuit board can be effectively reduced. Along the direction perpendicular to the surface of the circuit board, the circuit board comprises M sub-boards arranged in sequence, M is any integer not less than 2, and the M sub-boards comprise a first sub-board and a second sub-board. The thermal expansion coefficient of the first daughter board is smaller than that of the second daughter board, and the dielectric loss factor of the second daughter board is smaller than that of the first daughter board.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a circuit board, a communication device and a chip. Background Art

[0002] The communication device includes a circuit board and an electronic device connected to the surface of the circuit board. In order to improve the reliability of the communication device and the reliability of the electrical connection of the circuit board, it is necessary to suppress the coefficient of thermal expansion (CTE) mismatch between the circuit board and the electronic device.

[0003] The existing circuit board includes a first sub-board and a plurality of second sub-boards, wherein the first sub-board is located between the plurality of second sub-boards. To suppress CTE mismatch, the CTE of the first sub-board is smaller than the CTE of the second sub-board.

[0004] However, when the CTE of the first sub-board is reduced, the insertion loss of the first sub-board will be increased, and thus the insertion loss of the circuit board cannot be suppressed. A circuit board with high insertion loss cannot meet the increasing demand for information transmission rate. Summary of the invention

[0005] The embodiments of the present application provide a circuit board, a communication device and a chip. The circuit board is used to connect electronic devices. The circuit board is used to suppress the mismatch of thermal expansion coefficients between the circuit board and the electronic devices, and can effectively reduce the insertion loss of the circuit board.

[0006] In a first aspect, the present application provides a circuit board, which is used to connect electronic devices. In a direction perpendicular to the surface of the circuit board, the circuit board includes M sub-boards arranged in sequence, where M is an arbitrary integer not less than 2, and the M sub-boards include a first sub-board and a second sub-board. Among the M sub-boards, in a direction perpendicular to the surface of the circuit board, the first sub-board and the second sub-board are adjacent to each other, or at least one sub-board is spaced between the first sub-board and the second sub-board. The low thermal expansion coefficient performance and low dielectric loss factor performance shown in this aspect are decomposed into different sub-boards among the M sub-boards. Therefore, the thermal expansion coefficient of the first sub-board is smaller than that of the second sub-board, and the dielectric loss factor of the second sub-board is smaller than that of the first sub-board.

[0007] By using the circuit board shown in this aspect, when the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the second sub-board, the thermal expansion coefficient of the circuit board is effectively reduced, thereby effectively suppressing the mismatch of the thermal expansion coefficients between the circuit board and the electronic device, ensuring the stability of the electrical connection of the communication device, and improving the life of the communication device. When the dielectric loss factor of the second sub-board is smaller than the dielectric loss factor of the first sub-board, the insertion loss of the circuit board is effectively reduced, so that the circuit board shown in this aspect can meet the requirements of both low thermal expansion coefficient and low insertion loss.

[0008] Based on the first aspect, in an optional implementation manner, the Young's modulus of the second sub-plate is smaller than the Young's modulus of the first sub-plate.

[0009] With this implementation, due to the high Young's modulus of the second sub-board, the negative impact of the high thermal expansion coefficient of the second sub-board on the thermal expansion coefficient of the entire circuit board can be reduced as much as possible. Moreover, since the second sub-board has a lower Young's modulus, a small via pitch of the circuit board can be achieved.

[0010] Based on the first aspect, in an optional implementation, the M sub-boards include a plurality of the second sub-boards, and the plurality of the second sub-boards are symmetrically distributed around the first sub-board.

[0011] With this implementation, multiple second sub-boards are symmetrically distributed with the first sub-board as the center, so as to improve the overall flatness of the circuit board and improve the overall warping of the circuit board.

[0012] Based on the first aspect, in an optional implementation, the M sub-boards also include a third sub-board, and the second sub-board is located between the first sub-board and the second sub-board; the thermal expansion coefficient of the third sub-board is smaller than the thermal expansion coefficient of the second sub-board, and the dielectric loss factor of the second sub-board is smaller than the dielectric loss factor of the third sub-board.

[0013] By adopting this implementation, when the thermal expansion coefficient of the third sub-board is less than that of the second sub-board, the thermal expansion coefficient of the circuit board is effectively reduced, thereby effectively suppressing the thermal expansion coefficient mismatch of the circuit board, ensuring the stability of the electrical connection of the communication device, and improving the life of the communication device. When the dielectric loss factor of the second sub-board is less than that of the third sub-board, the insertion loss of the circuit board is effectively reduced, so that the circuit board shown in this aspect can take into account the requirements of low thermal expansion coefficient and low insertion loss. Moreover, because the second sub-board is located between the first sub-board and the third sub-board, the reliability of the circuit board structure is improved.

[0014] Based on the first aspect, in an optional implementation manner, the Young's modulus of the second sub-plate is smaller than the Young's modulus of the third sub-plate.

[0015] With this implementation, in the circuit board, the third sub-board is located at the outermost layer, so the Young's modulus of the third sub-board is greater than that of the second sub-board, thereby effectively improving the overall rigidity of the circuit board and reducing the footprint of the circuit board surface when mounting components.

[0016] Based on the first aspect, in an optional implementation, the M sub-boards include a plurality of the third sub-boards, and the plurality of the third sub-boards are symmetrically distributed around the first sub-board.

[0017] With this implementation, multiple third sub-boards are symmetrically distributed with the first sub-board as the center, so as to improve the overall flatness of the circuit board and improve the overall warping of the circuit board.

[0018] Based on the first aspect, in an optional implementation, within a target plane, the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the second sub-board, and the thermal expansion coefficient of the third sub-board is smaller than the thermal expansion coefficient of the second sub-board, and the target plane is parallel to the surface of the circuit board.

[0019] As shown in the present implementation, within the target plane, the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the second sub-board, and, within the target plane, the thermal expansion coefficient of the third sub-board is smaller than the thermal expansion coefficient of the second sub-board, thereby effectively suppressing the thermal expansion coefficient mismatch between the circuit board and the electronic device.

[0020] Based on the first aspect, in an optional implementation, the thickness of the first sub-board along the target direction is greater than the thickness of the second sub-board along the target direction, and the thickness of the first sub-board along the target direction is greater than the thickness of the third sub-board along the target direction, wherein the target direction is a direction perpendicular to the surface of the circuit board.

[0021] According to the implementation, since the thickness of the first sub-board is greater than the thickness of the second sub-board and greater than the thickness of the third sub-board, the thermal expansion coefficient of the circuit board is effectively reduced. Moreover, since the thickness of the second sub-board is relatively small, the negative impact of the second sub-board on the overall thermal expansion coefficient of the circuit board can be reduced, and the overall thickness of the circuit board can be reduced.

[0022] Based on the first aspect, in an optional implementation, the M sub-boards include a fourth sub-board, and the fourth sub-board is located between the first sub-board and the second sub-board along a direction perpendicular to the surface of the circuit board; the thermal expansion coefficient of the fourth sub-board is smaller than the thermal expansion coefficient of the second sub-board, and the dielectric loss factor of the second sub-board is smaller than the dielectric loss factor of the fourth sub-board.

[0023] By adopting this implementation, when the thermal expansion coefficient of the fourth sub-board is less than the thermal expansion coefficient of the second sub-board, the thermal expansion coefficient of the circuit board is effectively reduced, thereby effectively suppressing the thermal expansion coefficient mismatch of the circuit board, ensuring the stability of the electrical connection of the communication device, and improving the life of the communication device. When the dielectric loss factor of the second sub-board is less than the dielectric loss factor of the fourth sub-board, the insertion loss of the circuit board is effectively reduced, so that the circuit board shown in this aspect can take into account the requirements of low thermal expansion coefficient and low insertion loss.

[0024] Based on the first aspect, in an optional implementation manner, the Young's modulus of the second sub-plate is smaller than the Young's modulus of the fourth sub-plate.

[0025] With this implementation, due to the high Young's modulus of the second sub-board, the negative impact of the high thermal expansion coefficient of the second sub-board on the thermal expansion coefficient of the entire circuit board can be reduced as much as possible. Moreover, since the second sub-board has a lower Young's modulus, a small via pitch of the circuit board can be achieved.

[0026] Based on the first aspect, in an optional implementation, the second sub-board includes a first dielectric layer, the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the first dielectric layer, and the dielectric loss factor of the first dielectric layer is smaller than the dielectric loss factor of the first sub-board; the second sub-board also includes a second dielectric layer, along a direction perpendicular to the surface of the circuit board, the first dielectric layer includes a first surface and a second surface in opposite positions, the second dielectric layer is located on the first surface, and / or the second dielectric layer is located on the second surface, and the dielectric material of the second dielectric layer is different from the dielectric material of the first dielectric layer.

[0027] By adopting this implementation method, the thermal expansion coefficient and insertion loss of the circuit board can be effectively reduced.

[0028] Based on the first aspect, in an optional implementation manner, the first dielectric layer and the second dielectric layer satisfy at least one of the following conditions:

[0029] The dielectric loss factor of the second dielectric layer is smaller than the dielectric loss factor of the first dielectric layer, the Young's modulus of the second dielectric layer is larger than the Young's modulus of the first dielectric layer, and the thermal expansion coefficient of the second dielectric layer is smaller than the thermal expansion coefficient of the first dielectric layer.

[0030] By adopting this implementation method, the circuit board can meet the requirements of low thermal expansion coefficient and low insertion loss.

[0031] Based on the first aspect, in an optional implementation, the third sub-board includes a first dielectric layer, the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the first dielectric layer, and the dielectric loss factor of the first dielectric layer is smaller than the dielectric loss factor of the first sub-board; the third sub-board also includes a second dielectric layer, along a direction perpendicular to the surface of the circuit board, the first dielectric layer includes a first surface and a second surface in opposite positions, the second dielectric layer is located on the first surface, and / or the second dielectric layer is located on the second surface, and the dielectric material of the second dielectric layer is different from the dielectric material of the first dielectric layer.

[0032] By adopting this implementation method, the thermal expansion coefficient and insertion loss of the circuit board can be effectively reduced.

[0033] Based on the first aspect, in an optional implementation manner, the first dielectric layer and the second dielectric layer satisfy at least one of the following conditions:

[0034] The dielectric loss factor of the second dielectric layer is smaller than the dielectric loss factor of the first dielectric layer, the Young's modulus of the second dielectric layer is larger than the Young's modulus of the first dielectric layer, and the thermal expansion coefficient of the second dielectric layer is smaller than the thermal expansion coefficient of the first dielectric layer.

[0035] By adopting this implementation method, the circuit board can meet the requirements of low thermal expansion coefficient and low insertion loss.

[0036] Based on the first aspect, in an optional implementation, the first sub-board includes a first dielectric layer, the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the first dielectric layer, and the dielectric loss factor of the first dielectric layer is smaller than the dielectric loss factor of the first sub-board; the first sub-board also includes a second dielectric layer, along a direction perpendicular to the surface of the circuit board, the first dielectric layer includes a first surface and a second surface in opposite positions, the second dielectric layer is located on the first surface, and / or the second dielectric layer is located on the second surface, and the dielectric material of the second dielectric layer is different from the dielectric material of the first dielectric layer.

[0037] By adopting this implementation method, the thermal expansion coefficient and insertion loss of the circuit board can be effectively reduced.

[0038] Based on the first aspect, in an optional implementation manner, the first dielectric layer and the second dielectric layer satisfy at least one of the following conditions:

[0039] The dielectric loss factor of the second dielectric layer is smaller than the dielectric loss factor of the first dielectric layer, the Young's modulus of the second dielectric layer is larger than the Young's modulus of the first dielectric layer, and the thermal expansion coefficient of the second dielectric layer is smaller than the thermal expansion coefficient of the first dielectric layer.

[0040] By adopting this implementation method, the circuit board can meet the requirements of low thermal expansion coefficient and low insertion loss.

[0041] Based on the first aspect, in an optional implementation, the first sub-board or the third sub-board serves as a power layer or a ground layer, and the second sub-board serves as a signal layer.

[0042] In a second aspect, an embodiment of the present application provides a communication device, the communication device comprising a circuit board and an electronic device connected to the circuit board, the circuit board being as described in any one of the first aspects above. For the description of the beneficial effects of the circuit board in this aspect, please refer to the first aspect, and no further description will be given.

[0043] In a third aspect, an embodiment of the present application provides a chip, the chip includes a packaging shell, the packaging shell includes a circuit board and a bare chip connected to the circuit board, and the circuit board is as described in any one of the first aspects above. For the description of the beneficial effects of the circuit board in this aspect, please refer to the first aspect, and no further details will be given. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a structural example diagram of a communication device;

[0045] Figure 2 This is a structural example diagram of an existing circuit board;

[0046] Figure 3 This is a diagram showing an example of the structure of the first embodiment of the circuit board provided in this application;

[0047] Figure 4 A diagram showing a second exemplary structure of a circuit board provided in this application;

[0048] Figure 5 Another structural example diagram of an existing circuit board;

[0049] Figure 6 This is a structural example diagram of a third embodiment of the circuit board provided in this application;

[0050] Figure 7 This is a structural example diagram of a fourth embodiment of the circuit board provided in this application;

[0051] Figure 8 A diagram showing a fifth exemplary structure of a circuit board provided in the present application;

[0052] Fig. 9 This is a structural example diagram of the sixth embodiment of the circuit board provided in this application. DETAILED DESCRIPTION

[0053] The present application provides a communication device, which includes a circuit board and an electronic device connected to the surface of the circuit board. The communication device provided by the embodiment of the present application can effectively suppress the CTE mismatch between the circuit board and the electronic device.

[0054] For example Figure 1 As shown, Figure 1 : is a structural example diagram of a communication device. The communication device includes a printed circuit board (PCB) 101. The communication device also includes an electronic device connected to the surface of PCB101, and the electronic device can be a chip. The chip specifically includes a packaging shell 111, and the packaging shell 111 includes a substrate (Substrate) 112 and a bare chip (die) 113 connected to the surface of the substrate 112. The substrate 112 is connected to the surface of PCB101 through a ball grid array (BGA). In this embodiment, the type of circuit board included in the packaging shell 111 of the chip is a substrate. In other examples, the type of circuit board included in the packaging shell 111 can also be a PCB, then, die113 is connected to the surface of the PCB. Figure 1The example shown takes the electronic device connected to the surface of PCB101 as a chip. In other examples, the electronic device packaged on the surface of PCB101 can be any type of electronic components, such as resistors, capacitors, inductors, connectors, laser devices, power supplies, etc. The electronic device can also be a die, that is, the die is directly connected to the surface of PCB101. This example does not limit the type of equipment used by the communication device. For example, the communication device can be applied to optical transmission equipment, optical access equipment, routers, switches, wireless base stations, wireless remote access equipment, wireless baseband signal processing equipment, etc. It can also be a computing server (usually referred to as a server), a high performance computer (HPC), a storage server, or a memory resource pool, etc. The devices used by the communication device can also be various types of terminal devices, such as cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication functions, computing devices or other processing devices connected to wireless modems, vehicle-mounted devices, wearable devices, any communication networks, such as terminal devices in the fifth generation mobile communication technology (5G), terminal devices in the sixth generation mobile communication technology (6G), terminal devices in the future evolved public land mobile communication network (PLMN), etc., without specific limitation.

[0055] The target plane XY shown in this example refers to a direction parallel to the surface of PCB101, and the target direction Z is perpendicular to the target plane, that is, the target direction Z is perpendicular to the surface of PCB101. The PCB101 shown in this example and the substrate 112 in the package shell 111 are electrically connected by solder balls or solder paste welding. During the assembly and welding process, since the solder balls or solder paste need to be heated, both the PCB101 and the package shell 111 will be heated and their dimensions will change. The PCB101 has a first CTE in the target plane XY, and the package shell 111 has a second CTE in the target plane XY. The CTE mismatch of the communication device refers to a large gap between the first CTE and the second CTE. When the communication device has a CTE mismatch, the PCB101 and the package shell 111 will be deformed inconsistently during the heating and cooling process, which will cause internal stress at the solder joint position between the PCB101 and the package shell 111 when it returns to room temperature. The greater the gap between the first CTE of the PCB101 and the second CTE of the package shell 111, the greater the internal stress. When the internal stress exceeds the connection force of the solder joint, problems such as solder joint cracking will occur, resulting in failure of the electrical connection between PCB101 and the package shell 111. In addition, during the actual use of the communication device, if there is a large CTE gap between PCB101 and the package shell 111, due to factors such as changes in ambient temperature or heat generated during the use of the communication device, the solder joint will also be subjected to long-term thermal fatigue stress (also known as creep fatigue), and eventually the solder joint will crack and fail. In particular, when there are large fluctuations in ambient temperature cycles and the communication device is repeatedly powered on and off, there will be cyclic stress at the solder joint, resulting in failure of the electrical connection, affecting the service life of the communication device. There is also a CTE mismatch problem between the substrate 112 and the bare chip 113 shown in this example. For specific instructions, please refer to the description of the CTE mismatch between PCB101 and the package shell 111, which will not be elaborated on in detail.

[0056] Therefore, if the CTE mismatch of the communication equipment can be effectively suppressed, the stability of the electrical connection of the communication equipment can be effectively guaranteed, and the life of the communication equipment can be improved. Taking the CTE mismatch between PCB101 and the packaging shell 111 as an example, the dielectric material used to make PCB101 is composed of polymer resin, filler, fiber cloth, etc., and the CTE of the polymer resin is usually greater than 50 parts per million per degree Celsius (ppm / ℃). The packaging shell 111 is generally made of inorganic materials such as ceramics and silicon. Therefore, the CTE of PCB101 in the target plane XY is greater than the CTE of the packaging shell 111 in the target plane XY. Generally speaking, the CTE of the packaging shell 111 in the target plane XY is approximately 2 to 10 ppm / ℃, and the CTE of the dielectric material of PCB101 in the target plane XY is generally 15 to 25 ppm / ℃. Therefore, in order to suppress the CTE mismatch between PCB101 and the package shell 111, thereby improving the problem of solder joint cracking and electrical connection failure caused by CTE mismatch, which leads to a reduced life of the communication device, the CTE of the dielectric material of PCB101 in the target plane XY can be reduced, thereby reducing the gap between the first CTE and the second CTE, thereby achieving the purpose of suppressing the CTE mismatch between PCB101 and the package shell 111. Similarly, to suppress the CTE mismatch between the substrate 112 and the bare chip 113, the CTE of the substrate 112 in the target plane XY can also be reduced. For specific instructions, refer to the instructions for suppressing the CTE mismatch between PCB101 and the package shell 111, which will not be described in detail.

[0057] Combination Figure 2 The structure of the existing circuit board is specifically described as shown, wherein: Figure 2 The following is an example diagram of an existing circuit board structure. Figure 2 The circuit board shown is taken as a flip chip ball grid array package substrate (FCBGA) as an example. The circuit board includes a first sub-board 201. The first sub-board 201 is a copper-clad core board (Core) with copper foil on both sides. The first sub-board 201 is located between two second sub-boards 202. Among them, the second sub-board 202 is a multi-layer ajinomoto build-up film (ABF). The copper layer (i.e., seed layer) is deposited by a semi-additive process (SAP) to achieve electrical connection between two adjacent second sub-boards 202. Figure 2The thickness of the first sub-board 201 shown in the target direction Z is greater than the thickness of each second sub-board 202. In order to reduce the CTE of the entire circuit board in the target plane XY, the CTE of the first sub-board 201 is less than the CTE of the second sub-board 202 in the target plane XY, thereby reducing the CTE of the entire circuit board in the target plane XY. Among them, the first sub-board 201 can be a copper clad laminate (CCL) with copper clad on both sides. CCL refers to copper clad on both sides of a dielectric material. The dielectric material is generally formed of glass fiber, polymer resin, and filler.

[0058] As the transmission rate of communication equipment increases, the capacity of transmitted information also increases, and the requirements for the high-speed signal transmission performance of circuit boards are getting higher and higher. Therefore, circuit boards need to have the performance of suppressing the CTE mismatch between circuit boards and electronic devices and reducing insertion loss. Taking the circuit board as an example, how to reduce the insertion loss of PCB is explained in the existing solutions.

[0059] The insertion loss of PCB mainly comes from the dielectric loss and conductor loss of dielectric materials. The dielectric loss mainly depends on the dielectric loss factor (Df), dielectric constant (Dk) and frequency of the dielectric material. The lower the Df and Dk of the dielectric material, the better the insertion loss performance of the PCB. It can be understood that if the Df and Dk of the PCB can be effectively reduced, then the insertion loss of the PCB can be effectively reduced.

[0060] In order to improve the performance of communication equipment, it is necessary to make the PCB able to take into account both the suppression of CTE mismatch between the PCB and electronic devices and the reduction of insertion loss. In order to make the PCB able to take into account both the suppression of CTE mismatch between the PCB and electronic devices and the reduction of insertion loss, then, Figure 2 In the existing PCB shown, the dielectric material of the first sub-board 201 needs to have the performance of suppressing the CTE mismatch between the PCB and the electronic device and reducing the insertion loss. For example, the first sub-board 201 is a CCL. The CTE of the CCL is mainly affected by the polymer resin, filler, reinforcement material and copper foil, as shown in the following formula 1:

[0061] Formula 1:

[0062] In formula 1, a CCL refers to the CTE of the first sub-board 201, α refers to the thermal expansion coefficient, K refers to the Young's modulus, φ refers to the volume percentage, r refers to the polymer resin, f refers to the filling material, g refers to the reinforcing material, and c refers to the copper foil. For example, a rRefers to the thermal expansion coefficient of polymer resin, K r Refers to the Young's modulus of polymer resin, Refers to the volume percentage of polymer resin.

[0063] Since the copper foil used in CCL is mostly electrolytic copper or rolled copper, its purity is above 99.5%, and the CTE difference of different types of copper foil is small, all around 17ppm / ℃. The main factor affecting the CTE of CCL is polymer resin, followed by reinforcing materials (such as glass fiber cloth, etc.) and filling materials. Among them, for the CTE of the dielectric material in the target plane XY, the CTE of the reinforcing material is the key influencing factor.

[0064] Similarly, the main factors affecting the Df performance of CCL are polymer resin, reinforcing materials and filling materials. See the following formula 2:

[0065] Formula 2: Dfccl = VA*DfA+VB*DfB+VC*DfC

[0066] In Formula 2, Dfccl refers to Df of CCL. V refers to volume percentage, and A / B / C represents different components. For example, VA refers to the volume percentage of polymer resin, DfA refers to Df of polymer resin, VB refers to the volume percentage of filling material, DfB refers to Df of filling material, VC refers to the volume percentage of reinforcing material, and DfC refers to Df of reinforcing material.

[0067] However, it is difficult for the dielectric material of the first sub-board 201 to have both low insertion loss and low CTE performance in the target plane XY. For example, if it is necessary to achieve the purpose that the dielectric material used in the first sub-board 201 has both low insertion loss and low CTE in the target plane XY, for example, the CTE of the first sub-board 201 in the target plane XY is required to be ≤10ppm / ℃ and Df≤0.002@10 GHz. Among them, the Df value of the first sub-board 201 is positively correlated with the circuit board loss, that is, the smaller the Df value of the circuit board, the smaller the insertion loss of the circuit board. It can be understood that reducing the Df of the circuit board can achieve the purpose of low insertion loss of the circuit board. However, it is difficult to reduce the compatibility of reducing the CTE of the first sub-board 201 in the target plane XY and reducing the Df of the first sub-board 201. Because the dielectric material with low CTE in the target plane XY usually has a large Df. The dielectric material with a low Df has a high CTE in the target plane XY. For example, in order to achieve the purpose of low CTE of the first sub-board 201 in the target plane XY, the dielectric material of the first sub-board 201 can be a polymer resin with low CTE, but the polymer resin with low CTE usually has a large Df, that is, the polymer resin with low CTE usually does not have the performance of low Df. If the dielectric material of the first sub-board 201 is made of quartz cloth, the cost of the dielectric material will increase significantly and the processing difficulty will increase significantly, so that a small via pitch cannot be achieved. In order to reduce the CTE of the first sub-board 201 in the target plane XY, the proportion of fiber cloth can be increased in the dielectric material, so that the first sub-board 201 has both low CTE and low insertion loss performance. However, the first sub-board 201 with an increased fiber cloth ratio will have a fiber cloth interface, which is very likely to cause the conductive anodic filament (CAF) failure problem between the vias, especially when the via pitch is ≤200μm or less, the filler ratio with low CTE and low insertion loss performance will affect the impregnation performance of the interface, and the micro cracks on the fiber cloth interface caused by the drilling of high-density vias will deteriorate the CAF reliability and easily cause CAF failure. If the first sub-board 201 has a lower CTE in the target plane XY, it will cause the cost of the first sub-board 201 to increase significantly or the processing difficulty to increase significantly (such as the dielectric material of the first sub-board 201 uses quartz cloth, etc.), and the high filler filling used to reduce the CTE of the first sub-board 201 in the target plane XY affects the wetting performance between the polymer resin and the filler, and between the polymer resin and the glass fiber cloth, resulting in the deterioration of the heat resistance, CAF resistance, and highly accelerated stress test (HAST) resistance of the via.

[0068] The present application provides a communication device, which includes a circuit board and an electronic device electrically connected to the surface of the circuit board. For a description of the types of electronic devices, see Figure 1 The corresponding description is not repeated in detail. The circuit board of the communication device has both low insertion loss and low CTE performance. The circuit board shown in this embodiment can effectively suppress the CTE mismatch between the circuit board and the electronic device, improve the reliability of the circuit board, and at the same time effectively reduce the insertion loss of the circuit board to meet the increasing demand for information rate transmission of the circuit board. For example, the CTE of the circuit board provided in this embodiment is ≤15ppm / ℃, and Df ≤0.002@10GHz.

[0069] Figure 3 This is a structural example diagram of the first embodiment of the circuit board provided in this application. Figure 3 The following is an example of the structure of the circuit board in the coordinate system XYZ. For an explanation of the XYZ coordinate system, see Figure 1 The corresponding description is not elaborated in detail. The circuit board shown in this embodiment includes M sub-boards arranged in sequence along the target direction Z, where M is any integer not less than 2. The M sub-boards specifically include one or more first sub-boards 301. This embodiment does not limit the number of first sub-boards 301. This embodiment takes the example that the circuit board includes one first sub-board 301. The M sub-boards also include one or more second sub-boards. This embodiment does not limit the number of second sub-boards. This embodiment takes the example that the circuit board includes multiple second sub-boards. Take the example that the multiple second sub-boards are symmetrically distributed along the target direction Z with the first sub-board 301 as the center. For example, the circuit board includes two second sub-boards, namely a second sub-board 302 and a second sub-board 303. Along the target direction Z, the first sub-board 301 is located between the second sub-board 302 and the second sub-board 303. The circuit board also includes a conductive layer (for example Figure 2 Copper foil shown). It should be clear that the present embodiment does not limit the number of second sub-boards included in the circuit board. For example, the circuit board includes four second sub-boards. Then, two second sub-boards are superimposed on the upper surface of the first sub-board 301, and two second sub-boards are superimposed on the lower surface of the first sub-board 302. The circuit board shown in this example also includes a conductive layer located between two adjacent second sub-boards. It should be clear that the present embodiment takes multiple second sub-boards symmetrically distributed with the first sub-board 301 as the center to improve the overall flatness of the circuit board and the reliability of the circuit board structure as an example. In other examples, the multiple second sub-boards can also be asymmetrically distributed with the first sub-board 301 as the center. The present embodiment does not limit the positional relationship between the first sub-board 301 and the second sub-board. In other examples, the positional relationship between the first sub-board and the second sub-board in the circuit board can be interchangeable. For example, the second sub-board is located between multiple first sub-boards.

[0070] The M sub-boards shown in this embodiment may also include one or more third sub-boards. This embodiment does not limit the number of third sub-boards. This embodiment takes the circuit board including multiple third sub-boards as an example. Multiple third sub-boards are symmetrically distributed along the target direction Z with the first sub-board 301 as the center to improve the overall flatness of the circuit board and improve the reliability of the circuit board structure. For example, the circuit board includes two third sub-boards, namely the third sub-board 304 and the third sub-board 305. Along the target direction Z, the first sub-board 301, the second sub-board 302 and the second sub-board 303 are located between the third sub-board 304 and the third sub-board 305. That is, the third sub-board 304 is connected to the surface of the second sub-board 302 facing away from the first sub-board 301, and the third sub-board 305 is connected to the surface of the second sub-board 303 facing away from the first sub-board 301. The circuit board also includes a conductive layer located between the second sub-board 302 and the third sub-board 304, and a conductive layer located between the second sub-board 303 and the third sub-board 305. It should be clarified that this embodiment does not limit the number of third sub-boards included in the circuit board. For the description of the number and distribution form of the third sub-boards included in the circuit board, please refer to the description of the number and distribution form of the second sub-boards included in the circuit board, and no details will be given.

[0071] As can be seen from the above description, it is difficult for the same dielectric material to have both low CTE and low Df performances. As shown in this embodiment, in order to reduce the overall CTE and Df of the circuit board, the two performances of low CTE and low Df are decomposed into different sub-boards included in the circuit board. In this embodiment, the first sub-board has the performance of low CTE, and the second sub-board has the performance of low Df. It can be understood that in order to suppress the mismatch of CTE between the circuit board and the electronic device, the CTE of the circuit board needs to be reduced. The way to reduce the CTE of the circuit board shown in this embodiment is to ensure that the CTE of the first sub-board 301 is less than the CTE of the second sub-board. Specifically, in the target XY plane, the CTE of the first sub-board 301 is less than the CTE of the second sub-board. The CTE of the third sub-board shown in this embodiment is less than the CTE of the second sub-board. Specifically, in the target XY plane, the CTE of the third sub-board is less than the CTE of the second sub-board. It should be noted that the CTE of each sub-board shown in this embodiment is taken as an example of the CTE in the target plane. In other examples, the CTE of each sub-board may also be the CTE of each sub-board along the target direction Z, which is not specifically limited in this embodiment. It can be understood that the CTE of the second sub-board shown in this embodiment is the highest among the M sub-boards. This embodiment does not limit the size relationship between the CTE of the first sub-board and the CTE of the third sub-board.

[0072] When the CTE of the first sub-board and the third sub-board among the M sub-boards included in the circuit board are respectively smaller than the CTE of the second sub-board, the overall CTE of the circuit board can be effectively reduced. For a specific description, please refer to the following formula 3:

[0073] Taking the circuit board shown in this embodiment as a PCB as an example, it should be clear that the description of the circuit board type in this embodiment is not limited. For example, the circuit board can also be a substrate. For the description of the circuit board type, please refer to Figure 1 The corresponding instructions are not detailed here. The CTE of PCB is affected by the dielectric material and thickness used in PCB. When the proportion of copper foil in PCB is certain and the design of PCB is certain, the lower the CTE of dielectric material, the lower the CTE of PCB. The design of PCB includes vias, plug holes, solder mask, residual copper rate of graphics, etc., which are not limited to specific ones. The CTE of PCB can be obtained by formula 3:

[0074] Formula 3:

[0075] In formula 3, 1 to n are the codes of each sub-board on the PCB. The PCB includes sub-board 1, sub-board 2, and so on, to sub-board n. αn is the CTE of sub-board n, En is the Young's modulus of sub-board n, and φn is the volume ratio of sub-board n. From the above, it can be seen that if the CTE of the first sub-board 301 and the third sub-board is reduced, the overall CTE of the PCB can be effectively reduced, where the overall CTE of the PCB is a in formula 3. PCB .

[0076] It can be seen from the above description that it is difficult for a sub-board to have both low CTE and low insertion loss performance. In order to make the circuit board have both low CTE and low insertion loss performance, this embodiment decomposes the performance of low CTE and the performance of low insertion loss into different sub-boards included in the circuit board. Specifically, when the CTE of the second sub-board is the highest among the M sub-boards, then the Df of the second sub-board is the smallest among the M sub-boards, thereby reducing the overall CTE and insertion loss of the circuit board. To this end, in order to ensure that the insertion loss of the second sub-board is the lowest among the M sub-boards, then the Df of the second sub-board is smaller than the Df of the first sub-board, and the Df of the second sub-board is smaller than the Df of the third sub-board. This embodiment does not limit the size relationship between the Df of the first sub-board and the Df of the third sub-board. It can be understood that when the CTE of the second sub-board is the highest among the M sub-boards and the Df of the second sub-board is the smallest among the M sub-boards, then this embodiment decomposes the performance of low CTE and low insertion loss into two different sub-boards, that is, the first sub-board and the third sub-board have low CTE performance, and the second sub-board has low insertion loss performance.

[0077] In order to effectively reduce the overall CTE of the circuit board, the Young's modulus of the second sub-board is smaller than that of the first sub-board, and / or the Young's modulus of the second sub-board is smaller than that of the third sub-board. In this embodiment, the Young's modulus of the second sub-board is taken as an example, which is the lowest among the M sub-boards. Then, due to the low Young's modulus of the second sub-board, the negative impact of the high CTE of the second sub-board on the CTE of the entire circuit board can be reduced as much as possible. As shown in the above formula 3, in order to reduce the overall CTE of the circuit board, when the CTE and volume ratio of the M circuit boards are constant, the lower the Young's modulus of the second sub-board, the lower the overall CTE of the circuit board. Optionally, in the circuit board shown in this embodiment, the third sub-board is located in the outermost layer, so the Young's modulus of the third sub-board is the highest among the multiple sub-boards included in the circuit board, thereby effectively improving the overall rigidity of the circuit board and reducing the imprint when the circuit board surface is mounted. The following is a specific description of each sub-board of the circuit board:

[0078] The first sub-board 301 can be used as a power layer or ground layer with lower electrical requirements. Among them, the power layer will arrange power and ground lines to ensure that the power supply of the entire circuit board is stable and reliable. The ground layer will arrange ground lines and power lines to ensure that the ground connection of the entire circuit board is stable and reliable. The Young's modulus of the first sub-board 301 is greater than that of the second sub-board. The high Young's modulus of the first sub-board 301 can improve the reliability of the circuit board. The low CTE of the first sub-board 301 effectively reduces the overall CTE of the circuit board. It can be understood that the dielectric material of the first sub-board 301 is selected from dielectric materials with small CTE and no consideration of insertion loss. For example, the dielectric material of the first sub-board 301 can be bismaleimide triazine resin (BT resin) or high rigidity epoxy resin. The dielectric material of the first sub-board 301 also includes glass cloth with low CTE, thereby ensuring that the first sub-board 301 has a lower CTE and a higher Young's modulus. Among them, glass cloth with low CTE includes but is not limited to high-strength glass (T-glass) glass cloth, high-strength glass fiber (S-glass) glass cloth and any other type of reinforcing materials with low CTE and high Young's modulus. The copper foil located on both sides of the first sub-board 301 can be reverse (RTF) copper foil, RTF2, RTF3, high-frequency ultra-low profile copper foil (HVLP), ultra-thin detachable copper foil with a thickness of ≤5μm along the target direction Z, etc. based on the minimum line width requirement. The interface treatment agent between the glass cloth and the copper foil is selected based on the resin system, such as silane coupling agents containing amino or epoxy groups, etc., and is not specifically limited. The first sub-board 301 shown in this example has a CTE of ≤10ppm / ℃ and a Young's modulus of ≥10 gigapascals (GPa) in the target plane XY. Optionally, the first sub-board 301 can be a fiber-reinforced composite material with a glass transition temperature (Tg) ≥220℃. This embodiment does not limit the number of layers of the first sub-board 301. For example, the first sub-board 301 is designed to be a double-layer or multi-layer structure based on performance requirements such as power supply, heat conduction, and shielding. The overall thickness of the first sub-board is ≥400μm. The thickness of the first sub-board 301 along the target direction Z shown in this embodiment is greater than the thickness of the second sub-board along the target direction Z, and the thickness of the first sub-board 301 along the target direction Z is greater than the thickness of the third sub-board along the target direction Z. It can be understood that the thickness of the first sub-board 301 along the target direction Z is the highest among the M sub-boards. Then, when the first sub-board 301 has a lower CTE in the target plane XY, the overall CTE of the circuit board is effectively reduced.

[0079] Taking the second sub-board 302 as an example, the second sub-board 302 can be used as a signal layer (signal layers) with higher electrical requirements. The second sub-board 302 adopts a dielectric material with low Young's modulus and low insertion loss. That is, the Young's modulus of the second sub-board 302 is the lowest among the M sub-boards, and the Df of the second sub-board 302 is the lowest among the M sub-boards. For example, in order to achieve low insertion loss of the second sub-board 302, the Df of the second sub-board ≤ 0.002, and in order to achieve low Young's modulus of the second sub-board 302, the Young's modulus of the second sub-board 302 is ≤ 5GPa. The CTE of the second sub-board 302 shown in this example in the target plane XY is greater than the CTE of the first sub-board 301 in the target plane XY, so the CTE of the second sub-board 302 shown in this example in the target plane XY is ≤ 35ppm / ℃, Young's modulus ≤ 3GPa, and Dk ≤ 3.5. Optionally, the second sub-board 302 may be in the form of a film, a sheet or a resin coated copper foil (RCC). Optionally, if the second sub-board 302 is in the form of RCC, the selection of its copper foil is based on the circuit manufacturing process and the line width requirements. If it is a modified semi-addition process (mSAP) process with a line width of ≤40μm, it can be matched with a 1-5μm carrier copper foil, etc. If it is a negative film (tenting) process, it can be matched with RTF, RTF2, RTF3 or HVLP copper foil. The second sub-board 302 may not use a continuously woven fiber cloth as a reinforcing material to reduce the overall Young's modulus. The dielectric material of the second sub-board 302 can be selected from a thermosetting resin or a thermoplastic resin. Among them, the thermosetting resin can be a modified epoxy resin, a low-polarity resin, or a polyphenylene oxide (PPO), which can also be referred to as (polypheylene ether, PPE). The thermoplastic resin may be liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE) or polyimide (PI).

[0080] As the information transmission rate of communication equipment becomes higher and higher, the capacity of transmitted information is also increasing, which prompts the circuit boards used in communication equipment to develop towards high speed and high density. Correspondingly, the requirements for high-speed signal transmission performance of circuit boards are getting higher and higher, and the routing and / or via pitch are becoming more and more dense, and the size of electronic devices (such as chips, etc.) is getting larger and larger, resulting in higher and higher risks of reliability failures such as solder joint cracking, CAF, and HAST. In order to improve the reliability of communication equipment and achieve the purpose of reducing via pitch, the dielectric material used in the circuit board needs to have low insertion loss, small via pitch, and low CTE in the target plane XY. In the circuit board shown in this embodiment, the second sub-board has the performance of low Df and low Young's modulus, so that the second sub-board can achieve a small via pitch. Among them, pitch generally refers to the center distance between vias or pads on a circuit board. Specifically, because the second sub-board does not use continuously woven fiber cloth as a reinforcing material, the reliability capability of small pitch resistance to CAF, HAST, etc. can be improved in ultra-dense and small via pitch scenarios, especially in scenarios with pitch ≤ 200μm. The impedance control requirement can be met at a relatively low thickness. Since the thickness of the second sub-board is relatively small, the negative impact of the second sub-board on the overall CTE of the circuit board can be reduced, and the overall thickness of the circuit board can be reduced.

[0081] Taking the third sub-board 304 as an example, the third sub-board 304 is the outermost layer of the PCB. Because it is necessary to consider operations such as pad surface mounting technology (SMT), this embodiment takes the third sub-board 304 having the highest Young's modulus among the M sub-boards included in the circuit board as an example. Specifically, the third sub-board 304 has a Young's modulus ≥ 7GPa and a Df ≤ 0.004@10GHz. The CTE of the third sub-board 304 in the target plane XY is ≤ 30ppm / ℃. In order to reduce the conductor loss of the third sub-board 304, its copper foil uses a low-roughness copper foil with a micro-roughness ten-point height (Rz) ≤ 3μm, and the thickness is determined based on the minimum line width requirement. The thicknesses of the second sub-board 302 and the third sub-board 304 shown in this embodiment are ≤ 100μm as an example.

[0082] The Young's modulus of the circuit board can be obtained by the following formula 4:

[0083] Formula 4:

[0084] Among them, E PCBis the Young's modulus of the entire PCB, and 1 to n are the codes of each sub-board on the PCB. The PCB includes sub-board 1, sub-board 2, and so on, to sub-board n. En is the Young's modulus of sub-board n, and φn is the volume percentage of sub-board n. This embodiment can be based on formula 4 to achieve the design of the Young's modulus of M circuit boards, thereby ensuring that the Young's modulus of the second sub-board is the highest among the M sub-boards.

[0085] It can be understood that the structure of the circuit board shown in this embodiment can be used based on the requirements of the overall CTE and Young's modulus of the circuit board by using different CTE and Young's modulus dielectric materials in different sub-boards and matching the thickness of different sub-boards. In this embodiment, the purpose of reducing the overall CTE of the circuit board is achieved by reducing the CTE of the first sub-board and the third sub-board in the target plane XY, so that the CTE requirement of the second sub-board in the target plane XY can be relaxed. Since the CTE requirement of the second sub-board in the target plane XY is relaxed, the second sub-board can use a dielectric material with a relatively small Df, thereby ensuring that the circuit board provided by this embodiment can take into account the performance of low CTE and low insertion loss.

[0086] The structure of the circuit board is described below with a specific example:

[0087] Figure 4 This is a structural example diagram of the second embodiment of the circuit board provided in this application. Figure 4 The circuit board shown is a high density interconnector (HDI) circuit board as an example.

[0088] Figure 4 The following is an example of the structure of the circuit board in the coordinate system XYZ. For an explanation of the XYZ coordinate system, see Figure 1 The circuit board shown in this embodiment specifically includes a first sub-board 401. For a description of the structure of the first sub-board 401, see Figure 3The description of the corresponding first sub-board is not repeated in detail. The circuit board also includes multiple second sub-boards. In this embodiment, the circuit board includes six second sub-boards, that is, along the target direction Z, the circuit board includes second sub-board 411, second sub-board 412, second sub-board 413, second sub-board 414, second sub-board 415, and second sub-board 416 from top to bottom. This embodiment does not limit the number of second sub-boards. The circuit board may also include two third sub-boards, that is, along the target direction Z, the circuit board includes third sub-board 421 and third sub-board 422 from top to bottom. This embodiment does not limit the number of third sub-boards. This embodiment takes the example that multiple second sub-boards are symmetrically distributed around the first sub-board 401 as the center, and multiple third sub-boards are symmetrically distributed around the first sub-board 401 as the center. For a description of the positional relationship between the first sub-board, the second sub-board and the third sub-board shown in this embodiment, please refer to Figure 3 The corresponding embodiments are not described in detail. The M sub-boards shown in this embodiment may also include at least one fourth sub-board. In this embodiment, the circuit board includes two fourth sub-boards, namely the fourth sub-board 431 and the fourth sub-board 432. The plurality of fourth sub-boards are also symmetrically distributed around the first sub-board 401. Specifically, the fourth sub-board 431 is located between the second sub-board 412 and the first sub-board 401, and the fourth sub-board 432 is located between the second sub-board 414 and the first sub-board 401.

[0089] The dielectric material of the fourth sub-board shown in the embodiment may be the same as the dielectric material of the first sub-board, and / or the dielectric material of the fourth sub-board may be the same as the dielectric material of the third sub-board. In order to suppress the CTE mismatch between the circuit board and the electronic device in this embodiment, it is necessary to reduce the CTE of the circuit board. The method of reducing the CTE of the circuit board shown in this embodiment is that, in the XY plane, the CTE of the first sub-board 401 is smaller than the CTE of the second sub-board, the CTE of the third sub-board is smaller than the CTE of the second sub-board, and the CTE of the fourth sub-board is smaller than the CTE of the second sub-board. The CTEs of the first sub-board, the third sub-board and the fourth sub-board are respectively smaller than the CTE of the second sub-board, thereby effectively reducing the overall CTE of the circuit board, please refer to the description. Figure 3 The description of the corresponding embodiments is omitted here.

[0090] In order to make the circuit board have the performance of low CTE and low insertion loss at the same time, the Df of the second sub-board is the smallest among the M sub-boards in this embodiment, that is, the Df of the first sub-board 401 is greater than the Df of the second sub-board, the Df of the third sub-board is greater than the Df of the second sub-board, and the DF of the fourth sub-board is greater than the DF of the second sub-board. It can be understood that when the Df of the second sub-board is the lowest among the M circuit boards, the insertion loss of the circuit board is effectively reduced. In the circuit board shown in this embodiment, the third sub-board is located in the outermost layer, so the Young's modulus of the third sub-board is the highest among the M sub-boards included in the circuit board, thereby effectively improving the overall rigidity of the circuit board and reducing the footprint of the circuit board surface when mounting components. The Young's modulus of the second sub-board shown in this embodiment is the lowest among the M sub-boards, so due to the low Young's modulus of the second sub-board, the negative impact of the high CTE of the second sub-board on the CTE of the entire circuit board can be reduced as much as possible. The following is a specific description of each sub-board of the circuit board:

[0091] The first sub-board 401 can be used as a power layer or a ground layer. For a description of the power layer and the ground layer, see Figure 3 The corresponding description of the first sub-board is not repeated here. The first sub-board 401 shown in this embodiment has a high Young's modulus and a low CTE in the target plane XY, thereby improving the stability of the circuit board structure, reducing the overall CTE of the circuit board, and improving the overall warpage of the circuit board. The dielectric material of the first sub-board 401 is selected from a material with a CTE of ≤10ppm / ℃, a Young's modulus of ≥10GPa, and no consideration of Df in the target plane XY. For details, please refer to Figure 3 The corresponding dielectric material of the first sub-plate 301 is not described in detail. Based on the actual plate thickness and mechanical property control requirements, the thickness of the first sub-plate 401 is designed to be 100-1600 μm. This embodiment takes the thickness of the first sub-plate 401 as ≥200 μm as an example.

[0092] Taking the second sub-plate 411 as an example, the second sub-plate 411 can be in the form of a film material, a sheet material or RCC. The second sub-plate 411 does not use a continuously woven fiber cloth as a reinforcing material to reduce the overall Young's modulus. The dielectric material of the second sub-plate 411 can be selected from a thermosetting resin or a thermoplastic resin. For a description of a thermosetting resin or a thermoplastic resin, please refer to Figure 3The description of the corresponding second sub-board is not described in detail. The Df of the second sub-board 411 is ≤0.002, and the Young's modulus is ≤5GPa. The CTE of the second sub-board 411 in the target plane XY is ≤35ppm / ℃. In this embodiment, the Young's modulus of the second sub-board 411 is ≤3GPa, Dk≤3.5, and the thickness is ≤50μm. If the second sub-board 411 is made into an RCC form, its thickness and copper foil selection are determined by the circuit manufacturing process and line width requirements; if it is an mSAP process (line width 20~50μm), it can be matched with 1~3μm carrier copper foil, etc. If it is a tenting process (line width ≥40μm), it can be matched with RTF, RTF2, RTF3, HVLP and other copper foils. For the description of any second sub-board included in the circuit board, please refer to the description of the second sub-board 411, and the details are not repeated.

[0093] Taking the third sub-board 421 as an example, the third sub-board 421 can take into account both the performance of low CTE and low insertion loss. The dielectric material of the third sub-board 421 can be selected from materials with relatively small CTE and low insertion loss performance. Specifically, the CTE of the third sub-board 421 in the target plane XY is smaller than the CTE of the second sub-board in the target plane XY. The Df of the third sub-board 421 is greater than the Df of the second sub-board 411. For example, the dielectric material of the third sub-board 421 can be modified high-rigidity epoxy + BT resin. The dielectric material of the third sub-board 421 also partially introduces low-polarity CH resin, and controls the overall performance through prepolymerization. Optionally, the dielectric material of the third sub-board 421 can also be matched with glass cloth with low Dk to obtain good electrical properties. For example, the glass cloth can be NE-glass cloth (NE-glass), NER-glass cloth (NER-glass), low-loss glass cloth (L-glass), L2-glass and other glass cloths with low Dk. Optionally, in order to reduce conductor loss, the copper foil of the third sub-board 421 uses low-roughness copper foil with Rz≤3μm, and the thickness is determined based on the minimum line width requirement. Since the third sub-board 421 uses glass fiber cloth reinforced dielectric material, high-density via pitch is not set in this layer. The third sub-board 421 has CTE≤17ppm / ℃, Young's modulus≥7GPa, Df≤0.004@10GHz, and thickness≤100μm in the target plane XY. For the description of the fourth sub-board, please refer to the description of the first sub-board or the third sub-board 421, and no further details will be given.

[0094] The following is a description of the thickness of the copper foil of each sub-board of the circuit board, the thickness of each sub-board itself, and the copper foil coating process as shown in Table 1:

[0095] Table 1

[0096]

[0097]

[0098] It can be understood that Layer L1 is the copper foil covering the surface of the third sub-board 421 , Layer L2 is the copper foil covering the surface of the second sub-board 411 , and so on, Layer 12 is the copper foil covering the surface of the third sub-board 422 .

[0099] Based on the overall CTE and Young's modulus requirements of the PCB, the CTE and Young's modulus of the PCB can be adjusted by using dielectric materials with different CTE and Young's modulus properties on different sub-boards. For details, see Table 2 below:

[0100] Table 2

[0101]

[0102] The circuit board structures shown in Examples 1 to 8 shown in Table 2 all adopt Figure 4 In the embodiment shown, that is, the CTE of the first sub-board in the XY plane is the lowest among the multiple sub-boards included in the circuit board. The Young's modulus of the second sub-board is the lowest among the multiple sub-boards included in the circuit board. For each example described in Table 2, taking the dielectric material of the third sub-board as the same as the dielectric material of the fourth sub-board as an example, the CTE and Young's modulus of the third sub-board and the fourth sub-board in the target plane XY are between the first sub-board and the second sub-board. Specifically, in Example 1, the dielectric material of the first sub-board is a dielectric material reinforced with glass fiber cloth, and the CTE in the target plane XY is 8ppm / ℃, the Young's modulus is 30GPa, Df≥0.008 / 10GHz, and the thickness is 410μm. The third sub-board and the fourth sub-board use the same dielectric material. The third sub-board and the fourth sub-board both use a dielectric material reinforced with glass fiber cloth, and the CTE in the target plane XY is 15ppm / ℃, the Young's modulus is 20GPa, the Df is 0.004 / 10GHz, and the thickness is 40μm. The second sub-board uses a non-fiber-reinforced film material, with a CTE of 35ppm / ℃, a Young's modulus of 2GPa, a Df of 0.0012 / 10GHz, a thickness of 30μm, and a Dk of 3.0 in the target plane XY. Then, in Example 1, the CTE of the entire PCB in the target plane XY is 25.4ppm / ℃, and the Young's modulus is 11.9GPa. The Dk of the PCB is 3.0, and the Df is 0.012. Examples 2 to 8, and so on, are not repeated here.

[0103] like Figure 2 The performance of each sub-board of the circuit board shown can be seen in Table 3:

[0104] Table 3

[0105]

[0106]

[0107] For detailed description of the circuit board corresponding to Table 3, please refer to Figure 2 As shown, the details are not repeated here. In comparative example 1, the CTE of the dielectric material of the first sub-board in the target plane XY is 8ppm / ℃, the Young's modulus is 30GPa, and the thickness is 410μm. The CTE of the second sub-board in the target plane XY is 15ppm / ℃, the Young's modulus is 20GPa, and the thickness is 40μm. Because the dielectric material of the second sub-board in the existing circuit board cannot have both low CTE and low insertion loss performance, the Df of the second sub-board is relatively large, which is 0.0038@10GHz. That is, Figure 2 In the circuit board shown, the CTE of the first sub-board in the target plane XY is the lowest among all the sub-boards included in the circuit board, and the Young's modulus of the first sub-board is the highest among all the sub-boards included in the circuit board. Therefore, the corresponding CTE of the entire circuit board in the target plane XY is 28.7, and the Young's modulus is 12.1.

[0108] Combining Table 2 and Table 3, it can be seen that the Figure 4 The structure of the circuit board shown is Figure 2 The corresponding circuit board structure makes the CTE of the circuit board in the target plane XY lower. Figure 4 The circuit board shown can achieve the second sub-board with ultra-low Df and low Dk performance, can be made into high-speed signal layer transmission, and effectively reduce the purpose of insertion loss.

[0109] The structure of the circuit board shown in this embodiment is adopted, and the circuit board includes a plurality of dielectric materials with different properties, and the different properties such as low CTE, high Young's modulus, and low insertion loss in the target plane XY are decomposed into different sub-boards included in the circuit board. For example, the CTE of the first sub-board in the target plane XY is less than the CTE of the second sub-board in the target plane XY. The Young's modulus of the second sub-board is the lowest among the M sub-boards. The Df of the second sub-board is the lowest among the M sub-boards. It can be understood that the lower CTE and the lower Df in the target plane XY are decomposed into the first sub-board and the second sub-board respectively to achieve. Because the CTE of the first sub-board in the target plane XY is lower, the overall CTE of the circuit board in the target plane XY is effectively reduced. Because the Df of the second sub-board is lower, the insertion loss of the circuit board is effectively reduced. Moreover, the Young's modulus of the second sub-board is the lowest among the M sub-boards, which effectively suppresses the high CTE of the second sub-board and the negative impact on reducing the overall CTE of the circuit board. When the CTE of the circuit board in the target plane XY is reduced, the mismatch of CTE between the circuit board and the electronic components is effectively suppressed. The Young's modulus of the first sub-board and the Young's modulus of the third sub-board are both higher than that of the second sub-board, which effectively improves the reliability of the overall structure of the circuit board.

[0110] Since the first sub-board shown in this embodiment has a lower CTE in the target plane XY, and the first sub-board does not need to have a lower insertion loss (i.e., a lower Df), the dielectric material of the first sub-board does not need to take into account the performance of reducing CTE and reducing insertion loss at the same time, which effectively reduces the cost and manufacturing difficulty of the first sub-board. The circuit board shown in this embodiment can achieve the following goals, that is, the CTE of the entire circuit board in the target plane XY is ≤15ppm / ℃, and Df is ≤0.001, thereby ensuring that the entire circuit board has a low CTE in the target plane XY and has a low insertion loss, and ensuring the reliability of the circuit board structure.

[0111] Figure 4 The circuit board includes 12 layers of copper foil as an example. It should be noted that this embodiment does not limit the number of copper foils included in the circuit board. For example, the circuit board includes 16 layers of copper foil. Figure 5 The structure of an existing circuit board including 16 layers of copper foil is described as shown, wherein: Figure 5 Another structural example diagram of an existing circuit board is shown below.

[0112] The circuit board includes a first sub-board 501 with copper foil on both sides. For a description of the first sub-board 501, see Figure 2 The corresponding description is omitted here. The circuit board also includes 14 second sub-boards stacked in sequence from top to bottom along the Z direction, namely, second sub-board 511, second sub-board 512, second sub-board 513, second sub-board 514, second sub-board 515, second sub-board 516, second sub-board 517, second sub-board 518, second sub-board 519, second sub-board 520, second sub-board 521, second sub-board 522, second sub-board 523 and second sub-board 524. Among them, the 14 second sub-boards are symmetrically distributed with the first sub-board 501 as the center. For a description of each second sub-board, please refer to Figure 2 The corresponding description of the second sub-board is not repeated in detail. Figure 5 The corresponding circuit board includes 15 layers of copper foil, namely L1, L2, and so on, to L16. Among them, L1 is the copper foil covering the surface of the second sub-board 511, and so on, L16 is the copper foil covering the surface of the second sub-board 524. Figure 5 The performance of the corresponding circuit board can be seen in Table 4:

[0113] Table 4

[0114]

[0115] Use Figure 5 In the structure of the existing circuit board shown, the first sub-board 501 is covered with copper foils L8 and L9 on both sides, the thickness of the first sub-board 501 along the target direction Z is 400 μm, and the thickness of each of the 14 second sub-boards along the target direction Z is 70 μm. Figure 5 In the corresponding circuit board, the Young's modulus of the entire circuit board is 30.2 GPa, and the CTE in the target plane XY is 13.2 ppm / °C.

[0116] Figure 6 This is a structural example diagram of the third embodiment of the circuit board provided in this application. Figure 6 The circuit board shown in the embodiment also includes 15 layers of copper foil. The circuit board shown in this embodiment is a structural example diagram in the coordinate system XYZ. For an explanation of the coordinate system XYZ, please refer to Figure 3 The circuit board shown in this embodiment includes a sub-board 601, a sub-board 602, a sub-board 603 to a sub-board 615 which are sequentially stacked along the target direction Z. Figure 6 The performance of the corresponding circuit board can be seen in Table 5:

[0117] Table 5

[0118]

[0119]

[0120] Figure 6 In the corresponding circuit board example 1, sub-board 608 is the first sub-board, sub-boards 601, 603, 604, 605, 606, 609, 610, 611, 612, 613 are the third sub-boards, and sub-boards 602 and 614 are the second sub-boards. For the description of the first sub-board, the second sub-board and the third sub-board, see Figure 3 The corresponding description is not elaborated in detail. In the circuit board corresponding to Example 1, the performance of the first sub-board is that the CTE of the first sub-board 608 in the target plane XY is 10ppm / ℃, the Young's modulus is 20GPa, and the thickness along the target direction Z is 400μm. The CTE of each third sub-board in the target plane XY is 13ppm / ℃, the Young's modulus is 15GPa, and the thickness along the target direction Z is 70μm. The second sub-board can be in the form of RCC, and the CTE of each second sub-board in the target plane XY is 30ppm / ℃, the Young's modulus is 3GPa, and the thickness along the target direction Z is 50μm. As shown in Table 5, the CTE of the first sub-board in the XY plane is the lowest among all the sub-boards included in the circuit board. The Young's modulus of the second sub-board is the lowest among all the sub-boards included in the circuit board. For specific instructions, please refer to Figure 3 The corresponding description is omitted here. Then, the CTE of the entire circuit board shown in Example 1 in the target plane XY is 13.4, and the Young's modulus is 28.4 GPa.

[0121] In Example 2, sub-board 608 is the first sub-board, sub-boards 601, 604, 605, 606, 609, 610, 611, 612 are the third sub-boards, and sub-boards 602, 603, 614, 613 are the second sub-boards. For a description of the first sub-board, the second sub-board, and the third sub-board, see Figure 3 The corresponding description is not repeated here. For the description of the performance of the first sub-board, the second sub-board and the third sub-board, please refer to Example 1, and the specific description is not repeated here. Using the circuit board shown in Example 2, the CTE of the entire circuit board in the target plane XY is 13.6 and the Young's modulus is 26.7GPa.

[0122] In Example 3, sub-board 608 is the first sub-board, sub-boards 601, 604, 606, 607, 609, 610, 612, 615 are the third sub-boards, and sub-boards 602, 603, 605, 611, 613, 614 are the second sub-boards. For a description of the first sub-board, the second sub-board, and the third sub-board, see Figure 3 The corresponding description is not repeated here. For the description of the performance of the first sub-board, the second sub-board and the third sub-board, please refer to Example 1, and the specific description is not repeated here. Using the circuit board shown in Example 3, the CTE of the entire circuit board in the target plane XY is 13.8 and the Young's modulus is 24.9 GPa.

[0123] In Example 4, sub-board 608 is the first sub-board, sub-boards 601, 604, 606, 607, 609, 610, 612, 615 are the third sub-boards, and sub-boards 602, 603, 605, 611, 613, 614 are the second sub-boards. For a description of the first sub-board, the second sub-board, and the third sub-board, see Figure 3 The corresponding description is not repeated here. For the description of the performance of the first sub-board, the second sub-board and the third sub-board, please refer to Example 1, which is not repeated here. Using the circuit board shown in Example 4, the CTE of the entire circuit board in the target plane XY is 14.1 and the Young's modulus is 23.1 GPa.

[0124] Comparing Examples 1 to 4 in Table 4 and Table 5, it can be seen that Figure 6 The structure of the corresponding circuit board is different from that of the Figure 5 The corresponding results of the existing circuit board are: Figure 6 The structure of the circuit board shown can be close to or equivalent to the CTE of the existing circuit board, but Figure 6 The structure of the circuit board shown can effectively reduce the insertion loss.

[0125] In Example 5 shown in Table 5, sub-board 608 is the first sub-board, sub-boards 601, 604, 606, 607, 609, 610, 612, 615 are the third sub-boards, and sub-boards 602, 603, 605, 611, 613, 614 are the second sub-boards. For a description of the first sub-board, the second sub-board, and the third sub-board, see Figure 3 The corresponding description is not repeated in detail. The difference between Example 4 and Example 5 is that the thickness of the first sub-board shown in Example 5 along the target direction Z is 500um. For the description of the performance of the first sub-board, the second sub-board and the third sub-board, please refer to Example 1, and the specific description is not repeated. Using the circuit board shown in Example 4, the CTE of the entire circuit board in the target plane XY is 13.8 and the Young's modulus is 25.1GPa. By comparing Examples 4 and 5, it can be seen that when the thickness of the first sub-board along the target direction Z is increased, the CTE in the target plane XY will be reduced. For example, along the target direction Z, when the thickness of the first sub-board shown in Example 5 is greater than the thickness of the first sub-board shown in Example 4, the CTE of the circuit board shown in Example 5 in the target plane XY is less than the CTE of the circuit board shown in Example 4 in the target plane XY.

[0126] As shown in Table 5, the number of layers of the second sub-board included in the circuit board is different in different examples. For example, Example 1 shown in Table 5 includes two layers of second sub-boards, Example 2 includes four layers of second sub-boards, and Example 3 includes six layers of second sub-boards. Figure 6 The corresponding circuit board includes a fixed number of first sub-boards, second sub-boards and third sub-boards, and a different example is that the second sub-board has a different Young's modulus.

[0127] Table 6

[0128]

[0129] In Example 1 and Example 2 shown in Table 6, the first sub-board is sub-board 608, and the second sub-board is sub-board 602, 603, 605, 611, 613, and 614. The third sub-boards are all sub-boards 601, 604, 606, 607, 609, 610, 612, and 615. For the description of the performance of each sub-board, please refer to the corresponding description of Table 5, and the specific details are not repeated. The difference between Example 1 and Example 2 included in Table 6 is that the Young's modulus of the second sub-board shown in Example 1 is 1 GPa, and the Young's modulus of the second sub-board shown in Example 2 is 2 GPa. It can be seen from the comparison of Examples 1 and Example 2 included in Table 6 that when the Young's modulus of the second sub-board of Example 2 is greater than the Young's modulus of the first sub-board of Example 1, the Young's modulus of the entire circuit board of Example 2 is greater than the Young's modulus of the entire circuit board of Example 1. The CTE of the circuit board shown in Example 2 in the target plane XY is greater than the CTE of the circuit board shown in Example 1 in the target plane XY.

[0130] Figure 7 This is a structural example diagram of the fourth embodiment of the circuit board provided in this application. Figure 7 The figure shows the structure of the circuit board in the coordinate system XYZ. For the description of the coordinate system XYZ, please refer to Figure 3 The corresponding instructions are not elaborated in detail. Figure 7 The circuit board shown has multiple layers of first sub-boards distributed along the target direction Z. For example, the circuit board shown in this embodiment includes seven layers of first sub-boards, namely, the first sub-board 701, the first sub-board 702, the first sub-board 703, the first sub-board 704, the first sub-board 705, the first sub-board 706 and the first sub-board 707. This embodiment can design the number of layers of the first sub-board included in the circuit board based on the performance requirements such as power supply, heat conduction and shielding. Among them, the first sub-board 702, the first sub-board 704 and the first sub-board 706 are CCL, and the first sub-board 701, the first sub-board 703, the first sub-board 705 and the first sub-board 707 are prepreg (PP). It can be understood that among the multiple first sub-boards, among the two adjacent first sub-boards along the target direction Z, one first sub-board is CCL and the other first sub-board is PP. Optionally, the overall thickness of the multi-layer first sub-board along the target direction Z is ≥400μm. The circuit board also includes a multi-layer second sub-board and a third sub-board. For the description of the second sub-board and the third sub-board, please refer to the above embodiments and the details will not be repeated here.

[0131] The second sub-board shown in this embodiment can be in the form of a film material, a sheet material or RCC. For example, if the second sub-board is in the form of a film material or RCC, then the second sub-board specifically includes a first dielectric layer. The CTE of the first dielectric layer in the target plane XY is respectively greater than the CTE of the first sub-board and the CTE of the third sub-board, and the Df of the first dielectric layer is respectively less than the Df of the first sub-board and the Df of the third sub-board. For the description of the CTE, Df and Young's modulus of the first dielectric layer, please refer to the description of the CTE, Df and Young's modulus of the second sub-board shown in the above embodiment, and no further details are given. For example, the Df of the first dielectric layer shown in this example is ≤0.002, the Young's modulus is ≤5GPa, the CTE in the target plane XY is ≤35ppm / ℃, and the thickness is ≤50μm. The first dielectric layer has a first surface and a second surface in opposite positions, and the first surface and the second surface of the first dielectric layer are arranged along the target direction Z. That is, along the target direction Z, the first surface is the upper surface of the first dielectric layer, and the second surface is the lower surface of the first dielectric layer. At least one of the first surface or the second surface is covered with at least one second dielectric layer. For example, the first surface is covered with one, two or any number of second dielectric layers, and / or the second surface is covered with one, two or any number of second dielectric layers. The second dielectric layer is used to improve the bonding force between the second sub-board and the copper foil, or to improve the glue filling performance of the second sub-board, or to improve the indentation resistance of the surface layer of the second sub-board. The thickness of the second dielectric layer shown in this example along the target direction Z is ≤10μm. The dielectric material of the first dielectric layer shown in this example is different from the dielectric material of the second dielectric layer.

[0132] The first dielectric layer and the second dielectric layer shown in this example meet at least one of the following conditions:

[0133] The Df of the second dielectric layer is smaller than the Df of the first dielectric layer, the Young's modulus of the second dielectric layer is larger than the Young's modulus of the first dielectric layer, and the CTE of the second dielectric layer is smaller than the CTE of the first dielectric layer.

[0134] For example Figure 8 As shown, Figure 8The fifth embodiment structure example diagram of the circuit board provided in the present application. Taking the second sub-board as a film material as an example, specifically, the second sub-board includes a first dielectric layer 801 and a second dielectric layer 802 covering the first surface of the first dielectric layer 801. The circuit board may specifically include two second sub-boards 800, and the two second sub-boards 800 are symmetrically distributed with the first sub-board 810 as the center. For the specific description of the first sub-board 810 and the second sub-board 800 included in the circuit board, please refer to the above embodiment, and the specific description will not be repeated. It can be understood that since the second sub-board shown in this example includes a first dielectric layer and a second dielectric layer, then the second sub-board includes multiple layers of dielectric material, and this embodiment does not limit the number of dielectric material layers included in the second sub-board. This embodiment takes the circuit board including two second sub-boards as an example. In other examples, the circuit board may include any integer number of second sub-boards, and the number of second sub-boards included in the circuit board is not limited. The first sub-board, the third sub-board and the fourth sub-board provided in this embodiment may also include a first dielectric layer and a second dielectric layer. For the description of the first dielectric layer and the second dielectric layer, please refer to the description of the first dielectric layer and the second dielectric layer included in the first sub-board, and the details are not repeated here.

[0135] In the above embodiment, taking the circuit board as HDI as an example, the electrical interconnection between different sub-boards of the circuit board is through micro-buried blind vias. Specifically, HDI uses laser to directly drill holes on each sub-board to form conductive through-holes, buried vias and blind vias for realizing electrical interconnection between different sub-boards. Fig. 9 In the embodiment shown, the sub-boards included in the circuit board are electrically interconnected through through holes, wherein: Fig. 9 This is a structural example diagram of the sixth embodiment of the circuit board provided in this application. Fig. 9 The circuit board shown in the embodiment includes 15 layers of sub-boards as an example, that is, the circuit board shown in this embodiment arranges sub-boards 901, 902 to 915 in order from top to bottom according to the target direction Z. The circuit board includes 16 layers of copper foil, and Layer L1, Layer L2 to Layer L16 are arranged in order from top to bottom according to the target direction Z. Among them, Layer L1 is the copper foil covering the surface of sub-board 901, Layer L2 is the copper foil covering the surface of sub-board 902, and so on, and Layer 116 is the copper foil covering the surface of sub-board 915. It should be clear that this embodiment does not limit the number of sub-boards and copper foils included in the circuit board.

[0136] Specifically, the first sub-board included in the circuit board is sub-board 908, sub-board 901 and sub-board 915 are respectively the third sub-board, and sub-board 902, sub-board 903, sub-board 904, sub-board 905, sub-board 906, sub-board 907, sub-board 909, sub-board 910, sub-board 911, sub-board 912, sub-board 913 and sub-board 914 are respectively the second sub-boards. For the description of the first sub-board, the second sub-board and the third sub-board, please refer to the above embodiment, and the specific description is not repeated. The sub-board 901 and the sub-board 915 included in the circuit board shown in this embodiment are located on both sides of the outermost surface. The circuit board includes a plurality of through holes 920, and the through holes 920 pass through the various sub-boards included in the circuit board from one side of the sub-board 901, so that the through holes 920 pass through the entire circuit board along the target direction Z to pass through the sub-board 915. The through holes 920 can realize the electrical connection between the various sub-boards included in the circuit board, and provide electrical connection and mechanical support. This embodiment does not limit the number of through holes included in the circuit board. It can be understood that the CTE of the second sub-board in the target plane XY is the highest among the sub-boards included in the circuit board. The Young's modulus of the second sub-board is the lowest among the sub-boards included in the circuit board. The Df of the second sub-board is the lowest among the sub-boards included in the circuit board.

[0137] The performance of each sub-board included in the circuit board shown in this embodiment is shown in Table 7:

[0138] Table 7

[0139]

[0140]

[0141] Sub-board 908, which serves as the first sub-board, can be used as a power layer or a ground layer. The first sub-board has a high Young's modulus, which can improve the reliability of the circuit board. The low CTE of the first sub-board effectively reduces the overall CTE of the circuit board. It can be understood that the dielectric material of the first sub-board is selected from a material with a small CTE and no loss consideration. For the description of the specific dielectric material, please refer to the description of the dielectric material used to make the first sub-board shown in the above embodiment, and the details will not be repeated. The first sub-board shown in this embodiment has a CTE≤10ppm / ℃ in the target plane XY, a Young's modulus≥10GPa, and a thickness of 100~1600μm. For example, this embodiment takes the thickness of the first sub-board as ≥200μm.

[0142] As sub-board 901 and sub-board 915 of the third sub-board, the third sub-board is the outermost layer of the circuit board. The third sub-board shown in this embodiment can take into account the requirements of low CTE and low loss in the target plane XY. That is, the dielectric material of the third sub-board can be selected from materials with relatively small CTE and taking into account the insertion loss performance. For the description of the dielectric material of the third sub-board, please refer to the above embodiment, and the details will not be repeated. The copper foil Rz≤3μm covered on the third sub-board has a low roughness copper foil, and the thickness is determined based on the minimum line width requirement. The CTE of the third sub-board in the target plane XY is ≤17ppm / ℃, Young's modulus ≥7GPa, Df≤0.004@10GHz, and thickness ≤100μm.

[0143] Sub-board 902, sub-board 903, sub-board 904, sub-board 905, sub-board 906, sub-board 907, sub-board 909, sub-board 910, sub-board 911, sub-board 912, sub-board 913 and sub-board 914 as the second sub-board. The plurality of second sub-boards included in the circuit board can adopt two different structural forms. The second sub-boards of the two structural forms can be arranged at intervals, for example, sub-board 902, sub-board 904, sub-board 906, sub-board 910, sub-board 912, and sub-board 914 have a first structural form. Sub-board 903, sub-board 905, sub-board 907, sub-board 909, sub-board 911 and sub-board 913 have a second structural form. Among them, the first structural form refers to a semi-cured adhesive film, and the second structural form refers to a fully cured film. The second sub-plate is a dielectric material without continuous coding fiber cloth reinforcement to reduce Young's modulus. For the description of the dielectric material, please refer to the dielectric material used to make the second sub-plate shown in the above embodiment. For example, the second sub-plate has Df≤0.002, Young's modulus≤5GPa, CTE≤35ppm / ℃, and Dk≤3.5 in the target plane XY; preferably, its thickness is ≤50μm.

[0144] The performance of the circuit board shown in this embodiment is shown in Table 8:

[0145] Table 8

[0146]

[0147]

[0148] The circuit board shown in Table 8 includes 3 examples. In Example 1, the first sub-board of the circuit board has a CTE of 8, a Young's modulus of 30 GPa, and a thickness of 400 um in the target plane XY. The third sub-board has a CTE of 15, a Young's modulus of 20, and a thickness of 100 um in the target plane XY. The second sub-board has a CTE of 35, a Young's modulus of 2, and a thickness of 50 um in the target plane XY. In Example 1, the CTE of the entire circuit board in the target plane XY is 20.7 and the Young's modulus is 14.5. In Example 2, the first sub-board of the circuit board has a CTE of 8, a Young's modulus of 30, and a thickness of 400 um in the target plane XY. The third sub-board has a CTE of 15, a Young's modulus of 20, and a thickness of 100 um in the target plane XY. The second sub-board has a CTE of 30, a Young's modulus of 2, and a thickness of 50 um in the target plane XY. In Example 2, the CTE of the entire circuit board in the target plane XY is 20.7 and the Young's modulus is 14.3. In Example 3, the CTE of the first sub-board of the circuit board in the target plane XY is 8, the Young's modulus is 30, and the thickness is 400um. The CTE of the third sub-board in the target plane XY is 15, the Young's modulus is 20, and the thickness is 100um. The CTE of the second sub-board in the target plane XY is 25, the Young's modulus is 2, and the thickness is 50um. In Example 3, the CTE of the entire circuit board in the target plane XY is 20.7 and the Young's modulus is 14.1.

[0149] The performance of the existing circuit board is shown in Table 9:

[0150] Table 9

[0151]

[0152] For a description of existing circuit board structures, see Figure 2 The corresponding description will not be elaborated in detail. It can be understood that the first sub-board of the existing circuit board has a CTE of 8, a Young's modulus of 30, and a thickness of 200um in the target plane XY. The second sub-board has a CTE of 15, a Young's modulus of 20, and a thickness of 100 in the target plane XY. The CTE of the existing circuit board as a whole in the target plane XY is 26.2, and the Young's modulus is 14.9. Comparing Tables 8 and 9, it can be seen that the structure of the circuit board shown in this embodiment can effectively reduce the CTE of the circuit board as a whole in the target plane XY, and can ensure that the Young's modulus of the circuit board is close to that of the existing circuit board. It can be understood that the circuit board shown in this embodiment can take into account the requirements of low CTE and high Young's modulus of the circuit board.

[0153] The present application also provides a circuit board, which can be a PCB or a substrate. For details, see Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 or Fig. 9 The above is shown in any embodiment and no further details are given.

[0154] The embodiment of the present application also provides a communication system, wherein the communication system includes at least two connected communication devices. For a detailed description of the communication devices, see Figure 1 , Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 or Fig. 9 The above is shown in any embodiment and no further details are given.

[0155] The present application also provides a chip. For a description of the chip, see Figure 1 The corresponding instructions are not elaborated in detail.

[0156] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A circuit board, It is characterized in that Along a direction perpendicular to the surface of the circuit board, the circuit board includes M sub-boards arranged in sequence, where M is an arbitrary integer not less than 2, and the M sub-boards include a first sub-board and a second sub-board, wherein the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the second sub-board, and the dielectric loss factor of the second sub-board is smaller than the dielectric loss factor of the first sub-board.

2. The circuit board according to claim 1, It is characterized in that The Young's modulus of the second sub-plate is smaller than that of the first sub-plate.

3. The circuit board according to claim 1 or 2, It is characterized in that The M sub-boards include a plurality of the second sub-boards, and the plurality of the second sub-boards are symmetrically distributed with the first sub-board as the center.

4. The circuit board according to any one of claims 1 to 3, It is characterized in that The M sub-boards further include a third sub-board, and the second sub-board is located between the first sub-board and the second sub-board; The thermal expansion coefficient of the third sub-board is smaller than the thermal expansion coefficient of the second sub-board, and the dielectric loss factor of the second sub-board is smaller than the dielectric loss factor of the third sub-board.

5. The circuit board according to claim 4, It is characterized in that The Young's modulus of the second sub-plate is smaller than the Young's modulus of the third sub-plate.

6. The circuit board according to claim 4 or 5, It is characterized in that The M sub-boards include a plurality of the third sub-boards, and the plurality of the third sub-boards are symmetrically distributed with the first sub-board as the center.

7. The circuit board according to any one of claims 4 to 6, It is characterized in that In a target plane, the thermal expansion coefficient of the first sub-board is smaller than that of the second sub-board, and the thermal expansion coefficient of the third sub-board is smaller than that of the second sub-board, and the target plane is parallel to the surface of the circuit board.

8. The circuit board according to any one of claims 4 to 7, It is characterized in that The thickness of the first sub-board along the target direction is greater than the thickness of the second sub-board along the target direction, and the thickness of the first sub-board along the target direction is greater than the thickness of the third sub-board along the target direction, wherein the target direction is a direction perpendicular to the surface of the circuit board.

9. The circuit board according to any one of claims 4 to 8, It is characterized in that The M sub-boards include a fourth sub-board, and along a direction perpendicular to the surface of the circuit board, the fourth sub-board is located between the first sub-board and the second sub-board; The thermal expansion coefficient of the fourth sub-board is smaller than the thermal expansion coefficient of the second sub-board, and the dielectric loss factor of the second sub-board is smaller than the dielectric loss factor of the fourth sub-board.

10. The circuit board according to claim 9, It is characterized in that The Young's modulus of the second sub-plate is smaller than the Young's modulus of the fourth sub-plate.

11. The circuit board according to any one of claims 1 to 10, It is characterized in that The second sub-board includes a first dielectric layer, the thermal expansion coefficient of the first sub-board is smaller than the thermal expansion coefficient of the first dielectric layer, and the dielectric loss factor of the first dielectric layer is smaller than the dielectric loss factor of the first sub-board; The second sub-board also includes a second dielectric layer. Along a direction perpendicular to the surface of the circuit board, the first dielectric layer includes a first surface and a second surface that are located opposite to each other, the second dielectric layer is located on the first surface, and / or the second dielectric layer is located on the second surface, and the dielectric material of the second dielectric layer is different from the dielectric material of the first dielectric layer.

12. The circuit board according to claim 11, It is characterized in that The first dielectric layer and the second dielectric layer satisfy at least one of the following conditions: The dielectric loss factor of the second dielectric layer is smaller than the dielectric loss factor of the first dielectric layer, the Young's modulus of the second dielectric layer is larger than the Young's modulus of the first dielectric layer, and the thermal expansion coefficient of the second dielectric layer is smaller than the thermal expansion coefficient of the first dielectric layer.

13. A communication device, It is characterized in that The invention comprises a circuit board and an electronic device connected to the circuit board, wherein the circuit board is as claimed in any one of claims 1 to 12.

14. A chip, It is characterized in that The chip comprises a packaging shell, wherein the packaging shell comprises a circuit board and a bare chip connected to the circuit board, and the circuit board is as described in any one of claims 1 to 12.

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