Printed circuit board

Abstract

The invention provides a printed circuit board. The printed circuit board includes: an inorganic substrate; a through via hole passing through the inorganic substrate; a first insulating layer covering at least a portion of a side surface of the inorganic substrate; a second insulating layer disposed on an upper surface of each of the inorganic substrate and the first insulating layer; a third insulating layer disposed on a lower surface of each of the inorganic substrate and the first insulating layer; a first wiring layer disposed on an upper surface of the second insulating layer; and a second wiring layer disposed on a lower surface of the third insulating layer. The inorganic substrate includes silicon or ceramic. In a cross section of the printed circuit board, the inorganic substrate includes an upper end and a lower end having different widths.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0164535 filed on November 23, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Recently, as the market has changed from mobile devices to high-capacity servers, the amount of data has increased rapidly, and the development of servers, networks and storage devices has also been more rapid. Therefore, new high-layer structure boards have been expanding. Therefore, fan-out multi-chip modules (FOMCM), fan-out embedded bridges (FOEB), embedded multi-die interconnect bridges (EMIB), etc. have been developed. In order to cope with the high-capacity server market, many companies are trying to develop circuit boards with 2.xD as the ultimate goal. However, the printed circuit board according to the related art can basically have a high-layer structure, and the microcircuit can be applied to the printed circuit board. As a result, there are limitations in solving the problems in terms of actual yield and cost. Summary of the invention

[0004] One aspect of the present disclosure provides a printed circuit board including a high-density microcircuit that can be formed with a high yield and low cost.

[0005] Another aspect of the present disclosure provides a printed circuit board having excellent warpage control characteristics.

[0006] According to one aspect of the present disclosure, a printed circuit board is provided. First, in an inorganic substrate including silicon or ceramic, the inorganic substrate having through holes can be cut to form a plurality of cores having tapered side surfaces. Subsequently, the plurality of cores can be respectively arranged in a plurality of through-holes of a frame. After each of the plurality of through-holes is filled with a first insulating layer, the frame can be cut to form a plurality of unit boards. Subsequently, an insulating layer and a wiring layer can be formed on the unit board to manufacture a multilayer printed circuit board.

[0007] For example, the printed circuit board according to one aspect of the present disclosure may include: an inorganic substrate; a through hole passing through the inorganic substrate; a first insulating layer covering at least a portion of a side surface of the inorganic substrate; a second insulating layer disposed on an upper surface of each of the inorganic substrate and the first insulating layer; a third insulating layer disposed on a lower surface of each of the inorganic substrate and the first insulating layer; a first wiring layer disposed on an upper surface of the second insulating layer; and a second wiring layer disposed on a lower surface of the third insulating layer. The inorganic substrate may include silicon or ceramic. In a cross section of the printed circuit board, the inorganic substrate may include an upper end and a lower end having different widths.

[0008] A printed circuit board according to example embodiments of the present disclosure may include a high-density microcircuit that can be manufactured with a high yield and low cost.

[0009] A printed circuit board according to example embodiments of the present disclosure may have excellent warpage control characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a schematic block diagram of an example of an electronic device system; Figure 2 is a schematic perspective view of an example of an electronic device; Figure 3 is a schematic cross-sectional view of an example of a printed circuit board; FIG. 4A to FIG. 4D Is manufacturing Figure 3 A schematic cross-sectional view of an example process of a method for printing a printed circuit board in FIG. Figure 5A and Figure 5B is a schematic perspective view of an example process in which a plurality of cores arranged on a unit basis are arranged in a frame having a plurality of through-parts; Figure 6 and Figure 7 They are Figure 3 A schematic cross-sectional view of a variation of a printed circuit board in FIG. Figure 8 is a schematic cross-sectional view of another example of a printed circuit board; Fig. 9 and Fig.10 They are Figure 8 A schematic cross-sectional view of a variation of a printed circuit board in FIG. Fig.11 is a schematic cross-sectional view of another example of a printed circuit board; Fig.12 and Fig.13 They are Fig.11 A schematic cross-sectional view of a variation of a printed circuit board in FIG. Fig.14 is a schematic cross-sectional view of another example of a printed circuit board; Fig.15 and Fig.16 They are Fig.14 A schematic cross-sectional view of a variation of a printed circuit board in FIG. Fig.17 is a schematic cross-sectional view of another example of a printed circuit board; Fig.18 and Fig.19 They are Fig.17 A schematic cross-sectional view of a variation of a printed circuit board in FIG. Fig. 20 is a schematic cross-sectional view of another example of a printed circuit board; and Fig.21 and Fig. 22 They are Fig. 20 Schematic cross-sectional view of a variant of a printed circuit board. DETAILED DESCRIPTION

[0011] Hereinafter, exemplary embodiments of the present disclosure are described with reference to the accompanying drawings. For clearer description, the shapes and sizes of elements in the drawings may be exaggerated or reduced.

[0012] Electronic Devices Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0013] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010. Chip-related components 1020, network-related components 1030, other components 1040, etc. may be physically and / or electrically connected to the mainboard 1010. Such electronic components may be connected to other electronic components to be described below via various signal lines 1090.

[0014] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, etc.); application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips (such as analog-to-digital converters, application-specific integrated circuits (ASICs), etc.). However, the chip-related components 1020 are not limited thereto and may include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips.

[0015] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth ® , the third generation mobile communication technology (3G) protocol, the fourth generation mobile communication technology (4G) protocol and the fifth generation mobile communication technology (5G) protocol and any other wireless protocol and wired protocol specified after the above protocols. However, the network-related component 1030 is not limited thereto, and may also include components compatible with various other wireless standards or protocols or wired standards or protocols or components operating according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the above-mentioned chip-related component 1020.

[0016] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0017] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or are not physically and / or electrically connected to the mainboard 1010. The other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, and the like. However, the other electronic components are not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. In addition, depending on the type of the electronic device 1000, etc., the electronic device 1000 may also include other electronic components for various purposes.

[0018] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data.

[0019] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0020] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. A portion of the component 1120 may be the above-mentioned chip-related component, for example, a component package 1121, but the present disclosure is not limited thereto. The component package 1121 may be in the form of a printed circuit board, on the upper surface of which electronic components (including active components and / or passive components) are mounted. The electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0021] Printed Circuit Board Figure 3 is a schematic cross-sectional view of an example of a printed circuit board.

[0022] Reference Figure 3According to some example embodiments, a printed circuit board 100A may include: a core layer 111 including an inorganic substrate 111a; a first insulating layer 112 covering at least a portion of a side surface of the inorganic substrate 111a; a through via 131 passing through the core layer 111; a second insulating layer 113 disposed on an upper surface of each of the inorganic substrate 111a and the first insulating layer 112; a third insulating layer 114 disposed on a lower surface of each of the inorganic substrate 111a and the first insulating layer 112; a first wiring layer 121 disposed on an upper surface of the second insulating layer 113; a second wiring layer 122 disposed on a lower surface of the third insulating layer 114; a first connection via 132 passing through the second insulating layer 113 to connect the through via 131 and the first wiring layer 121 to each other; and a second connection via 133 passing through the third insulating layer 114 to connect the through via 131 and the second wiring layer 122 to each other. If necessary, the printed circuit board 100A may further include a capacitor 140 including a plurality of conductive trenches 141 each passing through a portion of the core layer 111. For example, each conductive trench 141 passes through a portion of the inorganic substrate 111a from the upper surface or the lower surface of the inorganic substrate 111a.

[0023] As described above, the core layer 111 may include an inorganic substrate 111a. In this case, the inorganic substrate 111a may include silicon or ceramic. Therefore, the inorganic substrate 111a may basically have excellent flatness, which may be more conducive to forming a high-density circuit with a fine pitch. In addition, compared with a general organic substrate, the inorganic substrate 111a having higher rigidity may be more conducive to warpage control. In addition, the core layer 111 may be based on a unit arrangement in which a through hole 131 is formed, and as Figure 3As shown, in the cross-section of the printed circuit board 100A, the core layer 111 (e.g., the inorganic substrate 111a) may include upper and lower ends with different widths. Additionally, for example, in the above cross-section of the printed circuit board 100A, the width of the upper end of the inorganic substrate 111a may be smaller than the width of its lower end. The side surface of the inorganic substrate 111a may be inclined. For example, the side surface of the inorganic substrate 111a may substantially have a tapered shape in the direction from the lower end to the upper end of the inorganic substrate 111a. Moreover, the side surface of the inorganic substrate 111a may be covered by the first insulating layer 112 and may not be exposed to the outside. More specifically, the side surface of the inorganic substrate 111a may be in contact with the first insulating layer 112. In addition, the second insulating layer 113 and the third insulating layer 114 may be laminated on the core layer 111 (e.g., the inorganic substrate 111a) and the first insulating layer 112, thereby further increasing the flatness. Thus, it may be more beneficial for forming high-density microcircuits with fine pitches. For example, it may be easier to provide a network board or a high-performance packaging board using the printed circuit board 100A. For example, the printed circuit board 100A can be used as a 2.xD flip chip board (FCB) (an interconnection package structure between 2D and 3D, such as 2.1D, 2.3D, and 2.5D).

[0024] The core layer 111 may further include inorganic insulating films 111b-1 and 111b-2 that cover at least a part of each of the upper and lower surfaces of the inorganic substrate 111a. For example, the inorganic substrate 111a may be a silicon board, and the inorganic insulating films 111b-1 and 111b-2 may include an oxide film 111b-1 and / or a nitride film 111b-2. As a non-limiting example, the core layer 111 may include a silicon board as the inorganic substrate 111a, and may further include: an oxide film 111b-1, disposed on the inorganic substrate 111a, the oxide film 111b-1 including SiO 2 etc.; and a nitride film 111b-2, disposed on the oxide film 111b-1, the nitride film 111b-2 including SiN etc. The inorganic substrate 111a may have a through-hole H in which a via hole 131 is provided, and the inorganic insulating films 111b-1 and 111b-2 may extend into the space between the inorganic substrate 111a and the via hole 131 to cover at least a part of the wall surface of the through-hole H. As described above, the inorganic insulating films 111b-1 and 111b-2 may be formed on the inorganic substrate 111a to protect the surface of the inorganic substrate 111a, provide an insulating region, and prevent short circuits in the via hole 131. Moreover, the nitride film 111b-2 may be spaced apart from the outer surface of the inorganic substrate 111a.

[0025] The through via 131 may include: a first metal layer 131a, which is disposed on the inorganic insulating films 111b-1 and 111b-2 in the through hole H; and a second metal layer 131b, which fills at least a portion of the through hole H on the first metal layer 131a. The first metal layer 131a may be a seed layer, and may be formed, for example, using electroless plating or sputtering. The first metal layer 131a may include titanium (Ti), copper (Cu), etc., but the present disclosure is not limited thereto. The second metal layer 131b may include a plating layer, and may be formed, for example, using electrolytic plating. The second metal layer 131b may include copper (Cu), but the present disclosure is not limited thereto. In the above-mentioned cross section of the printed circuit board 100A, the width of the second metal layer 131b may be greater than the width of the first metal layer 131a. The through via 131 may be, for example, a through silicon via (TSV), etc., and may be formed in the core layer 111 to provide an electrical connection path between the upper side and the lower side of the core layer 111. In the above section, the through hole 131 may have a cylindrical shape. For example, the side surface of the through hole 131 may be substantially perpendicular to the upper and lower surfaces of the through hole 131, but the present disclosure is not limited thereto, and the through hole 131 may have an hourglass shape as needed.

[0026] The first insulating layer 112, the second insulating layer 113, and the third insulating layer 114 may each include an organic insulating material. For example, the first insulating layer 112 may include an underfill resin (UR), an epoxy molding compound (EMC), a thermal interface material (TIM), etc., depending on the desired properties. In addition, the second insulating layer 113 and the third insulating layer 114 may include a prepreg (PPG) for wiring formation, an Ajinomoto deposited film (ABF), etc. Therefore, the first insulating layer 112 may form an interlayer boundary with each of the second insulating layer 113 and the third insulating layer 114. Before forming the second insulating layer 113 and the third insulating layer 114, the first insulating layer 112 may be planarized together with the core layer 111, so that the upper surface and the lower surface of the first insulating layer 112 may be substantially coplanar with the upper surface and the lower surface of the core layer 111, respectively. As required, the first insulating layer 112 may include the same organic insulating material as the organic insulating material included in the second insulating layer 113 and / or the third insulating layer 114. In this case, the first insulating layer 112 may be integrated with the second insulating layer 113 and / or the third insulating layer 114, and thus may not form an interlayer boundary with the second insulating layer 113 and / or the third insulating layer 114. For example, when the second insulating layer 113 and / or the third insulating layer 114 are formed, the first insulating layer 112 may also be formed.

[0027] The first connection via 132 and the second connection via 133 may be in direct contact with the through-hole 131. For example, the first connection via 132 may be in direct contact with the upper surface of the through-hole 131. In addition, the second connection via 133 may be in direct contact with the lower surface of the through-hole 131. For example, it may be difficult to ensure the adhesion of the wiring layer including the pad pattern and the like to the upper and lower surfaces of the core layer 111, so that the wiring layer including the pad pattern and the like may not be formed. The first connection via 132 and the second connection via 133 may have a tapered shape that tapers in opposite directions to each other in the vertical direction. For example, in the above-mentioned cross section, the width of the upper end of the first connection via 132 may be larger than the width of the lower end of the first connection via 132, and in the above-mentioned cross section, the width of the lower end of the second connection via 133 may be larger than the width of the upper end of the second connection via 133, but the present disclosure is not limited thereto.

[0028] A plurality of conductive grooves 141 may pass through the core layer 111, for example, may pass through a portion of the core layer 111 from the upper surface of the inorganic substrate 111a. Alternatively, a plurality of conductive grooves 141 may pass through the core layer 111, for example, may pass through a portion of the core layer 111 from the lower surface of the inorganic substrate 111a. In the above cross section, at least a portion of the plurality of conductive grooves 141 may overlap each other in a direction perpendicular to the vertical extension direction of the grooves. As a result, the capacitor 140 may be formed in the core layer 111. For example, the capacitor 140 may include a deep trench capacitor (DTC). As described above, the capacitor 140 may be designed in the core layer 111 as needed. Therefore, a capacitor may not be additionally installed on the core layer 111, thereby facilitating the miniaturization of the printed circuit board 100A.

[0029] Hereinafter, components of a printed circuit board 100A according to an example will be described in more detail with reference to the accompanying drawings.

[0030] The core layer 111 may include an inorganic substrate 111a and inorganic insulating films 111b-1 and 111b-2. The inorganic substrate 111a may include an inorganic insulating material. The inorganic insulating material may be, for example, silicon or ceramic. For example, the inorganic substrate 111a may be a silicon plate or a ceramic plate. The silicon plate may include pure silicon (Si). The ceramic plate may include, for example, aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon carbide (SiC), silicon nitride (Si 3 N 4 ), etc., but the present disclosure is not limited thereto. The inorganic insulating films 111b-1 and 111b-2 may include SiO 2 The oxide film 111 b - 1 includes SiN, etc., and the nitride film 111 b - 2 includes SiN, etc., but the present disclosure is not limited thereto.

[0031] The first insulating layer 112 may include an organic insulating material. The organic insulating material may be a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. As required, an inorganic filler and / or an organic filler may also be included. For example, depending on the desired properties, the first insulating layer 112 may include UR, EMC, TIM, etc. However, the present disclosure is not limited thereto, and as required, the first insulating layer 112 may include the same organic insulating material as the organic insulating material of the second insulating layer 113 and / or the third insulating layer 114 to be described below.

[0032] The second insulating layer 113 and the third insulating layer 114 may include an organic insulating material. The organic insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material including an inorganic filler, an organic filler and / or glass fiber (for example, glass fabric using glass cloth as an example) and a resin. For example, the organic insulating material may be a non-photosensitive insulating material such as ABF, PPG, etc., but the present disclosure is not limited thereto, and other polymer materials may be used. In addition, the organic insulating material may be a photosensitive insulating material such as a photosensitive dielectric (PID). In addition, the organic insulating material may include an adhesive sheet such as a bonding sheet (BS).

[0033] The first wiring layer 121 and the second wiring layer 122 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof, and preferably, may include copper (Cu), but the present disclosure is not limited thereto. The first wiring layer 121 and the second wiring layer 122 may perform various functions according to their design. For example, the first wiring layer 121 and the second wiring layer 122 may include a signal pattern, a power pattern, a ground pattern, and the like. Each of the above patterns may have various forms such as a line, a surface, a pad, and the like. The first wiring layer 121 and the second wiring layer 122 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, the first wiring layer 121 and the second wiring layer 122 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, the first wiring layer 121 and the second wiring layer 122 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). A sputtering layer may be included instead of the electroless plating layer (e.g., a chemical copper plating layer), and both the sputtering layer and the electroless plating layer (e.g., a chemical copper plating layer) may be included as needed.

[0034] The through via 131 may include a metal. The metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof, and preferably, may include copper (Cu), but the present disclosure is not limited thereto. The through via 131 may pass through a space between an upper surface and a lower surface of the core layer 111. The upper surface and the lower surface of the through via 131 may be substantially coplanar with the upper surface and the lower surface of the core layer 111, respectively. The through via 131 may perform various functions according to its design. For example, the through via 131 may include a ground via, a power via, a signal via, and the like. On a plane (perpendicular to the above-mentioned cross section), the through via 131 may have an approximately circular shape or an elliptical shape, but the present disclosure is not limited thereto. For example, in terms of ensuring close contact by increasing the specific surface area, the through hole 131 may have a shape similar to a flower on the above plane, for example, a flower may have a plurality of petals arranged around a pistil in a radially symmetrical or bilaterally symmetrical manner. Specifically, when viewed from above, the through hole 131 may have a trumpet shape or a lip shape, but is not limited thereto, and the through hole 131 may have other flower shapes.

[0035] The first connection via 132 and the second connection via 133 may include a metal. The metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof, and preferably, may include copper (Cu), but the present disclosure is not limited thereto. The first connection via 132 and the second connection via 133 may include a filling via that fills the via hole or a conformal via disposed along the wall surface of the via hole. The first connection via 132 and the second connection via 133 may perform various functions according to their design. For example, the first connection via 132 and the second connection via 133 may include a ground via, a power via, a signal via, and the like. The first connection via 132 and the second connection via 133 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). A sputtered layer may be included instead of an electroless plated layer (eg, a chemical copper plated layer), and both a sputtered layer and an electroless plated layer (eg, a chemical copper plated layer) may be included as necessary.

[0036] The capacitor 140 may include a deep trench capacitor (DTC). For example, the capacitor 140 may include a plurality of conductive trenches 141. Each of the plurality of conductive trenches 141 may include a metal. The metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof. The capacitor 140 may be electrically connected to at least a portion of the first wiring layer 121 and / or the second wiring layer 122 through a connection via or the like.

[0037] FIG. 4A to FIG. 4D Is manufacturing Figure 3 Schematic cross-sectional view of an example process of a method for printing a circuit board in FIG.

[0038] Reference Figure 4A , a core layer 111 in which one or more through vias 131 are formed may be prepared. For example, an inorganic substrate 111a including silicon or ceramics may be prepared. Subsequently, one or more through holes H may be formed in the inorganic substrate 111a using various methods such as laser processing, mechanical processing, chemical processing, etc. Subsequently, an inorganic insulating film 111b-1 and 111b-2 including an oxide film 111b-1 and / or a nitride film 111b-2 covering the surface of the inorganic substrate 111a and the wall surface of the through hole H may be formed using a deposition process, a coating process, etc. Subsequently, a first metal layer 131a may be formed on the wall surface of the through hole H using electroless plating or sputtering. Subsequently, a second metal layer 131b filling at least a portion of the through hole H may be formed on the first metal layer 131a using electrolytic plating, etc. In addition, a capacitor 140 including a plurality of conductive trenches 141 may be formed in the inorganic substrate 111a. Here, as Figure 4A As shown in , a plurality of conductive grooves 141 may pass through the inorganic insulating films 111b-1 and 111b-2. The seed layer and / or the plating layer on the upper and lower surfaces of the core layer 111 may be removed by etching or the like. Subsequently, the core layer 111 in which the through-holes 131 are formed may be cut on a unit basis. As a result, a plurality of core layers 111 having inclined side surfaces may be formed on a unit basis. For example, a plurality of core portions may be formed on a unit basis.

[0039] Reference Figure 4B , a core layer 111 having a through hole 131 formed therein and having an inclined side surface may be provided in the through portion 210H of the frame 210. For example, the tape 220 may be attached to the lower side of the frame 210 to block the lower side of the through portion 210H, and then the core layer 111 having the through hole 131 formed therein may be attached to the portion of the tape 220 exposed from the through portion 210H. The frame 210 may include various materials such as metal, organic insulating material, and the like. For example, the frame 210 may have a multilayer board structure formed using a copper clad laminate (CCL) or the like, but the present disclosure is not limited thereto. The frame 210 may be in the form of a fixture. The tape 220 may be a heat-resistant tape such as polyimide (PI), but the present disclosure is not limited thereto.

[0040] Reference Figure 4C, the remaining space of the through-hole 210H can be filled with the first insulating layer 112. As a result, the inclined side surfaces of the core layer 111 can be covered with the first insulating layer 112. In this case, a planarization process can be performed as needed. A bottom filling process, an encapsulation process, or a lamination process can be used to form the first insulating layer 112.

[0041] Referring to Figure 4D , the tape 220 can be removed. In addition, a second insulating layer 113 and a third insulating layer 114 can be formed on the upper and lower sides of each of the core layer 111 and the first insulating layer 112, respectively, using a lamination process or the like. Subsequently, via holes can be processed in the second insulating layer 113 and the third insulating layer 114, and then a plating process can be performed to form the first wiring layer 121 and the second wiring layer 122, as well as the first connection via 132 and the second connection via 133. Subsequently, the frame 210 can be removed. A dicing process can be used to remove the frame 210.

[0042] The printed circuit board 100A according to some example embodiments of the present disclosure can be manufactured using a series of processes. Other descriptions can be the same as those of the printed circuit board 100A according to the examples, and their repeated descriptions will be omitted.

[0043] Figure 5A and Figure 5B are schematic perspective views of an example process in which a plurality of core portions provided on a unit basis are provided in a frame having a plurality of through-holes.

[0044] Referring to Figure 5A , the frame 210 can have a plurality of through-holes 210H. The above Figure 4B processes can be used to dispose the core layer 111, e.g., a core portion, cut on a unit basis in the through-holes 210H.

[0045] Referring to Figure 5B , the core layer 111, e.g., a core portion, provided on a unit basis can be disposed in substantially the same form in the plurality of through-holes 210H. Thereafter, the above Figure 4C and Figure 4D processes can be used to manufacture a plurality of unit boards in the frame 210, and a dicing process can be used to obtain a plurality of printed circuit boards 100A.

[0046] The printed circuit board 100A according to some example embodiments of the present disclosure can be manufactured using a series of processes. Other descriptions can be the same as those of the printed circuit board 100A according to the examples and the method of manufacturing the printed circuit board 100A, and their repeated descriptions will be omitted.

[0047] Figure 6 and Figure 7 are respectively Figure 3 schematic cross-sectional views of variants of the printed circuit board in

[0048] Reference Figure 6 Compared with the printed circuit board 100A shown above, the printed circuit board 100B according to the variation may further include: one or more first stacked insulating layers 151, arranged on the upper surface of the second insulating layer 113; one or more first stacked wiring layers 152, arranged on the one or more first stacked insulating layers 151 and / or arranged in the one or more first stacked insulating layers 151; one or more first stacked via layers 153, passing through at least one of the one or more first stacked insulating layers 151; one or more second stacked insulating layers 161, arranged on the lower surface of the third insulating layer 114; one or more second stacked wiring layers 162, arranged on the one or more second stacked insulating layers 161 and / or arranged in the one or more second stacked The first resist layer 171 is provided on the upper surface of the uppermost first stacked insulating layer 151 among the one or more first stacked insulating layers 151, and the first resist layer 171 covers at least a portion of the uppermost first stacked wiring layer 152 among the one or more first stacked wiring layers 152; and the second resist layer 172 is provided on the lower surface of the lowermost second stacked insulating layer 161 among the one or more second stacked insulating layers 161, and the second resist layer 172 covers at least a portion of the lowermost second stacked wiring layer 162 among the one or more second stacked wiring layers 162. The first resist layer 171 may have a plurality of first openings h1 that expose at least a portion of the uppermost first stacked wiring layer 152. The second resist layer 172 may have a plurality of second openings h2 that expose at least a portion of the lowermost second stacked wiring layer 162. As described above, the printed circuit board 100B according to the modification may include the printed circuit board 100A according to the example as a core board, and may be a multilayer board further including a buildup structure on the upper and lower sides of the core board, respectively. For example, the printed circuit board 100B may be a multilayer board having a substantially symmetrical structure.

[0049] Reference Figure 7Compared with the printed circuit board 100A shown above, the printed circuit board 100C according to another modification may further include: one or more first buildup insulating layers 151 disposed on the upper surface of the second insulating layer 113; one or more first buildup wiring layers 152 disposed on and / or in the one or more first buildup insulating layers 151; one or more first buildup via layers 153 passing through at least one of the one or more first buildup insulating layers 151; a first resist layer 171 disposed on the upper surface of the uppermost first buildup insulating layer 151 among the one or more first buildup insulating layers 151, the first resist layer 171 covering at least a portion of the uppermost first buildup wiring layer 152 among the one or more first buildup wiring layers 152; and a second resist layer 172 disposed on the lower surface of the third insulating layer 114, the second resist layer 172 covering at least a portion of the second wiring layer 122. The first resist layer 171 may have a plurality of first openings h1 exposing at least a portion of the uppermost first buildup wiring layer 152. The second resist layer 172 may have a plurality of second openings h2 that expose at least a portion of the second wiring layer 122. As described above, a printed circuit board 100C according to another modification may include the printed circuit board 100A according to the example as a core board, and may be a multilayer board including a build-up structure on the upper side of the core board. For example, the printed circuit board 100C may be a multilayer board having an asymmetric structure.

[0050] Hereinafter, components of printed circuit boards 100B and 100C according to modifications will be described in more detail with reference to the accompanying drawings.

[0051] One or more first stacked insulating layers 151 and one or more second stacked insulating layers 161 may include an insulating material. The insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material including an inorganic filler, an organic filler and / or glass fiber (for example, glass fabric with glass cloth as an example) and the above resin. The insulating material may be a non-photosensitive insulating material such as ABF, PPG, etc., or may include a photosensitive insulating material such as PID. In addition, other polymer materials such as polyimide (PI), cycloolefin polymer (COP), etc. may be used. One or more first stacked insulating layers 151 and one or more second stacked insulating layers 161 may include substantially the same insulating material, but the present disclosure is not limited thereto, and one or more first stacked insulating layers 151 and one or more second stacked insulating layers 161 may include different insulating materials.

[0052] One or more first buildup wiring layers 152 and one or more second buildup wiring layers 162 may include a metal. The metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof, and preferably, may include copper (Cu), but the present disclosure is not limited thereto. One or more first buildup wiring layers 152 and one or more second buildup wiring layers 162 may perform various functions according to their design. For example, one or more first buildup wiring layers 152 and one or more second buildup wiring layers 162 may include a signal pattern, a power pattern, a ground pattern, and the like. Each of the above patterns may have various forms such as a line, a surface, a pad, and the like. One or more first buildup wiring layers 152 and one or more second buildup wiring layers 162 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, one or more first buildup wiring layers 152 and one or more second buildup wiring layers 162 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Optionally, one or more first build-up wiring layers 152 and one or more second build-up wiring layers 162 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). A sputtering layer may be included instead of an electroless plating layer (e.g., a chemical copper plating layer), and both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer) may be included as needed.

[0053] The one or more first stacked via layers 153 and the one or more second stacked via layers 163 may include a metal. The metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof, and preferably, may include copper (Cu), but the present disclosure is not limited thereto. The one or more first stacked via layers 153 and the one or more second stacked via layers 163 may include a filled via that fills the via hole or a conformal via disposed along the wall surface of the via hole. The one or more first stacked via layers 153 and the one or more second stacked via layers 163 may perform various functions according to their design. For example, the one or more first stacked via layers 153 and the one or more second stacked via layers 163 may include a ground via, a power via, a signal via, and the like. For example, in a cross section of the printed circuit board 100B, each of the one or more first stacked via layers 153 may have a shape that tapers in a direction opposite to the taper direction of each of the one or more second stacked via layers 163. One or more first stacked via layers 153 and one or more second stacked via layers 163 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). A sputtering layer may be included instead of an electroless plating layer (e.g., a chemical copper plating layer), and both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer) may be included as needed.

[0054] The first resist layer 171 and the second resist layer 172 may include a liquid solder resist or a film solder resist, but are not limited thereto, and other types of insulating materials such as ABF may also be used. As required, a surface treatment layer may be formed on the portion of the pattern exposed by the plurality of first openings h1 and the plurality of second openings h2. The surface treatment layer may be formed using electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) or electroless tin plating, electroless silver plating, electroless nickel plating / alternative gold plating, direct immersion gold (DIG) plating, hot air leveling (HASL), etc., but the present disclosure is not limited thereto. Optionally, as required, a metal bump may be formed on the portion of the pattern exposed by the plurality of first openings h1 and the plurality of second openings h2. The metal bump may include an under-bump metallization (UBM), but the present disclosure is not limited thereto.

[0055] The other descriptions may be the same as those of the printed circuit board 100A according to the example, and a repeated description thereof will be omitted.

[0056] Figure 8 is a schematic cross-sectional view of another example of a printed circuit board.

[0057] Fig. 9 and Fig.10 They are Figure 8 Schematic cross-sectional view of a variant of a printed circuit board.

[0058] Reference Figures 8 to 10 , respectively, compared to the printed circuit boards 100A, 100B, and 100C shown above, a printed circuit board 100D according to another example and printed circuit boards 100E and 100F according to variations thereof may further include: a third wiring layer 123 disposed on the upper surface of the inorganic substrate 111a and connected to the through-via 131, the third wiring layer 123 having at least a portion buried in the second insulating layer 113; and a fourth wiring layer 124 disposed on the lower surface of the inorganic substrate 111a and connected to the through-via 131, the fourth wiring layer 124 having at least a portion buried in the third insulating layer 114. The first connection via 132 may pass through the second insulating layer 113 to connect the first wiring layer 121 and the third wiring layer 123 to each other. The second connection via 133 may pass through the third insulating layer 114 to connect the second wiring layer 122 and the fourth wiring layer 124 to each other. As described above, the printed circuit board 100D according to another example and the printed circuit boards 100E and 100F according to variations thereof may further include a third wiring layer 123 and a fourth wiring layer 124, which are respectively provided on the upper surface and the lower surface of the inorganic substrate 111a, and the third wiring layer 123 and the fourth wiring layer 124 are in direct contact with the through via 131. As a result, the wiring can be designed more variously. For example, the degree of freedom of design can be increased.

[0059] Hereinafter, components of a printed circuit board 100D according to another example and printed circuit boards 100E and 100F according to modifications thereof will be described in more detail with reference to the accompanying drawings.

[0060] The third wiring layer 123 and the fourth wiring layer 124 may include a metal. The metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof, and preferably, may include copper (Cu), but the present disclosure is not limited thereto. The third wiring layer 123 and the fourth wiring layer 124 may perform various functions according to their design. For example, the third wiring layer 123 and the fourth wiring layer 124 may include a signal pattern, a power pattern, a ground pattern, and the like. Each of the above patterns may have various forms such as a line, a surface, a pad, and the like. The third wiring layer 123 and the fourth wiring layer 124 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, the third wiring layer 123 and the fourth wiring layer 124 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, the third wiring layer 123 and the fourth wiring layer 124 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). A sputtering layer may be included instead of the electroless plating layer (e.g., a chemical copper plating layer), and both the sputtering layer and the electroless plating layer (e.g., a chemical copper plating layer) may be included as needed.

[0061] The other descriptions may be the same as those of the printed circuit board 100A according to the example and the printed circuit boards 100B and 100C according to the modifications thereof, and a repeated description thereof will be omitted.

[0062] Fig.11 is a schematic cross-sectional view of another example of a printed circuit board.

[0063] Fig.12 and Fig.13 They are Fig.11 Schematic cross-sectional view of a variant of a printed circuit board.

[0064] Reference Figures 11 to 13, respectively, compared with the printed circuit board 100D according to another example and the printed circuit boards 100E and 100F according to its variations, the printed circuit board 100G according to another example and the printed circuit boards 100H and 100I according to its variations may further include: one or more intermediate insulating layers 181, disposed between the core layer 111 and the second insulating layer 113, for example, disposed between the inorganic substrate 111a and the second insulating layer 113; one or more intermediate wiring layers 182, disposed on the one or more intermediate insulating layers 181 and / or disposed in the one or more intermediate insulating layers 181; and one or more intermediate via layers 183, passing through at least one of the one or more intermediate insulating layers 181. The first insulating layer 112 may further cover at least a portion of the side surface of each of the one or more intermediate insulating layers 181. As described above, in the printed circuit board 100G according to another example and the printed circuit boards 100H and 100I according to its variations, an intermediate buildup structure may be further formed on the core layer 111, for example, an intermediate buildup structure may be further formed on the inorganic substrate 111a. For example, the core unit arranged on a unit basis may further include an intermediate stacking structure and may be arranged in the through-portion of the frame in a state where the intermediate stacking structure is formed. As a result, wiring can be designed more variously. For example, the degree of freedom in design can be increased.

[0065] Hereinafter, components of a printed circuit board 100G according to another example and printed circuit boards 100H and 100I according to modifications thereof will be described in more detail with reference to the accompanying drawings.

[0066] One or more intermediate insulating layers 181 may include an insulating material. The insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material including an inorganic filler, an organic filler and / or glass fiber (for example, glass fabric using glass cloth as an example) and the above resin. The insulating material may be a non-photosensitive insulating material such as ABF, PPG, etc., or may include a photosensitive insulating material such as PID, etc. In addition, other polymer materials such as polyimide (PI), cycloolefin polymer (COP), etc. may be used. One or more intermediate insulating layers 181 may include substantially the same insulating material, but the present disclosure is not limited thereto, and one or more intermediate insulating layers 181 may include different insulating materials.

[0067] One or more intermediate wiring layers 182 may include a metal. The metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof, and preferably, may include copper (Cu), but the present disclosure is not limited thereto. One or more intermediate wiring layers 182 may perform various functions according to their design. For example, one or more intermediate wiring layers 182 may include a signal pattern, a power pattern, a ground pattern, and the like. Each of the above patterns may have various forms such as a line, a surface, a pad, and the like. One or more intermediate wiring layers 182 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, one or more intermediate wiring layers 182 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, one or more intermediate wiring layers 182 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). A sputtered layer may be included instead of an electroless plated layer (eg, a chemical copper plated layer), and both a sputtered layer and an electroless plated layer (eg, a chemical copper plated layer) may be included as necessary.

[0068] One or more intermediate via layers 183 may include a metal. The metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof, and preferably, may include copper (Cu), but the present disclosure is not limited thereto. One or more intermediate via layers 183 may perform various functions according to their design. For example, one or more intermediate via layers 183 may include a signal pattern, a power pattern, a ground pattern, and the like. Each of the above patterns may have various forms such as a line, a surface, a pad, and the like. One or more intermediate via layers 183 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, one or more intermediate via layers 183 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Optionally, one or more intermediate via layers 183 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). A sputtering layer may be included instead of an electroless plating layer (e.g., a chemical copper plating layer), and both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer) may be included as needed.

[0069] Other descriptions may be the same as those of the printed circuit board 100A according to the example and the printed circuit boards 100B and 100C according to the modifications thereof and the printed circuit board 100D according to another example and the printed circuit boards 100E and 100F according to the modifications thereof, and duplicate descriptions thereof will be omitted.

[0070] Fig.14 is a schematic cross-sectional view of another example of a printed circuit board.

[0071] Fig.15 and Fig.16 They are Fig.14 Schematic cross-sectional view of a variant of a printed circuit board.

[0072] Reference Figures 14 to 16 , respectively, compared to the printed circuit board 100A according to the example and the printed circuit boards 100B and 100C according to the variations thereof, the printed circuit board 100J according to another example and the printed circuit boards 100K and 100L according to the variations thereof may further include a frame 210, and the frame 210 covers at least a portion of the side surface of the first insulating layer 112. The second insulating layer 113 may be provided to further extend to the upper side of the frame 210. For example, the second insulating layer 113 may further cover at least a portion of the upper surface of the frame 210. The third insulating layer 114 may be provided to further extend to the lower side of the frame 210. For example, the third insulating layer 114 may further cover at least a portion of the lower surface of the frame 210. The frame 210 may be provided to continuously surround substantially the entire side surface of the first insulating layer 112, and the first insulating layer 112 may be provided to continuously surround substantially the entire side surface of the core layer 111. As described above, in consideration of board properties (e.g., warpage control), the separation process may be performed so that the frame 210 used as a jig in the above process may remain on the outermost side. As a result, the printed circuit board 100J according to another example and the printed circuit boards 100K and 100L according to variations thereof may further include the frame 210 covering at least a portion of the side surface of the first insulating layer 112.

[0073] The other descriptions may be the same as those of the printed circuit board 100A according to the example and the printed circuit boards 100B and 100C according to the modifications thereof, and a repeated description thereof will be omitted.

[0074] Fig.17 is a schematic cross-sectional view of another example of a printed circuit board.

[0075] Fig.18 and Fig.19 They are Fig.17 Schematic cross-sectional view of a variant of a printed circuit board.

[0076] Reference Figures 17 to 19, respectively, compared with the printed circuit board 100D according to another example and the printed circuit boards 100E and 100F according to the variations thereof, the printed circuit board 100M according to another example and the printed circuit boards 100N and 100O according to the variations thereof may further include a frame 210, and the frame 210 covers at least a portion of the side surface of the first insulating layer 112. The second insulating layer 113 may be provided to further extend to the upper side of the frame 210. For example, the second insulating layer 113 may further cover at least a portion of the upper surface of the frame 210. The third insulating layer 114 may be provided to further extend to the lower side of the frame 210. For example, the third insulating layer 114 may further cover at least a portion of the lower surface of the frame 210. The frame 210 may be provided to continuously surround substantially the entire side surface of the first insulating layer 112, and the first insulating layer 112 may be provided to continuously surround substantially the entire side surface of the core layer 111. As described above, in consideration of board properties (e.g., warpage control), the separation process may be performed so that the frame 210 used as a jig in the above process may remain on the outermost side. As a result, the printed circuit board 100M according to another example and the printed circuit boards 100N and 100O according to variations thereof may further include the frame 210 covering at least a portion of the side surface of the first insulating layer 112.

[0077] Other descriptions may be the same as those of the printed circuit board 100A according to the example and the printed circuit boards 100B and 100C according to the modifications thereof and the printed circuit board 100D according to another example and the printed circuit boards 100E and 100F according to the modifications thereof, and duplicate descriptions thereof will be omitted.

[0078] Fig. 20 is a schematic cross-sectional view of another example of a printed circuit board.

[0079] Fig.21 and Fig. 22 They are Fig. 20 Schematic cross-sectional view of a variant of a printed circuit board.

[0080] Reference Figure 20 to Figure 22, respectively, compared with the printed circuit board 100G according to another example and the printed circuit boards 100H and 100I according to the variations thereof, the printed circuit board 100P according to another example and the printed circuit boards 100Q and 100R according to the variations thereof may further include a frame 210, and the frame 210 covers at least a portion of the side surface of the first insulating layer 112. The second insulating layer 113 may be provided to further extend to the upper side of the frame 210. For example, the second insulating layer 113 may further cover at least a portion of the upper surface of the frame 210. The third insulating layer 114 may be provided to further extend to the lower side of the frame 210. For example, the third insulating layer 114 may further cover at least a portion of the lower surface of the frame 210. The frame 210 may be provided to continuously surround substantially the entire side surface of the first insulating layer 112, and the first insulating layer 112 may be provided to continuously surround substantially the entire side surface of the core layer 111. As described above, in consideration of board properties (e.g., warpage control), the separation process may be performed so that the frame 210 used as a jig in the above process may be retained on the outermost side. As a result, the printed circuit board 100P according to another example and the printed circuit boards 100Q and 100R according to modifications thereof may further include the frame 210 covering at least a portion of the side surface of the first insulating layer 112.

[0081] Other descriptions may be the same as those of the printed circuit board 100A according to the example and the printed circuit boards 100B and 100C according to the modifications thereof and the printed circuit board 100G according to another example and the printed circuit boards 100H and 100I according to the modifications thereof, and duplicate descriptions thereof will be omitted.

[0082] As used herein, the term "covering" may include completely covering and at least partially covering, and may include directly covering and indirectly covering. In addition, the term "filling" may include not only completely filling, but also roughly filling, for example, may include the situation where there are some gaps, pores, etc. In addition, the term "surrounding" may include not only completely surrounding, but also roughly surrounding. In addition, "exposing" may include not only completely exposing, but also exposing at least a portion of the structure, and "exposing" may mean that a component is exposed from another component in which the component is buried. For example, an opening that exposes a pad may mean exposing the pad from a resist layer, and a surface treatment layer may be further disposed on the exposed pad.

[0083] As used herein, the term "substantially" may be a concept including process errors or positional deviations occurring in a manufacturing process, errors in measurement, etc. For example, "substantially vertical" may include not only "completely vertical" but also "approximately vertical". Furthermore, "substantially coplanar" may include not only "completely coplanar" but also "approximately coplanar".

[0084] As used herein, the same insulating material may not only mean the same insulating material, but also the same type of insulating material. Therefore, the composition of the insulating material may be substantially the same, but the specific composition ratio of the insulating material may be slightly different.

[0085] As used herein, a cross-sectional shape may refer to the cross-sectional shape of an object when the object is cut vertically, or the cross-sectional shape of an object when the object is viewed from a side view. In addition, a shape on a plane may refer to the shape of an object when the object is cut horizontally, or the plane shape of an object when the object is viewed from a top view or an upward view.

[0086] As used herein, for the sake of ease, upper side, upper part, upper surface, etc. are used to refer to the direction toward the surface on which the electronic component can be mounted based on the cross section of the drawings, and lower side, lower part, lower surface, etc. are used to refer to the opposite direction. However, the above directions are defined for the convenience of description. Therefore, it should be understood that the scope of the claims is not particularly limited by the above directions, and the concepts of "upper" and "lower" can be changed at any time.

[0087] As used herein, the term "connection" may refer not only to "direct connection" but also to "indirect connection" via an adhesive layer or the like. The term "electrical connection" may include a case where components are "physically connected" and a case where components are "not physically connected." In addition, the terms "first," "second," and the like may be used to distinguish a component from another component, and may not limit the order and / or importance associated with the components, etc. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of example embodiments.

[0088] As used herein, thickness, width, length, and depth may be measured using a scanning electron microscope or an optical microscope based on a cross section obtained by polishing or cutting a printed circuit board. The cross section may be a vertical cross section or a horizontal cross section, and each value may be measured based on a desired cross section. When a value is not constant, the value may be determined as an average of values ​​measured at five arbitrary points.

[0089] As used herein, the term "example embodiment" or "some example embodiments" is provided to emphasize a particular feature, structure, or characteristic, and does not necessarily refer to the same example embodiment. In addition, particular characteristics or features may be combined in any suitable manner in one or more example embodiments. For example, unless described as being contrary to or inconsistent with the content in other example embodiments, the content described in a particular example embodiment may also be used in other example embodiments even if not described in other example embodiments.

[0090] The terms used herein are only used to describe specific example embodiments, and the present disclosure is not limited thereby.As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0091] As used herein, the term "substantially" means a small, insignificant amount that one skilled in the art would expect from an absolute or perfect condition, dimension, measurement, result, etc., but which would not significantly affect overall performance and allows for variations. When applied to a number or parameter or a property that can be expressed in a number, "substantially" means within 10 percent.

[0092] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: Inorganic substrates; a through hole passing through the inorganic substrate; a first insulating layer covering at least a portion of a side surface of the inorganic substrate; a second insulating layer, disposed on an upper surface of the inorganic substrate and an upper surface of the first insulating layer; a third insulating layer, disposed on a lower surface of the inorganic substrate and a lower surface of the first insulating layer; a first wiring layer disposed on a portion of an upper surface of the second insulating layer; as well as a second wiring layer provided on a portion of the lower surface of the third insulating layer, Wherein, the inorganic substrate comprises silicon or ceramic, and In a cross section of the printed circuit board, the inorganic substrate includes an upper end and a lower end having different widths.

2. The printed circuit board according to claim 1, wherein: In the cross section of the printed circuit board, the width of the upper end of the inorganic substrate is smaller than the width of the lower end of the inorganic substrate, and The side surface of the inorganic substrate is inclined.

3. The printed circuit board according to claim 1, further comprising: an inorganic insulating film covering at least a portion of each of the upper surface and the lower surface of the inorganic substrate, and The side surface of the inorganic substrate is in contact with the first insulating layer.

4. The printed circuit board according to claim 3, wherein: The inorganic insulating film includes: an oxide film disposed on the inorganic substrate; and a nitride film disposed on the oxide film and spaced apart from an outer surface of the inorganic substrate.

5. The printed circuit board according to claim 3, wherein: The inorganic substrate has a through hole in which the through via is provided, and The inorganic insulating film extends to a space between the inorganic substrate and the through via to further cover at least a portion of a wall surface of the through via.

6. The printed circuit board according to claim 5, wherein: The through via includes: a first metal layer, which is arranged on the inorganic insulating film in the through hole; and a second metal layer, which fills at least a portion of the through hole on the first metal layer, and in the cross-section of the printed circuit board, the second metal layer has a width greater than a width of the first metal layer.

7. The printed circuit board according to claim 1, wherein: The first insulating layer, the second insulating layer, and the third insulating layer each include an organic insulating material.

8. The printed circuit board according to claim 7, wherein: The first insulating layer forms an interlayer boundary with each of the second insulating layer and the third insulating layer, and The upper surface and the lower surface of the first insulating layer are substantially coplanar with the upper surface and the lower surface of the inorganic substrate, respectively.

9. The printed circuit board according to claim 7, wherein: The first insulating layer is integrated with at least one of the second insulating layer and the third insulating layer without an interlayer boundary.

10. The printed circuit board according to claim 1, further comprising: a first connection via hole passing through the second insulating layer, the first connection via hole connecting the through via hole and the first wiring layer to each other; as well as A second connection via passes through the third insulating layer, and the second connection via connects the through via and the second wiring layer to each other.

11. The printed circuit board according to claim 1, further comprising: a third wiring layer disposed on the upper surface of the inorganic substrate, connected to the through vias, and at least partially buried in the second insulating layer; a fourth wiring layer disposed on the lower surface of the inorganic substrate, connected to the through via, and at least partially buried in the third insulating layer; a first connection via hole passing through the second insulating layer, the first connection via hole connecting the first wiring layer and the third wiring layer to each other; as well as A second connection via passes through the third insulating layer, and the second connection via connects the second wiring layer and the fourth wiring layer to each other.

12. The printed circuit board according to claim 11, further comprising: One or more intermediate insulating layers, disposed between the inorganic substrate and the second insulating layer; one or more intermediate wiring layers, disposed on the one or more intermediate insulating layers and / or disposed in the one or more intermediate insulating layers; as well as one or more intermediate via layers, passing through at least one of the one or more intermediate insulating layers, Wherein, the first insulating layer further covers at least a portion of a side surface of each of the one or more intermediate insulating layers.

13. The printed circuit board according to claim 1, further comprising: One or more first build-up insulating layers, disposed on the upper surface of the second insulating layer; One or more first build-up wiring layers, disposed on the one or more first build-up insulating layers and / or disposed in the one or more first build-up insulating layers; one or more first build-up via layers, passing through at least one of the one or more first build-up insulating layers; One or more second build-up insulating layers, disposed on the lower surface of the third insulating layer; One or more second build-up wiring layers, disposed on the one or more second build-up insulating layers and / or disposed in the one or more second build-up insulating layers; one or more second build-up via layers, passing through at least one of the one or more second build-up insulating layers; A first resist layer is disposed on an upper surface of a top first stacked insulating layer among the one or more first stacked insulating layers, wherein the first resist layer covers at least a portion of a top first stacked wiring layer among the one or more first stacked wiring layers; as well as a second resist layer disposed on a lower surface of the lowest second stacked insulating layer among the one or more second stacked insulating layers, the second resist layer covering at least a portion of the lowest second stacked wiring layer among the one or more second stacked wiring layers, wherein the first resist layer has a plurality of first openings for exposing at least a portion of the uppermost first buildup wiring layer, and The second resist layer has a plurality of second openings that expose at least a portion of the lowermost second buildup wiring layer.

14. The printed circuit board according to claim 1, further comprising: One or more first build-up insulating layers, disposed on the upper surface of the second insulating layer; One or more first build-up wiring layers, disposed on the one or more first build-up insulating layers and / or disposed in the one or more first build-up insulating layers; one or more first build-up via layers, passing through at least one of the one or more first build-up insulating layers; A first resist layer is disposed on an upper surface of a top first stacked insulating layer among the one or more first stacked insulating layers, wherein the first resist layer covers at least a portion of a top first stacked wiring layer among the one or more first stacked wiring layers; as well as a second resist layer disposed on the lower surface of the third insulating layer, the second resist layer covering at least a portion of the second wiring layer, wherein the first resist layer has a plurality of first openings for exposing at least a portion of the uppermost first buildup wiring layer, and The second resist layer has a plurality of second openings exposing at least a portion of the second wiring layer.

15. The printed circuit board according to claim 1, 10, 11 or 12, further comprising: a frame covering at least a portion of a side surface of the first insulating layer, wherein the second insulating layer is arranged to further extend onto the upper surface of the frame, and The third insulating layer is configured to further extend onto the lower surface of the frame.

16. The printed circuit board according to claim 1, further comprising: A capacitor includes a plurality of conductive trenches penetrating a portion of the inorganic substrate from the upper surface or the lower surface of the inorganic substrate.

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