Circuit board preparation method capable of quickly locating foreign matters in build-up layers of IC substrates

Abstract

The present invention discloses a circuit board preparation method for quickly locating foreign objects in the build-up layer of an IC carrier board, belonging to the technical field of circuit board preparation. The method includes the following steps: S1, setting a carrier copper foil on a substrate; S2, setting an ultra-thin copper layer on the carrier copper foil; S3, laying a dry film on the ultra-thin copper layer; S4, exposing and developing the dry film; S5, electroplating the exposed ultra-thin copper layer to form a conductive pattern; S6, removing the dry film on the surface of the ultra-thin copper layer; S7, laminating an insulating material on the surface of the ultra-thin copper layer; S8, peeling the ultra-thin copper layer from the carrier copper foil; S9, etching to remove the ultra-thin copper layer on the surface of the insulating material to expose the conductive pattern. During the electroplating process, the ultra-thin copper layer serves as a substrate, enabling the ultra-thin copper layer to uniformly receive electroplating treatment. This helps to form a uniform conductive layer and improve the conductivity and reliability of the circuit board.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board preparation, and more specifically, to a circuit board preparation method for quickly locating foreign objects in the build-up layer of an IC carrier board. Background Art

[0002] With the rapid development of electronic technology, integrated circuit (IC) carrier boards are increasingly widely used in modern electronic devices. As a key connecting component between the chip and the external circuit, the quality and reliability of the IC carrier board play a crucial role in the performance of the entire electronic system. In the manufacturing process of the IC carrier board, the build-up process is an important link to achieve multi-layer interconnection. However, various foreign objects, such as particles, fibers, metal fragments, etc., may be introduced during the build-up process, and these foreign objects may cause faults such as short circuits, open circuits, and signal interference, seriously affecting the performance and reliability of the IC carrier board.

[0003] To solve these problems, some improvement measures have been adopted in the existing technologies, but these measures are often complex in process, high in cost, and ineffective. Therefore, a circuit board preparation method for quickly locating foreign objects in the build-up layer of an IC carrier board is needed to improve the electrical conductivity and reliability of the circuit board while reducing the preparation cost. Summary of the Invention

[0004] 1. Technical Problems to be Solved

[0005] The purpose of the present invention is to provide a circuit board preparation method for quickly locating foreign objects in the build-up layer of an IC carrier board to solve the problems raised in the above background art.

[0006] 2. Technical Solutions

[0007] The present invention is realized through the following technical solutions:

[0008] A circuit board preparation method for quickly locating foreign objects in the build-up layer of an IC carrier board includes the following steps:

[0009] S1. Set a carrier copper foil on the substrate;

[0010] S2. Set an ultra-thin copper layer on the carrier copper foil;

[0011] S3. Lay a dry film on the ultra-thin copper layer;

[0012] S4. Expose and develop the dry film;

[0013] S5. Electroplate the exposed ultra-thin copper layer to form a conductive pattern;

[0014] S6. Remove the dry film on the surface of the ultra-thin copper layer;

[0015] S7. Press an insulating material on the surface of the ultra-thin copper layer;

[0016] S71: Marking layer production before lamination

[0017] A micron-scale positioning grid is laser-etched on the surface of an extremely thin copper layer to form a coordinate reference system. The grid lines are printed with nano-carbon ink to ensure that they can be completely transferred to the surface of the insulating layer during subsequent peeling.

[0018] S72: Smart insulation lamination

[0019] The epoxy resin composite material containing thermochromic microcapsules is used. When the pressing temperature reaches a certain temperature, the normal area will show a uniform green color. When there is foreign matter, due to the difference in local thermal conductivity, the microcapsules trigger red-green dual-color development, and the color difference ΔE>15 can be visually identified.

[0020] S8, peeling off the extremely thin copper layer from the carrier copper foil;

[0021] S9, etching and removing the extremely thin copper layer on the surface of the insulating material to expose the conductive pattern.

[0022] As an optional solution of the technical solution of this application document, step S8 also includes optical positioning detection:

[0023] Three-wavelength multispectral scanning was performed immediately after stripping, through:

[0024] Mesh deformation analysis: compare the original coordinates and locate the area with offset > 5μm;

[0025] Chromaticity threshold determination: Establish CIELab color gamut model and automatically mark abnormal points with Δa>2.5;

[0026] Surface topology reconstruction: White light interferometry generates 3D topography images.

[0027] As an optional solution of the technical solution of the present application document, short circuit detection of the conductive pattern is also included, including initial inspection of the conductive pattern and re-inspection after lamination, wherein the initial inspection of the conductive pattern includes: inserting after the electroplating process in step S5:

[0028] Deploy a four-probe matrix test system with a spacing of 0.1mm and probe impedance <0.5Ω;

[0029] Use digital multimeter to establish a distributed detection network:

[0030] Test mode: Automatically switch between DC impedance and adjacent line insulation resistance;

[0031] Sampling frequency: 200 points / second;

[0032] Embedded test points: Set a gold-nickel alloy test pad with a diameter of 50μm at the end of the pattern with a spacing of 150μm.

[0033] As an alternative solution to the technical solution of this application document, the reinspection after lamination includes: adding after laminating the insulating material in step S7:

[0034] Adaptive probe calibration:

[0035] Using the positioning grid coordinates of step S71; the laser-assisted positioning system automatically compensates for the Z-axis lamination thickness deviation;

[0036] Abnormal impedance determination: When the resistance value between adjacent lines < 10Ω, a short-circuit alarm is triggered;

[0037] Insulation failure warning: When the resistance between lines < 1MΩ, a three-level alarm is activated

[0038] Hot-swap detection module: Online replacement of faulty probes.

[0039] As an alternative solution to the technical solution of this application document, the thickness of the carrier copper foil is 12μm to 70μm, and the material is high-purity copper or copper alloy.

[0040] As an alternative solution to the technical solution of this application document, the thickness of the ultra-thin copper layer is 0.5μm to 12μm, and it is formed by an electrolytic copper plating bath.

[0041] As an alternative solution to the technical solution of this application document, the dry film thickness is 10μm to 50μm, and the dry film is a photosensitive dry film, which is tightly attached to the ultra-thin copper layer by lamination.

[0042] When electroplating the ultra-thin copper layer, the current density is 1A / dm² to 10A / dm².

[0043] As an alternative solution to the technical solution of this application document, the insulating material is an epoxy resin composite material containing thermochromic microcapsules, including a combination of thermochromic microcapsules and epoxy resin.

[0044] As an alternative solution to the technical solution of this application document, the thickness of the insulating material is 20μm to 50μm.

[0045] 3. Beneficial effects

[0046] Compared with the prior art, the beneficial effects of the present invention are:

[0047] 1) The ultra-thin copper layer provides the necessary mechanical strength for the ultra-thin copper layer to prevent it from cracking or wrinkling during the processing. Integrating laser etching grid and multi-spectral imaging to achieve foreign object detection.

[0048] 2) During the electroplating process, the ultra-thin copper layer serves as a substrate, enabling the ultra-thin copper layer to uniformly receive electroplating treatment. This helps to form a uniform conductive layer and improve the electrical conductivity and reliability of the circuit board.

[0049] 3) During the electroplating process, the use of an extremely thin copper layer can increase the overall board thickness, thereby improving the flatness of the printed circuit board within the electroplating line body.

[0050] 4) By collaborating the probe matrix with a distributed multimeter to achieve short - circuit detection, the circuit pattern can be exposed on the surface of the insulating material, facilitating short - circuit measurement of the circuit pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a flowchart of a circuit board preparation method that can quickly locate foreign objects in the build - up layer of an IC carrier board. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0052] Next, the technical solution of the present invention will be clearly and completely described in conjunction with the accompanying drawings.

[0053] Embodiment 1:

[0054] Please refer to Figure 1 , the present invention provides a technical solution:

[0055] A circuit board preparation method that can quickly locate foreign objects in the build - up layer of an IC carrier board, including the following steps:

[0056] S1. Set a carrier copper foil on the substrate;

[0057] S2. Set an extremely thin copper layer on the carrier copper foil;

[0058] S3. Lay a dry film on the extremely thin copper layer;

[0059] S4. Expose and develop the dry film;

[0060] S5. Electroplate the exposed extremely thin copper layer to form a conductive pattern;

[0061] S6. Remove the dry film on the surface of the extremely thin copper layer;

[0062] S7. Press an insulating material on the surface of the extremely thin copper layer;

[0063] S71: Fabrication of the marking layer before pressing

[0064] Laser - etch a micron - level positioning grid (line width 5μm, spacing 200μm) on the surface of the extremely thin copper layer to form a coordinate reference system. The grid lines are printed with nano - carbon ink to ensure complete transfer to the surface of the insulating layer during subsequent peeling.

[0065] S72: Intelligent pressing of the insulating material

[0066] Use an epoxy resin composite material containing thermochromic microcapsules (particle size 1 - 3μm). When the lamination temperature reaches 180°C, the normal area shows a uniform green color; when there are foreign objects (such as metal chips or fibers), due to local thermal conductivity differences, the microcapsules trigger red - green dual - color development, and a color difference ΔE > 15 can be visually identified.

[0067] S8. Peel off an extremely thin copper layer from the carrier copper foil;

[0068] S9. Etch away the extremely thin copper layer on the surface of the insulating material to expose the conductive pattern.

[0069] S81. Optical positioning detection

[0070] Immediately after peeling, perform multi - spectral scanning at three wavelengths (365nm / 520nm / 850nm) through:

[0071] Grid deformation analysis: Compare with the original coordinates to locate areas with an offset > 5μm;

[0072] Chromaticity threshold determination: Establish a CIELab color gamut model to automatically mark abnormal points with Δa > 2.5;

[0073] Surface topology reconstruction: A white - light interferometer generates a 3D topography map (resolution 0.1μm);

[0074] Use a handheld color - separation card (PANTONE QC color card) to directly compare with abnormal color patches. The red area is the foreign - object point; Configure a 20 - fold magnifying glass (with a 100μm scale built - in), and quickly read the position of the foreign object through grid coordinates (accuracy ±50μm). This can effectively improve the detection rate of foreign objects > 40μm, shorten the positioning time to, and is compatible with existing production - line equipment with low transformation costs. Through multi - dimensional criteria of color - shape - position, it can effectively distinguish real foreign objects from pseudo - defects (such as resin flow marks), and the misjudgment rate < 0.3%.

[0075] Example 2:

[0076] On the basis of Example 1, further add the function of detecting short - circuits in the conductive pattern, specifically as follows:

[0077] It includes an initial inspection of the conductive pattern and a re - inspection after lamination. Among them, the initial inspection of the conductive pattern includes: Insert after the electroplating process in step S5:

[0078] Deploy a four - probe matrix test system (spacing 0.1mm, probe impedance < 0.5Ω)

[0079] Use a digital multimeter (Agilent 34465A, 6½ digits) to establish a distributed detection network:

[0080] Test mode: Automatically switch between DC impedance (range 0 - 100Ω) and adjacent - line insulation resistance (range 0 - 10MΩ);

[0081] Sampling frequency: 200 points per second

[0082] Embedded test point design: Set gold-nickel alloy test discs with a diameter of 50 μm (spacing 150 μm) at the end of the pattern.

[0083] Re-inspection after lamination (combining foreign object coordinates)

[0084] Add after laminating the insulating material in S7:

[0085] Adaptive probe calibration:

[0086] Utilize the positioning grid coordinates of S71 (accuracy of ±5 μm)

[0087] The laser-assisted positioning system automatically compensates for the Z-axis lamination thickness deviation (compensation range of ±25 μm)

[0088] Impedance anomaly determination: When the resistance between adjacent lines < 10 Ω, a short circuit alarm is triggered;

[0089] Insulation failure warning: When the resistance between lines < 1 MΩ, a three-level alarm is activated;

[0090] Specific examples are as follows:

[0091] The thickness of the carrier copper foil is 12 μm to 70 μm, and the material is high-purity copper or copper alloy.

[0092] The thickness of the ultra-thin copper layer is 0.5 μm to 12 μm, formed by an electrolytic copper plating bath.

[0093] The dry film thickness is 10 μm to 50 μm. The dry film is a photosensitive dry film and is tightly bonded to the ultra-thin copper layer by lamination.

[0094] When electroplating the ultra-thin copper layer, the current density is 1 A / dm² to 10 A / dm².

[0095] The insulating material is an epoxy resin composite containing thermochromic microcapsules, including a combination of thermochromic microcapsules and epoxy resin; Thermochromic microcapsules: Daikin Industries DT-180 type, particle size 1.8 μm ± 0.2 μm; Color change threshold: 180 °C ± 2 °C for 120 seconds triggers color change (green Lab* = 70 / 0 / 60 → red Lab* = 45 / 75 / 40); Epoxy resin: Dow DER-662, containing 0.05 wt% fluorescent tracer (excitation wavelength 365 nm, emission wavelength 420 nm).

[0096] Four-probe matrix: Japanese KLA CPE-200 system, probe spacing 0.1 mm, contact resistance < 0.3 Ω;

[0097] Multimeter network: 6 Keysight 34465A are synchronized for acquisition, sampling rate is 50 kSa / s, and the noise suppression ratio > 80 dB;

[0098] Test point design: Gold-plated pad with a diameter of 50 μm (Ni / Au = 5 μm / 0.05 μm), contact impedance repeatability CV < 1.2%;

[0099] Light source configuration:

[0100] UV band: 365 nm LED array (intensity 50 mW / cm²)

[0101] Visible light: Ring-shaped white LED (color temperature 5500K, CRI > 95)

[0102] Infrared: 850 nm VCSEL module (power density 10 mW / mm²)

[0103] Table 1 Comparison table of foreign object detection performance

[0104]

[0105] Table 2: Comparison table of short-circuit detection capabilities

[0106]

[0107] Through this embodiment, the collaborative prevention and control of foreign objects and short-circuit defects is achieved, and foreign objects can be effectively and quickly detected without using destructive methods such as substrate stripping and grinding, effectively improving the substrate yield.

Claims

1. A method for preparing a circuit board capable of quickly locating foreign matter on an IC substrate layer, characterized in that: The following steps are involved: S1. Arranging a carrier copper foil on a substrate; S2, providing an extremely thin copper layer on the carrier copper foil; S3, laying a dry film on the very thin copper layer; S4, exposing and developing the dry film; S5, electroplating the exposed extremely thin copper layer to form a conductive pattern; S6. Remove the dry film on the surface of the extremely thin copper layer; S7. Laminating insulating material on the surface of the extremely thin copper layer; S71: Marking layer production before lamination A micron-scale positioning grid is laser-etched on the surface of an extremely thin copper layer to form a coordinate reference system. The grid lines are printed with nano-carbon ink to ensure that they can be completely transferred to the surface of the insulating layer during subsequent peeling. S72: Smart insulation lamination The epoxy resin composite material containing thermochromic microcapsules is used. When the pressing temperature reaches a certain temperature, the normal area will show a uniform green color. When there is foreign matter, due to the difference in local thermal conductivity, the microcapsules trigger red-green dual-color development, and the color difference ΔE>15 can be visually identified. S8, peeling off the extremely thin copper layer from the carrier copper foil; S9, etching and removing the extremely thin copper layer on the surface of the insulating material to expose the conductive pattern.

2. The method for preparing a circuit board capable of quickly locating foreign matter on an IC carrier layer according to claim 1, characterized in that: The step S8 also includes optical positioning detection: Three-wavelength multispectral scanning was performed immediately after stripping, through: Mesh deformation analysis: compare the original coordinates and locate the area with offset > 5μm; Chromaticity threshold determination: Establish CIELab color gamut model and automatically mark abnormal points with Δa>2.5; Surface topology reconstruction: White light interferometry generates 3D topography images.

3. The method for preparing a circuit board capable of quickly locating foreign matter on an IC carrier layer according to claim 1, characterized in that: It also includes short circuit detection of the conductive pattern, including initial inspection of the conductive pattern and re-inspection after pressing, wherein the initial inspection of the conductive pattern includes: inserting after the electroplating process in step S5: Deploy a four-probe matrix test system with a spacing of 0.1mm and probe impedance <0.5Ω; Use digital multimeter to establish a distributed detection network: Test mode: Automatically switch between DC impedance and adjacent line insulation resistance; Sampling frequency: 200 points / second; Embedded test points: Set a gold-nickel alloy test pad with a diameter of 50μm at the end of the pattern with a spacing of 150μm.

4. The method for preparing a circuit board capable of quickly locating foreign matter on an IC carrier layer according to claim 3, characterized in that: The post-pressing re-inspection includes: adding the following steps after the insulating material is pressed in step S7: Adaptive Probe Calibration: Using the positioning grid coordinates of step S71, the laser-assisted positioning system automatically compensates for the Z-axis pressing thickness deviation; Impedance abnormality judgment: when the adjacent line resistance is less than 10Ω, a short circuit alarm is triggered; Insulation failure warning: When the line resistance is less than 1MΩ, the three-level alarm is activated Hot-swap detection module: Replace faulty probes online.

5. The method for preparing a circuit board capable of quickly locating foreign matter on an IC carrier layer according to claim 1, characterized in that: The carrier copper foil has a thickness of 12 μm to 70 μm and is made of high-purity copper or copper alloy.

6. The method for preparing a circuit board capable of quickly locating foreign matter on an IC carrier layer according to claim 1, characterized in that: The ultra-thin copper layer has a thickness of 0.5 μm to 12 μm and is formed by an electrolytic copper plating bath.

7. The method for preparing a circuit board capable of quickly locating foreign matter on an IC carrier layer according to claim 1, characterized in that: The dry film has a thickness of 10 μm to 50 μm, and is a photosensitive dry film that is tightly attached to the extremely thin copper layer by lamination.

8. The method for preparing a circuit board capable of quickly locating foreign matter on an IC carrier layer according to claim 1, characterized in that: When electroplating extremely thin copper layers, the current density is 1A / dm²~10A / dm².

9. The method for preparing a circuit board capable of quickly locating foreign matter on an IC carrier layer according to claim 1, characterized in that: The insulating material is an epoxy resin composite material containing thermochromic microcapsules, including a combination of thermochromic microcapsules and epoxy resin.

10. The method for preparing a circuit board capable of quickly locating foreign matter on an IC carrier layer according to claim 1, characterized in that: The thickness of the insulating material is 20 μm to 50 μm.

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