Preparation method of depletion mode transistor and depletion mode transistor

Abstract

The invention relates to a preparation method of a depletion mode transistor and the depletion mode transistor. The method comprises the following steps: providing a substrate of a first ion type; forming a drift region of a second ion type on one side of the substrate of the first ion type; forming a first groove, a second groove and a third groove in the top of the substrate of the first ion type; forming a field oxide layer on the drift region of the second ion type; forming a gate oxide layer on the substrate of the first ion type by using a self-alignment process, forming a polycrystalline silicon layer on the gate oxide layer, and forming a well region of the first ion type in the substrate of the first ion type; forming a lightly doped region of a second ion type in the substrate of the first ion type; forming polysilicon gate side walls on two sides of the polysilicon layer; and forming a source electrode of the first ion type in the well region of the first ion type, and forming a drain electrode of the second ion type in the drift region of the second ion type. The use of extra photomasks can be reduced at least, the number of layers of photoetching plates is reduced, and the production cost of transistors is reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a method for preparing a depletion-mode transistor and a depletion-mode transistor. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, MOSFET is divided into two structures: enhancement type and depletion type according to whether there is an original conductive channel. Taking N-type MOSFET as an example, for enhancement type NMOS, a conductive channel will only be formed when the voltage from the gate to the source VGS>0. At this time, loading a voltage between the source and the drain will generate a large source-drain current; while for depletion type NMOS, there is an original conductive channel. Even when the gate bias VGS=0, loading a voltage between the source and the drain will generate a large source-drain current. Only when VGS<0 and increases to a certain value, the original conductive channel disappears and the NMOS tube is turned off. In some specific applications, such as surge and high voltage protection, anti-reverse connection protection or solid-state relays, high voltage dissipation is required, that is, the device needs to be turned on when VGS=0, and the device needs to withstand a certain drain voltage when it is turned on or off. DEMOS has the advantages of high withstand voltage and low on-resistance and can be used as a high voltage switch and high voltage and high current driver. It is a good choice as a high voltage dissipation.

[0003] Traditional consumption-free FETs usually use two methods to form the original conductive channel: one is to perform ion implantation in the gate oxide layer to attract substrate electrons / holes to form a conductive channel; the other is to perform ion implantation directly under the gate oxide to form the original conductive channel. The common point of these two methods is that they require additional photomasks for ion implantation, which increases the manufacturing cost. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a depletion-mode transistor and a depletion-mode transistor to address the above technical problems, which can at least reduce the use of additional masks, reduce the number of layers of photolithography boards, and reduce the production cost of transistors.

[0005] In order to achieve the above-mentioned objectives and other objectives, in a first aspect, the present disclosure provides a method for preparing a depletion-type transistor, comprising: providing a substrate of a first ion type; forming a drift region of a second ion type on one side of the substrate of the first ion type; forming a first groove, a second groove and a third groove on the top of the substrate of the first ion type, the first groove being close to one side of the substrate of the first ion type, the third groove being close to the other side of the substrate of the first ion type, the second groove being located between the third groove and the drift region of the second ion type, and the first groove being at least partially located in the drift region of the second ion type; forming a field oxide layer on the drift region of the second ion type, the top surface of the field oxide layer being higher than the top surface of the substrate of the first ion type, and the bottom surface of the field oxide layer being higher than the bottom surface of the drift region of the second ion type; using a self-alignment process, forming a gate oxide layer on the substrate of the first ion type, and forming a gate oxide layer on the gate oxide layer A polysilicon layer is formed on the substrate, and a well region of the first ion type is formed in the substrate of the first ion type, the gate oxide layer is in contact with the drift region of the second ion type, the field oxide layer and the substrate of the first ion type, the polysilicon layer is in contact with the field oxide layer, the well region of the first ion type crosses the second trench laterally, and contacts the third trench; a lightly doped region of the second ion type is formed in the substrate of the first ion type, the lightly doped region of the second ion type is located between the drift region of the second ion type and the well region of the first ion type, the top surface of the lightly doped region of the second ion type contacts the bottom surface of the gate oxide layer, and one side of the lightly doped region of the second ion type contacts the well region of the first ion type; polysilicon gate sidewalls are formed on both sides of the polysilicon layer; a source of the first ion type is formed in the well region of the first ion type, and a drain of the second ion type is formed in the drift region of the second ion type.

[0006] In the preparation method of the depletion-mode transistor in the above-mentioned embodiment, in the process of forming the depletion-mode transistor, based on the self-alignment process, the gate oxide layer, the polysilicon layer and the well region are formed in one step. There is no need to use different masks and plates during photolithography when forming the gate oxide layer, the polysilicon layer and the well region, thereby reducing the use of additional masks, reducing the number of layers of the photolithography plate, and reducing the production cost of the transistor.

[0007] In one embodiment, a drift region of a second ion type is formed on one side of a substrate of a first ion type, comprising: forming a first pad oxide layer on the substrate of the first ion type through a furnace tube thermal oxidation process; photolithography the pad oxide layer to form a first mask layer, the first mask layer exposing a first pattern required to form a drift region of the second ion type; and performing ion implantation of the second ion type using the first mask layer as a mask to form a drift region of the second ion type on one side of the substrate of the first ion type.

[0008] In one embodiment, the implantation energy of the second ion type ion implantation using the first mask layer as a mask is 30 KeV to 600 KeV, and the implantation dose is to .

[0009] In one embodiment, the steps of forming a first groove, a second groove and a third groove on the top of a first ion type substrate include: removing the first mask layer, and forming a second pad oxide layer on the first ion type substrate through a furnace tube thermal oxidation process; forming a first dielectric layer on the second pad oxide layer, and the first dielectric layer is used as a barrier layer for chemical mechanical polishing; using the second pad oxide layer and the dielectric layer as mask layers, performing photolithography and etching to form a first groove, a second groove and a third groove on the top of the first ion type substrate; filling the first groove, the second groove and the third groove based on a high-density plasma enhanced chemical vapor deposition process, and performing annealing to repair lattice damage; using chemical mechanical grinding to the first dielectric layer, and using a wet method to remove the remaining dielectric layer, to form an active area and an isolation area in the first ion type substrate.

[0010] In one of the embodiments, a field oxide layer is formed on a drift region of a second ion type, comprising: forming a second dielectric layer on a top surface of a substrate of a first ion type based on a furnace tube thermal oxidation process; using the second dielectric layer as a barrier layer for field region oxidation, defining a field oxide region by photolithography and etching processes, and forming a field oxide barrier layer; forming a field oxide layer by a thermal oxidation process, and removing the second dielectric layer and the second pad oxide layer by a wet method to form a field oxide layer.

[0011] In one embodiment, a gate oxide layer is formed on a substrate of a first ion type, and a polysilicon layer is formed on the gate oxide layer, including: forming a gate oxide layer on the top surface of the substrate of the first ion type based on a thermal oxidation process; depositing a polysilicon layer on the gate oxide layer, and defining the area where the polysilicon layer needs to be left by photolithography and etching; using a self-alignment process, photolithography, etching, and ion implantation of the first ion type to define the well region, polysilicon layer and gate oxide layer of the first ion type.

[0012] In one embodiment, the implantation energy of the first ion type ion implantation is 20 KeV to 280 KeV, and the implantation dose is to .

[0013] In one embodiment, the step of forming a lightly doped region of a second ion type in a substrate of a first ion type comprises: performing ion implantation of the lightly doped region of the first ion type at a preset ion implantation angle; wherein the preset ion implantation angle is 15° to 45°, the implantation energy of the lightly doped region of the first ion type is 50 KeV to 80 KeV, and the implantation dose of the lightly doped region of the first ion type is to .

[0014] In one embodiment, the steps of forming a source of the first ion type in a well region of the first ion type and forming a drain of the second ion type in a drift region of the second ion type include: performing source ion implantation of the first ion type and performing drain ion implantation of the second ion type; wherein the implantation energy of the source ion implantation of the first ion type is 30 KeV to 50 KeV and the implantation dose is to The second ion type drain ion implantation energy is 10 KeV to 15 KeV, and the implantation dose is to .

[0015] In a second aspect, an embodiment of the present disclosure further provides a depletion-mode transistor, comprising: a substrate of a first ion type; a drift region of a second ion type, located on one side of the substrate of the first ion type; a first trench, a second trench, and a third trench, located on the top of the substrate of the first ion type, the first trench being close to one side of the substrate of the first ion type, the third trench being close to the other side of the substrate of the first ion type, the second trench being between the third trench and the drift region of the second ion type, and the first trench being at least partially located in the drift region of the second ion type; a field oxide layer, located in the drift region of the second ion type, the top surface of the field oxide layer being higher than the top surface of the substrate of the first ion type, and the bottom surface of the field oxide layer being higher than the bottom surface of the drift region of the second ion type; a gate oxide layer and a polysilicon layer, the gate oxide layer being located on the substrate of the first ion type, the polysilicon layer being located on the gate oxide layer, and the gate oxide layer and the second ion type The drift region, the field oxide layer and the substrate of the first ion type form contact, and the polysilicon layer forms contact with the field oxide layer; the well region of the first ion type is located in the substrate of the first ion type, the well region of the first ion type laterally spans the second trench and contacts the third trench; the lightly doped region of the second ion type is located in the substrate of the first ion type, the lightly doped region of the second ion type is located between the drift region of the second ion type and the well region of the first ion type, the top surface of the lightly doped region of the second ion type contacts the bottom surface of the gate oxide layer, and one side of the lightly doped region of the second ion type contacts the well region of the first ion type; the polysilicon gate sidewalls are located on both sides of the polysilicon layer; the source of the first ion type and the drain of the second ion type, the source of the first ion type is located in the well region of the first ion type, and the drain of the second ion type is located in the drift region of the second ion type.

[0016] The depletion-mode transistor in the above-mentioned embodiment forms a gate oxide layer, a polysilicon layer and a well region in one step based on a self-alignment process. There is no need to use different masks and plates during photolithography when forming the gate oxide layer, the polysilicon layer and the well region, thereby reducing the use of additional masks, reducing the number of layers of photolithography plates, and reducing the production cost of transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic flow chart of a method for preparing a depletion-mode transistor provided in an embodiment;

[0019] Figure 2 A schematic structural diagram of a structure obtained in step S2000 in a method for preparing a depletion-mode transistor provided in an embodiment;

[0020] Figure 3 Schematic diagram of the structure obtained in step S4000 in the method for preparing a depletion-mode transistor provided in one embodiment;

[0021] Figure 4 A schematic diagram of a longitudinal cross-sectional structure of a structure obtained in step S5000 in a method for preparing a depletion-mode transistor provided in an embodiment Figure 1 ;

[0022] Figure 5 FIG. 1 is a schematic diagram of a structure obtained in step S5000 in a method for preparing a depletion-mode transistor provided in an embodiment. Figure 2 ;

[0023] Figure 6 Schematic diagram of the structure obtained in step S7000 in the method for preparing a depletion-mode transistor provided in one embodiment.

[0024] Description of reference numerals:

[0025] 201, substrate of the first ion type; 202, drift region of the second ion type; 301, first trench; 302, second trench; 303, third trench; 304, field oxide layer; 401, gate oxide layer; 502, polysilicon layer; 503, well region of the first ion type; 601, lightly doped region of the second ion type; 602, polysilicon gate sidewall; 603, source of the first ion type; 604, drain of the second ion type. DETAILED DESCRIPTION

[0026] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used in the specification of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0028] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0029] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0030] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0031] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0032] Please refer to Figure 1-Figure 6 The present disclosure provides a method for preparing a contact hole 1001, comprising the following steps:

[0033] Step S1000: providing a substrate 201 of a first ion type.

[0034] Step S2000 : forming a drift region 202 of a second ion type on one side of a substrate 201 of a first ion type.

[0035] Step S3000 : forming a first trench 301 , a second trench 302 and a third trench 303 on the top of a substrate 201 of a first ion type.

[0036] Among them, the first trench 301 is close to one side of the first ion type substrate 201, the third trench 303 is close to the other side of the first ion type substrate 201, the second trench 302 is located between the third trench 303 and the drift region 202 of the second ion type, and the first trench 301 is at least partially located in the drift region 202 of the second ion type.

[0037] Step S4000 : forming a field oxide layer 304 on the drift region 202 of the second ion type.

[0038] The top surface of the field oxide layer 304 is higher than the top surface of the substrate 201 of the first ion type, and the bottom surface of the field oxide layer 304 is higher than the bottom surface of the drift region 202 of the second ion type.

[0039] Step S5000 : using a self-aligned process, a gate oxide layer 401 is formed on a first ion type substrate 201 , a polysilicon layer 502 is formed on the gate oxide layer 401 , and a first ion type well region 503 is formed in the first ion type substrate 201 .

[0040] Among them, the gate oxide layer 401 forms contact with the drift region 202 of the second ion type, the field oxide layer 304 and the substrate 201 of the first ion type, the polysilicon layer 502 forms contact with the field oxide layer 304, and the well region 503 of the first ion type laterally spans the second trench 302 and contacts the third trench 303.

[0041] Step S6000: forming a lightly doped region 601 of a second ion type in a substrate 201 of a first ion type.

[0042] Among them, the lightly doped region 601 of the second ion type is located between the drift region 202 of the second ion type and the well region 503 of the first ion type, the top surface of the lightly doped region 601 of the second ion type contacts the bottom surface of the gate oxide layer 401, and one side of the lightly doped region 601 of the second ion type contacts the well region 503 of the first ion type.

[0043] Step S7000 : forming polysilicon gate spacers 602 on both sides of the polysilicon layer 502 .

[0044] Step S8000 : forming a source 603 of a first ion type in the well region 503 of a first ion type, and forming a drain 604 of a second ion type in the drift region 202 of a second ion type.

[0045] In the preparation method of the depletion-mode transistor in the above-mentioned embodiment, in the process of forming the depletion-mode transistor, based on the self-alignment process, the gate oxide layer 401, the polysilicon layer 502 and the well region are formed in one step. There is no need to use different masks and plates during photolithography when forming the gate oxide layer 401, the polysilicon layer 502 and the well region, thereby reducing the use of additional masks, reducing the number of layers of the photolithography plate, and reducing the transistor production cost.

[0046] In step S2000, please refer to Figure 1-Figure 2 Taking depletion-type DENMOS as an example, the first ion type is P-type, and the second ion type is N-type. A pad oxide layer (PAD OX) is generated on the surface of the silicon substrate by furnace thermal oxidation, and then the required ion implantation area is formed by photolithography, and then N-type ion implantation is performed. Finally, the photoresist is removed to form a drift region, which can carry the high voltage at the drain end.

[0047] Specifically, a drift region 202 of a second ion type is formed on one side of a substrate 201 of a first ion type, including: forming a first pad oxide layer on the substrate 201 of the first ion type through a furnace tube thermal oxidation process; photolithography of the pad oxide layer to form a first mask layer, the first mask layer exposing a first pattern required to form the drift region 202 of the second ion type; and performing ion implantation of the second ion type using the first mask layer as a mask to form a drift region 202 of the second ion type on one side of the substrate 201 of the first ion type.

[0048] The implantation energy of the second ion type ion implantation using the first mask layer as a mask is 30 KeV to 600 KeV, and the implantation dose is to .

[0049] As an example, the implantation energy of the second ion type ion implantation using the first mask layer as a mask may be 30 KeV, 70 KeV, 150 KeV, 230 KeV, 310 KeV, 430 KeV, 500 KeV, 520 KeV, 600 KeV, etc.

[0050] As an example, the implantation dose of the second ion type ion implantation using the first mask layer as a mask can be , , , etc.

[0051] In step S3000, the steps of forming the first groove 301, the second groove 302 and the third groove 303 on the top of the first ion type substrate 201 include: removing the first mask layer, and forming a second pad oxide layer on the first ion type substrate 201 through a furnace tube thermal oxidation process; forming a first dielectric layer on the second pad oxide layer, and the first dielectric layer is used as a barrier layer for chemical mechanical polishing; using the second pad oxide layer and the dielectric layer as mask layers, performing photolithography and etching to form the first groove 301, the second groove 302 and the third groove 303 on the top of the first ion type substrate 201; filling the first groove 301, the second groove 302 and the third groove 303 based on a high-density plasma enhanced chemical vapor deposition process, and performing annealing to repair lattice damage; using chemical mechanical grinding to the first dielectric layer, and using a wet method to remove the remaining dielectric layer, to form an active area and an isolation area in the first ion type substrate 201.

[0052] In step S4000, a field oxide layer 304 is formed on the drift region 202 of the second ion type, including: forming a second dielectric layer on the top surface of the first ion type substrate 201 based on a furnace tube thermal oxidation process; using the second dielectric layer as a barrier layer for field region oxidation, and using photolithography and etching processes to define the field oxygen region to form a field oxygen barrier layer; forming the field oxide layer 304 by a thermal oxidation process, and removing the second dielectric layer and the second pad oxide layer by a wet method to form the field oxide layer 304.

[0053] As an example, after removing the first mask layer damaged by ion implantation, a PAD OX layer is regrown by thermal oxidation, and then a first dielectric layer (SiN) is grown as a barrier layer for CMP. After that, three grooves are formed by photolithography and etching, and then three grooves are filled by high-density plasma enhanced chemical vapor deposition (HD-PECVD), and annealing is performed to repair lattice damage, and then chemical mechanical polishing (CMP) is used to grind to SIN, and the remaining SiN is removed by wet method to form an active area and an isolation area. Then, a second dielectric layer (SiN) is regrown in the furnace tube as a barrier layer for field area oxidation, and then the field oxide area is defined by photolithography and etching, and the field oxide layer 304 is grown by thermal oxidation process, and finally SiN and Pad OX are removed by wet method to form a field oxide area. The field oxide layer can play a role in increasing the breakdown voltage.

[0054] As an example, see Figure 3 , Figure 3 The transistor structure is shown after the first trench 301, the second trench 302, the third trench 303 and the field oxide layer 304 are formed, the first trench 301 is close to one side of the substrate 201 of the first ion type, the third trench 303 is close to the other side of the substrate 201 of the first ion type, the second trench 302 is located between the third trench 303 and the drift region 202 of the second ion type, the first trench 301 is at least partially located in the drift region 202 of the second ion type, the top surface of the field oxide layer 304 is higher than the top surface of the substrate 201 of the first ion type, and the bottom surface of the field oxide layer 304 is higher than the bottom surface of the drift region 202 of the second ion type.

[0055] In step S5000, a gate oxide layer 401 is formed on a first ion type substrate 201, and a polysilicon layer 502 is formed on the gate oxide layer 401, including: forming a gate oxide layer 401 on the top surface of the first ion type substrate 201 based on a thermal oxidation process; depositing a polysilicon layer 502 on the gate oxide layer 401, and defining an area where the polysilicon layer 502 needs to be left by photolithography and etching; using a self-alignment process, photolithography, etching, and ion implantation of the first ion type to define a first ion type well region 503, a polysilicon layer 502, and a gate oxide layer 401.

[0056] Here, taking the depletion-type DENMOS device as an example, the well region of the first ion type (P-type) is tangent to the polysilicon gate, so that it can be avoided that a large number of P-type ions are contained on the channel surface after ion implantation, making it impossible for the device to have an original N-type conductive channel.

[0057] As an example, see Figure 4-Figure 5 The gate oxide layer 401 is in contact with the drift region 202 of the second ion type, the field oxide layer 304 and the substrate 201 of the first ion type, the polysilicon layer 502 is in contact with the field oxide layer 304 , and the well region 503 of the first ion type laterally spans the second trench 302 and is in contact with the third trench 303 .

[0058] The implantation energy of the first ion type ion implantation is 20 KeV to 280 KeV, and the implantation dose is to .

[0059] As an example, the implantation energy of the ion implantation of the first ion type may be 20 KeV, 90 KeV, 115 KeV, 200 KeV, 280 KeV, or the like.

[0060] As an example, the implantation dose of the first ion type ion implantation may be , , etc.

[0061] In step S6000 , the step of forming a second ion type lightly doped region 601 in a first ion type substrate 201 includes: performing ion implantation of the first ion type lightly doped region at a preset ion implantation angle.

[0062] The preset ion implantation angle is 15° to 45°, the implantation energy of the first ion type lightly doped region ion implantation is 50 KeV to 80 KeV, and the implantation dose of the first ion type lightly doped region ion implantation is to .

[0063] Here, ion implantation of the lightly doped region of the first ion type can not only suppress the hot carrier effect, but also neutralize the first ion type region under the gate oxide, so that an original conductive channel of the second ion type is formed under the channel after ion implantation annealing.

[0064] As an example, the preset ion implantation angle may be 15°, 25°, 40°, 45°, etc.

[0065] As an example, the implantation energy of the lightly doped region ion implantation of the first ion type may be 50 KeV, 60 KeV, 65 KeV, 70 KeV, 80 KeV, etc.

[0066] As an example, the implantation dose of the first ion type lightly doped region ion implantation may be , , , etc.

[0067] Here, the present application uses a self-aligned process to form a well region and combines it with an oblique angle ion implantation, so that the ions diffuse naturally after annealing to form a conductive channel with a high depletion resistance.

[0068] In step S7000, the steps of forming a first ion type source 603 in the first ion type well region 503 and forming a second ion type drain 604 in the second ion type drift region 202 include: performing ion implantation of the first ion type source 603 and performing ion implantation of the second ion type drain 604.

[0069] The injection energy of the first ion type source ion injection is 30 KeV to 50 KeV, and the injection dose is to The injection energy of the second ion type drain ion injection is 10 KeV to 15 KeV, and the injection dose is to .

[0070] As an example, the implantation energy of the first ion type source 603 ion implantation may be 30 KeV, 40 KeV, or 50 KeV.

[0071] As an example, the implantation dose of the first ion type source 603 ion implantation is , , , etc.

[0072] As an example, the implantation energy of the drain 604 ion implantation of the second ion type is 10 KeV, 12 KeV, 15 KeV, etc.

[0073] As an example, the implantation dose of the second ion type drain 604 ion implantation is , , , etc.

[0074] As an example, see Figure 6The lightly doped region 601 of the second ion type is located in the substrate 201 of the first ion type, the lightly doped region 601 of the second ion type is located between the drift region 202 of the second ion type and the well region 503 of the first ion type, the top surface of the lightly doped region 601 of the second ion type contacts the bottom surface of the gate oxide layer 401, and one side of the lightly doped region 601 of the second ion type contacts the well region 503 of the first ion type; the polysilicon gate sidewalls 602 are located on both sides of the polysilicon layer 502; the source 603 of the first ion type is located in the well region 503 of the first ion type, and the drain 604 of the second ion type is located in the drift region 202 of the second ion type.

[0075] In the preparation method of the depletion-mode transistor in the above-mentioned embodiment, in the process of forming the depletion-mode transistor, based on the self-alignment process, the gate oxide layer 401, the polysilicon layer 502 and the well region are formed in one step. There is no need to use different masks and plates during photolithography when forming the gate oxide layer 401, the polysilicon layer 502 and the well region, thereby reducing the use of additional masks, reducing the number of layers of the photolithography plate, and reducing the transistor production cost.

[0076] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0077] Based on the same inventive concept, the embodiment of the present disclosure also provides a depletion-mode transistor obtained by the method for preparing the depletion-mode transistor in the above embodiment. The implementation scheme for solving the problem provided by the depletion-mode transistor is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more depletion-mode transistor embodiments provided below can refer to the limitations of the preparation method of the depletion-mode transistor in the above text, and will not be repeated here.

[0078] In some embodiments, please refer to Figure 6A depletion-mode transistor includes: a substrate 201 of a first ion type; a drift region 202 of a second ion type, located on one side of the substrate 201 of the first ion type; a first trench 301, a second trench 302, and a third trench 303, located on the top of the substrate 201 of the first ion type, the first trench 301 is close to one side of the substrate 201 of the first ion type, the third trench 303 is close to the other side of the substrate 201 of the first ion type, the second trench 302 is located between the third trench 303 and the drift region 202 of the second ion type The first trench 301 is at least partially located in the drift region 202 of the second ion type; the field oxide layer 304 is located in the drift region 202 of the second ion type, the top surface of the field oxide layer 304 is higher than the top surface of the substrate 201 of the first ion type, and the bottom surface of the field oxide layer 304 is higher than the bottom surface of the drift region 202 of the second ion type; the gate oxide layer 401 and the polysilicon layer 502, the gate oxide layer 401 is located on the substrate 201 of the first ion type, the polysilicon layer 502 is located on the gate oxide layer 401, and the gate oxide layer 401 and the drift region 202 of the second ion type are connected. 202, the field oxide layer 304 is in contact with the substrate 201 of the first ion type, and the polysilicon layer 502 is in contact with the field oxide layer 304; the well region 503 of the first ion type is located in the substrate 201 of the first ion type, and the well region 503 of the first ion type crosses the second trench 302 laterally and contacts the third trench 303; the lightly doped region 601 of the second ion type is located in the substrate 201 of the first ion type, and the lightly doped region 601 of the second ion type is located between the drift region 202 of the second ion type and the first ion type The top surface of the second ion type lightly doped region 601 is in contact with the bottom surface of the gate oxide layer 401, and one side of the second ion type lightly doped region 601 is in contact with the first ion type well region 503; the polysilicon gate sidewall 602 is located on both sides of the polysilicon layer 502; the source 603 of the first ion type and the drain 604 of the second ion type, the source 603 of the first ion type is located in the well region 503 of the first ion type, and the drain 604 of the second ion type is located in the drift region 202 of the second ion type.

[0079] The depletion-mode transistor in the above embodiment forms the gate oxide layer 401, the polysilicon layer 502 and the well region in one step based on the self-alignment process, and does not need to use different masks and plates when performing photolithography when forming the gate oxide layer 401, the polysilicon layer 502 and the well region, thereby reducing the use of additional masks, reducing the number of layers of photolithography plates, and reducing the production cost of transistors. The technical features of the above embodiment can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above embodiment are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for preparing a depletion-mode transistor, characterized in that: The method comprises: providing a substrate of a first ion type; forming a drift region of a second ion type on one side of the substrate of the first ion type; Forming a first trench, a second trench and a third trench on the top of the substrate of the first ion type, wherein the first trench is close to one side of the substrate of the first ion type, the third trench is close to the other side of the substrate of the first ion type, the second trench is located between the third trench and the drift region of the second ion type, and the first trench is at least partially located in the drift region of the second ion type; forming a field oxide layer on the drift region of the second ion type, wherein the top surface of the field oxide layer is higher than the top surface of the substrate of the first ion type, and the bottom surface of the field oxide layer is higher than the bottom surface of the drift region of the second ion type; Using a self-aligned process, a gate oxide layer is formed on the substrate of the first ion type, a polysilicon layer is formed on the gate oxide layer, and a well region of the first ion type is formed in the substrate of the first ion type, the gate oxide layer is in contact with a drift region of the second ion type, a field oxide layer and the substrate of the first ion type, the polysilicon layer is in contact with the field oxide layer, and the well region of the first ion type laterally spans the second trench and is in contact with the third trench; forming a lightly doped region of a second ion type in a substrate of the first ion type, the lightly doped region of the second ion type being located between a drift region of the second ion type and a well region of the first ion type, the top surface of the lightly doped region of the second ion type being in contact with the bottom surface of the gate oxide layer, and one side of the lightly doped region of the second ion type being in contact with the well region of the first ion type; forming polysilicon gate sidewalls on both sides of the polysilicon layer; A source of a first ion type is formed in the well region of the first ion type, and a drain of a second ion type is formed in the drift region of the second ion type.

2. The preparation method according to claim 1, characterized in that: Forming a drift region of a second ion type on one side of the substrate of the first ion type, comprising: Forming a first pad oxide layer on the substrate of the first ion type by a furnace thermal oxidation process; Performing photolithography on the pad oxide layer to form a first mask layer, wherein the first mask layer exposes a first pattern required for forming a drift region of a second ion type; Ion implantation of a second ion type is performed using the first mask layer as a mask to form a drift region of the second ion type on one side of the substrate of the first ion type.

3. The preparation method according to claim 2, characterized in that: The second ion type ion implantation is performed using the first mask layer as a mask, and the implantation energy is 30 KeV to 600 KeV, and the implantation dose is to .

4. The preparation method according to claim 1, characterized in that: The steps of forming a first trench, a second trench and a third trench on the top of the substrate of the first ion type include: removing the first mask layer, and forming a second pad oxide layer on the substrate of the first ion type through a furnace thermal oxidation process; forming a first dielectric layer on the second pad oxide layer, wherein the first dielectric layer is used as a barrier layer for chemical mechanical polishing; Using the second pad oxide layer and the dielectric layer as mask layers, photolithography and etching are performed to form a first trench, a second trench, and a third trench on the top of the first ion type substrate; Filling the first trench, the second trench and the third trench based on a high-density plasma enhanced chemical vapor deposition process, and performing annealing to repair lattice damage; Chemical mechanical polishing is performed to the first dielectric layer, and the remaining dielectric layer is removed by wet method to form an active region and an isolation region in the first ion type substrate.

5. The preparation method according to claim 1, characterized in that: Forming a field oxide layer on the drift region of the second ion type includes: Based on a furnace tube thermal oxidation process furnace tube, forming a second dielectric layer on the top surface of the first ion type substrate; Using the second dielectric layer as a barrier layer for field region oxidation, photolithography and etching processes are used to define the field oxygen region to form a field oxygen barrier layer; A field oxide layer is formed by utilizing a thermal oxidation process, and the second dielectric layer and the second pad oxide layer are removed by a wet method to form a field oxide layer.

6. The preparation method according to claim 1, characterized in that: Forming a gate oxide layer on the substrate of the first ion type, and forming a polysilicon layer on the gate oxide layer, comprising: Forming a gate oxide layer on the top surface of the substrate of the first ion type based on a thermal oxidation process; Depositing a polysilicon layer on the gate oxide layer, and defining the area where the polysilicon layer needs to be left by photolithography and etching; By utilizing a self-alignment process, photolithography, etching, and ion implantation of the first ion type, a well region, a polysilicon layer, and a gate oxide layer of the first ion type are defined.

7. The preparation method according to claim 6, characterized in that: The implantation energy of the first ion type ion implantation is 20 KeV to 280 KeV, and the implantation dose is to .

8. The preparation method according to claim 1, characterized in that: The step of forming a lightly doped region of a second ion type in a substrate of the first ion type comprises: Performing ion implantation of a first ion type into the lightly doped region at a preset ion implantation angle; The preset ion implantation angle is 15° to 45°, the implantation energy of the first ion type lightly doped region ion implantation is 50 KeV to 80 KeV, and the implantation dose of the first ion type lightly doped region ion implantation is to .

9. The preparation method according to claim 1, characterized in that: The steps of forming a source of the first ion type in the trap region of the first ion type and forming a drain of the second ion type in the drift region of the second ion type include: Performing source ion implantation of a first ion type and performing drain ion implantation of a second ion type; The injection energy of the first ion type source ion injection is 30 KeV to 50 KeV, and the injection dose is to The injection energy of the second ion type drain ion injection is 10 KeV to 15 KeV, and the injection dose is to .

10. A depletion mode transistor, characterized in that: include: a substrate of a first ion type; A drift region of a second ion type is located on one side of the substrate of the first ion type; A first trench, a second trench and a third trench are located on the top of the substrate of the first ion type, the first trench is close to one side of the substrate of the first ion type, the third trench is close to the other side of the substrate of the first ion type, the second trench is located between the third trench and the drift region of the second ion type, and the first trench is at least partially located in the drift region of the second ion type; a field oxide layer, located in the drift region of the second ion type, wherein the top surface of the field oxide layer is higher than the top surface of the substrate of the first ion type, and the bottom surface of the field oxide layer is higher than the bottom surface of the drift region of the second ion type; A gate oxide layer and a polysilicon layer, wherein the gate oxide layer is located on the substrate of the first ion type, the polysilicon layer is located on the gate oxide layer, the gate oxide layer is in contact with a drift region of the second ion type, a field oxide layer and the substrate of the first ion type, and the polysilicon layer is in contact with the field oxide layer; A trap region of a first ion type is located in the substrate of the first ion type, the trap region of the first ion type laterally spans the second trench and contacts the third trench; A lightly doped region of a second ion type is located in the substrate of the first ion type, the lightly doped region of the second ion type is located between a drift region of the second ion type and a well region of the first ion type, a top surface of the lightly doped region of the second ion type is in contact with a bottom surface of the gate oxide layer, and a side of the lightly doped region of the second ion type is in contact with the well region of the first ion type; Polysilicon gate sidewalls, located on both sides of the polysilicon layer; A source of a first ion type and a drain of a second ion type, wherein the source of the first ion type is located in a well region of the first ion type, and the drain of the second ion type is located in a drift region of the second ion type.

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