Display apparatus and method of manufacturing same

Abstract

The present application provides a display apparatus and a method of manufacturing the same, the display apparatus including: a substrate including an emission area and a non-emission area; a first light emitting element on the emission region of the substrate; a pixel defining layer on the non-emission region of the substrate and defining a first opening; a bank layer on the pixel defining layer, defining a second opening, and including a conductive material; a first encapsulation layer on the first light emitting element and including an inorganic material; and a second encapsulation layer on the first encapsulation layer and containing an organic material, in which a cavity is formed between the first encapsulation layer and the bank layer in a direction perpendicular to the substrate, the cavity overlaps the emission region and the non-emission region, and the cavity is filled with the second encapsulation layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0161837 filed in the Korean Intellectual Property Office on November 21, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Aspects of some embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background Art

[0004] With the development of the information society, more and more demands are put forward for display devices that display images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, and an organic light-emitting display device. In the light-emitting display device among the flat panel display devices, because each pixel of the display panel generally includes a light-emitting element that can emit light by itself, an image can be displayed without a backlight unit that provides light to the display panel.

[0005] Recently, with the development of various electronic devices, consumers' demand for high-resolution display devices is also increasing. Because high-resolution display devices may require high pixel integration density, the interval between light-emitting elements overlapping each emission area may be narrowed. Therefore, high-resolution display devices can be formed by a pattern process that forms individual pixels instead of a mask process.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0007] Aspects of the present disclosure provide a high-resolution display device by forming a light emitting element through a photolithography patterning process without a mask.

[0008] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to some embodiments of the present disclosure, a display device includes: a substrate including an emission region and a non-emission region; a first light-emitting element on the emission region of the substrate; a pixel defining layer located on the non-emission region of the substrate and defining a first opening; a levee layer located on the pixel defining layer, defining a second opening and comprising a conductive material; a first encapsulation layer located on the first light-emitting element and comprising an inorganic material; and a second encapsulation layer located on the first encapsulation layer and comprising an organic material, wherein a cavity is formed between the first encapsulation layer and the levee layer in a direction perpendicular to the substrate, the cavity overlaps with the emission region and the non-emission region, and the cavity is filled with the second encapsulation layer.

[0010] According to some embodiments, the display device may further include a second light-emitting element separated from the first light-emitting element, and a dam layer is inserted between the first light-emitting element and the second light-emitting element, wherein the first light-emitting element includes: a first anode electrode on a substrate; a first light-emitting layer on the first anode electrode; and a first cathode electrode on the first light-emitting layer, and the second light-emitting element includes: a second anode electrode separated from the first anode electrode, and a pixel defining layer is inserted between the first anode electrode and the second anode electrode; a second light-emitting layer on the second anode electrode; and a second cathode electrode on the second light-emitting layer.

[0011] According to some embodiments, the bank layer may include a first side surface contacting the first cathode electrode, a second side surface contacting the second cathode electrode, and a first surface contacting the second encapsulation layer and connecting the first side surface to the second side surface.

[0012] According to some embodiments, the first cathode electrode and the second cathode electrode may be electrically connected through a bank layer.

[0013] According to some embodiments, the first light emitting layer may contact the first side surface, and the second light emitting layer may contact the second side surface.

[0014] According to some embodiments, the first encapsulation layer may include a first inorganic layer contacting the first light emitting element and a second inorganic layer contacting the second light emitting element, and the first inorganic layer and the second inorganic layer are spaced apart from each other in a portion overlapping the non-emission region.

[0015] According to some embodiments, the cavity formed between the bank layer and the first inorganic layer in a direction perpendicular to the substrate may have a first height, and the cavity formed between the bank layer and the second inorganic layer in a direction perpendicular to the substrate may have a second height.

[0016] According to some embodiments, the first height and the second height may be different from each other.

[0017] According to some embodiments, the second height may be greater than the first height.

[0018] According to some embodiments, the first surface may not be in contact with the first encapsulation layer.

[0019] According to some embodiments, the first surface may be spaced apart from the first encapsulation layer with the cavity interposed between the first surface and the first encapsulation layer.

[0020] According to some embodiments, the display device may further include a residual pattern between the first anode electrode and the pixel defining layer in a direction perpendicular to the substrate, wherein the residual pattern may be in contact with the first light emitting layer.

[0021] According to some embodiments, in plan view, the first opening may be completely surrounded by the second opening.

[0022] According to some embodiments, the display device may further include an auxiliary encapsulation layer between the first encapsulation layer and the second encapsulation layer, wherein the auxiliary encapsulation layer completely covers the first encapsulation layer in a portion overlapping with the emission area and the non-emission area, and the auxiliary encapsulation layer contacts the first surface, and the auxiliary encapsulation layer completely covers the first surface.

[0023] According to some embodiments of the present disclosure, a display device may include: a substrate including a first emission region, a second emission region, and a non-emission region between the first emission region and the second emission region; a first light-emitting element on the first emission region of the substrate; a second light-emitting element on the second emission region of the substrate; a pixel defining layer located on the non-emission region of the substrate and defining a first opening; a levee layer defining a second opening on the pixel defining layer; a first inorganic layer located on the first light-emitting element; a second inorganic layer located on the second light-emitting element and separated from the first inorganic layer; and an organic encapsulation layer located on the first inorganic layer and the second inorganic layer, wherein the first light-emitting element and the first inorganic layer are in contact with one side surface of the levee layer facing the first emission region, and the second light-emitting element and the second inorganic layer are in contact with another side surface of the levee layer facing the second emission region, and the first inorganic layer and the second inorganic layer are separated from each other without overlapping with the non-emission region.

[0024] According to some embodiments, the first opening may be internal to the second opening.

[0025] According to some embodiments, the bank layer may include a first surface facing the organic encapsulation layer, and the first and second inorganic layers may include a protrusion that protrudes more toward the organic encapsulation layer than the first surface.

[0026] According to some embodiments, the display device may further include a residual pattern between the substrate and the pixel defining layer in a direction perpendicular to the substrate, wherein the residual pattern and the protrusion may not overlap each other.

[0027] According to some embodiments of the present disclosure, a method for manufacturing a display device includes: forming a substrate including an emission region and a non-emission region, an anode electrode on the emission region of the substrate, and a sacrificial layer on the anode electrode, and forming a pixel defining layer completely covering the sacrificial layer and the substrate, and a dam material layer completely covering the pixel defining layer; forming a photoresist on the dam material layer, etching the dam material layer and the pixel defining layer overlapping the anode electrode to expose the sacrificial layer, and then etching the sidewalls of the dam material layer and the sacrificial layer to expose the anode electrode and form the dam layer; forming a light-emitting layer and a cathode electrode on the anode electrode and the photoresist, and forming a first encapsulation layer on the cathode electrode; and removing the light-emitting layer, the cathode electrode, and the first encapsulation layer located in other areas except the emission region and the peripheral portion of the emission region, wherein, when the light-emitting layer and the cathode electrode are removed, a cavity is formed between the first encapsulation layer and the dam layer in a direction perpendicular to the substrate.

[0028] According to some embodiments, when etching the sidewall of the bank material layer to form the bank layer, the photoresist may form a tip that protrudes more toward the emission region than the sidewall of the bank layer.

[0029] A display device according to some embodiments may form a light-emitting element overlapping each emission region without a mask by using a photoresist having a tip protruding toward the emission region during a manufacturing process of the display device. In addition, a display device according to some embodiments may include a dam structure including a conductive material in a portion overlapping a non-emission region.

[0030] Therefore, the display device according to some embodiments can form separate pixels in the portion overlapping each emission region, and the separate pixels can be electrically connected through the embankment structure. Therefore, the display device according to some embodiments can provide a high-resolution display device that is relatively easy to manufacture.

[0031] However, the features of the embodiments of the present disclosure are not limited to the features illustrated and described above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent by describing aspects of some embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0033] Figure 1 is a perspective view of an electronic device according to some embodiments;

[0034] Figure 2 is a perspective view showing a display device included in an electronic device according to some embodiments;

[0035] Figure 3 According to some embodiments Figure 2 A schematic cross-sectional view of a display device;

[0036] Figure 4 is a diagram showing that according to some embodiments Figure 3 A plan view of the arrangement of the emission regions in the display area;

[0037] Figure 5 According to some embodiments, Figure 4 A schematic cross-sectional view of a display area taken along line X1-X1';

[0038] Figure 6 According to some embodiments Figure 5 An enlarged schematic cross-sectional view of a first emission region and a second emission region in FIG.

[0039] Figure 7 According to some embodiments Figure 5 An enlarged schematic cross-sectional view of the second emission region and the third emission region in FIG.

[0040] Figure 8 According to some embodiments, Figure 4 A schematic cross-sectional view of a display layer according to some embodiments, taken along line X1-X1';

[0041] Fig. 9 According to some embodiments, Figure 4 A schematic cross-sectional view of a display layer according to some embodiments, taken along line X1-X1';

[0042] Fig.10 According to some embodiments, Figure 4 A schematic cross-sectional view of a display layer according to some embodiments, taken along line X1-X1'; and

[0043] Figures 11 to 19 is a diagram showing that according to some embodiments, Figure 5 A cross-sectional view of a schematic manufacturing method of a display layer in a display device. DETAILED DESCRIPTION

[0044] Hereinafter, the aspects of some embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always represent the same elements. However, the present disclosure can be implemented in various different forms and should not be understood as being limited to the embodiments described herein. Specifically, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects and features of the present disclosure will be fully conveyed to those skilled in the art. Therefore, it is not necessary to describe processes, elements and techniques for those of ordinary skill in the art in order to fully understand the aspects and features of the present disclosure. Unless otherwise stated, in all drawings and written descriptions, the same reference numerals represent the same elements, and therefore, the redundant description of the same elements may not be repeated.

[0045] When a certain embodiment can be implemented differently, the specific process order may be different from the described order. For example, two processes described in succession may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0046] In the accompanying drawings, for the sake of clarity, the relative size, thickness and ratio of elements, layers and regions can be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "below", "below", "below", "below", "above", "on", etc. can be used in this article to describe the relationship between an element (multiple elements) or feature (multiple features) and another (multiple) element or another (multiple) feature as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms are intended to include different orientations of the device in use or in operation. For example, if the device in the accompanying drawings flips, the element described as "below" or "below" or "below" of other elements or features will be oriented to "above" other elements or features. Therefore, the exemplary terms "below" and "below" can cover both above and below orientations. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly.

[0047] In the drawings, the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other or substantially perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0048] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer or first section described below may be referred to as the second element, second component, second region, second layer or second section.

[0049] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, the layer, region, or element may be directly electrically connected to the other layer, region, or element, and / or the layer, region, or element and the other layer, region, or element may be indirectly electrically connected with one or more intervening layers, regions, or elements therebetween. In addition, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0050] The terms used herein are for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, as used herein, the singular forms "one" and "the" are intended to also include plural forms. It will also be understood that the terms "include", "comprise", "include", "include", "have", "have" and "have", when used in this specification, specify the existence of the described features, wholes, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items. For example, the statement "A and / or B" means A, B, or A and B. When a statement such as "at least one of ..." is after an element list, the elements of the entire list are modified, rather than the individual elements of the list. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or any combination of one or more of a, b, and.

[0051] As used herein, the terms "substantially," "about," and similar terms are used as approximate terms rather than as terms of degree, and are intended to allow for the inherent deviations of measurements or calculations that one of ordinary skill in the art will recognize. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0053] Figure 1 is a schematic perspective view of an electronic device 1 according to some embodiments.

[0054] refer to Figure 1 , the electronic device 1 displays a moving image (e.g., a video image) or a still image (e.g., a static image). The electronic device 1 may refer to any electronic device that provides a display screen. Examples of the electronic device 1 may include, for example, a television that provides a display screen, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, a video camera, etc.

[0055] Figure 1A first direction (X-axis direction), a second direction (Y-axis direction) and a third direction (Z-axis direction) are defined. The first direction (X-axis direction) and the second direction (Y-axis direction) may be perpendicular to each other, the first direction (X-axis direction) and the third direction (Z-axis direction) may be perpendicular to each other, and the second direction (Y-axis direction) and the third direction (Z-axis direction) may be perpendicular to each other. It can be understood that the first direction (X-axis direction) refers to the horizontal direction in the accompanying drawings, the second direction (Y-axis direction) refers to the vertical direction in the accompanying drawings, and the third direction (Z-axis direction) refers to the upward direction and the downward direction (i.e., the thickness direction) in the accompanying drawings. In the following description, unless otherwise specified, "direction" may refer to two directions extending along the direction. In addition, when it is necessary to distinguish between two "directions" extending on both sides, one side will be referred to as "one side in the direction", and the other side will be referred to as "the other side in the direction". Reference Figure 1 , wherein the direction in which an arrow indicating a direction points is referred to as one side, and the direction opposite to the direction in which the arrow indicating the direction points is referred to as the other side.

[0056] In the following, in order to simplify the description, when referring to the surface of the electronic device 1 or each component constituting the electronic device 1, a surface facing one side in the direction in which the image is displayed (i.e., the third direction (Z-axis direction)) is referred to as the top surface, and the surface opposite to the one surface is referred to as the other surface. However, the present disclosure is not limited to this, and one surface and the other surface of the component may be referred to as the front surface and the rear surface, respectively, or may also be referred to as the first surface or the second surface. In addition, when describing the relative position of each of the components of the electronic device 1, one side of the third direction (Z-axis direction) may be referred to as the upper side, and the other side of the third direction (Z-axis direction) may be referred to as the lower side.

[0057] The shape of the electronic device 1 can be variously modified. For example, the electronic device 1 can have a shape such as a horizontally elongated rectangular shape, a vertically elongated rectangular shape, a square shape, a quadrilateral shape with rounded corners (vertices), other polygonal shapes, and a circular shape.

[0058] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where a picture or image can be displayed, and the non-display area NDA is an area where a picture or image is not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may substantially occupy the center of the electronic device 1.

[0059] Figure 2 is a perspective view illustrating a display device 10 included in the electronic device 1 according to some embodiments.

[0060] refer to Figure 2 According to one embodiment, an electronic device 1 may include a display device 10. The display device 10 may provide a picture displayed by the electronic device 1. Examples of the display device 10 may include an inorganic light emitting diode display device, an organic light emitting display device, a quantum dot light emitting display device, a plasma display device, and a field emission display device. In the following description, an example of applying an organic light emitting diode display device as a display device will be described, but the embodiments according to the present disclosure are not limited thereto, and other display devices may be applied within the spirit and scope of the embodiments according to the present disclosure.

[0061] The display device 10 may have a planar shape similar to that of the electronic device 1. For example, in a plan view, the display device 10 may have a shape similar to a rectangular shape having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). The edge where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) meet may be rounded to have a curvature, but is not limited thereto, and may be formed at a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape, and may be formed in a shape similar to another polygonal shape, a circular shape, or an elliptical shape.

[0062] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0063] The display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA arranged around the display area DA (eg, around the display area DA or outside the footprint of the display area DA).

[0064] The display area DA may emit light from a plurality of openings or a plurality of emission areas to be described later. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening, and a self-luminous element. For example, the self-luminous element may include at least one of an organic light-emitting diode (LED) including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, and a micro-LED, but is not limited thereto. In the following figures, the case where the self-luminous element is an organic light-emitting diode is shown by way of example.

[0065] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100 .

[0066] The sub-region SBA may be a region extending from one side of the main region MA. The sub-region SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (e.g., the third direction (Z-axis direction)). The sub-region SBA may include a display driver 200 and a pad portion connected to the circuit board 300. According to some embodiments, the sub-region SBA may be omitted, and the display driver 200 and the pad portion may be located in the non-display area NDA.

[0067] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be located in the sub-region SBA and may overlap with the main region MA in the thickness direction by bending of the sub-region SBA. For another example, the display driver 200 may be mounted on the circuit board 300.

[0068] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0069] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to the touch sensor layer 180 (see FIG. 1 ) of the display panel 100. Figure 3 ). The touch driver 400 may be formed as an integrated circuit.

[0070] Figure 3 yes Figure 2 Schematic cross-sectional view of a display device 10.

[0071] refer to Figure 3 , the display panel 100 may include a display layer DPL, a touch sensor layer 180 and a color filter layer 190. The display layer DPL may include a substrate 110, a thin film transistor layer 130, a display element layer 150 and a thin film encapsulation layer 170.

[0072] The substrate 110 may be a base substrate or a base member. The substrate 110 may be a flexible substrate that can be bent, folded, or rolled without damaging the display device 10. For example, the substrate 110 may include a polymer resin such as polyimide (PI), but is not limited thereto according to embodiments of the present disclosure. According to some embodiments, the substrate 110 may include a glass material or a metal material.

[0073] The thin film transistor layer 130 may be located on the substrate 110. The thin film transistor layer 130 may be located in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor layer 130 may include a pixel PX (see Figure 4 ) of a plurality of thin film transistors TFT (see Figure 5 ).

[0074] The display element layer 150 may be located on the thin film transistor layer 130. The display element layer 150 may be located to overlap with the display area DA. The display element layer 150 may include a plurality of display elements ED (see Figure 5 ). For example, the display element according to some embodiments may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but embodiments according to the present disclosure are not limited thereto.

[0075] The thin film encapsulation layer 170 may be located on the display element layer 150. The thin film encapsulation layer 170 may be positioned to overlap the display area DA and the non-display area NDA. For example, the thin film encapsulation layer 170 may extend to cover the entire display area DA and enter the non-display area NDA. The thin film encapsulation layer 170 may cover the top surface and the side surface of the display element layer 150 and protect the display element layer 150 from external oxygen and moisture. The thin film encapsulation layer 170 may include at least one inorganic layer and at least one organic layer for encapsulating the display element layer 150.

[0076] The touch sensor layer 180 may be located on the thin film encapsulation layer 170. The touch sensor layer 180 may be located to overlap the display area DA and the non-display area NDA. The touch sensor layer 180 may sense a user's touch by using a mutual capacitance method or a self capacitance method.

[0077] The color filter layer 190 may be located on the touch sensor layer 180. The color filter layer 190 may be located to overlap the display area DA and the non-display area NDA. The color filter layer 190 may absorb part of the light from outside the display device 10 to reduce the reflected light due to the external light. Therefore, the color filter layer 190 may prevent or reduce the color distortion caused by the reflection of the external light.

[0078] Since the color filter layer 190 is directly located on the touch sensor layer 180, the display device 10 may not require a separate substrate for the color filter layer 190. Therefore, the thickness of the display device 10 may be relatively small. In addition, according to some embodiments, the color filter layer 190 may be omitted.

[0079] like Figure 3As shown in , a portion of the display layer DPL overlapping the sub-area SBA may be bent. When the portion of the display layer DPL is bent, the display driver 200, the circuit board 300, and the touch driver 400 may overlap the main area MA in the third direction (Z-axis direction).

[0080] Figure 4 It is shown Figure 3 FIG. 1 is a plan view of an exemplary arrangement of emission areas EA in a display area DA.

[0081] refer to Figure 4 According to some embodiments, the display area DA may include a plurality of first, second, and third emission areas EA1, EA2, and EA3 and a non-emission area NLA. The non-emission area NLA may be positioned to surround the plurality of first, second, and third emission areas EA1, EA2, and EA3.

[0082] The non-emission area NLA may block each light emitted from the plurality of first emission areas EA1, the second emission area EA2, and the third emission area EA3. Therefore, the non-emission area NLA may help prevent or reduce the mixing of the corresponding lights emitted from the plurality of first emission areas EA1, the second emission areas EA2, and the third emission areas EA3. The inorganic pixel defining layer 151 (see Figure 5 ) and the bank layer 161 (see Figure 5 ) can be located in the non-emission area NLA.

[0083] The emission area EA may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that emit light of different colors. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may emit red light, green light, and blue light, respectively, and the color of the light emitted from each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be different according to the type of light emitting element ED to be described later. According to some embodiments, the first emission area EA1 may emit red light of a first color, the second emission area EA2 may emit green light of a second color, and the third emission area EA3 may emit green light of a third color, but is not limited thereto according to the embodiments of the present disclosure. In the accompanying drawings, the size and shape of each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 are shown to be the same, but are not limited thereto. The size and shape of each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be freely adjusted according to the desired characteristics.

[0084] A plurality of first emission areas EA1, second emission areas EA2, and third emission areas EA3 may be defined by a first opening OP1 and a second opening OP2. For example, the first opening OP1 may be defined by an inorganic pixel defining layer 151 to be described later, and the second opening OP2 may be defined by a bank layer 161, which will be described later. In a plan view, the second opening OP2 may completely surround the first opening OP1, and the second opening OP2 may be completely surrounded by the non-emission area NLA.

[0085] According to some embodiments, at least one first emission region EA1, at least one second emission region EA2, and at least one third emission region EA3 positioned adjacent to each other may constitute a pixel group PXG. The pixel group PXG may be the smallest unit emitting white light. However, the types and / or quantities of the first emission region EA1, the second emission region EA2, and the third emission region EA3 constituting the pixel group PXG may be variously changed according to the embodiments.

[0086] Figure 5 It is along Figure 4 Schematic cross-sectional view of the display area DA taken along line X1 - X1 ′. Figure 5 1 is a partial cross-sectional view of the display device 10 overlapping with the display area DA, and shows a schematic cross section of the display layer DPL. That is, Figure 5 The cross-section of the substrate 110, the thin film transistor layer 130, the display element layer 150 and the thin film encapsulation layer 170 of the display device 10 according to some embodiments is shown. Figure 3 The substrate 110 is described in detail in FIG. 1 , so the description of the substrate 110 will be omitted.

[0087] refer to Figure 5 , the thin film transistor layer 130 may be located on the substrate 110. The thin film transistor layer 130 may include a first buffer layer 111, a thin film transistor TFT, a gate insulating layer 113, a first interlayer insulating layer 121, a capacitor electrode CPE, a second interlayer insulating layer 123, a first connection electrode CNE1, a first through hole layer 125, a second connection electrode CNE2, and a second through hole layer 127.

[0088] The first buffer layer 111 may be located on the substrate 110. The first buffer layer 111 may include an inorganic layer capable of preventing or reducing air or moisture penetration. For example, the first buffer layer 111 may include a plurality of inorganic layers alternately stacked.

[0089] The thin film transistor TFT may be located on the first buffer layer 111 and may constitute a pixel circuit of each of the plurality of pixels. For example, the thin film transistor TFT may be a switching transistor or a driving transistor of the pixel circuit. The thin film transistor TFT may include an active layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0090] The active layer ACT may be located on the first buffer layer 111. The active layer ACT may overlap the gate electrode GE in the third direction (Z-axis direction) and may be insulated from the gate electrode GE by the gate insulating layer 113. In a portion of the active layer ACT, the material of the active layer ACT may be made into a conductor to form a source electrode SE and a drain electrode DE.

[0091] The gate electrode GE may be located on the gate insulating layer 113. The gate electrode GE may overlap the active layer ACT with the gate insulating layer 113 interposed therebetween.

[0092] The gate insulating layer 113 may be on the active layer ACT. The gate insulating layer 113 may cover the active layer ACT and the first buffer layer 111 and may insulate the active layer ACT from the gate electrode GE. The gate insulating layer 113 may include a contact hole through which the first connection electrode CNE1 passes.

[0093] The first interlayer insulating layer 121 may cover the gate electrode GE and the gate insulating layer 113. The first interlayer insulating layer 121 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer 121 may be connected to the contact hole of the gate insulating layer 113 and the contact hole of the second interlayer insulating layer 123.

[0094] The capacitor electrode CPE may be located on the first interlayer insulating layer 121. The capacitor electrode CPE may overlap the gate electrode GE in the third direction (Z-axis direction). The capacitor electrode CPE and the gate electrode GE may form a capacitance.

[0095] The second interlayer insulating layer 123 may cover the capacitor electrode CPE and the first interlayer insulating layer 121. The second interlayer insulating layer 123 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer 123 may be connected to the contact hole of the first interlayer insulating layer 121 and the contact hole of the gate insulating layer 113.

[0096] The first connection electrode CNE1 may be located on the second interlayer insulating layer 123. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole provided in the first interlayer insulating layer 121, the second interlayer insulating layer 123, and the gate insulating layer 113 to contact the drain electrode DE of the thin film transistor TFT.

[0097] The first via layer 125 may cover the first connection electrode CNE1 and the second interlayer insulating layer 123. The first via layer 125 may planarize the lower structure. The first via layer 125 may include a contact hole through which the second connection electrode CNE2 passes.

[0098] The second connection electrode CNE2 may be located on the first via layer 125. The second connection electrode CNE2 may be inserted into a contact hole formed in the first via layer 125 to contact the first connection electrode CNE1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the first, second, and third anode electrodes AE1, AE3.

[0099] The second via layer 127 may cover the second connection electrode CNE2 and the first via layer 125. The second via layer 127 may include contact holes through which the first, second, and third anode electrodes AE1, AE3 pass.

[0100] The display element layer 150 may be located on the second via hole layer 127. The display element layer 150 may include a light emitting element ED, an inorganic pixel defining layer 151, a residual pattern 153, and a bank layer 161.

[0101] The light emitting element ED according to some embodiments may include a first light emitting element ED1 located in a portion overlapping with the first emission region EA1, a second light emitting element ED2 located in a portion overlapping with the second emission region EA2, and a third light emitting element ED3 located in a portion overlapping with the third emission region EA3. The first light emitting element ED1 may include a first anode electrode AE1, a first light emitting layer EL1, and a first cathode electrode CE1, the second light emitting element ED2 may include a second anode electrode AE2, a second light emitting layer EL2, and a second cathode electrode CE2, and the third light emitting element ED3 may include a third anode electrode AE3, a third light emitting layer EL3, and a third cathode electrode CE3. Each of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may emit light of different colors according to the materials of the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3. For example, the first light emitting element ED1 may emit red light of a first color, the second light emitting element ED2 may emit green light of a second color, and the third light emitting element ED3 may emit blue light of a third color.

[0102] The first to third anode electrodes AE1, AE2, and AE3 according to some embodiments may be located on the second via layer 127. The first to third anode electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first and second connection electrodes CNE1 and CNE2.

[0103] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may include a first anode electrode AE1 located in the first emission area EA1, a second anode electrode AE2 located in the second emission area EA2, and a third anode electrode AE3 located in the third emission area EA3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be positioned on the second through hole layer 127 to be spaced apart from each other.

[0104] According to some embodiments, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may have a structure formed by stacking a material layer having a high work function, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (In 2 O 3)) and a stacked structure formed of a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. For example, the first anode electrode AE1, the second anode electrode AE2 and the third anode electrode AE3 may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag and ITO / Ag / ITO, but are not limited thereto.

[0105] The inorganic pixel defining layer 151 may be positioned on the second via hole layer 127 and the first, second, and third anode electrodes AE1, AE2, and AE3. The inorganic pixel defining layer 151 may be positioned in a portion overlapping the non-emission area NLA.

[0106] The inorganic pixel defining layer 151 according to some embodiments may define a first opening OP1 overlapping the first emission area EA1, the second emission area EA2, and the third emission area EA3. The inorganic pixel defining layer 151 may be completely located on the second through-hole layer 127, and may expose portions of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. In other words, the inorganic pixel defining layer 151 may expose the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 in a portion overlapping the first opening OP1.

[0107] The inorganic pixel defining layer 151 may include an inorganic insulating material. For example, the inorganic pixel defining layer 151 may include at least one of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0108] The bank layer 161 may be positioned on the inorganic pixel defining layer 151. The bank layer 161 may define a second opening OP2 defining the first, second, and third emission areas EA1, EA2, and EA3, and the light emitting element ED according to some embodiments may be arranged to overlap the second opening OP2.

[0109] The bank layer 161 according to some embodiments may include a conductive metal material. For example, the bank layer 161 may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0110] According to some embodiments, the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 may be located on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3, respectively. The first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 may be organic light emitting layers made of organic materials, and may be formed on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3, respectively, by a deposition process. For the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3, when the thin film transistor TFT applies a voltage (e.g., a set voltage or a predetermined voltage) to the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3, and the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 receive a common voltage or a cathode voltage, each of the holes and the electrons may move to the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 through the hole transport layer and the electron transport layer, and the holes and the electrons may be recombined with each other in the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 to emit light.

[0111] The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may include the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 located in the corresponding emission areas EA1, EA2, and EA3. For example, the first light-emitting layer EL1 may be a light-emitting layer emitting red light of a first color, the second light-emitting layer EL2 may be a light-emitting layer emitting green light of a second color, and the third light-emitting layer EL3 may be a light-emitting layer emitting blue light of a third color, but the present disclosure is not limited thereto.

[0112] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 according to some embodiments may be spaced apart from each other in the third direction (Z-axis direction) from the inorganic pixel defining layer 151. The residual pattern 153 may be positioned in a portion where the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 are separated from the inorganic pixel defining layer 151. The residual pattern 153 will be described later.

[0113] The first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 may be located on the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3, respectively. The first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 may include a transparent conductive material so that light generated in the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 may be emitted. The first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 may receive a common voltage or a low potential voltage. When the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 receive a voltage corresponding to the data voltage and the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 receive a low potential voltage, a potential difference is formed between the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 and the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3, so that the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 may emit light.

[0114] According to some embodiments, the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 may include a material layer having a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). The first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 may further include a transparent metal oxide layer on the material layer having a low work function.

[0115] The first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 may include the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 located in the corresponding emission areas EA1, EA2, and EA3. The first cathode electrode CE1 may be located on the first light emitting layer EL1 in the first emission area EA1, the second cathode electrode CE2 may be located on the second light emitting layer EL2 in the second emission area EA2, and the third cathode electrode CE3 may be located on the third light emitting layer EL3 in the third emission area EA3.

[0116] The first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 included according to some embodiments may be spaced apart from each other while overlapping the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. In other words, the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 included according to some embodiments may not be directly connected but may be electrically connected through the bank layer 161.

[0117] The thin film encapsulation layer 170 may be positioned on the display element layer 150. The thin film encapsulation layer 170 according to some embodiments may include a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175 that are sequentially stacked.

[0118] The first encapsulation layer 171 may be positioned on the bank layer 161 and the first, second, and third cathode electrodes CE1, CE2, and CE3, and the first encapsulation layer 171 may contact the bank layer 161 and the first, second, and third cathode electrodes CE1, CE2, and CE3. The first encapsulation layer 171 may cover a contour formed by the bank layer 161 and the first, second, and third cathode electrodes CE1, CE2, and CE3. Therefore, the first encapsulation layer 171 may have a stepped portion.

[0119] The first encapsulation layer 171 may include a first inorganic layer 171-1, a second inorganic layer 171-2, and a third inorganic layer 171-3 positioned to overlap the first emission region EA1, the second emission region EA2, and the third emission region EA3, respectively. The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be spaced apart from each other in a first direction (X-axis direction), and the embankment layer 161 is interposed between the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3. In addition, according to some embodiments, a cavity may be formed between the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 and the embankment layer 161 in a third direction (Z-axis direction).

[0120] In the drawings, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 are shown as being formed on the same layer, but the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be formed in different processes, respectively. According to some embodiments, the first inorganic layer 171-1 may be formed after forming the first cathode electrode CE1, the second inorganic layer 171-2 may be formed after forming the second cathode electrode CE2, and the third inorganic layer 171-3 may be formed after forming the third cathode electrode CE3. The manufacturing process will be described later.

[0121] The first encapsulation layer 171 may include an inorganic material, such as aluminum oxide (Al 2 O 3 ), titanium oxide (Ti 2 O 3 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO), silicon oxide (SiO2 ), silicon nitride (Si 3 N 4 ) and silicon oxynitride (Si 2 N 2 O).

[0122] The second encapsulation layer 173 may be positioned on the first encapsulation layer 171. The second encapsulation layer 173 may flatten a stepped portion formed by the first encapsulation layer 171 in a portion overlapping the first, second, and third emission regions EA1, EA2, and EA3, and the second encapsulation layer 173 may fill a cavity formed between the first encapsulation layer 171 and the bank layer 161 in a portion overlapping the first, second, and third emission regions EA1, EA2, and EA3 and the non-emission region NLA.

[0123] The second encapsulation layer 173 may include a polymer-based material. Examples of polymer-based materials may include acrylic resin, epoxy resin, polyimide, polyethylene, etc. For example, the second encapsulation layer 173 may include an acrylic resin such as polymethyl methacrylate, polyacrylic acid, etc. The second encapsulation layer 173 may be formed by curing a monomer or applying a polymer.

[0124] The third encapsulation layer 175 may be positioned on the second encapsulation layer 173 and may completely cover the second encapsulation layer 173. The third encapsulation layer 175 may include an inorganic material and may include the same material as the first encapsulation layer 171. Redundant descriptions will be omitted. For example, the second encapsulation layer 173 and / or the third encapsulation layer 175 may be an organic encapsulation layer.

[0125] Figure 6 yes Figure 5 An enlarged schematic cross-sectional view of the first emission region and the second emission region in FIG.

[0126] refer to Figure 6 , the first emission area EA1 according to some embodiments may be positioned between the non-emission areas NLA located on both sides in the first direction (X-axis direction). In addition, the second emission area EA2 according to some embodiments may be spaced apart from the first emission area EA1, and the non-emission area NLA may be interposed between the first emission area EA1 and the second emission area EA2.

[0127] The inorganic pixel defining layer 151 according to some embodiments may be located in a portion overlapping the non-emission area NLA, and the first light emitting element ED1 and the second light emitting element ED2 according to some embodiments may be separated and insulated by the inorganic pixel defining layer 151. The inorganic pixel defining layer 151 may include a stepped portion according to the contour of a structure located therebelow.

[0128] The bank layer 161 according to some embodiments may be located in a portion overlapping the non-emission area NLA, and may be located on and in contact with the inorganic pixel defining layer 151. The bank layer 161 according to some embodiments may electrically connect the first cathode electrode CE1 and the second cathode electrode CE2 arranged to be spaced apart by including a conductive material. As described above, the inorganic pixel defining layer 151 may define a first opening OP1, the bank layer 161 may define a second opening OP2, and in a cross-sectional view, the first opening OP1 may be located inside the second opening OP2.

[0129] According to some embodiments, the bank layer 161 may include a first surface 1 a , a second surface 1 b , a first side surface 1 c , and a second side surface 1 d .

[0130] According to some embodiments, the first surface 1a of the bank layer 161 may be a surface facing the inorganic pixel defining layer 151. The first surface 1a of the bank layer 161 may be in contact with the inorganic pixel defining layer 151, and may include a step portion formed by the inorganic pixel defining layer 151. The second surface 1b of the bank layer 161 may be a surface opposite to the first surface 1a. The second surface 1b may not include a step portion, and may be a surface in contact with the second encapsulation layer 173.

[0131] According to some embodiments, the first side surface 1c of the bank layer 161 may be a surface facing the first emission area EA1, and may be a surface connecting the first surface 1a to the second surface 1b. The first side surface 1c may include a structure that is more recessed toward the non-emission area NLA than the inorganic pixel defining layer 151 in the first direction (X-axis direction). The first side surface 1c according to some embodiments may contact the first light emitting layer EL1, the first cathode electrode CE1, and the first inorganic layer 171-1.

[0132] The second side surface 1d of the bank layer 161 may be a surface facing the second emission area EA2, and may be a surface connecting the first surface 1a to the second surface 1b. The second side surface 1d may include a structure that is more recessed toward the non-emission area NLA than the inorganic pixel defining layer 151 in the first direction (X-axis direction). In addition, the second side surface 1d may contact the second light emitting layer EL2, the second cathode electrode CE2, and the second inorganic layer 171-2.

[0133] The display device 10 according to some embodiments may include a sacrificial layer SFL during a manufacturing process (see Fig.11). The sacrificial layer SFL may be located between the inorganic pixel defining layer 151 and the first anode electrode AE1 and between the inorganic pixel defining layer 151 and the second anode electrode AE2, respectively, and then a portion of the sacrificial layer SFL may be removed in a subsequent wet etching process. At this time, portions of the sacrificial layer SFL that are not removed may remain as residual patterns 153 between the inorganic pixel defining layer 151 and the first anode electrode AE1 and between the inorganic pixel defining layer 151 and the second anode electrode AE2, respectively.

[0134] The residual pattern 153 may include an oxide semiconductor. For example, the residual pattern 153 may include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium tin oxide (ITO).

[0135] The first light emitting layer EL1 according to some embodiments may be located on the first anode electrode AE1 in a portion overlapping the first emission area EA1, may be in contact with the first side surface 1c of the bank layer 161, and may be completely covered by the first cathode electrode CE1. In addition, the first light emitting layer EL1 according to some embodiments may be in contact with the residual pattern 153 on both sides in the first direction (X-axis direction).

[0136] The second light emitting layer EL2 according to some embodiments may be located on the second anode electrode AE2 in a portion overlapping the second emission region EA2, may be in contact with the second side surface 1d of the bank layer 161, and may be completely covered by the second cathode electrode CE2. In addition, the second light emitting layer EL2 according to some embodiments may be in contact with the residual pattern 153 on both sides in the first direction (X-axis direction).

[0137] The first cathode electrode CE1 according to some embodiments may be located on the first light emitting layer EL1 in a portion overlapping the first emission region EA1, and the first cathode electrode CE1 may completely cover the first light emitting layer EL1. In addition, the first cathode electrode CE1 may contact the first side surface 1c of the bank layer 161 within the second opening OP2, and may be completely covered by the first inorganic layer 171-1 in a portion overlapping the first emission region EA1.

[0138] The second cathode electrode CE2 according to some embodiments may be located on the second light emitting layer EL2 in a portion overlapping with the second emission region EA2, and the second cathode electrode CE2 may completely cover the second light emitting layer EL2. In addition, the second cathode electrode CE2 may contact the second side surface 1d of the bank layer 161, and may be completely covered by the second inorganic layer 171-2 in a portion overlapping with the second emission region EA2.

[0139] The first encapsulation layer 171 according to some embodiments may include a first inorganic layer 171 - 1 and a second inorganic layer 171 - 2 The first inorganic layer 171 - 1 and the second inorganic layer 171 - 2 may be spaced apart from each other in a portion overlapping the non-emission area NLA.

[0140] The first inorganic layer 171-1 according to some embodiments may completely cover the first cathode electrode CE1 in a portion overlapping with the first emission region EA1, and may be in contact with the first cathode electrode CE1. In addition, the first inorganic layer 171-1 may cover the first side surface 1c of the bank layer 161, and may be in contact with the first side surface 1c of the bank layer 161. In addition, the first inorganic layer 171-1 according to some embodiments may completely cover the cavity in a portion overlapping with the first emission region EA1. In other words, the cavity may be completely surrounded by the first inorganic layer 171-1 in a portion overlapping with the first emission region EA1.

[0141] In addition, the first inorganic layer 171-1 according to some embodiments may overlap the bank layer 161 in a portion overlapping the non-emission area NLA, and may not contact the second surface 1b of the bank layer 161. In other words, the first inorganic layer 171-1 may be spaced apart from the second surface 1b of the bank layer 161 in the third direction (Z-axis direction) with a cavity interposed between the first inorganic layer 171-1 and the bank layer 161.

[0142] The second inorganic layer 171-2 according to some embodiments may completely cover the second cathode electrode CE2 in a portion overlapping with the second emission region EA2, and may be in contact with the second cathode electrode CE2. In addition, the second inorganic layer 171-2 may completely cover the second side surface 1d of the bank layer 161, and may be in contact with the second side surface 1d. To this end, the second inorganic layer 171-2 according to some embodiments may completely cover the cavity in a portion overlapping with the second emission region EA2. In other words, the cavity may be completely surrounded by the second inorganic layer 171-2 in a portion overlapping with the second emission region EA2.

[0143] In addition, the second inorganic layer 171-2 according to some embodiments may overlap the bank layer 161 in a portion overlapping the non-emission area NLA, and may not contact the second surface 1b of the bank layer 161. In other words, the second inorganic layer 171-2 may be spaced apart from the second surface 1b of the bank layer 161 in the third direction (Z-axis direction) with a cavity interposed between the second inorganic layer 171-2 and the bank layer 161.

[0144] During the process of manufacturing the display device 10 according to some embodiments, a process of completely positioning the photoresist, the first light emitting layer EL1, and the first cathode electrode CE1 on the second surface 1b of the bank layer 161 and covered by the first inorganic layer 171-1 may be included. However, the photoresist, the first light emitting layer EL1, and the first cathode electrode CE1 located on the second surface 1b may be removed by a subsequent etching process. Therefore, a cavity may be formed between the second surface 1b of the bank layer 161 and the first inorganic layer 171-1.

[0145] In the next process of manufacturing the display device 10 according to some embodiments, a process of completely positioning the photoresist, the second light emitting layer EL2, and the second cathode electrode CE2 on the first inorganic layer 171-1 and the second surface 1b and covered by the second inorganic layer 171-2 may be included. However, the photoresist, the second light emitting layer EL2, and the second cathode electrode CE2, the portions located on the first inorganic layer 171-1 and the second surface 1b may be removed by a subsequent etching process, and thus, a cavity may be formed between the second surface 1b of the bank layer 161 and the second inorganic layer 171-2. The manufacturing process will be described later.

[0146] According to some embodiments, a height of the cavity formed between the first inorganic layer 171-1 and the second surface 1b of the bank layer 161 may be defined as a first height H1, and a height of the cavity formed between the second inorganic layer 171-2 and the second surface 1b of the bank layer 161 may be defined as a second height H2.

[0147] According to some embodiments, the first height H1 and the second height H2 may be different from each other. For example, the second height H2 may be greater than the first height H1. As described above, this may be due to the fact that during the manufacturing process of the display device 10, the cavity formed to overlap the second inorganic layer 171-2 is formed in a subsequent process when compared with the cavity formed to overlap the first inorganic layer 171-1.

[0148] The second encapsulation layer 173 according to some embodiments may be located on the first encapsulation layer 171. As described above, the second encapsulation layer 173 may planarize the first inorganic layer 171-1 and the second inorganic layer 171-2 in the portion overlapping the first emission region EA1 and the second emission region EA2, and the second encapsulation layer 173 may fill the inside of the cavity overlapping the first inorganic layer 171-1 and the inside of the cavity overlapping the second inorganic layer 171-2 in the portion overlapping the non-emission region NLA. In other words, the second encapsulation layer 173 may be located between the second surface 1b of the bank layer 161 and the first encapsulation layer 171.

[0149] Figure 7 yes Figure 5An enlarged schematic cross-sectional view of the second emission region and the third emission region in FIG.

[0150] refer to Figure 7 According to some embodiments, the second emission area EA2 may be positioned between the non-emission areas NLA on both sides in the first direction (X-axis direction). In addition, according to some embodiments, the third emission area EA3 may be spaced apart from the second emission area EA2, and the non-emission area NLA may be interposed between the second emission area EA2 and the third emission area EA3.

[0151] The inorganic pixel defining layer 151 according to some embodiments may be located in a portion overlapping the non-emission area NLA, and the second and third light emitting elements ED2 and ED3 according to some embodiments may be separated and insulated by the inorganic pixel defining layer 151. Other redundant descriptions are omitted.

[0152] The bank layer 161 according to some embodiments may electrically connect the second cathode electrode CE2 and the third cathode electrode CE3 arranged to be spaced apart by including a conductive material.

[0153] According to some embodiments, the bank layer 161 according to some embodiments may include a first surface 1a, a second surface 1b, a second side surface 1d, and a third side surface 1e. The first surface 1a, the second surface 1b, and the second side surface 1d of the bank layer 161 have been described above, and descriptions thereof will be omitted.

[0154] The third side surface 1e of the bank layer 161 may be a surface facing the third emission area EA3, may be a surface connecting the first surface 1a to the second surface 1b, and may be opposite to the second side surface 1d. The third side surface 1e may include a structure that is more recessed toward the non-emission area NLA than the inorganic pixel defining layer 151 in the first direction (X-axis direction). In addition, the third side surface 1e may contact the third light emitting layer EL3, the third cathode electrode CE3, and the third inorganic layer 171-3.

[0155] In the manufacturing process of forming the light emitting element ED according to some embodiments, the sacrificial layer SFL may be located between the inorganic pixel defining layer 151 and the third anode electrode AE3, and then a portion of the sacrificial layer SFL may be removed by a subsequent wet etching process. At this time, the portion of the sacrificial layer SFL that is not removed may remain as a residual pattern 153 between the inorganic pixel defining layer 151 and the third anode electrode AE3.

[0156] The third light emitting layer EL3 according to some embodiments may be located on the third anode electrode AE3 in a portion overlapping the third emission area EA3, may be in contact with the third side surface 1e of the bank layer 161, and may be completely covered by the third cathode electrode CE3. The third light emitting layer EL3 according to some embodiments may be in contact with the residual pattern 153 on both sides in the first direction (X-axis direction).

[0157] The third cathode electrode CE3 according to some embodiments may be located on the third light emitting layer EL3 in a portion overlapping the third emission area EA3 , may be in contact with the third side surface 1 e of the bank layer 161 , and may be completely covered by the third inorganic layer 171 - 3 .

[0158] The third inorganic layer 171-3 according to some embodiments may completely cover the third cathode electrode CE3 in a portion overlapping with the third emission area EA3, and may be in contact with the third cathode electrode CE3. In addition, the third inorganic layer 171-3 may completely cover the third side surface 1e of the bank layer 161, and may be in contact with the third side surface 1e of the bank layer 161. In addition, the third inorganic layer 171-3 according to some embodiments may completely cover the cavity in a portion overlapping with the third emission area EA3. In other words, the cavity may be completely surrounded by the third inorganic layer 171-3 in a portion overlapping with the third emission area EA3.

[0159] In addition, the third inorganic layer 171-3 according to some embodiments may overlap the bank layer 161 in a portion overlapping the non-emission region NLA, and may not contact the second surface 1b of the bank layer 161. In other words, the third inorganic layer 171-3 may be spaced apart from the second surface 1b of the bank layer 161 in the third direction (Z-axis direction) with a cavity interposed between the third inorganic layer 171-3 and the bank layer 161. Other redundant descriptions will be omitted.

[0160] During the manufacturing process, as a subsequent process after the process of forming a cavity between the second surface 1b of the bank layer 161 and the second inorganic layer 171-2, the process of manufacturing the display device 10 according to some embodiments may include a process in which a photoresist, a third light emitting layer EL3, and a third cathode electrode CE3 are completely formed on the second inorganic layer 171-2 and the second surface 1b and covered by the third inorganic layer 171-3. However, portions of the photoresist, the third light emitting layer EL3, and the third cathode electrode CE3 located on the second inorganic layer 171-2 and the second surface 1b may be removed by a subsequent etching process, and thus, a cavity may be formed between the second surface 1b of the bank layer 161 and the third inorganic layer 171-3.

[0161] In some embodiments, the height of the cavity formed between the third inorganic layer 171-3 and the second surface 1b of the bank layer 161 may be defined as a third height H3, and the second height H2 and the third height H3 may be different from each other. For example, the third height H3 may be greater than the second height H2. As described above, this may be due to the fact that during the manufacturing process of the display device 10, a cavity formed to overlap the third inorganic layer 171-3 is formed in a subsequent process when compared with a cavity formed to overlap the second inorganic layer 171-2.

[0162] Figure 8 According to some embodiments, Figure 4 Schematic cross-sectional view of display layers according to some embodiments, taken along line X1-X1'.

[0163] refer to Figure 8 The display device 30 according to some embodiments may be different from the display device 10 according to some embodiments in including an auxiliary inorganic layer (auxiliary encapsulation layer) 172. In other words, the thin film encapsulation layer 170 according to some embodiments may include a first encapsulation layer 171, an auxiliary inorganic layer 172, a second encapsulation layer 173, and a third encapsulation layer 175.

[0164] The auxiliary inorganic layer 172 included in the display device 30 according to some embodiments may completely cover the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 arranged to be spaced apart from each other in portions overlapping the first emission region EA1, the second emission region EA2, and the third emission region EA3, and the non-emission region NLA, respectively. That is, the auxiliary inorganic layer 172 may be arranged to completely overlap the first emission region EA1, the second emission region EA2, and the third emission region EA3, and the non-emission region NLA. The auxiliary inorganic layer 172 according to some embodiments may cover the outline formed by the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3.

[0165] Specifically, the auxiliary inorganic layer 172 may include a step portion in a portion overlapping the first emission region EA1, the second emission region EA2, and the third emission region EA3, may form a cavity in a portion overlapping the first emission region EA1, the second emission region EA2, and the third emission region EA3 and the non-emission region NLA, and may cover the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3. However, the present disclosure is not limited thereto, and according to a structure formed by the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3, the auxiliary inorganic layer 172 may cover the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 without forming a cavity.

[0166] The auxiliary inorganic layer 172 according to some embodiments may include an inorganic material. For example, the auxiliary inorganic layer 172 may include aluminum oxide (Al 2 O 3 ), titanium oxide (Ti 2 O 3 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and silicon oxynitride (Si 2 N 2 O). Other redundant descriptions will be omitted.

[0167] The second encapsulation layer 173 according to some embodiments may be positioned on the auxiliary inorganic layer 172, and may fill the stepped portion and the cavity formed by the auxiliary inorganic layer 172. Redundant descriptions will be omitted.

[0168] Fig. 9 According to some embodiments, Figure 4 Schematic cross-sectional view of display layers according to some embodiments, taken along line X1-X1'.

[0169] refer to Fig. 9 The display device 50 according to some embodiments may be different from the display device 10 according to some embodiments in that the first encapsulation layer 171 does not overlap with the non-emission area NLA and is arranged to overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0170] The first encapsulation layer 171 included in the display device 50 according to some embodiments may include a first inorganic layer 171-1, a second inorganic layer 171-2, and a third inorganic layer 171-3 located in portions overlapping the first emission region EA1, the second emission region EA2, and the third emission region EA3, respectively. The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 according to some embodiments may completely cover the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 in portions overlapping the first emission region EA1, the second emission region EA2, and the third emission region EA3, respectively, and may completely cover both side surfaces of the bank layer 161 facing the corresponding emission regions among the first emission region EA1, the second emission region EA2, and the third emission region EA3. Since the first, second, and third inorganic layers 171-1, 171-2, and 171-3 cover the outline formed by the first, second, and third light emitting elements ED1, ED2, and ED3 and the bank layer 161, the first, second, and third inorganic layers 171-1, 171-2, and 171-3 may include a stepped portion.

[0171] The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 according to some embodiments may not overlap with the non-emission area NLA. In other words, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 according to some embodiments may not overlap with the inorganic pixel defining layer 151 and the embankment layer 161 in the third direction (Z-axis direction). In the manufacturing process of the display device 50 according to some embodiments, this can be formed by etching portions of the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 by a dry etching process performed after photolithography patterning.

[0172] The second encapsulation layer 173 according to some embodiments may fill the stepped portions of the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 in the portion overlapping the first emission region EA1, the second emission region EA2, and the third emission region EA3. Therefore, the stepped portions included in the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 according to some embodiments may be planarized.

[0173] The second surface 1b included in the bank layer 161 according to some embodiments may be completely covered by the second encapsulation layer 173 in a portion overlapping the non-emission area NLA. Other overlapping descriptions of structures and features will be omitted.

[0174] Fig.10 According to some embodiments, Figure 4Schematic cross-sectional view of display layers according to some embodiments, taken along line X1-X1'.

[0175] refer to Fig.10 , the display device 70 according to some embodiments may be different from the display device 10 according to some embodiments in that the first encapsulation layer 171 does not overlap with the non-emission area NLA and includes a protrusion P in a portion overlapping with the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0176] The first encapsulation layer 171 included in the display device 70 according to some embodiments may include a first inorganic layer 171-1, a second inorganic layer 171-2, and a third inorganic layer 171-3 located in portions overlapping the first emission region EA1, the second emission region EA2, and the third emission region EA3, respectively. The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may completely cover the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 in portions overlapping the first emission region EA1, the second emission region EA2, and the third emission region EA3, and may completely cover both side surfaces of the bank layer 161 facing the corresponding emission regions of the first emission region EA1, the second emission region EA2, and the third emission region EA3. Since the first, second, and third inorganic layers 171-1, 171-2, and 171-3 cover the outline formed by the first, second, and third light emitting elements ED1, ED2, and ED3 and the bank layer 161, the first, second, and third inorganic layers 171-1, 171-2, and 171-3 may include a stepped portion.

[0177] In addition, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 according to some embodiments may include a protrusion P in a portion overlapping the first emission region EA1, the second emission region EA2, and the third emission region EA3. The protrusion P may be a portion protruding toward one side in the third direction (Z-axis direction) when compared with the second surface 1b of the bank layer 161. In the manufacturing process of the display device 70 according to some embodiments, this may be formed by etching portions of the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 by a dry etching process performed after photolithography patterning.

[0178] The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 according to some embodiments may not overlap with the non-emission area NLA. In other words, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 according to some embodiments may not overlap with the inorganic pixel defining layer 151 and the bank layer 161 in the third direction (Z-axis direction).

[0179] The second encapsulation layer 173 according to some embodiments may fill the stepped portions of the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 in the portions overlapping the first emission region EA1, the second emission region EA2, and the third emission region EA3, and may completely cover the protrusions P included in the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3. Other overlapping descriptions of structures and features will be omitted.

[0180] Figures 11 to 19 It is shown Figure 5 2 is a cross-sectional view of a schematic manufacturing method of the display device 10. Hereinafter, the manufacturing process of the display device 10 will be described with respect to the formation order of each layer.

[0181] refer to Fig.11 , a plurality of first anode electrodes AE1, second anode electrodes AE2, and third anode electrodes AE3 are formed on the thin film transistor layer 130. The first anode electrodes AE1, the second anode electrodes AE2, and the third anode electrodes AE3 may be arranged to be spaced apart from each other on the thin film transistor layer 130. According to some embodiments, the thin film transistor layer 130 may be located on the substrate 110, and the structure of the thin film transistor layer 130 is the same as that of the above reference Figure 5 The structure of the thin film transistor layer 130 described is the same. A detailed description of the structure of the thin film transistor layer 130 will be omitted.

[0182] Subsequently, a sacrificial layer SFL may be positioned on each of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The sacrificial layer SFL may be positioned on each of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3, and then a portion of the sacrificial layer SFL may be removed in a subsequent process to form a space in which the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 are located. The sacrificial layer SFL may help prevent or reduce the top surfaces of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 from contacting the inorganic pixel defining layer 151. The sacrificial layer SFL may include an oxide semiconductor, and therefore, may have an etching rate different from that of the pixel defining material layer 151L and the embankment material layer 161L.

[0183] The pixel defining material layer 151L and the bank material layer 161L may be located on the plurality of first anode electrodes AE1, second anode electrodes AE2, and third anode electrodes AE3 and the sacrificial layer SFL. The pixel defining material layer 151L may be arranged to completely cover the sacrificial layer SFL and the thin film transistor layer 130, and the bank material layer 161L may be arranged to completely cover the pixel defining material layer 151L.

[0184] Next, a first photoresist PR1 is formed on the bank material layer 161L. The first photoresist PR1 may be formed to expose a portion overlapping the first anode electrode AE1. Subsequently, a first etching process (first etching) is performed to etch portions of the pixel defining material layer 151L and the bank material layer 161L by using the first photoresist PR1 as a mask. As an example, the first etching process may be performed as a dry etching process.

[0185] Through the present process, the bank material layer 161L and the pixel defining material layer 151L overlapping the first anode electrode AE1 may be etched, and thus, a portion of the sacrificial layer SFL positioned on the first anode electrode AE1 may be exposed.

[0186] Next, refer to Fig.12 , a second etching process (second etching) is performed using the first photoresist PR1 as a mask. For example, the second etching process (second etching) may be performed as a wet etching process.

[0187] In the present process, the side surface of the bank material layer 161L may be recessed in the first direction (X-axis direction) when compared with the pixel defining material layer 151L, and therefore, the first photoresist PR1 may include a tip TIP that protrudes much more than the bank material layer 161L. Meanwhile, in the present process, a portion of the sacrificial layer SFL arranged to overlap the first anode electrode AE1 may be removed. However, the sacrificial layer SFL may not be completely removed and may remain as a partial residual pattern 153 in the space between the pixel defining material layer 151L and the first anode electrode AE1.

[0188] Next, refer to Fig.13, the first light emitting layer EL1 and the first cathode electrode CE1 may be deposited on the first anode electrode AE1. The first light emitting layer EL1 according to some embodiments may be formed by a thermal evaporation process. Because the first photoresist PR1 includes a tip TIP that protrudes much more than the embankment material layer 161L, the first light emitting layer EL1 may be formed on the first anode electrode AE1 without a mask. However, the deposition process for forming the first light emitting layer EL1 may be performed by tilting at an angle of 45° to 50° from the top surface of the first anode electrode AE1. Therefore, the first light emitting layer EL1 may be formed to fill the separation space between the first anode electrode AE1 and the pixel defining material layer 151L, and the first light emitting layer EL1 may also be formed on a portion of the side surface of the embankment material layer 161L covered by the protruding tip TIP of the first photoresist PR1.

[0189] In the present process, the first light emitting layer EL1 according to some embodiments may also be formed over the first photoresist PR1 overlapping the second anode electrode AE2 and the third anode electrode AE3. In the first light emitting layer EL1 positioned over the first photoresist PR1, since the first photoresist PR1 includes a tip TIP, the first light emitting layer EL1 on the first anode electrode AE1 may be formed by disconnection without connection.

[0190] The first cathode electrode CE1 according to some embodiments may be formed by a thermal evaporation process. The deposition process for forming the first cathode electrode CE1 may be performed by tilting at an angle of 30° or less from the top surface of the first anode electrode AE1. In other words, the deposition process for forming the first cathode electrode CE1 may be performed by tilting at an angle relatively close to the horizontal direction than the deposition process for forming the first light emitting layer EL1. Therefore, the first cathode electrode CE1 may completely cover the first light emitting layer EL1, and may completely cover the first light emitting layer EL1 even on the side surface of the embankment material layer 161L covered by the protruding tip TIP of the first photoresist PR1. Through this process, the first light emitting element ED1 may be formed.

[0191] Next, a first encapsulation material layer 171L is formed to completely cover the first cathode electrode CE1. A chemical vapor deposition (CVD) process may be performed on the first encapsulation material layer 171L, and the first encapsulation material layer 171L may form a uniform layer regardless of the step portion of the lower structure. For example, the first encapsulation material layer 171L may also cover the undercut region formed by the protruding tip TIP of the first photoresist PR1 and the bank material layer 161L.

[0192] refer to Fig.14, a second photoresist PR2 is formed on a portion overlapping with the first light emitting element ED1 and the periphery of the first light emitting element ED1, and a third etching process (third etching) is performed to etch a partial structure of an area other than a portion overlapping with the first light emitting element ED1 (e.g., the first emission area EA1) and a periphery of the first light emitting element ED1 (e.g., the first emission area EA1). As an example, the third etching process may be performed alternately between a wet process and a dry etching process. In other words, in the present process, the first light emitting layer EL1, the first cathode electrode CE1, and the first encapsulation material layer 171L in the portion where the second photoresist PR2 is not formed may be completely removed.

[0193] refer to Fig.15 , the first light emitting element ED1 and the first inorganic layer 171 - 1 may be formed by this process, and at the same time, a cavity may be formed between the first inorganic layer 171 - 1 and the bank material layer 161L in the third direction (Z-axis direction).

[0194] Next, refer to Figures 16 to 18 , repeat the above process to form the second light emitting element ED2.

[0195] Specifically, a first photoresist PR1 having a thickness capable of covering the first inorganic layer 171 - 1 and the cavity overlapping the first inorganic layer 171 - 1 is formed on the bank material layer 161L. The first photoresist PR1 is formed to expose a portion of the second anode electrode AE2.

[0196] Next, the bank material layer 161L and the pixel defining material layer 151L overlapping the second anode electrode AE2 are etched by a dry etching process, and then a portion of the bank material layer 161L is etched by a wet etching process so that the first photoresist PR1 has a tip TIP. In other words, when compared with the pixel defining material layer 151L, a portion of the bank material layer 161L is etched so that the bank material layer 161L can be recessed in the first direction (X-axis direction).

[0197] At the same time, a portion of the sacrificial layer SFL located on the second anode electrode AE2 is removed to expose a portion of the second anode electrode AE2. In this process, the sacrificial layer SFL may not be completely removed, and a portion of the residual pattern 153 may remain in the space between the pixel defining material layer 151L and the second anode electrode AE2.

[0198] Next, refer to Fig.17, a second light emitting layer EL2 and a second cathode electrode CE2 are deposited on the second anode electrode AE2. According to some embodiments, because the first photoresist PR1 includes a tip TIP, the second light emitting layer EL2 and the second cathode electrode CE2 may be deposited without a mask. Therefore, the second light emitting layer EL2 and the second cathode electrode CE2 may also be deposited on the first photoresist PR1. The second light emitting layer EL2 according to some embodiments may contact the residual pattern 153.

[0199] Subsequently, after the second cathode electrode CE2 is completely formed on the first encapsulation material layer 171L, a second photoresist PR2 is formed on the portion overlapping the second anode electrode AE2 and the periphery of the second anode electrode AE2, and a partial structure of the region other than the portion overlapping the periphery of the second anode electrode AE2 and the second anode electrode AE2 is etched (fourth etching). In other words, the second light emitting layer EL2, the second cathode electrode CE2, and the first encapsulation material layer 171L in the portion where the second photoresist PR2 is not formed can be completely removed.

[0200] refer to Fig.18 , the second light emitting element ED2 and the second inorganic layer 171 - 2 may be formed by this process, and a cavity may be formed between the second inorganic layer 171 - 2 and the bank material layer 161L.

[0201] refer to Fig.19 , the above process of forming the second light-emitting element ED2 is repeated again to form the third light-emitting element ED3. Through this process, the third light-emitting element ED3 and the third inorganic layer 171-3 can be formed, and a cavity can be formed between the third inorganic layer 171-3 and the embankment layer 161. Through this process, the first encapsulation material layer 171L can be in the form of the first inorganic layer 171-1, the second inorganic layer 171-2 and the third inorganic layer 171-3, the embankment material layer 161L can be in the form of the embankment layer 161, and the pixel defining material layer 151L can be in the form of the inorganic pixel defining layer 151.

[0202] As shown in the figure, the height of the cavity formed to overlap with the first inorganic layer 171-1 in the third direction (Z-axis direction), the height of the cavity formed to overlap with the second inorganic layer 171-2, and the height of the cavity formed to overlap with the third inorganic layer 171-3 may be formed differently. For example, the height of the cavity arranged to overlap with the third inorganic layer 171-3 may be the highest, and the height of the cavity formed to overlap with the first inorganic layer 171-1 may be the lowest. This may be caused by the fact that the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 are not formed in the same process but are formed sequentially.

[0203] Next, the second encapsulation layer 173 is completely formed to planarize the stepped portion included in the first encapsulation layer 171, and the third encapsulation layer 175 is completely formed on the second encapsulation layer 173. The second encapsulation layer 173 may be formed to fill the cavity.

[0204] As described above, the display device 10 according to some embodiments uses the tip TIP included in the first photoresist PR1 during the manufacturing process, so that the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 can be formed without a mask. Therefore, the display device 10 according to some embodiments can have high-resolution features and can be easily manufactured.

[0205] The above is an example of some embodiments of the present disclosure, and should not be construed as limiting the present disclosure. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications can be made in the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the features or aspects within each embodiment should generally be considered to be other similar features or aspects that can be used in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, unless otherwise specifically indicated, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it is to be understood that the above is an explanation of various example embodiments, and should not be construed as a limitation to the specific embodiments disclosed herein, and various modifications and other example embodiments of the disclosed embodiments are intended to be included in the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. Display equipment, including: A substrate including an emitting region and a non-emitting region; a first light emitting element, on the emission region of the substrate; a pixel defining layer on the non-emitting area of ​​the substrate and defining a first opening; a bank layer, on the pixel defining layer, defining a second opening and comprising a conductive material; a first encapsulation layer, on the first light-emitting element and comprising an inorganic material; as well as a second encapsulation layer, on the first encapsulation layer and comprising an organic material, wherein a cavity is formed between the first encapsulation layer and the bank layer in a direction perpendicular to the substrate, The cavity overlaps the emitting region and the non-emitting region, and The cavity is filled with the second encapsulation layer.

2. The display device according to claim 1, further comprising a second light emitting element spaced apart from the first light emitting element, and the bank layer is interposed between the first light emitting element and the second light emitting element, in, The first light emitting element comprises: a first anode electrode on the substrate; a first light emitting layer on the first anode electrode; and a first cathode electrode on the first light emitting layer, and The second light emitting element comprises: a second anode electrode spaced apart from the first anode electrode, with the pixel defining layer interposed between the first anode electrode and the second anode electrode; a second light emitting layer on the second anode electrode; and The second cathode electrode is on the second light emitting layer.

3. The display device according to claim 2, wherein: The bank layer comprises: a first side surface, in contact with the first cathode electrode; a second side surface in contact with the second cathode electrode; and The first surface contacts the second encapsulation layer and connects the first side surface to the second side surface.

4. The display device according to claim 3, wherein: The first cathode electrode and the second cathode electrode are electrically connected through the bank layer.

5. The display device according to claim 4, wherein: The first light emitting layer is in contact with the first side surface, and the second light emitting layer is in contact with the second side surface.

6. The display device according to claim 2, wherein: The first encapsulation layer includes a first inorganic layer in contact with the first light emitting element and a second inorganic layer in contact with the second light emitting element, and The first inorganic layer and the second inorganic layer are spaced apart from each other in a portion overlapping the non-emission region.

7. The display device according to claim 6, wherein: A cavity formed between the bank layer and the first inorganic layer in the direction perpendicular to the substrate has a first height, and a cavity formed between the bank layer and the second inorganic layer in the direction has a second height.

8. The display device according to claim 7, wherein: The first height and the second height are different from each other.

9. The display device according to claim 7, wherein: The second height is greater than the first height.

10. The display device according to claim 3, wherein: The first surface does not contact the first encapsulation layer.

11. The display device according to claim 10, wherein: The first surface is spaced apart from the first encapsulation layer, and the cavity is interposed between the first surface and the first encapsulation layer.

12. The display device according to claim 2, further comprising a residual pattern between the first anode electrode and the pixel defining layer in the direction perpendicular to the substrate, in, The residual pattern contacts the first light emitting layer.

13. The display device according to claim 1, wherein: In a plan view, the first opening is completely surrounded by the second opening.

14. The display device according to claim 4, further comprising an auxiliary encapsulation layer between the first encapsulation layer and the second encapsulation layer, in, The auxiliary encapsulation layer completely covers the first encapsulation layer in a portion overlapping the emission region and the non-emission region, and The auxiliary encapsulation layer contacts the first surface, and the auxiliary encapsulation layer completely covers the first surface.

15. Display equipment, including: A substrate comprising a first emission region, a second emission region, and a non-emitting region between the first emission region and the second emission region; a first light emitting element, on the first emission region of the substrate; a second light emitting element, on the second emission region of the substrate; a pixel defining layer on the non-emitting area of ​​the substrate and defining a first opening; a bank layer defining a second opening on the pixel defining layer; a first inorganic layer, on the first light-emitting element; a second inorganic layer on the second light-emitting element and spaced apart from the first inorganic layer; as well as an organic encapsulation layer, on the first inorganic layer and the second inorganic layer, wherein the first light emitting element and the first inorganic layer are in contact with a side surface of the bank layer facing the first emission region, The second light emitting element and the second inorganic layer are in contact with the other side surface of the bank layer facing the second emission region, and The first inorganic layer and the second inorganic layer are spaced apart from each other without overlapping the non-emission region.

16. The display device according to claim 15, wherein: The first opening is inside the second opening.

17. The display device according to claim 16, wherein: The bank layer includes a first surface facing the organic encapsulation layer, and The first inorganic layer and the second inorganic layer include protrusions that protrude more toward the organic encapsulation layer than the first surface.

18. The display device according to claim 17, further comprising a residual pattern between the substrate and the pixel defining layer in a direction perpendicular to the substrate, in, The residual pattern and the protrusion do not overlap each other.

19. A method for manufacturing a display device, comprising: forming a substrate including an emission region and a non-emission region, an anode electrode on the emission region of the substrate, and a sacrificial layer on the anode electrode, and forming a pixel defining layer completely covering the sacrificial layer and the substrate and a bank material layer completely covering the pixel defining layer; forming a photoresist on the bank material layer, etching the bank material layer and the pixel defining layer overlapping the anode electrode to expose the sacrificial layer, and then etching a sidewall of the bank material layer and the sacrificial layer to expose the anode electrode and form a bank layer; forming a light emitting layer and a cathode electrode on the anode electrode and the photoresist, and forming a first encapsulation layer on the cathode electrode; as well as removing the light emitting layer, the cathode electrode and the first encapsulation layer in other regions except the emission region and the peripheral portion of the emission region, When the light emitting layer and the cathode electrode are removed, a cavity is formed between the first encapsulation layer and the bank layer in a direction perpendicular to the substrate.

20. The method according to claim 19, wherein: When the sidewall of the bank material layer is etched to form the bank layer, the photoresist forms a tip that protrudes more toward the emission region than the sidewall of the bank layer.

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