Semiconductor structure and operation method thereof

Abstract

The invention provides a semiconductor structure and an operation method thereof. The semiconductor structure comprises a grid electrode, a channel structure, a grid electrode insulating layer, a source electrode and a drain electrode. The channel structure comprises a threshold switching material, wherein the channel structure comprises a layered channel, a columnar channel or a plurality of nanosheet channels; the gate insulating layer is arranged between the gate and the channel structure; the source electrode is in direct contact with the channel structure; and a drain directly contacting the channel structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure and an operating method thereof. Background Art

[0002] In the back end of line (BEOL) process of integrated circuits, doped silicon can be used as a channel material when manufacturing transistors; however, the dopant is usually activated by a high temperature, such as 600°C to 1000°C. This high temperature may damage the metal wiring in the integrated circuit and reduce the performance of the integrated circuit. For example, oxide semiconductors can be used as channel materials. Oxide semiconductors have a lower process temperature, but have a problem of low carrier mobility. For example, two-dimensional materials can be used as channel materials. Two-dimensional materials have a lower process temperature, but have a problem of poor uniformity. In view of the above, it is necessary to provide a new semiconductor structure to overcome the above problems. Summary of the invention

[0003] The present disclosure provides a semiconductor structure, which includes a first gate, a channel structure, a first gate insulating layer, a source and a drain. The channel structure includes a threshold switching material, wherein the channel structure includes a layered channel, a columnar channel or a plurality of nanosheet channels. The first gate insulating layer is disposed between the first gate and the channel structure. The source directly contacts the channel structure. The drain directly contacts the channel structure.

[0004] In some embodiments, the threshold switching material includes an ovonic threshold switching material (OTS material), a mixed-ionic-electronic-conduction material (MIEC material), a phase change material (PCM), or a combination thereof.

[0005] In some embodiments, the threshold switching material is a chalcogenide.

[0006] In some embodiments, the bidirectional threshold switching material includes AsSeGe, InAsSeGe, SiAsSeGe, CAsSeGe, CTe, BTe, GeCTe, NGeCTe, or combinations thereof.

[0007] In some embodiments, the mixed ion-electron conductor material includes CuSbGeTe, CuSbGeSTe, or a combination thereof.

[0008] In some embodiments, the source and the drain contact an upper surface of the channel structure, and the first gate insulating layer is disposed between the source and the drain.

[0009] In some embodiments, the channel structure is disposed on the source and the drain, the first gate insulating layer is disposed on the channel structure, and the first gate is disposed on the first gate insulating layer.

[0010] In some embodiments, the semiconductor structure further includes: a second gate and a second gate insulating layer, wherein the second gate insulating layer is disposed on the second gate, and the source and the drain are disposed on the second gate insulating layer.

[0011] In some embodiments, the source and the drain are disposed on the channel structure, the first gate insulating layer is disposed on the source and the drain, and the first gate is disposed on the first gate insulating layer.

[0012] In some embodiments, the semiconductor structure further includes: a second gate and a second gate insulating layer, wherein the second gate insulating layer is disposed on the second gate, and the channel structure is disposed on the second gate insulating layer.

[0013] In some embodiments, the first gate insulating layer is disposed on the first gate, the source and the drain are disposed on the first gate insulating layer, and the channel structure is disposed on the source and the drain.

[0014] In some embodiments, the first gate insulating layer is disposed on the first gate, the channel structure is disposed on the first gate insulating layer, and the source and the drain are disposed on the channel structure.

[0015] In some embodiments, the semiconductor structure further includes: a second gate and a second gate insulating layer, wherein the second gate insulating layer is disposed on the second gate, and the channel structure is disposed on the second gate insulating layer. Of the source and the drain, the first one directly contacts the upper surface of the channel structure, and the second one directly contacts the lower surface of the channel structure. The first gate insulating layer is disposed on the channel structure, and the first gate is disposed on the first gate insulating layer.

[0016] In some embodiments, the first gate covers a plurality of sidewalls and a top surface of the channel structure.

[0017] In some embodiments, the channel structure includes the nanosheet channels, and the first gate surrounds the nanosheet channels.

[0018] In some embodiments, the semiconductor structure further includes an insulating layer, wherein the insulating layer is disposed between the source and the drain, and the channel structure directly contacts the insulating layer, the source, and the drain.

[0019] The present disclosure provides an operating method for a semiconductor structure, which includes the following operations: receiving a semiconductor structure of any of the aforementioned embodiments; and applying a first voltage to a drain, wherein the absolute value of the first voltage is greater than the absolute value of a switching threshold voltage of a threshold switching material of a channel structure.

[0020] In some embodiments, the operating method further includes: applying a second voltage to the first gate to regulate a switching threshold voltage of a threshold switching material of the channel structure.

[0021] In some embodiments, the threshold switching material is a bidirectional threshold switching material and the first voltage is a positive voltage.

[0022] In some embodiments, the threshold switching material is a mixed ionic-electronic conductor material, and the first voltage is a positive voltage or a negative voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present disclosure may be more fully understood by reading the following detailed description of embodiments and referring to the accompanying drawings.

[0024] Figure 1 is a schematic cross-sectional view of a semiconductor structure according to various embodiments of the present disclosure.

[0025] Figure 2A , Figure 3A , Figure 4 and Figure 5A is a schematic diagram of an operating semiconductor structure according to various embodiments of the present disclosure.

[0026] Figure 2B For operation Figure 2A Drain current-drain voltage diagram of the semiconductor structure.

[0027] Figure 3B For operation Figure 3A Schematic diagram of drain current-drain voltage of a semiconductor structure.

[0028] Figure 5B For operation Figure 5A Schematic diagram of drain current-drain voltage of a semiconductor structure.

[0029] Figure 6 , Figure 7 , Figure 8 and Fig.10 is a schematic cross-sectional view of a semiconductor structure according to various embodiments of the present disclosure.

[0030] Fig.9A is a schematic three-dimensional diagram of a semiconductor structure according to various embodiments of the present disclosure.

[0031] Fig. 9BAccording to various embodiments of the present disclosure Fig.9A A schematic cross-sectional view of a semiconductor structure along section line aa.

[0032] Fig.11 is a schematic three-dimensional diagram of a semiconductor structure according to various embodiments of the present disclosure.

[0033] Fig. 12A According to various embodiments of the present disclosure Fig.11 A schematic cross-sectional view of a semiconductor structure along a section line AA'.

[0034] Fig. 12B According to various embodiments of the present disclosure Fig.11 A schematic cross-sectional view of a semiconductor structure along a section line BB'.

[0035] Fig.13A According to various embodiments of the present disclosure Fig.11 A schematic cross-sectional view of a semiconductor structure along a section line AA'.

[0036] Fig. 13B According to various embodiments of the present disclosure Fig.11 A schematic cross-sectional view of a semiconductor structure along a section line BB'.

[0037] Description of Reference Numerals

[0038] 100, 200, 400, 612, 614, 616, 618, 622, 624, 626, 628, 632, 634, 712, 714, 716, 718, 722, 724, 726, 728, 812, 814, 816, 818, 900, 1000, 1100: semiconductor structure

[0039] 110, 112, 640, 1010, 1110: substrate

[0040] 114: Insulation layer

[0041] 210, 220, 310, 320, 330, 340, 350: lines

[0042] 510, 520, 530, 540: lines

[0043] 662, 664, 672: first gate insulating layer

[0044] 666, 930, 1040, GI: Gate insulation layer

[0045] 668, 674: second gate insulating layer

[0046] 1020: Overlay

[0047] 1022: Source / drain layer

[0048] 1024: Insulation layer

[0049] 1120: Threshold switching material layer 1130: Isolation structure

[0050] 1150: Gate structure

[0051] 1152: Gate insulation layer

[0052] 1160: Gate spacer

[0053] 1170: Interlayer dielectric layer

[0054] 1180: Contact etch stop layer

[0055] 1190: Internal spacer

[0056] aa, A-A', B-B': hatching line

[0057] CS, CS1, CS2, 652, 654, 656, 658, 659, 920, 1030, 1122, 1124: Channel structure

[0058] D, D1, 940, 1144: drain

[0059] G, G15, 910, 1050, 1154: Gate

[0060] G11, G12, G13, G14: First gate

[0061] G21: Second gate

[0062] S, S1, 950, 1142: Source

[0063] SD1: First source / drain

[0064] SD2: Second source / drain

[0065] US1, US2, US3: upper surface DETAILED DESCRIPTION

[0066] The following multiple embodiments are described and disclosed in detail with the accompanying drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details are not intended to limit the present disclosure. That is, in the disclosed partial embodiments, these practical details are not necessary. In addition, to simplify the drawings, some existing structures and elements will be illustrated in schematic form in the drawings.

[0067] In this article, it is understood that the words first, second, third, etc. are used to describe various elements, components, regions, layers, and / or blocks. However, these elements, components, regions, layers, and / or blocks should not be limited by these words. These words are limited to identifying a single element, component, region, layer, and / or block. Therefore, a first element, component, region, layer, and / or block in the following text may also be referred to as a second element, component, region, layer, and / or block without departing from the original intention of the present disclosure.

[0068] The present disclosure provides a semiconductor structure, which includes a gate, a channel structure, a gate insulating layer, a source and a drain. This semiconductor structure is a three-terminal switching device. The channel structure includes a threshold switching material, wherein the channel structure includes a layered channel, a columnar channel or a plurality of nanosheet channels. The gate insulating layer is disposed between the gate and the channel structure. The source directly contacts the channel structure. The drain directly contacts the channel structure. The semiconductor structure disclosed in the present disclosure can be used as a transistor in the back-end process (BEOL) of a monolithic 3-dimensional integration, for example, but is not limited thereto. The channel structure disclosed in the present disclosure includes a threshold switching material. The threshold switching material can be made into a channel structure at a lower process temperature (e.g., equal to or lower than 500° C.), while still having a high carrier mobility, so that when the semiconductor structure is operated, a high current can flow through the semiconductor structure. In addition, other components (e.g., metal lines) in the monolithic 3-dimensional integration will not be damaged by this process temperature. Various embodiments of the present disclosure will be described below with drawings.

[0069] Figure 1 1 is a schematic cross-sectional view of a semiconductor structure 100 according to various embodiments of the present disclosure. Figure 1As shown, the semiconductor structure 100 includes a substrate 110, a gate G, a channel structure CS, a gate insulating layer GI, a source S and a drain D. The substrate 110 includes a substrate 112 and an insulating layer 114. In some embodiments, the substrate 112 is a semiconductor substrate or a glass substrate. In some embodiments, the substrate 112 includes any suitable semiconductor material. The semiconductor material includes, for example, one or more materials, such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, germanium, gallium arsenide, other suitable semiconductor materials or combinations thereof. In some embodiments, the insulating layer 114 includes oxide, nitride or a combination thereof, such as silicon dioxide, silicon nitride or a combination thereof. In some embodiments, the substrate 112 is a silicon wafer. The channel structure CS is disposed on the substrate 110. The channel structure CS includes a threshold switching material and is a layered channel. The gate G is disposed above the channel structure CS. The gate insulating layer GI is disposed between the gate G and the channel structure CS to separate the gate G from the channel structure CS, and the gate insulating layer GI is disposed between the source S and the drain D. The source S and the drain D directly contact the upper surface US1 of the channel structure CS. In some embodiments, the gate insulating layer GI includes oxide, nitride or a combination thereof, such as silicon dioxide, hafnium oxide, aluminum oxide, silicon nitride or a combination thereof. In some embodiments, the gate G, the source S and the drain D each include W, TiN, Pt, Ti, Ru, Mo, Al, Cu or a combination thereof.

[0070] In some embodiments, the threshold switching material includes a bidirectional threshold switching material, a mixed ion-electron conductor material, a phase change material, or a combination thereof. The phase change material is, for example, a Mott transition material. In some embodiments, the threshold switching material is a chalcogenide. In some embodiments, the bidirectional threshold switching material is an arsenic-containing chalcogenide, an arsenic-free chalcogenide, or a combination thereof. In some embodiments, the bidirectional threshold switching material includes AsSeGe, InAsSeGe, SiAsSeGe, CAsSeGe, CTe, BTe, GeCTe, NGeCTe, or a combination thereof. In some embodiments, the bidirectional threshold switching material further includes one or more dopants, such as B, In, C, Si, S, or a combination thereof. In some embodiments, the mixed ion-electron conductor material is a copper-containing chalcogenide. In some embodiments, the mixed ion-electron conductor material includes CuSbGeTe, CuSbGeSTe, or a combination thereof. In some embodiments, the phase change material includes GeSbTe, SiGeSb, Sb 2 Te 3 、GeTe、Cr 2 Ge 2 Te 6 , VO 2、MoO 2 、V 2 O 3 、NbO 2 , Fe 3 O 4 、FeS、Ta 2 O 5 、Ti 3 O 5 、Ti 2 O 3 、LaCoO 3 、SmNiO 3 or a combination thereof, wherein the ratio of elements in GeSbTe and SiGeSb can be adjusted arbitrarily. The performance of the phase change material is similar to that of the bidirectional threshold switching material.

[0071] In some embodiments, the channel structure CS including the threshold switching material can be formed by sputtering, atomic layer deposition (ALD) or chemical vapor deposition (CVD). In some embodiments, the formation temperature is 100°C to 500°C, for example, 100, 150, 200, 250, 300, 350, 400, 450 or 500°C. It is worth noting that in the channel structure CS including the threshold switching material formed at a temperature equal to or lower than 400°C, the carriers have a high mobility. Therefore, when operating (turning on) the channel structure CS of the semiconductor structure 100 of the present disclosure, a high current may flow through the semiconductor structure 100, and the current may be, for example, higher than 5000000A / cm 2 .

[0072] Figure 2A FIG. 2 is a schematic diagram of a semiconductor structure 200 in operation according to various embodiments of the present disclosure. Figure 2AAs shown, the semiconductor structure 200 includes a substrate 110, a gate G, a channel structure CS1, a gate insulating layer GI, a source S and a drain D. The channel structure CS1 is a bidirectional threshold switching material layer. In some embodiments, the bidirectional threshold switching material layer is an arsenic-containing chalcogenide layer or an arsenic-free chalcogenide layer. In some embodiments, the bidirectional threshold switching material layer includes AsSeGe, InAsSeGe, SiAsSeGe, CAsSeGe, CTe, BTe, GeCTe, NGeCTe or a combination thereof. The channel structure CS1 is disposed on the substrate 110. The gate G is disposed above the channel structure CS1. The gate insulating layer GI is disposed between the gate G and the channel structure CS1 to separate the gate G from the channel structure CS1. In addition, the gate insulating layer GI is disposed between the source S and the drain D. The source S and the drain D directly contact the upper surface US2 of the channel structure CS1.

[0073] Please continue to refer to Figure 2A . The semiconductor structure 200 is a three-terminal switch device. When operating the semiconductor structure 200, the source S can be grounded, a bias can be applied to the drain D, and no bias can be applied to the gate G. When no bias is applied to the gate G, the semiconductor structure 200 can be used as a two-terminal switch device. More specifically, the present disclosure provides an operation method of the semiconductor structure 200, which includes the following operations: receiving the semiconductor structure 200. Applying a first voltage to the drain D, the absolute value of the first voltage is greater than the absolute value of the switching threshold voltage of the threshold switching material of the channel structure CS1, and current will flow through the channel structure CS1.

[0074] Figure 2B For operation Figure 2A Drain current-drain voltage diagram of the semiconductor structure 200, wherein the channel structure CS1 is an In-doped AsSeGe layer. Figure 2B As shown, line 210 is the result of the drain current changing with the drain voltage when the drain voltage is applied for the first time. Multiple lines 220 are the results of the drain current changing with the drain voltage when the drain voltage is applied for the second, third, fourth and fifth times. These lines 220 are substantially overlapped. It can be seen from lines 210 and 220 that when the drain voltage is higher than the switching threshold voltage of the channel structure CS1, the current will flow through the channel structure CS1.

[0075] Figure 3A2 is a schematic diagram of operating a semiconductor structure 200 according to various embodiments of the present disclosure. The semiconductor structure 200 is a three-terminal switch device. When operating the semiconductor structure 200, the source S can be grounded, a bias voltage can be applied to the drain D, and a bias voltage can be applied to the gate G. More specifically, the present disclosure provides an operation method of the semiconductor structure 200, which includes the following operations: receiving the semiconductor structure 200. Applying a first voltage to the drain D, the absolute value of the first voltage is greater than the absolute value of the switching threshold voltage of the threshold switching material of the channel structure CS1. Applying a second voltage to the gate G to regulate the switching threshold voltage of the threshold switching material of the channel structure CS1, wherein the threshold switching material is a bidirectional threshold switching material, and the first voltage is a positive voltage. The switching performance of the semiconductor structure 200, such as the switching threshold voltage, the holding voltage, and the forming voltage, is adjustable and controllable. When a positive voltage is applied to the gate G, an electric field is formed in the vertical direction in the channel structure CS1, so that the electrons in the channel structure CS1 accumulate in the upper part of the channel structure CS1, and therefore, the semiconductor structure 200 is more easily turned on. The switching threshold voltage and holding voltage of the channel structure CS1 decrease as the second voltage increases. When a negative voltage is applied to the gate G, an electric field is formed in the vertical direction of the channel structure CS1, so that the electrons in the channel structure CS1 are away from the upper part of the channel structure CS1, and therefore, the semiconductor structure 200 is less likely to be turned on. Through the above operation method, the semiconductor structure 200 can be turned on, and current flows through the channel structure CS1.

[0076] Figure 3B For operation Figure 3A Schematic diagram of drain current-drain voltage of semiconductor structure 200, wherein channel structure CS1 is an AsSeGe layer doped with In. Line 310 is the result of the change of drain current with drain voltage when -2V is applied to gate G. Line 320 is the result of the change of drain current with drain voltage when 0V is applied to gate G. Line 330 is the result of the change of drain current with drain voltage when 2V is applied to gate G. Line 340 is the result of the change of drain current with drain voltage when 4V is applied to gate G. Line 350 is the result of the change of drain current with drain voltage when 6V is applied to gate G. It can be seen from the above lines that the electrical performance of semiconductor structure 200 can be regulated by the voltage applied to gate G. When a positive voltage is applied to gate G, the electrons in channel structure CS1 will approach upper surface US2, thereby making semiconductor structure 200 easier to be turned on. Therefore, the switching threshold voltage and holding voltage of channel structure CS1 will decrease as the voltage applied to gate G increases. When -2V is applied to the gate G, the drain current becomes smaller. When 6V is applied to the gate G, the drain current-drain voltage is linearly related, which conforms to Ohm's law.

[0077] Figure 4 FIG. 4 is a schematic diagram of a semiconductor structure 400 in operation according to various embodiments of the present disclosure. Figure 4 As shown, the semiconductor structure 400 includes a substrate 110, a gate G, a channel structure CS2, a gate insulating layer GI, a source S and a drain D. The channel structure CS2 is a mixed ion-electron conductor material layer. In some embodiments, the mixed ion-electron conductor material layer is a copper-containing chalcogenide layer. In some embodiments, the mixed ion-electron conductor material layer includes CuSbGeTe, CuSbGeSTe or a combination thereof. The channel structure CS2 is disposed on the substrate 110. The gate G is disposed above the channel structure CS2. The gate insulating layer GI is disposed between the gate G and the channel structure CS2 to separate the gate G from the channel structure CS2. In addition, the gate insulating layer GI is disposed between the source S and the drain D. The source S and the drain D directly contact the upper surface US3 of the channel structure CS2.

[0078] Please continue to refer to Figure 4 . The semiconductor structure 400 is a three-terminal switch device. When operating the semiconductor structure 400, the source S can be grounded, a bias can be applied to the drain D, and no bias can be applied to the gate G. When no bias is applied to the gate G, the semiconductor structure 400 can be used as a two-terminal switch device. More specifically, the present disclosure provides an operation method of a semiconductor structure 400, which includes the following operations: receiving the semiconductor structure 400. Applying a first voltage to the drain D, the absolute value of the first voltage is greater than the absolute value of the switching threshold voltage of the threshold switching material of the channel structure CS2, and current will flow through the channel structure CS2. The channel structure CS2 is a mixed ion-electron conductor material layer, and the mixed ion-electron conductor material is bipolar. The first voltage can be a positive voltage or a negative voltage. When the absolute value of the positive voltage or negative voltage applied to the drain D is greater than the absolute value of the switching threshold voltage of the mixed ion-electron conductor material, the semiconductor structure 400 can be turned on.

[0079] Figure 5A4 is a schematic diagram of operating a semiconductor structure 400 according to various embodiments of the present disclosure. The semiconductor structure 400 is a three-terminal switch device. When operating the semiconductor structure 400, the source S can be grounded, a bias voltage can be applied to the drain D, and a bias voltage can be applied to the gate G. More specifically, the present disclosure provides an operation method of a semiconductor structure 400, which includes the following operations: receiving the semiconductor structure 400. Applying a first voltage to the drain D, the absolute value of the first voltage is greater than the absolute value of the switching threshold voltage of the threshold switching material of the channel structure CS2, wherein the first voltage is a positive voltage or a negative voltage. Applying a second voltage to the gate G to regulate the switching threshold voltage of the threshold switching material of the channel structure CS2, wherein the threshold switching material is a mixed ion-electron conductor material. The switching performance of the semiconductor structure 400 is adjustable and controllable. When a negative voltage is applied to the gate G, an electric field is formed in the vertical direction of the channel structure CS2, so that the cations (such as copper ions) in the channel structure CS2 accumulate in the upper part of the channel structure CS2, and therefore, the semiconductor structure 400 is more easily turned on. The switching threshold voltage and holding voltage of the channel structure CS2 decrease as the second voltage decreases. When a positive voltage is applied to the gate G, an electric field is formed in the vertical direction of the channel structure CS2, so that the cations (such as copper ions) in the channel structure CS2 are away from the upper part of the channel structure CS2, and therefore, the semiconductor structure 400 is less likely to be turned on. Through the above operation method, the semiconductor structure 400 can be turned on, and current will flow through the channel structure CS2.

[0080] Figure 5B For operation Figure 5A Schematic diagram of drain current-drain voltage of semiconductor structure 400, wherein channel structure CS2 is a CuSbGeSTe layer. Line 510 is the result of the change of drain current with drain voltage when -6V is applied to gate G. Line 520 is the result of the change of drain current with drain voltage when -3V is applied to gate G. Line 530 is the result of the change of drain current with drain voltage when 0V is applied to gate G. Line 540 is the result of the change of drain current with drain voltage when 3V is applied to gate G. It can be seen from the above lines that the electrical performance of semiconductor structure 400 can be regulated by the voltage applied to gate G. When a negative voltage is applied to gate G, the copper ions in channel structure CS2 will approach the upper surface US3, making semiconductor structure 400 easier to open. Therefore, the switching threshold voltage and holding voltage of channel structure CS2 will decrease as the voltage applied to gate G decreases. When 3V is applied to gate G, the leakage current will decrease. When -6V is applied to the gate G, the drain current-drain voltage is linearly related, which conforms to Ohm's law.

[0081] For the materials, operation methods and advantages of the semiconductor structures of various embodiments described in the following of this disclosure, please refer to the aforementioned Figures 1 to 5BEmbodiments of the semiconductor structure.

[0082] Figure 6 , Figure 7 and Figure 8 is a schematic cross-sectional view of a semiconductor structure according to various embodiments of the present disclosure. Figure 6 , Figure 7 and Figure 8 The channel structure in is a layered channel.

[0083] like Figure 6 As shown, the semiconductor structure 612 includes a substrate 640, a source S1, a drain D1, a channel structure 652, a first gate insulating layer 662, and a first gate G11. The source S1 and the drain D1 are disposed on the substrate 640. The channel structure 652 is disposed on the source S1 and the drain D1. The first gate insulating layer 662 is disposed on the channel structure 652. The first gate G11 is disposed on the first gate insulating layer 662. In the semiconductor structure 612, the projection of the first gate G11 on the substrate 640 overlaps with the projection of the source S1 and the drain D1 on the substrate 640. Figure 6 As shown, the difference between the semiconductor structure 612 and the semiconductor structure 614 is that the lengths of the first gate G11 and the first gate G12 are different. In the semiconductor structure 614, the projection of the first gate G12 on the substrate 640 does not overlap with the projection of the source S1 and the drain D1 on the substrate 640. Figure 6 As shown, the difference between the semiconductor structure 612 and the semiconductor structure 616 is that the lengths of the first gate G11 and the first gate G13 are different. In the semiconductor structure 616, the projection of the first gate G13 on the substrate 640 overlaps with the projection of the source S1 on the substrate 640, but does not overlap with the projection of the drain D1 on the substrate 640. Figure 6 As shown, the difference between the semiconductor structure 612 and the semiconductor structure 618 is that the lengths of the first gate G11 and the first gate G14 are different. In the semiconductor structure 618, the projection of the first gate G14 on the substrate 640 overlaps with the projection of the drain D1 on the substrate 640, but does not overlap with the projection of the source S1 on the substrate 640.

[0084] like Figure 6 As shown, the semiconductor structure 622 includes a substrate 640, a source S1, a drain D1, a channel structure 654, a first gate insulating layer 664 and a first gate G11. The channel structure 654 is disposed on the substrate 640. The source S1 and the drain D1 are disposed on the channel structure 654. The first gate insulating layer 664 is disposed on the source S1 and the drain D1. The first gate G11 is disposed on the first gate insulating layer 664. In the semiconductor structure 622, the projection of the first gate G11 on the substrate 640 overlaps with the projection of the source S1 and the drain D1 on the substrate 640. Figure 6As shown, the difference between the semiconductor structure 622 and the semiconductor structure 624 is that the lengths of the first gate G11 and the first gate G12 are different. In the semiconductor structure 624, the projection of the first gate G12 on the substrate 640 does not overlap with the projection of the source S1 and the drain D1 on the substrate 640. Figure 6 As shown, the difference between the semiconductor structure 622 and the semiconductor structure 626 is that the lengths of the first gate G11 and the first gate G13 are different. In the semiconductor structure 626, the projection of the first gate G13 on the substrate 640 overlaps with the projection of the source S1 on the substrate 640, but does not overlap with the projection of the drain D1 on the substrate 640. Figure 6 As shown, the difference between the semiconductor structure 622 and the semiconductor structure 628 is that the lengths of the first gate G11 and the first gate G14 are different. In the semiconductor structure 628, the projection of the first gate G14 on the substrate 640 overlaps with the projection of the drain D1 on the substrate 640, but does not overlap with the projection of the source S1 on the substrate 640.

[0085] like Figure 6 As shown, the semiconductor structure 632 includes a substrate 640, a source S1, a drain D1, a channel structure 656, a gate insulating layer 666 and a gate G15. The gate G15 is disposed on the substrate 640. The gate insulating layer 666 is disposed on the gate G15. The source S1 and the drain D1 are disposed on the gate insulating layer 666. The channel structure 656 is disposed on the source S1 and the drain D1. Figure 6 As shown, the semiconductor structure 634 includes a substrate 640, a source S1, a drain D1, a channel structure 658, a gate insulating layer 666 and a gate G15. The gate G15 is disposed on the substrate 640. The gate insulating layer 666 is disposed on the gate G15. The channel structure 656 is disposed on the gate insulating layer 666. The source S1 and the drain D1 are disposed on the channel structure 656.

[0086] like Figure 7As shown, the semiconductor structure 712 includes a substrate 640, a source S1, a drain D1, a channel structure 652, a first gate insulating layer 662, a second gate insulating layer 668, a first gate G11 and a second gate G21. The difference between the semiconductor structure 712 and the semiconductor structure 612 is that the semiconductor structure 712 also includes: a second gate G21 and a second gate insulating layer 668, wherein the second gate G21 is disposed on the substrate 640, the second gate insulating layer 668 is disposed on the second gate G21, and the source S1 and the drain D1 are disposed on the second gate insulating layer 668. The thickness of the first gate insulating layer 662 and the second gate insulating layer 668 is the same or different. The first gate insulating layer 662 can be thicker than the second gate insulating layer 668, or the second gate insulating layer 668 can be thicker than the first gate insulating layer 662. Similarly, compared with the semiconductor structures 614 , 616 , 618 , the semiconductor structures 714 , 716 , 718 further include: a second gate G21 and a second gate insulating layer 668 , wherein the second gate G21 is disposed on the substrate 640 , the second gate insulating layer 668 is disposed on the second gate G21 , and the source S1 and the drain D1 are disposed on the second gate insulating layer 668 .

[0087] like Figure 7 As shown, the semiconductor structure 722 includes a substrate 640, a source S1, a drain D1, a channel structure 654, a first gate insulating layer 664, a second gate insulating layer 668, a first gate G11 and a second gate G21. The difference between the semiconductor structure 722 and the semiconductor structure 622 is that the semiconductor structure 722 also includes: a second gate G21 and a second gate insulating layer 668, wherein the second gate G21 is disposed on the substrate 640, the second gate insulating layer 668 is disposed on the second gate G21, and the channel structure 654 is disposed on the second gate insulating layer 668. The thickness of the first gate insulating layer 664 and the second gate insulating layer 668 is the same or different. The first gate insulating layer 664 can be thicker than the second gate insulating layer 668, or the second gate insulating layer 668 can be thicker than the first gate insulating layer 664. Similarly, compared with the semiconductor structures 624 , 626 , and 628 , the semiconductor structures 724 , 726 , and 728 further include: a second gate G21 and a second gate insulating layer 668 , wherein the second gate G21 is disposed on the substrate 640 , the second gate insulating layer 668 is disposed on the second gate G21 , and the channel structure 654 is disposed on the second gate insulating layer 668 .

[0088] Please continue to refer to Figure 7, the operation method of controlling the switching threshold voltage of the channel structures 652 and 654 includes: applying a first voltage to the first gate G11, applying a second voltage to the second gate G21, and the first voltage and the second voltage can be the same or different. Since the channel structures 652 and 654 can be controlled by two gates, the channel structures 652 and 654 can be controlled more accurately, and the leakage current of the channel structures 652 and 654 will be smaller.

[0089] like Figure 8 As shown, the semiconductor structure 812 includes a substrate 640, a first source / drain SD1, a second source / drain SD2, a channel structure 659, a first gate insulating layer 672, a second gate insulating layer 674, a first gate G11, and a second gate G21. The second gate G21 is disposed on the substrate 640. The second gate insulating layer 674 is disposed on the second gate G21. The channel structure 659 is disposed on the second gate insulating layer 674. The first source / drain SD1 contacts the upper surface of the channel structure 659, and the second source / drain SD2 contacts the lower surface of the channel structure 659. In some embodiments, one of the first source / drain SD1 and the second source / drain SD2 is a source, and the other is a drain. Therefore, among the source and the drain, the first directly contacts the upper surface of the channel structure 659, and the second directly contacts the lower surface of the channel structure 659. The first gate insulating layer 672 is disposed on the channel structure 659. The first gate G11 is disposed on the first gate insulating layer 672. The thickness of the first gate insulating layer 672 and the second gate insulating layer 674 may be the same or different. The first gate insulating layer 672 may be thicker than the second gate insulating layer 674, or the second gate insulating layer 674 may be thicker than the first gate insulating layer 672.

[0090] Please continue to refer to Figure 8 In the semiconductor structure 812, the projection of the first gate G11 on the substrate 640 overlaps with the projection of the first source / drain SD1 and the second source / drain SD2 on the substrate 640. Figure 8 As shown, the difference between the semiconductor structure 812 and the semiconductor structure 814 is that the lengths of the first gate G11 and the first gate G12 are different. In the semiconductor structure 814, the projection of the first gate G12 on the substrate 640 does not overlap with the projection of the first source / drain SD1 and the second source / drain SD2 on the substrate 640. Figure 8 As shown, the difference between the semiconductor structure 812 and the semiconductor structure 816 is that the lengths of the first gate G11 and the first gate G13 are different. In the semiconductor structure 816, the projection of the first gate G13 on the substrate 640 overlaps with the projection of the first source / drain SD1 on the substrate 640, but does not overlap with the projection of the second source / drain SD2 on the substrate 640. Figure 6As shown, the difference between the semiconductor structure 612 and the semiconductor structure 618 is that the lengths of the first gate G11 and the first gate G14 are different. In the semiconductor structure 618, the projection of the first gate G14 on the substrate 640 overlaps with the projection of the second source / drain SD2 on the substrate 640, but does not overlap with the projection of the first source / drain SD1 on the substrate 640.

[0091] Please continue to refer to Figure 8 The method for controlling the switching threshold voltage of the channel structure 659 includes: applying a first voltage to the first gate G11, applying a second voltage to the second gate G21, and the first voltage and the second voltage can be the same or different. Since the channel structure 659 can be controlled by two gates, the channel structure 659 can be controlled more accurately, and the leakage current of the channel structure 659 will be smaller.

[0092] Fig.9A is a schematic three-dimensional diagram of a semiconductor structure 900 according to various embodiments of the present disclosure. Fig. 9B According to various embodiments of the present disclosure Fig.9A A schematic cross-sectional view of the semiconductor structure 900 along the section line aa. Fig.9A As shown, the semiconductor structure 900 includes a gate 910, a channel structure 920, a gate insulating layer 930, a drain 940 and a source 950. The gate insulating layer 930 surrounds the channel structure 920, wherein the channel structure 920 is a columnar channel. The gate 910 surrounds the gate insulating layer 930 and is separated from the channel structure 920 by the gate insulating layer 930. The drain 940 and the source 950 are directly in contact with both ends of the channel structure 920, respectively.

[0093] Fig.101 is a schematic cross-sectional view of a semiconductor structure 1000 according to various embodiments of the present disclosure. The semiconductor structure 1000 includes a substrate 1010, a stack 1020, a channel structure 1030, a gate insulating layer 1040 and a gate 1050. The channel structure 1030 is a layered channel. The stack 1020 includes a plurality of source / drain layers 1022 and a plurality of insulating layers 1024 that are alternately stacked. The channel structure 1030 covers the sidewalls of the stack 1020. In more detail, the channel structure 1030 directly contacts the plurality of sidewalls of the source / drain layer 1022 and the insulating layer 1024. Each source / drain layer 1022 may be a source or a drain. For example, two adjacent source / drain layers 1022 are a source and a drain, respectively, the insulating layer 1024 is disposed between the source / drain layers 1022, and the channel structure 1030 directly contacts the plurality of sidewalls of the source and the drain. The gate insulating layer 1040 covers the channel structure 1030. The gate 1050 covers the gate insulating layer 1040. When the semiconductor structure 1000 is operated, the current flowing through the channel structure 1030 is substantially perpendicular to the upper surface of the substrate 1010. When a voltage is applied to the gate 1050, an induced electric field can be generated in the gate insulating layer 1040, and this induced electric field can control whether the channel structure 1030 is turned on. When the conduction state of the channel structure 1030 is to be read, a voltage can be applied between any two source / drain layers 1022 to read the current value. In addition, the number of source / drain layers 1022 and insulating layers 1024 in the stack 1020 can be arbitrarily adjusted according to design requirements. In some embodiments, the insulating layer 1024 includes an oxide, a nitride, or a combination thereof, such as silicon dioxide, silicon nitride, or a combination thereof.

[0094] Fig.11 1 is a three-dimensional schematic diagram of a semiconductor structure 1110 according to various embodiments of the present disclosure. When the semiconductor structure 1110 is a fin field-effect transistor (Fin Field-Effect Transistor, FinFET), the cross-sectional schematic diagram of the semiconductor structure 1110 along the section line AA' is shown in FIG. Fig. 12A For a cross-sectional view of the semiconductor structure 1110 along the section line BB', please refer to Fig. 12B .like Fig.11 , Fig. 12A and Fig. 12BAs shown, the semiconductor structure 1110 includes a substrate 1010, a threshold switching material layer 1120, an isolation structure 1130, a source 1142, a drain 1144, a gate structure 1150, a gate spacer 1160, a contact etch stop layer (CESL layer) 1180 and an interlayer dielectric layer (ILD layer) 1170. The threshold switching material layer 1120 is disposed on the substrate 1010. The threshold switching material layer 1120 has at least one channel structure 1122, and the channel structure 1122 is a fin structure, which is also a layered channel. Although Fig. 12A Only one fin structure is shown, but the number of fin structures can be adjusted arbitrarily according to design requirements. The isolation structure 1130 can be a shallow trench isolation (STI) structure. The isolation structure 1130 is used to separate adjacent channel structures 1122. The channel structure 1122 can protrude above and between adjacent isolation structures 1130. The gate structure 1150 spans the channel structure 1122 and covers multiple sidewalls and top surfaces of the channel structure 1122. In more detail, the gate structure 1150 includes a gate insulating layer 1152 and a gate 1154. The gate insulating layer 1152 is disposed between the channel structure 1122 and the gate 1154. The gate 1154 covers multiple sidewalls and top surfaces of the gate insulating layer 1152 and the channel structure 1122. The gate insulating layer 1152 may include an interfacial layer (IL layer) and a high-k gate insulating layer (high-k insulating layer) located on the interfacial layer. For example, the interfacial layer includes silicon oxide or the like. For example, the high-k gate insulating layer includes a metal oxide, such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, lanthanum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, barium zirconium oxide, aluminum oxide, or a combination thereof. A pair of gate spacers 1160 spans the channel structure 1122 and is disposed on both sides of the gate structure 1150. The source 1142 and the drain 1144 are respectively disposed on both sides of the channel structure 1122 and directly contact the channel structure 1122. The contact etch stop layer 1180 covers the gate spacer 1160, the upper surface of the source 1142, and the upper surface of the drain 1144. The interlayer dielectric layer 1170 covers the contact etch stop layer 1180.

[0095] Please refer again Fig.11 When the semiconductor structure 1110 is a gate-all-around transistor (GAA), the cross-sectional view of the semiconductor structure 1110 along the section line AA' is shown in FIG. Fig.13AFor a cross-sectional view of the semiconductor structure 1110 along the section line BB', please refer to Fig. 13B .like Fig.11 , Fig.13A and Fig. 13B As shown, the semiconductor structure 1110 includes a substrate 1010, a threshold switching material layer 1120, an isolation structure 1130, a source 1142, a drain 1144, a gate structure 1150, a gate spacer 1160, a contact etch stop layer 1180, an interlayer dielectric layer 1170 and a plurality of inner spacers 1190. The threshold switching material layer 1120 is disposed on the substrate 1010. The threshold switching material layer 1120 has at least one channel structure 1124, and the channel structure 1124 includes a plurality of nanosheet channels. Fig.13A Only three nanosheet channels are shown, but the number of nanosheet channels can be adjusted arbitrarily according to design requirements. The isolation structure 1130 can be an STI structure. The gate structure 1150 surrounds the nanosheet channels. In more detail, the gate structure 1150 includes a gate insulating layer 1152 and a gate 1154. The gate insulating layer 1152 is disposed between the channel structure 1124 and the gate 1154. The gate 1154 surrounds the nanosheet channels. The gate insulating layer 1152 may include an interface layer and a high-k gate insulating layer on the interface layer. The internal spacer 1190 is sandwiched between the gate structure 1150 and the source 1142, and is sandwiched between the gate structure 1150 and the drain 1144. A pair of gate spacers 1160 spans the channel structure 1122 and is disposed on both sides of the gate structure 1150. The source 1142 and the drain 1144 are respectively disposed on both sides of the channel structure 1124 including the nanosheet channels, and directly contact the channel structure 1124. The contact etch stop layer 1180 covers the gate spacer 1160 , the upper surface of the source 1142 , and the upper surface of the drain 1144 . The interlayer dielectric layer 1170 covers the contact etch stop layer 1180 .

[0096] In summary, the present disclosure provides a semiconductor structure and an operating method thereof, wherein a channel structure of the semiconductor structure includes a threshold switching material. The channel structure can be manufactured at a relatively low process temperature and still have a high carrier mobility. Furthermore, when the semiconductor structure of the present disclosure is integrated into a process such as BEOL, the process temperature for forming the channel structure will not damage other components, so that other components still maintain good electrical performance.

[0097] Although the present disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0098] It is obvious to those skilled in the art that various modifications and changes can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and changes of the present disclosure that fall within the scope of the appended claims.

Claims

1. A semiconductor structure comprising: a first gate; a channel structure comprising a threshold switching material, wherein the channel structure comprises a layered channel, a columnar channel or a plurality of nanosheet channels; a first gate insulating layer, disposed between the first gate and the channel structure; a source electrode directly contacting the channel structure; as well as A drain electrode directly contacts the channel structure. 2 . The semiconductor structure according to claim 1 , wherein the threshold switching material comprises a bidirectional threshold switching material, a mixed ion-electron conductor material, a phase change material or a combination thereof. The semiconductor structure according to claim 2 , wherein the threshold switching material is a chalcogenide. 4 . The semiconductor structure according to claim 2 , wherein the bidirectional threshold switching material comprises AsSeGe, InAsSeGe, SiAsSeGe, CAsSeGe, CTe, BTe, GeCTe, NGeCTe or a combination thereof.

5. The semiconductor structure of claim 2, wherein the mixed ion-electron conductor material comprises CuSbGeTe, CuSbGeSTe or a combination thereof. 6 . The semiconductor structure according to claim 1 , wherein the source and the drain contact an upper surface of the channel structure, and the first gate insulating layer is disposed between the source and the drain. 7 . The semiconductor structure according to claim 1 , wherein the channel structure is disposed on the source and the drain, the first gate insulating layer is disposed on the channel structure, and the first gate is disposed on the first gate insulating layer.

8. The semiconductor structure according to claim 7, further comprising: A second gate and a second gate insulating layer, wherein the second gate insulating layer is disposed on the second gate, and the source and the drain are disposed on the second gate insulating layer. 9 . The semiconductor structure according to claim 1 , wherein the source and the drain are disposed on the channel structure, the first gate insulating layer is disposed on the source and the drain, and the first gate is disposed on the first gate insulating layer.

10. The semiconductor structure according to claim 9, further comprising: A second gate and a second gate insulating layer, wherein the second gate insulating layer is disposed on the second gate, and the channel structure is disposed on the second gate insulating layer. 11 . The semiconductor structure according to claim 1 , wherein the first gate insulating layer is disposed on the first gate, the source and the drain are disposed on the first gate insulating layer, and the channel structure is disposed on the source and the drain. 12 . The semiconductor structure according to claim 1 , wherein the first gate insulating layer is disposed on the first gate, the channel structure is disposed on the first gate insulating layer, and the source and the drain are disposed on the channel structure.

13. The semiconductor structure of claim 1, further comprising: A second gate and a second gate insulating layer, wherein the second gate insulating layer is arranged on the second gate, the channel structure is arranged on the second gate insulating layer, in the source and the drain, a first one directly contacts an upper surface of the channel structure, and a second one directly contacts a lower surface of the channel structure, the first gate insulating layer is arranged on the channel structure, and the first gate is arranged on the first gate insulating layer.

14. The semiconductor structure according to claim 1, wherein the first gate covers a plurality of sidewalls and a top surface of the channel structure. 15 . The semiconductor structure according to claim 1 , wherein the channel structure comprises the nanosheet channels, and the first gate surrounds the nanosheet channels. 16 . The semiconductor structure according to claim 1 , further comprising an insulating layer, wherein the insulating layer is disposed between the source and the drain, and the channel structure directly contacts a plurality of sidewalls of the insulating layer, the source, and the drain.

17. A method for operating a semiconductor structure, comprising: Receiving a semiconductor structure according to any one of claims 1 to 16; as well as A first voltage is applied to the drain, wherein an absolute value of the first voltage is greater than an absolute value of a switching threshold voltage of the threshold switching material of the channel structure.

18. The operating method according to claim 17, further comprising: A second voltage is applied to the first gate to adjust the switching threshold voltage of the threshold switching material of the channel structure. 19 . The operating method according to claim 17 , wherein the threshold switching material is a bidirectional threshold switching material, and the first voltage is a positive voltage. 20 . The operating method according to claim 17 , wherein the threshold switching material is a mixed ion-electron conductor material, and the first voltage is a positive voltage or a negative voltage.

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