Main and standby clock switching circuit

Abstract

The embodiment of the invention provides a main and standby clock switching circuit, which comprises a clock disconnection identification circuit, a clock selection and reset control generation circuit connected with the clock disconnection identification circuit, and a clock switching circuit connected with the clock selection and reset control generation circuit, the detection module is used for determining whether the master clock is offline according to a master clock signal of the master clock and outputting a detection signal; the clock selection and reset control generation circuit is used for generating a clock selection signal and a reset and release signal of the clock switching circuit according to the detection signal, and inputting the clock selection signal and the reset and release signal to the clock switching circuit; and the clock switching circuit is used for determining whether to switch the master clock to the backup clock according to the clock selection signal and the reset and release signal.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of circuit design, and more particularly, to a primary and backup clock switching circuit. Background Art

[0002] In the design of a System on Chip (SOC), there is usually a switch between a high-frequency primary clock WORK_CLK (or called working clock) and a low-frequency backup clock BAK_CLK; in the low-power mode, the primary clock is turned off or the primary clock is accidentally lost (for example, when the high-frequency clock WORK_CLK is output by a Phase Management Area (PMA), a Phase Locked Loop (PLL), etc., when the PMA and PLL enter the reset state or the input clock of the PMA and PLL drops out of line, the high-frequency clock output by the PMA and PLL will drop out of line and be lost), the switch will be made from WORK_CLK to BAK_CLK.

[0003] However, in the related art, when detecting whether the primary clock drops out of line, it depends on the frequency relationship between the primary clock and the backup clock, and a counter; when detecting whether the primary clock drops out of line, the backup clock is used to count the clock cycle after dividing the WORK_CLK. When the frequency of the primary clock is low and the clock frequency after dividing the primary clock is even lower, it may be impossible to determine whether the clock drops out of line or it is impossible to predict when it can be determined whether the primary clock drops out of line, or it may take many cycles to determine whether the clock drops out of line, and there is a problem of clock switching glitches when the clock drops out of line.

[0004] In view of the related art, it is necessary to rely on an additional reference clock to identify whether the primary clock drops out of line, and there is a problem of clock switching glitches when the primary clock drops out of line. Currently, no effective solution has been proposed.

[0005] Therefore, it is necessary to improve the related art to overcome the above-mentioned defects in the related art. Summary of the Invention

[0006] The embodiments of the present application provide a primary and backup clock switching circuit to at least solve the problems in the related art that it is necessary to rely on an additional reference clock to identify whether the primary clock drops out of line, and there are clock switching glitches when the primary clock drops out of line.

[0007] According to an embodiment of the present application, a primary and backup clock switching circuit is provided, including: a clock dropout identification circuit, a clock selection and reset control generation circuit connected to the clock dropout identification circuit, and a clock switching circuit connected to the clock selection and reset control generation circuit. Among them, the clock dropout identification circuit is used to determine whether the primary clock drops out according to the primary clock signal of the primary clock, and output a detection signal; the clock selection and reset control generation circuit is used to generate a clock selection signal and a reset and release signal of the clock switching circuit according to the detection signal, and input the clock selection signal and the reset and release signal to the clock switching circuit; the clock switching circuit is used to determine whether to switch the primary clock to the backup clock according to the clock selection signal and the reset and release signal.

[0008] In an exemplary embodiment, the clock dropout identification circuit includes: a delay circuit, a multiplexer connected to the delay circuit, a first logic gate connected to the multiplexer, a first reset register connected to the first logic gate, and a first inverter connected to the first reset register. Among them, the delay circuit is used to delay the primary clock signal to obtain a plurality of delayed primary clock signals, and input the plurality of delayed primary clock signals to the multiplexer; the multiplexer is used to determine a target primary clock signal among the plurality of delayed primary clock signals, and input the target primary clock signal to the first logic gate; the first logic gate is used to perform a logical OR operation on the target primary clock signal and the primary clock signal to obtain a first reset signal, and input the first reset signal to the first reset register; the first inverter is used to invert the primary clock signal to obtain an inverted primary clock signal, and input the inverted primary clock signal to the first reset register; the first reset register is used to determine whether the primary clock drops out according to the received high-level signal, the first reset signal, and the inverted primary clock signal, and output the detection signal.

[0009] In an exemplary embodiment, the delay circuit includes: multiple groups of delay units, where the delay unit is used to delay the primary clock signal to obtain the delayed primary clock signal.

[0010] In an exemplary embodiment, the clock selection and reset control generation circuit includes: an enable signal generation circuit, a clock selection signal generation circuit, a reset and release signal generation circuit, and a primary clock signal output circuit connected to the enable signal generation circuit. Among them, the enable signal generation circuit is used to generate a first enable signal according to the detection signal; the clock selection signal generation circuit is used to generate the clock selection signal according to the first enable signal;

[0011] The reset and release signal generation circuit is configured to generate the reset and release signal according to the first enable signal; the main clock signal output circuit is configured to determine whether to output the main clock signal according to the first enable signal.

[0012] In an exemplary embodiment, the enable signal generation circuit includes: a second inverter, a first data synchronization unit connected to the second inverter, a second logic gate connected to the first data synchronization unit, and a second data synchronization unit connected to the second logic gate. Wherein, the second inverter is configured to perform an inversion operation on the detection signal to obtain an inverted detection signal, and input the inverted detection signal to the first data synchronization unit; the first data synchronization unit is configured to perform data synchronization on the inverted detection signal according to the backup clock to obtain a first synchronization signal, and input the first synchronization signal to the second logic gate; the second data synchronization unit is configured to perform data synchronization on the active switching signal according to the backup clock to obtain a second synchronization signal, and input the second synchronization signal to the second logic gate, where the active switching signal is used to indicate the indication information sent by the target object; the second logic gate is configured to perform a logical OR operation on the first synchronization signal and the second synchronization signal to obtain the first enable signal.

[0013] In an exemplary embodiment, the clock selection signal generation circuit includes: a second reset register, a third reset register connected to the second reset register, and a third inverter connected to the third reset register. Wherein, the second reset register is configured to receive the first enable signal, the backup clock signal and the second reset signal corresponding to the backup clock signal, and determine a first output signal according to the first enable signal, the backup clock signal and the second reset signal, and output the first output signal to the third reset register; the third reset register is configured to receive the first output signal, the backup clock signal and the second reset signal corresponding to the backup clock signal, and determine a second output signal according to the first output signal, the backup clock signal and the second reset signal, and output the second output signal to the third inverter; the third inverter is configured to perform an inversion operation on the second output signal to generate the clock selection signal.

[0014] In an exemplary embodiment, the reset and release signal generation circuit includes: a rising edge detection circuit, a fourth inverter connected to the rising edge detection circuit, and a cascaded reset synchronization unit connected to the fourth inverter. The rising edge detection circuit is configured to receive the second output signal, perform a target operation on the second output signal to obtain a third output signal, and input the third output signal to the fourth inverter. The fourth inverter is configured to perform an inversion operation on the third output signal to obtain an inverted fourth output signal, and input the fourth output signal to the cascaded reset synchronization unit. The cascaded reset synchronization unit is configured to synchronize the fourth output signal according to the backup clock to generate the reset and release signal.

[0015] In an exemplary embodiment, the rising edge detection circuit is further configured to latch the second output signal to obtain a second input signal, perform an inversion operation on the second input signal to obtain a third input signal, and perform a logical AND operation on the third input signal and the second output signal to obtain the third output signal.

[0016] In an exemplary embodiment, the master clock signal output circuit includes: a dedicated clock gating unit, and a fifth inverter connected to the dedicated clock gating unit. The fifth inverter is configured to perform an inversion operation on the first enable signal to obtain a second enable signal, and input the second enable signal to the enable terminal of the dedicated clock gating unit. The dedicated clock gating unit is configured to determine whether to output the master clock signal according to the second enable signal.

[0017] In an exemplary embodiment, the clock switching circuit is further configured to determine to switch the master clock to the backup clock according to the clock selection signal and the reset and release signal when the dedicated clock gating unit does not output the master clock signal, and determine not to allow switching the master clock to the backup clock according to the clock selection signal and the reset and release signal when the dedicated clock gating unit outputs the master clock signal.

[0018] According to another embodiment of the present application, there is also provided a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any one of the above method embodiments when running.

[0019] According to another embodiment of the present application, there is also provided an electronic device including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0020] According to another embodiment of the present application, a computer program product is further provided, including a computer program, and when the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0021] The master-slave clock switching circuit in the present application includes: a clock disconnection identification circuit, a clock selection and reset control generation circuit connected to the clock disconnection identification circuit, and a clock switching circuit connected to the clock selection and reset control generation circuit. Among them, the clock disconnection identification circuit is used to determine whether the master clock is disconnected according to the master clock signal of the master clock, and output a detection signal; the clock selection and reset control generation circuit is used to generate a clock selection signal and a reset and release signal of the clock switching circuit according to the detection signal, and input the clock selection signal and the reset and release signal of the clock switching circuit to the clock switching circuit; the clock switching circuit is used to determine whether to switch the master clock to the backup clock according to the clock selection signal and the reset and release signal of the clock switching circuit, that is, the clock disconnection identification circuit in the embodiment of the present application can quickly identify whether the master clock is disconnected only through the master clock signal; the clock selection and reset control generation circuit generates a clock selection signal and a reset and release signal according to the detection signal to ensure glitch-free clock switching; the clock switching circuit responds to the clock selection signal and the reset and release signal to achieve seamless switching between the master clock and the backup clock, ensuring the stability and continuity of the clock signal during the switching process and avoiding glitches. Therefore, the problem of relying on an additional reference clock to identify whether the master clock is disconnected and the problem of glitches in clock switching when the master clock is disconnected can be solved. Description of the Drawings

[0022] Figure 1 is the circuit diagram of the master-slave clock switching circuit according to the embodiment of the present application;

[0023] Figure 2 is the circuit diagram of the clock disconnection identification circuit according to the optional embodiment of the present application;

[0024] Figure 3 is the signal timing diagram of the clock disconnection identification circuit according to the optional embodiment of the present application;

[0025] Figure 4 is the circuit diagram of the clock selection and reset generation circuit according to the optional embodiment of the present application;

[0026] Figure 5 is the circuit diagram of the master-slave clock switching circuit according to the optional embodiment of the present application;

[0027] Figure 6 is the circuit diagram of the clock switching device according to the optional embodiment of the present application;

[0028] Figure 7 It is a schematic diagram of clock switching output in case of clock disconnection according to an alternative embodiment of the present application. Detailed implementation manners

[0029] In the following, embodiments of the present application will be described in detail with reference to the accompanying drawings and in combination with embodiments.

[0030] It should be noted that the terms "first", "second", etc. in the description and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence.

[0031] In this embodiment, a primary and backup clock switching circuit is provided. Figure 1 It is a circuit diagram of the primary and backup clock switching circuit according to an embodiment of the present application, as Figure 1 shown. The primary and backup clock switching circuit includes the following:

[0032] A clock disconnection identification circuit 12, a clock selection and reset control generation circuit 14 connected to the clock disconnection identification circuit 12, and a clock switching circuit 16 connected to the clock selection and reset control generation circuit 14. Among them,

[0033] The clock disconnection identification circuit 12 is used to determine whether the primary clock is disconnected according to the primary clock signal of the primary clock, and output a detection signal.

[0034] The clock selection and reset control generation circuit 14 is used to generate a clock selection signal and a reset and release signal for the clock switching circuit according to the detection signal, and input the clock selection signal and the reset and release signal to the clock switching circuit 16.

[0035] The clock switching circuit 16 is used to determine whether to switch the primary clock to a backup clock according to the clock selection signal and the reset and release signal.

[0036] The master-slave clock switching circuit in this application includes: a clock dropout identification circuit, a clock selection and reset control generation circuit connected to the clock dropout identification circuit, and a clock switching circuit connected to the clock selection and reset control generation circuit. Among them, the clock dropout identification circuit is used to determine whether the master clock drops out according to the master clock signal of the master clock and output a detection signal; the clock selection and reset control generation circuit is used to generate a clock selection signal and a reset and release signal of the clock switching circuit according to the detection signal, and input the clock selection signal and the reset and release signal of the clock switching circuit to the clock switching circuit; the clock switching circuit is used to determine whether to switch the master clock to the backup clock according to the clock selection signal and the reset and release signal of the clock switching circuit. That is, in the clock dropout identification circuit in the embodiment of this application, it can quickly identify whether the master clock drops out only through the master clock signal; the clock selection and reset control generation circuit generates a clock selection signal and a reset and release signal of the clock switching circuit according to the detection signal to ensure glitch-free clock switching; the clock switching circuit responds to the clock selection signal and the reset and release signal of the clock switching circuit to achieve seamless switching between the master clock and the backup clock, ensuring the stability and continuity of the clock signal during the switching process and avoiding the generation of glitches. Therefore, it can solve the problems of relying on an additional reference clock to identify whether the master clock drops out and having glitches in clock switching when the master clock drops out.

[0037] Optionally, the clock dropout identification circuit in the embodiment of this application includes: a delay circuit, a multiplexer connected to the delay circuit, a first logic gate connected to the multiplexer, a first reset register connected to the first logic gate, and a first inverter connected to the first reset register. Among them,

[0038] The delay circuit is used to delay the master clock signal to obtain a plurality of delayed master clock signals, and input the plurality of delayed master clock signals into the multiplexer;

[0039] The multiplexer is used to determine a target master clock signal among the plurality of delayed master clock signals and input the target master clock signal into the first logic gate;

[0040] The first logic gate is used to perform a logical OR operation on the target master clock signal and the master clock signal to obtain a first reset signal, and input the first reset signal into the first reset register;

[0041] The first inverter is used to perform an inversion operation on the master clock signal to obtain an inverted master clock signal, and input the inverted master clock signal into the first reset register;

[0042] The first reset register is used to determine whether the main clock is offline according to the received high-level signal, the first reset signal, and the inverted main clock signal, and output the detection signal.

[0043] Wherein, the delay circuit includes: multiple groups of delay units, and the delay unit is used to delay the main clock signal to obtain the delayed main clock signal.

[0044] In the embodiment of the present application, the clock offline identification circuit is implemented by comparing the phase relationship between the clock signal and its delayed signal. Specifically, the clock offline identification circuit first uses a delay unit (such as an inverter or a buffer) to delay the main clock signal to generate a clock signal with a phase shift. The amount of delay is selected by dly_sel, which usually needs to be set between 1 / 4 and 1 / 2 of the signal period of the main clock signal to ensure that there is a certain overlap between the main clock signal and the delayed clock signal when the clock is normal. However, when the main clock signal is offline, this overlap will disappear.

[0045] By using a logical "OR" gate (OR1) to combine the main clock signal and the delayed clock signal, under normal circumstances, due to the presence and phase difference of the clock signal, at least at a certain point in time, one of the two signals will be high level. Therefore, the output RSTN of the "OR" gate will also remain high level. When the main clock is offline, both the main clock signal and the delayed clock signal will become low level, without signal rising edges or falling edges. Therefore, the output of the "OR" gate will also become a continuous low level.

[0046] The D terminal of the first reset register is connected to the high level "1", the CK terminal is connected to the inverted output of the main clock signal, and the reset terminal is connected to the output of the "OR" gate, that is, the first reset signal.

[0047] When the main clock signal is normal, the first reset signal is at a high level, and the input of the Q terminal of the first reset register (i.e., the detection signal) remains at a high level "1", indicating that the clock is online. When the main clock is offline, the first reset signal becomes low level, the first reset register is reset, and the input of its Q terminal (i.e., the detection signal) becomes low level "0", indicating that the main clock is offline.

[0048] It should be noted that the detection signal indicates whether the main clock is offline in the form of a logic level. When the main clock is normal and present, the detection signal outputs a high level (usually indicating 1), indicating that the main clock is running normally without dropping offline. On the contrary, when the main clock is offline, the detection signal outputs a low level (usually indicating 0), which triggers the mechanism to automatically switch to the backup clock BAKCLK.

[0049] Optionally, the circuit diagram of the clock dropout recognition circuit in the embodiments of the present application is as shown in Figure 2 and includes:

[0050] The dropout clock recognition circuit performs N groups of delays on CLK1 (i.e., the above-mentioned main clock signal) using delay units with a group of 2 inverters or units with a group of 1 buffer; the outputs of the different groups of unit delays are all introduced into the input terminals of the multiplexer, and the SEL terminal of the multiplexer is connected to the dly_sel signal. Among them, by changing the dly_sel terminal, WORK_CLK with different delays can be selected; the output of the multiplexer is CLK1 after phase delay, which is called CLK2 (i.e., the above-mentioned delayed main clock signal). The amount of delay is selected using dly_sel, and the inserted delay selected by dly_sel is usually set between 1 / 4 and 1 / 2 of the signal period of the main clock signal. CLK1 and CLK2 are subjected to an "OR" ( Figure 2 OR1 in the above, the above-mentioned first logic gate) logic and then the output RSTN (i.e., the above-mentioned first reset signal) is connected to the reset terminal of the first reset register. The clock terminal CK interface of the first reset register is connected to the output of CLK1 after passing through an inverter, the D terminal is connected to a high level or a constant "1", and the reset terminal is connected to the output of "OR1". The output Q terminal of the first reset register can realize that when WORK_CLK exists, Q of the first reset register (called LOSS_N_SEL in Figure 3 and also the above-mentioned detection signal) outputs a high level '1', and when WORK_CLK drops out and becomes low level, Q of the first reset register (also called LOSS_N_SEL and also the above-mentioned detection signal) outputs a low level '0'. Among them, the signal timing diagram of the clock dropout recognition circuit in the optional embodiment of the present application is as shown in Figure 3 and is as follows.

[0051] The detection signal is the key to automatic clock fault detection and recovery, enabling the circuit to automatically identify and respond to the main clock dropout event without relying on external instructions. In the embodiments of the present application, the detection signal acts on the clock switching logic to achieve automatic or forced switching between the main clock and the backup clock, ensuring that the circuit can correctly and seamlessly use the available clock source under any conditions (such as the working clock dropping out or the need to actively switch to the backup clock). And in the embodiments of the present application, the clock dropout recognition circuit quickly identifies whether the main clock drops out by using multiple groups of delay units, selectively inserting different amounts of delay, and comparing the phase with the main clock signal.

[0052] Optionally, the above-mentioned clock selection and reset control generation circuit includes: an enable signal generation circuit, a clock selection signal generation circuit, a reset and release signal generation circuit, and a main clock signal output circuit connected to the enable signal generation circuit, where

[0053] The enabling signal generation circuit is configured to generate a first enabling signal according to the detection signal;

[0054] The clock selection signal generation circuit is configured to generate the clock selection signal according to the first enabling signal; the reset and release signal generation circuit is configured to generate the reset and release signal according to the first enabling signal; the main clock signal output circuit is configured to determine whether to output the main clock signal according to the first enabling signal.

[0055] Optionally, the above-mentioned enabling signal generation circuit includes: a second inverter, a first data synchronization unit connected to the second inverter, a second logic gate connected to the first data synchronization unit, and a second data synchronization unit connected to the second logic gate, wherein

[0056] The second inverter is configured to invert the detection signal to obtain an inverted detection signal, and input the inverted detection signal to the first data synchronization unit;

[0057] The first data synchronization unit is configured to perform data synchronization on the inverted detection signal according to the backup clock to obtain a first synchronization signal, and input the first synchronization signal to the second logic gate;

[0058] The second data synchronization unit is configured to perform data synchronization on the active switching signal according to the backup clock to obtain a second synchronization signal, and input the second synchronization signal to the second logic gate, wherein the active switching signal is used to indicate the indication information sent by the target object;

[0059] The second logic gate is configured to perform a logical OR operation on the first synchronization signal and the second synchronization signal to obtain the first enabling signal.

[0060] In the embodiment of the present application, as Figure 4As shown, the detection signal LOSS_N_SEL and the active switching signal FORCE_SEL are first synchronized by the data synchronization units (sync_data1 and sync_data2, i.e., the above-mentioned first data synchronization unit and second data synchronization unit) to ensure that no glitches or metastability problems are introduced when the signals change. Among them, LOSS_N_SEL being 0 indicates that the main clock is offline, and being 1 indicates that the main clock is normal; FORCE_SEL being 0 indicates no processing and no switching, and being 1 indicates forced switching. This is an external control signal used to directly control the clock source switching operation of the clock switching circuit. When FORCE_SEL is set to 1, it forces the circuit to switch from the current main clock, WORK_CLK, to the backup clock BAK_CLK, even if the main clock is not offline. When FORCE_SEL is set to 0, the circuit decides whether to switch back to the main clock based on whether the main clock is offline and the internal logic.

[0061] The inverted signals of the synchronized FORCE_SEL (i.e., the above-mentioned second synchronization signal) and LOSS_N_SEL (i.e., the above-mentioned first synchronization signal) (i.e., not LOSS_N_SEL, which is also the above-mentioned inverted detection signal) are subjected to an "OR" logic operation to generate the first enable signal rev_en_icg signal. The function of the first enable signal rev_en_icg is to control the ICG unit (i.e., the above-mentioned clock gating unit) and the subsequent reset signal generation.

[0062] In the embodiment of the present application, by cascading the structure in the present application to the common clock switching circuit with a switching backpressure structure, the disadvantage that the original structure cannot switch after clock loss is effectively solved, and the advantage of glitch-free switching is inherited, which is applicable to clock supply scenarios with reliability and security requirements.

[0063] Optionally, the above-mentioned clock selection signal generation circuit includes: a second reset register, a third reset register connected to the second reset register, and a third inverter connected to the third reset register, where

[0064] The second reset register is used to receive the first enable signal, the backup clock signal, and the second reset signal corresponding to the backup clock signal, and determine a first output signal according to the first enable signal, the backup clock signal, and the second reset signal, and output the first output signal to the third reset register;

[0065] The third reset register is used to receive the first output signal, the backup clock signal, and the second reset signal corresponding to the backup clock signal, and determine a second output signal according to the first output signal, the backup clock signal, and the second reset signal, and output the second output signal to the third inverter;

[0066] The third inverter is configured to invert the second output signal to generate the clock selection signal.

[0067] As Figure 4 shown, one path of the first enable signal directly serves as the D-terminal input of the second reset register and the third reset register. The Q-terminal output of the third reset register (i.e., the above-mentioned second output signal) serves as the input of the rising-edge detection circuit in the reset and release signal generation circuit, which is used to detect the rising edge of the second output signal and invert the second output signal to generate the clock selection signal clkswitch_sel, where clkswitch_sel is used to control which clock signal is selected as the output signal. Usually, it is a binary signal. For example, 0 indicates the selection of BAK_CLK, and 1 indicates the selection of WORK_CLK.

[0068] Optionally, the above-mentioned reset and release signal generation circuit includes: a rising-edge detection circuit, a fourth inverter connected to the rising-edge detection circuit, and a cascaded reset synchronization unit, where

[0069] the rising-edge detection circuit is configured to receive the second output signal, perform a target operation on the second output signal to obtain a third output signal, and input the third output signal to the fourth inverter;

[0070] the fourth inverter is configured to invert the third output signal to obtain an inverted fourth output signal, and input the fourth output signal to the cascaded reset synchronization unit;

[0071] the cascaded reset synchronization unit is configured to synchronize the fourth output signal according to the backup clock to generate the reset and release signal.

[0072] As Figure 4 shown, the above-mentioned second output signal is also input to the rising-edge detection circuit (i.e., Figure 4 the pos_detect module in), and the role of the pos_detect module is to detect the rising edge of the second output signal. When a rising edge is detected (i.e., after WORK_CLK is switched to BAK_CLK and then returns to normal), the output of pos_detect is inverted and latched by the fourth reset register to generate a pulse signal (i.e., the above-mentioned fourth output signal).

[0073] The pulse signal is synchronized and its duration is controlled through the reset synchronizer (sync_rstn1, sync_rstn2, and sync_rstn3, i.e., the above-mentioned cascaded reset synchronizing unit), and finally a reset and release signal (i.e., the clkswitch_rstn signal) is generated. The clkswitch_rstn signal ensures that after the clkswitch_sel signal changes, the reset operation of the clock switching circuit occurs at the correct time point, avoiding glitches.

[0074] The reset and release signal is the signal that controls the reset of the clock switching circuit. When clkswitch_rstn is at a low level, it indicates that the reset signal is activated, and the clock switching circuit is placed in a known initial state, usually turning off the currently output clock signal and preparing for switching. When clkswitch_rstn is at a high level, it indicates that the reset signal is released, and the clock switching circuit can operate normally. When implementing glitch-free clock switching, it should be ensured that the reset pulse width of the reset and release signal is long enough to allow the stable switching of the clkswitch_sel signal, and at the same time, it should not be too long to avoid affecting the timely enabling of the clock signal.

[0075] It should be noted that the reset synchronizing unit is used to manage the reset signal of the circuit, ensuring that the triggering of the reset signal is asynchronous, but the release of the reset signal is synchronous. The reset signal is usually used to restore the circuit to a known initial state, which is crucial for the initialization and fault recovery of the circuit. However, glitches in the asynchronous reset signal may cause the instability of the circuit state. The reset synchronizing unit synchronously releases the reset signal using the next rising edge (or falling edge, depending on the design) of the clock signal after the reset signal is triggered, which can filter out glitches and ensure that the circuit can correctly enter the synchronous operation state after reset. This mechanism of "asynchronous triggering, synchronous release" ensures that the circuit will not enter an unknown state due to glitches or timing issues during the reset process, and at the same time, it also speeds up the reset response speed.

[0076] Optionally, the rising edge detection circuit is further configured to latch the second output signal to obtain a second input signal; invert the second input signal to obtain a third input signal; and perform a logical AND operation on the third input signal and the second output signal to obtain the third output signal.

[0077] The above-mentioned rising edge detection circuit (i.e., as Figure 4The pos_detect module) is used to detect the positive edge of the input signal, that is, the transition of the signal from low level to high level. This module is particularly useful in sequential circuits because it can help the circuit identify the occurrence of specific events. For example, in the embodiments of this application, it is used to detect the effective change of the clock switching signal, and then trigger the corresponding clock switching action. In Figure 4 The pos_detect module shown in Figure 4 receives the input signal r0 and obtains the output r8 after registering the signal for 8 beats. Here, the "registering" operation means sampling the input signal using the clock signal and storing the signal state through the register. After inverting r8 and performing an "AND" operation with r0, it can be detected whether a positive edge has occurred on the r0 signal within 8 clock cycles. If r0 changes from low level to high level within 8 clock cycles, the result of the "AND" operation between the inverted r8 and r0 will be high level, indicating that a positive edge has been detected.

[0078] Through the above operations, the stability and accuracy of the clock switching signal can be ensured, avoiding misoperations caused by glitches or short-term signal instability. By using a synchronous reset signal (clkswitch_rstn), it is possible to further ensure that there are no glitches and the correctness of the clock switching logic during the clock dropout identification and switching process.

[0079] Optionally, the above main clock signal output circuit includes: a dedicated clock gating unit, and a fifth inverter connected to the dedicated clock gating unit, where

[0080] The fifth inverter is used to invert the first enable signal to obtain a second enable signal and input the second enable signal to the enable terminal of the dedicated clock gating unit;

[0081] The dedicated clock gating unit is used to determine whether to output the main clock signal according to the second enable signal.

[0082] It should be noted that the inverted version (i.e., the second enable signal) of the above first enable signal rev_en_icg is used for the enable terminal of the dedicated clock gating unit ICG. When rev_en_icg is 1, its inverted version is 0, and at this time the ICG is closed, preventing WORK_CLK from passing through; when rev_en_icg is 0, its inverted version is 1, and at this time the ICG is open, allowing WORK_CLK to pass through.

[0083] Through the above circuit, it is possible to ensure that the main clock is turned off in a timely manner when needed, avoiding glitches or instability during the clock switching process, and at the same time reopening the main clock at the appropriate time to achieve seamless switching from the backup clock BAK_CLK to the main clock WORK_CLK.

[0084] In an exemplary embodiment, the clock switching circuit is further configured to determine to switch the main clock to the backup clock according to the clock selection signal and the reset and release signal when the dedicated clock gating unit does not output the main clock signal; and determine not to allow switching the main clock to the backup clock according to the clock selection signal and the reset and release signal when the dedicated clock gating unit outputs the main clock signal.

[0085] Through the intelligent switching mechanism in the embodiments of the present application, it can be ensured that when the main clock fails, the system can automatically and seamlessly switch to the backup clock, and when the main clock is working properly, the system can stably use the main clock, avoiding unnecessary switching operations and improving the efficiency and stability of the system.

[0086] For example, in the initial state: clkswitch_rstn is at a high level, clkswitch_sel is 1, and the output clock is WORK_CLK at this time; pull down the clkswitch_rstn signal to activate the reset, and the output clock is temporarily turned off at this time. Under the protection of the activated reset signal, change clkswitch_sel from 1 to 0, indicating that BAK_CLK is to be selected as the output clock. After confirming that the clkswitch_sel signal has stabilized at 0, pull up the clkswitch_rstn signal to release the reset, and at this time clkswitch will output BAK_CLK as the clock signal.

[0087] Through the above process, it is ensured that no uncertain intermediate state occurs during the clock signal switching, thus realizing a glitch-free clock switching.

[0088] Obviously, the above-described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. To better understand the above circuit, the following will describe the above process in conjunction with embodiments, but it is not used to limit the technical solutions of the embodiments of the present invention. Specifically:

[0089] In an alternative embodiment, Figure 5 is a circuit diagram of the main and backup clock switching circuit according to an alternative embodiment of the present application, specifically including:

[0090] a clock disconnection identification circuit and a clock switching device; wherein, the clock switching device includes: a reset and release generation circuit for clock selection and clock switching and a clock switching circuit clkswitch;

[0091] Among them, as Figure 6As shown, when the clock switching device is initialized, WORK_CLK is normal, BAK_CLK is normal, BAK_RSTN (i.e., the reset signal corresponding to the above backup clock signal) has been reset and released, LOSS_N_SEL is 1, and FORCE_SEL is 0.

[0092] Manually changing FORCE_SEL from 0 to 1 can switch the out of clkswitch from WORK_CLK to BAK_CLK; manually changing FORCE_SEL from 1 to 0 can switch the out of clkswitch from BAK_CLK to WORK_CLK. When manually changing FORCE_SEL from 0 to 1, Figure 4 the ICG in it will be turned off, and clkswitch_work_clk_g will stop outputting WORK_CLK; Figure 6 the output clkswitch_sel of it will become 0, clkswitch_rstn will output a negative pulse, and will not be reset and released until after the change of clkswitch_sel; Figure 5 the output clk_o in it is the switched clock, which will change from when WORK_CLK is normal to no clock for a period of time and then switch to BAK_CLK.

[0093] When WORK_CLK is lost, LOSS_N_SEL output by the clock dropout identification circuit will change from 1 to 0, Figure 4 the output clkswitch_sel of it will become 0, clkswitch_rstn will output a negative pulse, and will not be reset and released until after the change of clkswitch_sel; Figure 6 the output clk_o in it is the switched clock, which will change from when WORK_CLK is normal to no clock for a period of time and then switch to BAK_CLK.

[0094] When WORK_CLK changes from lost to normal, LOSS_N_SEL output by the clock dropout identification circuit will change from 0 to 1, Figure 4 the output clkswitch_sel of it will become 1, and clkswitch_rstn will not change and remains reset and released; Figure 4 the ICG in it will be turned on, and clkswitch_work_clk_g will output normal WORK_CLK; Figure 7 the output clk_o in it is the switched clock, which will change from when BAK_CLK is normal to no clock for a period of time and then switch to WORK_CLK.

[0095] Among them, as Figure 4As shown, the reset and release generation circuit for clock selection and clock switching and the clock switching circuit clkswitch have inputs WORK_CLK, BAK_CLK, BAK_RSTN, LOSS_N_SEL, FORCE_SEL, and outputs clkswithch_sel, clkswitch_rstn, clkswitch_work_clk_g. LOSS_N_SEL being 0 indicates clock loss, and being 1 indicates normal clock; FORCE_SEL being 0 indicates no processing and no switching, and being 1 indicates forced switching.

[0096] Figure 4 In the reset and release generation circuit for clock selection and clock switching as shown, after LOSS_N_SEL is inverted, it is synchronized by the data synchronization unit sync_data1 (sync_data is a 2-stage or 3-stage DFF synchronization structure, and the trailing number identifier is for differentiating multiple ones); FORCE_SEL is synchronized by the data synchronization unit sync_data2; the outputs of sync_data1 and sync_data2 are subjected to an "OR" logic, and the output of the OR is called the rev_en_icg signal; the rev_en_icg signal is connected to two inputs; one of the inputs connected by rev_en_icg is also the input of an inverter, and its inverted output is connected to the en end of the ICG unit; at the same time, the other input connected by rev_en_icg is also connected to the D end of the second reset register, and the Q end of the third reset register is also connected to the D end of the third reset register; the output of the third reset register is connected to two inputs, one input is the input of the pos detect module, and the other is the input of an inverter, and its inverted output is used as the clkswitch_sel output.

[0097] In the pos_detect module, r0, which is the input, is clocked by a register for 8 beats to obtain the output r8. The output of the "AND" operation between the inverted r8 and r0 is used as the output of pos_detect; after this output is inverted, it is clocked by the fourth reset register; the output of the fourth reset register is connected to the rstn end of sync_rstn1 (sync_rstn is a reset synchronizer that realizes the function of asynchronous reset and synchronous release, where the number identifier is for differentiating different sync_rstn units). The output of sync_rstn1 is cascaded with sync_rstn2, the output of sync_rstn2 is cascaded with sync_rstn3, and the output of sync_rstn2 is used as the clkswitch_rstn output.

[0098] WORK_CLK is connected to the CLK terminal of the ICG unit. The en terminal of the ICG unit is connected to the inverted output of rev_icg_en. The output of the ICG unit serves as the output clkswitch_work_clk_g.

[0099] In Figure 4 the registers, the CK clock terminals of sync_data and sync_rstn are both connected to BAK_CLK, and the reset rstn is both connected to BAK_RSTN.

[0100] Figure 7 is the schematic diagram of the clock switching output timing when the main clock drops out in the embodiments of the present application; when the main clock does not drop out and FORCE_SEL changes from 0 to 1, the change timing of FORCE_SEL is the same as that of Figure 7 the change timing of LOSS_N_SEL in Figure 7 the change behaviors of clkswitch_sel, clkswitch_rstn, and clk_o in

[0101] In the embodiments of the present application, clock dropout detection and identification can be completed without introducing a new clock, and the identification structure is simple and occupies few resources; for the clock switching device, without using a set register, only a reset register can be used to complete the clock switching after the clock drops out; the circuit structure is simple, without introducing new types of physical implementation units, and has low requirements for physical implementation; the clock switching device can filter out the glitches on the switching signal; after the clock drops out, it can be automatically switched to the backup clock; after the clock is restored, it is automatically switched to WORK_CLK; and there can be glitch-free switching during clock switching.

[0102] Obviously, those skilled in the art should understand that the circuits of the present application described above can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. They can be implemented by program codes executable by the computing device. Thus, they can be stored in a storage device and executed by the computing device. And in some cases, the steps shown or described can be executed in a different order from here, or they can be separately made into individual integrated circuit modules, or multiple modules or steps among them can be made into a single integrated circuit module for implementation. In this way, the present application is not limited to any specific combination of hardware and software.

[0103] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application shall be included within the protection scope of the present application.

Claims

1. A master-slave clock switching circuit, characterized in that: It includes: a clock offline identification circuit, a clock selection and reset control generation circuit connected to the clock offline identification circuit, and a clock switching circuit connected to the clock selection and reset control generation circuit, wherein: The clock offline identification circuit is used to determine whether the master clock is offline according to the master clock signal of the master clock, and output a detection signal; The clock selection and reset control generation circuit is used to generate a clock selection signal and a reset and release signal of a clock switching circuit according to the detection signal, and input the clock selection signal and the reset and release signal to the clock switching circuit; The clock switching circuit is used to determine whether to switch the main clock to the backup clock according to the clock selection signal and the reset and release signal.

2. The circuit according to claim 1, characterized in that The clock offline identification circuit comprises: A delay circuit, a multiplexer connected to the delay circuit, a first logic gate connected to the multiplexer, a first reset register connected to the first logic gate, and a first inverter connected to the first reset register, wherein: The delay circuit is used to delay the master clock signal to obtain a plurality of delayed master clock signals, and input the plurality of delayed master clock signals into the multiplexer; The multiplexer is used to determine a target master clock signal from among the multiple delayed master clock signals, and input the target master clock signal into the first logic gate; The first logic gate is used to perform a logic OR operation on the target master clock signal and the master clock signal to obtain a first reset signal, and input the first reset signal to the first reset register; The first inverter is used to invert the main clock signal to obtain an inverted main clock signal, and input the inverted main clock signal into the first reset register; The first reset register is used to determine whether the main clock is offline according to the received high-level signal, the first reset signal and the inverted main clock signal, and output the detection signal.

3. The circuit according to claim 2, characterized in that The delay circuit comprises: A plurality of groups of delay units, wherein the delay unit is used to delay the master clock signal to obtain the delayed master clock signal.

4. The circuit according to claim 1, characterized in that The clock selection and reset control generation circuit comprises: An enable signal generating circuit, a clock selection signal generating circuit, a reset and release signal generating circuit and a main clock signal output circuit connected to the enable signal generating circuit, wherein: The enable signal generating circuit is used to generate a first enable signal according to the detection signal; The clock selection signal generating circuit is used to generate the clock selection signal according to the first enable signal; The reset and release signal generating circuit is used to generate the reset and release signals according to the first enable signal; The main clock signal output circuit is used to determine whether to output the main clock signal according to the first enable signal.

5. The circuit according to claim 4, characterized in that The enable signal generating circuit comprises: a second inverter, a first data synchronization unit connected to the second inverter, a second logic gate connected to the first data synchronization unit, and a second data synchronization unit connected to the second logic gate, wherein: The second inverter is used to perform an inversion operation on the detection signal to obtain an inverted detection signal, and input the inverted detection signal to the first data synchronization unit; The first data synchronization unit is used to perform data synchronization on the inverted detection signal according to the backup clock to obtain a first synchronization signal, and input the first synchronization signal to the second logic gate; The second data synchronization unit is used to perform data synchronization on the active switching signal according to the backup clock to obtain a second synchronization signal, and input the second synchronization signal to the second logic gate, wherein the active switching signal is used to indicate the indication information sent by the target object; The second logic gate is used to perform a logic OR operation on the first synchronization signal and the second synchronization signal to obtain the first enable signal.

6. The circuit according to claim 4, characterized in that The clock selection signal generating circuit comprises: a second reset register, a third reset register connected to the second reset register, and a third inverter connected to the third reset register, wherein: The second reset register is used to receive the first enable signal, the backup clock signal and a second reset signal corresponding to the backup clock signal, and determine a first output signal according to the first enable signal, the backup clock signal and the second reset signal, and output the first output signal to the third reset register; The third reset register is used to receive the first output signal, the backup clock signal and a second reset signal corresponding to the backup clock signal, determine a second output signal according to the first output signal, the backup clock signal and the second reset signal, and output the second output signal to the third inverter; The third inverter is used to perform an inversion operation on the second output signal to generate the clock selection signal.

7. The circuit according to claim 6, characterized in that The reset and release signal generating circuit comprises: A rising edge detection circuit, a fourth inverter connected to the rising edge detection circuit, and a cascade reset synchronization unit connected to the fourth inverter, wherein: The rising edge detection circuit is used to receive the second output signal, perform a target operation on the second output signal to obtain a third output signal, and input the third output signal to the fourth inverter; The fourth inverter is used to perform an inversion operation on the third output signal to obtain an inverted fourth output signal, and input the fourth output signal to the cascade reset synchronization unit; The cascade reset synchronization unit is used to synchronize the fourth output signal according to the backup clock to generate the reset and release signal.

8. The circuit according to claim 7, characterized in that The rising edge detection circuit is further used to beat the second output signal to obtain a second input signal; Performing an inversion operation on the second input signal to obtain a third input signal; A logic AND operation is performed on the third input signal and the second output signal to obtain the third output signal.

9. The circuit according to claim 4, characterized in that The main clock signal output circuit comprises: A dedicated clock gating unit, a fifth inverter connected to the dedicated clock gating unit, wherein: The fifth inverter is used to invert the first enable signal to obtain a second enable signal, and input the second enable signal to the enable terminal of the dedicated clock gating unit; The dedicated clock gating unit is used to determine whether to output the main clock signal according to the second enable signal.

10. The circuit according to claim 9, characterized in that The clock switching circuit is further used to determine, according to the clock selection signal and the reset and release signal, whether to switch the main clock to the backup clock when the dedicated clock gating unit does not output the main clock signal; In the case where the dedicated clock gating unit outputs the main clock signal, it is determined according to the clock selection signal and the reset and release signal that the main clock is not allowed to be switched to the backup clock.

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