DSP (Digital Signal Processor) data security system and method for inertial navigation equipment based on NVRAM (Non-Volatile Random Access Memory)

Abstract

The invention relates to an NVRAM (Non-Volatile Random Access Memory)-based DSP (Digital Signal Processor) data security system and method for inertial navigation equipment, NVRAM extension is realized by utilizing an SIP (Session Initiation Protocol) interface of a DSP, and an extended running RAM and a data storage ROM (Read Only Memory) of the DSP are combined based on the high-speed access characteristic of the RAM and the nonvolatile characteristic of the ROM of the NVRAM. And continuous operation and data integrity of inertial navigation equipment can be maintained. And the equipment can immediately and continuously provide accurate navigation service after the power supply is recovered without a tedious re-alignment or calibration process. The use of the NVRAM chip not only ensures the safe storage of key data in the DSP, but also greatly improves the recovery speed and reliability of the inertial navigation equipment. According to the method, the energy consumption ratio of the inertial navigation equipment can be remarkably improved on the premise of not increasing additional write-in of a processor and hardware redundancy, meanwhile, the complexity of an external expansion circuit of a DSP (Digital Signal Processor) can be effectively reduced, and the reliability of the inertial navigation equipment is effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of inertial navigation, and in particular, relates to a DSP data preservation system and method for inertial navigation devices based on NVRAM. Background Art

[0002] The traditional data preservation solutions for the digital systems of inertial navigation devices can be divided into two types: data backup and dual-machine design.

[0003] The data backup method regularly backs up the key data in the system, which can be stored locally or in the cloud, ensuring that the data can be restored even if the hardware device fails. In this solution, the DSP processor needs to perform additional data writing operations, which will cause great pressure on the processor and system bandwidth when the amount of data to be preserved is large.

[0004] The dual-machine design solution adopts a hardware redundancy mechanism in the system design, such as using dual-machine hot standby or distributed clusters. Once the main system fails, the standby system can immediately take over and continue to provide services, while ensuring that the data is not lost, and various strategies such as full backup, incremental backup, or differential backup can be selected. The hardware redundancy in this solution brings greater power consumption and a more complex system composition while improving the reliability. Summary of the Invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and propose a DSP data preservation system and method for inertial navigation devices based on NVRAM, which can significantly improve the energy consumption ratio of inertial navigation devices without increasing the additional writing of the processor and hardware redundancy, effectively reduce the complexity of the DSP external expansion circuit, and effectively improve the reliability of inertial navigation devices.

[0006] The present invention solves its technical problems by adopting the following technical solutions:

[0007] A DSP data preservation system for inertial navigation devices based on NVRAM includes an NVRAM chip and its peripheral circuit, a DSP, and a FLASH chip and its peripheral circuit. The NVRAM chip and its peripheral circuit are used to merge and integrate the external expansion operating RAM and data storage ROM of the DSP into one NVRAM chip, reducing the complexity of the DSP external expansion circuit and the system size. The FLASH chip and its peripheral circuit are used as the program memory ROM of the DSP.

[0008] Moreover, the NVRAM chip uses RC5NS128K8-PSO. The peripheral circuit of the NVRAM chip includes resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, capacitor C1 and capacitor C2. Among them, the WP pin of the NVRAM chip is connected to the 3.3V power supply through resistor R2, the HOLD pin of the NVRAM chip is connected to the 3.3V power supply through resistor R1, the VSS pin of the NVRAM chip is grounded, the CS pin of the NVRAM chip is connected to the SPI0_CS_N pin of the DSP through resistor R6, the CS pin of the NVRAM chip is connected to the 3.3V power supply through resistor R7, the SCK pin of the NVRAM chip is connected to the SPI0_CSK pin of the DSP through resistor R5, the SI pin of the NVRAM chip is connected to the SPI0_SIMO pin of the DSP through resistor R4, the SO pin of the NVRAM chip is connected to the SPI0_SOMI pin of the DSP through resistor R3, the VCAP pin of the NVRAM chip is grounded through capacitor C2, the VCC pin of the NVRAM chip is connected to the 3.3V power supply, and the VCC pin of the NVRAM chip is grounded through capacitor C1.

[0009] Moreover, the FLASH chip uses SM25QH32M. The peripheral circuit of the FLASH chip includes resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, resistor R14 and capacitor C3. Among them, the CS pin of the FLASH chip is connected to the interface power supply DVDD3318 through resistor R9, the CS pin of the FLASH chip is connected to the SPI1_CS_N pin of the DSP chip through resistor R11, the Q pin of the FLASH chip is connected to the SPI1_SOMI pin of the DSP chip through resistor R12, the VSS of the FLASH chip is grounded, the D pin of the FLASH chip is connected to the SPI1_SIMO pin of the DSP chip through resistor R14, the C pin of the FLASH chip is connected to the SPI1_SCK pin of the DSP chip through resistor R13, the HOLD pin of the FLASH chip is connected to the interface power supply DVDD3318 through resistor R10, the VCC pin of the FLASH chip is connected to the interface power supply DVDD3318, and the VCC pin of the FLASH chip is grounded through capacitor C3.

[0010] A data preservation method for a DSP data preservation system for an inertial navigation device based on NVRAM includes the following steps:

[0011] Step 1: When the device is powered on, the DSP loads the DSP program stored in the FLASH. First, it reads the device status flag from the NVRAM chip to determine whether there is a sudden power failure. If so, go to Step 2; otherwise, go to Step 4.

[0012] Step 2: Read the operating state of the DSP before power-off stored in the NVRAM. The DSP restores to the working state before power-off according to the operating state information of the DSP program read from the NVRAM.

[0013] Step 3: Read the latest angular velocity information and acceleration information from the gyroscopes and accelerometers in the X, Y, and Z directions, and combine them with the historical position information, azimuth information, and velocity information read from the NVRAM chip. Perform fusion and processing operations through the navigation algorithm to carry out precise navigation calculations and end.

[0014] Step 4: Manually input the current position information, combine the latest angular velocity information and acceleration information read from the gyroscopes and accelerometers in the X, Y, and Z directions, re-perform the device alignment operation, complete the power-off reloading of the inertial navigation device, and end.

[0015] The advantages and positive effects of the present invention are:

[0016] The present invention uses the SIP interface of the DSP to realize NVRAM expansion. Based on the high-speed access characteristics of the RAM and the non-volatile characteristics of the ROM of the NVRAM, the extended operating RAM and data storage ROM of the DSP are combined. Even in the case of a sudden power interruption, the present invention can maintain the continuous operation of the inertial navigation device and the integrity of the data. Without the need for a cumbersome re-alignment or calibration process, the device can immediately continue to provide accurate navigation services after the power is restored. The use of the NVRAM chip not only ensures the safe storage of key data in the DSP but also significantly improves the recovery speed and reliability of the inertial navigation device. Without adding additional writes by the processor and hardware redundancy, the present invention can significantly improve the energy consumption ratio of the inertial navigation device, effectively reduce the complexity of the external expansion circuit of the DSP, and effectively improve the reliability of the inertial navigation device. Description of the Drawings

[0017] Figure 1 It is the system structure diagram of the present invention;

[0018] Figure 2 It is the NVRAM chip and its peripheral circuit diagram of the present invention

[0019] Figure 3 It is the FLASH chip and its peripheral circuit diagram of the present invention

[0020] Figure 4 It is the data preservation flow chart of the present invention. Detailed Embodiments

[0021] The following further describes the present invention in conjunction with the drawings.

[0022] A DSP data preservation system for an inertial navigation device based on NVRAM, as Figure 1 shown, is composed of digital circuits, including an NVRAM chip and its peripheral circuits, a DSP, and a FLASH chip and its peripheral circuits. The NVRAM chip and its peripheral circuits are used to combine the externally extended operating RAM and data storage ROM of the DSP into one NVRAM chip, reducing the complexity of the DSP external extension circuit and decreasing the system size. The FLASH chip and its peripheral circuits are used as the program memory ROM of the DSP.

[0023] The FLASH chip serves as the program memory ROM of the DSP, and the NVRAM chip serves as the extended operating RAM and data storage ROM of the DSP. The program code of the DSP is stored in the FLASH chip. In the NVRAM chip, a part is used as the data storage ROM to store navigation information in real time, including position information, azimuth information, speed information, etc. Another part is used as the data cache RAM to store the running state of the DSP program in real time, including the execution point of the program, the state of variables, etc. When the power is cut off, the NVRAM chip can save all the stored information to the internal FLASH of the chip.

[0024] The NVRAM chip uses the RC5NS128K8-PSO of Hunan Rongchuang Microelectronics Co., Ltd. The NVRAM chip combines a 1-Mbit SRAM with a 1-Mbit flash non-volatile element in each memory cell with a serial SPI interface. The memory structure is 128K×8bit. It can realize the self-start of data transfer from SRAM to non-volatile elements when the power is off. When powered on, the data is restored from the non-volatile memory to the SRAM. The pin definitions of the RC5NS128K8-PSO chip are shown in Table 1.

[0025] Table 1 Pin Definitions of RC5NS128K8-PSO Chip

[0026]

[0027]

[0028] The connection concept and corresponding functions between the NVRAM chip and the DSP are as follows: The pin DSP_SPI0_SOMI of the DSP is connected to the output pin 13 of the RC5NS128K8-PSO for data reading. The pin SP_SPI0_SIMO of the DSP is connected to the input pin 12 of the RC5NS128K8-PSO for data writing. The pin SP_SPI0_SCK of the DSP is connected to the pin 11 of the RC5NS128K8-PSO for serial clock input. The pin SP_SPI0_CS_N of the DSP is connected to the pin 10 of the RC5NS128K8-PSO for chip selection. The pins 5 and 6 of the RC5NS128K8-PSO are pulled up to 3.3V through a 10K resistor to achieve non-write protection and non-suspend serial bus operation. The pin 14 of the RC5NS128K8-PSO is connected to a 220μF tantalum capacitor, which is an automatic storage capacitor to supply power to the NVRAM during the breakpoint period to store data from the SRAM to the non-volatile component.

[0029] As Figure 2 shown, the peripheral circuit of the NVRAM chip includes resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, capacitor C1, and capacitor C2. Among them, the WP pin of the NVRAM chip is connected to the 3.3V power supply through resistor R2, the HOLD pin of the NVRAM chip is connected to the 3.3V power supply through resistor R1, the VSS pin of the NVRAM chip is grounded, the CS pin of the NVRAM chip is connected to the SPI0_CS_N pin of the DSP through resistor R6, the CS pin of the NVRAM chip is connected to the 3.3V power supply through resistor R7, the SCK pin of the NVRAM chip is connected to the SPI0_CSK pin of the DSP through resistor R5, the SI pin of the NVRAM chip is connected to the SPI0_SIMO pin of the DSP through resistor R4, the SO pin of the NVRAM chip is connected to the SPI0_SOMI pin of the DSP through resistor R3, the VCAP pin of the NVRAM chip is grounded through capacitor C2, the VCC pin of the NVRAM chip is connected to the 3.3V power supply, and the VCC pin of the NVRAM chip is grounded through capacitor C1.

[0030] The FLASH chip uses the SM25QH32M of Shenzhen Guowei Electronics Co., Ltd. The function of the FLASH chip is to serve as the program storage ROM of the DSP. After the DSP is powered on, according to the BOOT setting, the program code in the FLASH chip is loaded into the program RAM of the DSP to make it run normally. The pin definitions of the SM25QH32M chip are shown in Table 2.

[0031] Table 2 Pin Definitions of the SM25QH32M Chip

[0032]

[0033]

[0034] The connection idea and corresponding functions between the FLASH chip and the DSP are as follows: The pin DSP_SPI1_SOMI of the DSP is connected to the output 2 pin of the SM25QH32M for data reading. The pin SP_SPI1_SIMO of the DSP is connected to the input 5 pin of the SM25QH32M for data writing. The pin SP_SPI1_SCK of the DSP is connected to the 6 pin of the SM25QH32M for serial clock input. The pin SP_SPI1_CS_N of the DSP is connected to the 1 pin of the SM25QH32M for chip selection. The 3rd and 7th pins of the RC5NS128K8-PSO are pulled up to 3.3V through a 10K resistor to achieve non-write protection and non-suspended serial bus operation.

[0035] As Figure 3 shown, the peripheral circuit of the FLASH chip includes resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, resistor R14 and capacitor C3. Among them, the CS pin of the FLASH chip is connected to the interface power supply DVDD3318 through resistor R9, the CS pin of the FLASH chip is connected to the SPI1_CS_N pin of the DSP chip through resistor R11, the Q pin of the FLASH chip is connected to the SPI1_SOMI pin of the DSP chip through resistor R12, the VSS of the FLASH chip is grounded, the D pin of the FLASH chip is connected to the SPI1_SIMO pin of the DSP chip through resistor R14, the C pin of the FLASH chip is connected to the SPI1_SCK pin of the DSP chip through resistor R13, the HOLD pin of the FLASH chip is connected to the interface power supply DVDD3318 through resistor R10, the VCC pin of the FLASH chip is connected to the interface power supply DVDD3318, and the VCC pin of the FLASH chip is grounded through capacitor C3.

[0036] A data preservation method for a DSP data preservation system for an inertial navigation device based on NVRAM, as Figure 2 shown, includes the following steps:

[0037] Step 1: When the device is powered on, the DSP loads the DSP program stored in the FLASH. First, read the device status flag from the NVRAM chip and determine whether there is a sudden power-off. If so, proceed to Step 2; otherwise, proceed to Step 4.

[0038] Step 2: Read the running state of the DSP before power-off stored in the NVRAM. The DSP restores to the working state of the DSP before power-off according to the running state information of the DSP program read from the NVRAM.

[0039] Step 3: Read the latest angular velocity information and acceleration information from the gyroscopes and accelerometers in the X, Y, and Z directions, and combine them with the historical position information, azimuth information, and velocity information read from the NVRAM chip. Perform fusion and processing operations through the navigation algorithm to conduct precise navigation calculations and end;

[0040] Step 4: Manually input the current position information, combine it with the latest angular velocity information and acceleration information read from the gyroscopes and accelerometers in the X, Y, and Z directions, re-perform the device alignment operation, complete the power-off and reloading of the inertial navigation device, and end.

[0041] According to the above DSP data preservation system for inertial navigation devices based on NVRAM, experiments are carried out to illustrate the effects of the present invention.

[0042] To verify the correctness and reliability of the DSP system data preservation method for inertial navigation devices based on NVRAM, board-level verification was carried out in the initial stage of the present invention. The data preservation test under power interruption was carried out using a circuit board. The circuit board was connected to a programmable power supply, and the programmable power supply was set to interrupt the power supply once every 1 minute. After each power-on, it was observed on the upper computer whether the data sent by the DSP was continuous and uninterrupted before and after the power interruption to verify whether the data preservation was successful.

[0043] After the circuit board passed the assessment and met all indicators, it has been applied to multiple types of inertial navigation devices, and its performance and reliability have been strictly examined and verified.

[0044] The advantage of this design is that even in the case of a sudden power interruption, it can maintain the continuous operation of the inertial navigation device and the integrity of the data. There is no need to perform a cumbersome realignment or calibration process, and the device can immediately continue to provide accurate navigation services after the power is restored. The use of the NVRAM chip not only ensures the secure storage of key data in the DSP, but also greatly improves the recovery speed and reliability of the inertial navigation device.

[0045] The present invention utilizes the SIP interface of the DSP to achieve NVRAM expansion. Based on the high-speed access characteristics of RAM and the non-volatile characteristics of ROM possessed by NVRAM, the expanded operating RAM and data storage ROM of the DSP are combined. Even in the case of a sudden power interruption, the present invention can maintain the continuous operation of the inertial navigation device and the integrity of the data. Without the need for a cumbersome realignment or calibration process, the device can immediately continue to provide accurate navigation services after the power is restored. The use of the NVRAM chip not only ensures the secure storage of key data in the DSP, but also significantly improves the recovery speed and reliability of the inertial navigation device. Without increasing the additional writing of the processor and hardware redundancy, the present invention can significantly improve the energy consumption ratio of the inertial navigation device, effectively reduce the complexity of the external expansion circuit of the DSP, and effectively improve the reliability of the inertial navigation device.

[0046] It should be emphasized that the embodiments described in the present invention are illustrative rather than restrictive. Therefore, the present invention includes, but is not limited to, the embodiments described in the specific implementation manners. Any other implementation manners derived by those skilled in the art based on the technical solutions of the present invention also belong to the scope of protection of the present invention.

Claims

1. A DSP data preservation system for inertial navigation equipment based on NVRAM, characterized in that: It includes an NVRAM chip and its peripheral circuits, a DSP and a FLASH chip and its peripheral circuits. The NVRAM chip and its peripheral circuits are used to merge the external extended operation RAM and data storage ROM of the DSP into one NVRAM chip, thereby reducing the complexity of the DSP external extension circuit and the system size. The FLASH chip and its peripheral circuits are used as the program memory ROM of the DSP.

2. The NVRAM-based DSP data preservation system for inertial navigation equipment according to claim 1, characterized in that: The NVRAM chip adopts RC5NS128K8-PSO, and the peripheral circuit of the NVRAM chip includes resistors R1, R2, R3, R4, R5, R6, R7, capacitors C1 and C2, wherein the WP pin of the NVRAM chip is connected to a 3.3V power supply through resistor R2, the HOLD pin of the NVRAM chip is connected to a 3.3V power supply through resistor R1, the VSS pin of the NVRAM chip is grounded, the CS pin of the NVRAM chip is connected to the SPI0_CS_N pin of the DSP through resistor R6, and the NVR The CS pin of the AM chip is connected to the 3.3V power supply through resistor R7, the SCK pin of the NVRAM chip is connected to the SPI0_CSK pin of the DSP through resistor R5, the SI pin of the NVRAM chip is connected to the SPI0_SIMO pin of the DSP through resistor R4, the SO pin of the NVRAM chip is connected to the SPI0_SOMI pin of the DSP through resistor R3, the VCAP pin of the NVRAM chip is grounded through capacitor C2, the VCC pin of the NVRAM chip is connected to the 3.3V power supply, and the VCC pin of the NVRAM chip is grounded through capacitor C1.

3. The NVRAM-based DSP data preservation system for inertial navigation equipment according to claim 1, characterized in that: The FLASH chip adopts SM25QH32M, and the peripheral circuit of the FLASH chip includes resistors R8, R9, R10, R11, R12, R13, R14 and capacitor C3, wherein the CS pin of the FLASH chip is connected to the interface power supply DVDD3318 through the resistor R9, the CS pin of the FLASH chip is connected to the SPI1_CS_N pin of the DSP chip through the resistor R11, the Q pin of the FLASH chip is connected to the SPI1_SOMI pin of the DSP chip through the resistor R12, the VSS of the FLASH chip is grounded, the D pin of the FLASH chip is connected to the SPI1_SIMO pin of the DSP chip through the resistor R14, the C pin of the FLASH chip is connected to the SPI1_SCK pin of the DSP chip through the resistor R13, the HOLD pin of the FLASH chip is connected to the interface power supply DVDD3318 through the resistor R10, the VCC pin of the FLASH chip is connected to the interface power supply DVDD3318, and the VCC pin of the FLASH chip is grounded through the capacitor C3.

4. A data preservation method for a DSP data preservation system for an inertial navigation device based on NVRAM according to any one of claims 1 to 3, characterized in that: The following steps are involved: Step 1: When the device is powered on, the DSP loads the DSP program stored in the FLASH, and first reads the device status flag from the NVRAM chip to determine whether the power is suddenly cut off. If so, proceed to step 2, otherwise proceed to step 4; Step 2, read the DSP running state before power failure stored in NVRAM, and restore the DSP to the working state of the DSP before power failure according to the running state information of the DSP program read from NVRAM; Step 3: read the latest angular velocity information and acceleration information from the gyroscope and accelerometer in the X, Y, and Z directions, and combine them with the historical position information, orientation information, and speed information read from the NVRAM chip, and perform fusion and processing operations through the navigation algorithm to perform accurate navigation calculations and end; Step 4: Manually input the current position information, read the latest angular velocity information and acceleration information from the gyroscope and accelerometer in the X, Y, and Z directions, re-align the device, power off and reload the inertial navigation device, and end.

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