A method and device for supporting consistent multi-chip interconnection interruption

Abstract

The present invention discloses a method and device for supporting consistent multi-chip interconnect interrupts. The method includes configuring the number of chips supported, setting the cross-chip parameters of the chips to determine the addresses of each chip and the depth of the routing table; designating a chip responsible for managing consistency as a management chip, configuring a routing table for each chip and connecting all the chips to each other, and designating the number of slow peripheral interrupts that each chip is responsible for managing; when the interrupt controller of a certain chip receives an interrupt, if the interrupt is a cross-chip interrupt, it is dispatched to the corresponding management chip through the on-chip network and high-speed interconnect interface according to the interrupt route configured in the routing table; the management chip calls the interrupt handler for processing and returns an interrupt confirmation. The present invention can support the current multi-chip interrupt consistency maintenance, realize interrupt processing across any number of chips, improve the performance of the processor, and has the advantages of low hardware implementation complexity, small area overhead, and high cost performance.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-chip integration based on a multi-chip system, and in particular to a method and device for supporting consistent multi-chip interconnection interruption. Background Art

[0002] For the past 50 years, the semiconductor industry has consistently advanced at the pace of Moore's Law, with transistor density steadily increasing, gradually reaching the exascale level, posing significant density and cost challenges. As Moore's Law approaches its limits, traditional monolithic semiconductor devices can no longer meet the performance or functionality requirements of certain compute-intensive, workload-heavy applications. Multi-chip systems (MSoCs) are emerging as a solution to surpass Moore's Law and address complex system challenges. They enable faster and more cost-effective system functionality expansion, reduce risk, and achieve higher throughput at lower power consumption, helping to meet the rapidly growing demand for processing power. Simultaneously, MCM (Multi-Chip Module) technology, a next-generation microelectronics packaging and assembly technology developed based on printed circuit boards (PCBs) and surface mount technology (SMT), is designed to meet the evolving needs of modern electronic systems for shorter, smaller, lighter, thinner, faster speeds, higher performance, higher reliability, and lower cost. It is a powerful tool for system integration. With the development of MCMs and the increasing number of integrated chips, traditional interrupt controllers are struggling to meet the interrupt interconnection and processing requirements of MCMs. Summary of the Invention

[0003] The technical problem to be solved by the present invention is as follows: In response to the above-mentioned problems in the prior art, a method and device for supporting consistent multi-chip interconnection interrupts are provided. The present invention has the advantages of being able to expand chips and thus improve processor performance, while having the advantages of low hardware implementation complexity, small area overhead, and high cost performance.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A method for supporting consistent multi-chip interconnect interrupts, comprising:

[0006] S101, configure the number of supported chips through registers, set the chip's cross-chip parameters to determine the address of each chip and the depth of the routing table; designate a chip responsible for consistency management as the management chip, configure routing tables for each chip according to the depth of the routing table configured by the registers, connect all chips to each other, and specify the number of slow peripheral interrupts that each chip is responsible for managing;

[0007] S102, when the interrupt controller of a chip receives an interrupt, it dispatches it to the processor core in the corresponding management chip or directly to the processor core in the chip through the on-chip network and high-speed interconnect interface according to the interrupt route configured in the routing table; the processor core calls the interrupt handler to process it and returns an interrupt confirmation.

[0008] Optionally, the following configurations of the management chip and the remaining chips remain consistent: the bit width of the routing attributes, the total number of slow peripheral interrupt groups, whether high-speed peripheral interrupts are supported, security disable settings, the total number of chips supported, the chip address bit width, the number of routing attribute layers of the chip, and the number of cores supported by each chip.

[0009] Optionally, the routing table configured in step S101 is composed of a set of registers that specify the connection relationship between any number of chips, wherein the configured information includes: a chip register, which is used to describe the address for controlling cross-chip routing during cross-chip transmission, the starting value of the slow peripheral interrupt group managed by the chip, the number of slow peripheral interrupt groups managed by the chip, the status of routing table updates, the connection status of the chip, and other information; a chip default register, which is used to describe the management chip responsible for managing consistency, the routing table update status, and other information; a chip status register, which is used to describe the consistency status of the routing table; configuring the routing table and connecting all chips to each other in step S101 includes:

[0010] S301, configure the chip default register and designate a management chip to be responsible for managing consistency;

[0011] S302, configuring the chip register responsible for managing the consistency chip and specifying the slow peripheral interrupt group managed by the chip;

[0012] S303: Read the chip status register of the chip responsible for managing consistency until the routing table is in a consistent state; read the number of chips supported by the register configuration, and determine the addresses of each chip based on the chip's cross-chip parameters. Traverse and select a chip from the set of chips other than the management chip as the chip to be connected;

[0013] S304, configuring the chip register of the chip to be connected;

[0014] S305, reading the chip default register until the routing table is updated and the chip to be connected is determined to be connected;

[0015] S306, determine whether there are still chips in the chip set other than the management chip that have not been traversed. If there are still chips that have not been traversed, continue to traverse the chip set other than the management chip and select one chip as the chip to be connected, and jump to step S304; otherwise, determine that all chips are connected to each other.

[0016] Optionally, the routing table is stored inside the interrupt controller, and each chip has a copy of the routing table, and the information of the copy of the routing table in each chip must always be consistent. When the slow peripheral interrupt group allocation information or connection status of any chip changes, the synchronization operation of the copy of the routing table is triggered:

[0017] S401, the chip where the slow peripheral interrupt group allocation information and connection status configuration change occurs sends its configuration information to the management chip responsible for consistency management;

[0018] S402, after receiving the request, the management chip responsible for consistency management updates the routing table;

[0019] S403: The management chip responsible for consistency management sends the new routing table information to all connected chips to update the copy of the routing table inside the interrupt controller of each chip.

[0020] Optionally, in step S102, when the interrupt controller of a chip receives an interrupt, it includes determining the type of interrupt. If the interrupt type is a slow peripheral interrupt, a high-speed peripheral interrupt, or a software interrupt type interrupt, the interrupt is determined to be a cross-chip interrupt, and is dispatched to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnection interface according to the interrupt route configured in the routing table; otherwise, if the interrupt type is a private peripheral interrupt, the interrupt is determined to be a non-cross-chip interrupt, and is directly dispatched to the processor core in this chip according to the interrupt route configured in the routing table.

[0021] Optionally, step S102 further includes dispatching the interrupt directly to the processor core in the current chip according to the interrupt route configured in the routing table when the interrupt is a non-cross-chip interrupt, including:

[0022] S501, the interrupt controller in the chip processes the interrupt by sending the interrupt to the processor core that initiates the private peripheral interrupt in the chip;

[0023] S502: The processor core acknowledges the interrupt and returns a response, and the interrupt controller sets its state to active.

[0024] S503: After the processor core completes the processing, the active state of the interrupt is cleared.

[0025] Optionally, the routing table groups multiple slow peripheral interrupts into one group, and step S102 further includes dispatching the interrupt to a corresponding processor core in the management chip through the on-chip network and the high-speed interconnect interface according to the interrupt route configured in the routing table when the interrupt is a slow peripheral interrupt, including:

[0026] S601, obtaining configuration information of the slow peripheral interrupt group of the current chip, and adding the minimum value of the slow peripheral interrupt group to the number of slow peripheral interrupt groups as the maximum value of the slow peripheral interrupt group;

[0027] S602, comparing the minimum value of the slow peripheral interrupt hardwired line plus the slow peripheral interrupt group with the maximum value of the slow peripheral interrupt group;

[0028] S603: If the speed is less than the maximum value of the slow peripheral interrupt group, then the routing information is obtained and sent to the designated processor core for processing via the on-chip network and the high-speed interconnect interface, and the process jumps to step S604; if the speed is greater than the maximum value of the slow peripheral interrupt group, then an error is reported, and the process ends and exits.

[0029] S604: The processor core acknowledges the interrupt and returns a response, and the interrupt controller sets the interrupt status to active.

[0030] S605, the processor core completes the processing and clears the active state of the interrupt;

[0031] Step S102 also includes dispatching the interrupt to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnect interface according to the interrupt route configured in the routing table when the interrupt is a high-speed peripheral interrupt, including:

[0032] S701, obtaining the physical interrupt number and routing of the high-speed peripheral interrupt through the interrupt converter in the interrupt controller;

[0033] S702, the interrupt controller sends the information to the corresponding management chip through the on-chip network and the high-speed interconnection interface according to the routing information;

[0034] S703, read the interrupt configuration table to obtain the enable and priority information of the high-speed peripheral interrupt;

[0035] S704, the interrupt controller sends the interrupt to the designated processor core for processing;

[0036] S705, the processor core acknowledges the interrupt, and the interrupt controller clears the pending state of the high-speed peripheral interrupt;

[0037] Step S102 also includes dispatching the interrupt to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnect interface according to the interrupt route configured in the routing table when the interrupt is a software interrupt, including:

[0038] S801: The interrupt controller receives a command to generate a software interrupt and returns a response to the processor core that initiated the software interrupt.

[0039] S802, the interrupt controller sends the software interrupt to the designated processor core for processing according to the routing information;

[0040] S803: The processor core acknowledges the interrupt and returns a response, and the interrupt controller sets the interrupt status to active.

[0041] S804: The processor core completes the processing and clears the active state of the interrupt.

[0042] In addition, the present invention also provides a device for supporting consistent multi-chip interconnection interruption, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the method for supporting consistent multi-chip interconnection interruption.

[0043] In addition, the present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is used to be programmed or configured by a microprocessor to execute the method for supporting consistent multi-chip interconnect interruption.

[0044] Compared with the prior art, the present invention mainly has the following advantages: the present invention includes adding multiple chip registers to realize the configuration of any number of chips. After the number of chips is configured, the corresponding parameters, cross-chip address bit width and routing table depth will change accordingly. In addition, in order to support the connection and consistency management of multiple chips, the register address space of the chip register is expanded. First, the chip default register is configured to specify a chip management consistency. Secondly, the chip register is configured to configure the slow peripheral interrupt group of this chip. The connection of all chips is completed in turn, and the interrupt is initiated. It is sent to the corresponding processor core for processing according to its routing configuration. The processor core calls the interrupt handler to perform interrupt response processing and return interrupt confirmation. The present invention can support the current multi-chip interrupt consistency maintenance, realize interrupt processing across any number of chips, and thus improve the performance of the processor. At the same time, it has the advantages of low hardware implementation complexity, small area overhead, and high cost performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Schematic diagram of the basic process of the method of the embodiment of the present invention.

[0046] Figure 2 Schematic diagram of the system topology in an embodiment of the present invention.

[0047] Figure 3 Schematic diagram of multiple registers in an embodiment of the present invention.

[0048] Figure 4 This is a schematic diagram of the routing in the embodiment of the present invention.

[0049] Figure 5 Schematic diagram of routing table storage information in an embodiment of the present invention.

[0050] Figure 6 Schematic diagram of the private peripheral interrupt processing flow in an embodiment of the present invention.

[0051] Figure 7 2 is a schematic diagram of a slow peripheral interrupt processing flow in an embodiment of the present invention.

[0052] Figure 8 2 is a schematic diagram of a high-speed peripheral interrupt processing flow in an embodiment of the present invention.

[0053] Figure 9 Schematic diagram of the software interrupt processing flow in an embodiment of the present invention.

[0054] Figure 10 Schematic diagram of the microprocessor connection topology of two sockets in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] like Figure 1 As shown, the method for supporting consistent multi-chip interconnect interruption in this embodiment includes:

[0056] S101, configure the number of supported chips through registers, set the chip's cross-chip parameters to determine the address of each chip and the depth of the routing table; designate a chip responsible for managing consistency as the management chip, configure routing tables for each chip based on the depth of the routing table configured by registers, connect all chips to each other, and specify the number of slow peripheral interrupts each chip is responsible for managing; to achieve complete consistency of multi-chip configuration, this embodiment configures the number of supported chips through registers and sets related cross-chip parameters. This embodiment specifies which chip is responsible for managing consistency, configures the routing table, specifies the number of slow peripheral interrupts each chip is responsible for managing, and connects all chips to each other;

[0057] S102, when the interrupt controller of a chip receives an interrupt, it dispatches it to the processor core in the corresponding management chip or directly to the processor core in the chip through the on-chip network and high-speed interconnect interface according to the interrupt route configured in the routing table; the processor core calls the interrupt handler to process it and returns an interrupt confirmation, such as Figure 2 As shown, chip0 and chip1 represent two different chips. Figure 2 The example of two chips is used for illustration only, but the method of this embodiment is applicable to the case where multiple chips are interconnected. Figure 2The microprocessor of this embodiment includes multiple chips, each of which includes an interrupt controller, an on-chip network, multiple processor cores, and a high-speed interconnect interface. The interrupt controller is connected to multiple slow peripherals and high-speed peripherals, and the interrupt controller is connected to multiple processor cores via the on-chip network. To achieve complete consistency in the connection and configuration of multiple chips, in this embodiment, the following configurations of the management chip and the remaining chips remain consistent: the bit width of the routing attribute, the total number of slow peripheral interrupt groups, whether high-speed peripheral interrupts are supported, the security disable setting, the total number of chips supported, the chip address bit width, the number of chip routing attribute layers, and the number of cores supported by each chip.

[0058] like Figure 3 As shown, in this embodiment, a 32-bit multi-chip register is defined. The register field is chip_num, which is used to identify the number of supported chips. After configuring chip_num, you can execute:

[0059] S201, set the number of supported chips according to chip_num;

[0060] S202, setting the bit width of the cross-chip address according to the number of supported chips;

[0061] S203: Set the depth of the routing table.

[0062] In this embodiment, the routing table configured in step S101 is composed of a group of registers that specify the connection relationship between any number of chips, where the configured information includes: a chip register, which is used to describe the address for controlling cross-chip routing during cross-chip transmission, the starting value of the slow peripheral interrupt group managed by the chip, the number of slow peripheral interrupt groups managed by the chip, the status of routing table updates, the connection status of the chip, and other information; a chip default register, which is used to describe the chip responsible for managing consistency, the routing table update status, and other information; a chip status register, which is used to describe information such as the consistency status of the routing table.

[0063] Configuring the routing table and connecting all chips to each other in step S101 includes:

[0064] S301, configure the chip default register and designate a chip to be responsible for consistency management;

[0065] S302, configuring the chip register responsible for managing the consistency chip and specifying the slow peripheral interrupt group managed by the chip;

[0066] S303: Read the chip status register of the chip responsible for managing consistency until the routing table is in a consistent state; read the number of chips supported by the register configuration, and determine the addresses of each chip based on the chip's cross-chip parameters. Traverse and select a chip from the set of chips other than the management chip as the chip to be connected;

[0067] S304, configuring the chip register of the chip to be connected;

[0068] S305, reading the chip default register until the routing table is updated and the chip to be connected is determined to be connected;

[0069] S306, determine whether there are still chips in the chip set other than the management chip that have not been traversed. If there are still chips that have not been traversed, continue to traverse the chip set other than the management chip and select one chip as the chip to be connected, and jump to step S304; otherwise, determine that all chips are connected to each other.

[0070] like Figure 4 As shown, in this embodiment, the routing table is stored inside the interrupt controller. In order to maintain consistency among multiple chips, each chip has a copy of the routing table (Chip0~Chipn), which is used to record the allocation of slow peripheral interrupt groups, connection status, consistency status, etc. of each chip, as shown in FIG. Figure 5 As shown, the chip number occupies [7:0] for a total of 8 bits, the minimum value of the slow peripheral interrupt group occupies [15:8] for a total of 8 bits, the number of slow peripheral interrupt groups occupies [23:16] for a total of 8 bits, the chip number of the management chip occupies [28:24] for a total of 5 bits, the connection status occupies

[29] for a total of 1 bit, and the consistency status occupies [31:30] for a total of 2 bits, for a total of 32 bits. The routing table configuration information in each chip must always remain consistent, and the slow peripheral interrupt group allocation information and connection status of any chip will change. When the slow peripheral interrupt group allocation information and connection status of any chip change, the synchronization operation of the routing table copy is triggered:

[0071] S401, the chip whose slow peripheral interrupt group allocation information and connection status configuration has changed sends its configuration information to the chip responsible for consistency management;

[0072] S402, after receiving the request, the chip responsible for consistency management updates the routing table;

[0073] S403: The chip responsible for consistency management sends the new routing table information to all connected chips to update the copy of the routing table inside the interrupt controller of each chip.

[0074] In this embodiment, the processing of private peripheral interrupts, slow peripheral interrupts, high-speed peripheral interrupts, and software interrupt type interrupts is supported, wherein slow peripheral interrupts, high-speed peripheral interrupts, and software interrupt type interrupts support cross-chip processing. In step S102 of this embodiment, when the interrupt controller of a certain chip receives an interrupt, it includes determining the type of interrupt. If the interrupt type is a slow peripheral interrupt, a high-speed peripheral interrupt, or a software interrupt type interrupt, the interrupt is determined to be a cross-chip interrupt and is dispatched to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnect interface according to the interrupt route configured in the routing table; otherwise, if the interrupt type is a private peripheral interrupt, the interrupt is determined to be a non-cross-chip interrupt and is directly dispatched to the processor core in the current chip according to the interrupt route configured in the routing table.

[0075] like Figure 6 As shown, step S102 also includes dispatching the interrupt directly to the processor core in the current chip according to the interrupt route configured in the routing table when the interrupt is a non-cross-chip interrupt (private peripheral interrupt), including:

[0076] S501, the interrupt processor processes the interrupt according to the processor core that initiated the private peripheral interrupt;

[0077] S502: The processor core acknowledges the interrupt and returns a response, and the interrupt controller sets its state to active.

[0078] S503: The processor core completes the processing and clears the interrupt active state.

[0079] In this embodiment, the configuration of the routing table mainly affects the processing of slow peripheral interrupts. The routing table groups multiple slow peripheral interrupts into a group, specifically 32 slow peripheral interrupts into a group, and supports 960 slow peripheral interrupts, that is, supports 30 slow peripheral interrupt groups.

[0080] like Figure 7 As shown, step S102 also includes dispatching the interrupt to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnection interface according to the interrupt route configured in the routing table when the interrupt is a slow peripheral interrupt, including:

[0081] S601, obtaining configuration information of the slow peripheral interrupt group of the current chip, and adding the minimum value of the slow peripheral interrupt group to the number of slow peripheral interrupt groups as the maximum value of the slow peripheral interrupt group;

[0082] S602, comparing the minimum value of the slow peripheral interrupt hardwired line plus the slow peripheral interrupt group with the maximum value of the slow peripheral interrupt group;

[0083] S603: If the value is less than the maximum value of the slow peripheral interrupt group, then obtain routing information, send it to the designated processor core for processing, and jump to step S604; if the value is greater than the maximum value of the slow peripheral interrupt group, then report an error, end, and exit;

[0084] S604: The processor core acknowledges the interrupt and returns a response, and the interrupt controller sets its state to active.

[0085] S605: The processor core completes the processing and clears the interrupt active state.

[0086] like Figure 8 As shown, step S102 also includes dispatching the interrupt to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnection interface according to the interrupt route configured in the routing table when the interrupt is a high-speed peripheral interrupt, including:

[0087] S701, obtaining the physical interrupt number and routing of the high-speed peripheral interrupt through the interrupt converter in the interrupt controller;

[0088] S702, the interrupt controller sends the message to the corresponding chip according to the routing;

[0089] S703, read the interrupt configuration table to obtain the enable and priority information of the high-speed peripheral interrupt;

[0090] S704, the interrupt controller sends the signal to a designated processor core for processing;

[0091] S705: The processor core acknowledges the interrupt and the interrupt controller clears the interrupt pending state.

[0092] like Figure 9 As shown, step S102 of this embodiment also includes dispatching the interrupt to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnection interface according to the interrupt route configured in the routing table when the interrupt is a software interrupt, including:

[0093] S801: The interrupt controller receives a command to generate a software interrupt and returns a response to the processor core that initiated the software interrupt.

[0094] S802, the interrupt controller sends the software interrupt to the designated processor core for processing according to the routing information;

[0095] S803: The processor core acknowledges the interrupt and returns a response, and the interrupt controller sets its state to active.

[0096] S804: The processor core completes the processing and clears the interrupt active state.

[0097] In summary, the method of this embodiment includes adding multiple chip registers to realize the configuration of any number of chips. After the number of chips is configured, the corresponding parameters, cross-chip address bit width and routing table depth will change accordingly. In addition, in order to support the connection and consistency management of multiple chips, the register address space of the chip register is expanded. First, the chip default register is configured to specify a chip management consistency. Secondly, the chip register is configured to configure the slow peripheral interrupt group of this chip, and the connection of all chips is completed in turn. The interrupt is initiated and sent to the corresponding processor core for processing according to its routing configuration. The processor core calls the interrupt handler to perform interrupt response processing and return interrupt confirmation. The method of this embodiment can support the maintenance of multi-chip interrupt consistency in the current multi-chip, can realize interrupt processing across any number of chips, and thus improve the performance of the processor. At the same time, it has the advantages of low hardware implementation complexity, small area overhead and high cost performance.

[0098] In addition, the present invention also provides a device for supporting high-speed peripheral message interruption, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the method for supporting consistent multi-chip interconnection interruption. Figure 10 As shown, multiple chips in the same socket Scoket or multiple chips in different socket Scokets are connected through multiple high-speed interconnection interfaces. Figure 10 Specifically, the invention relates to a microprocessor with two sockets Scoket, each microprocessor includes four chips chip0 to chip3, wherein the interrupt controller of each chip is programmed or configured to execute the method for supporting consistent multi-chip interconnection interrupt.

[0099] In addition, the present invention also provides a computer-readable storage medium, in which a computer program is stored. The computer program is used to be programmed or configured by a microprocessor to execute the method for supporting consistent multi-chip interconnect interruption.

[0100] Those skilled in the art should understand that the technical solution provided by the present invention may be in the form of a method, a system, or a computer program product. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions described in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including the instruction device, which implements the function specified in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0101] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for supporting consistent multi-chip interconnect interruption, characterized in that: include: S101, configure the number of supported chips through registers, set the chip's cross-chip parameters to determine the address of each chip and the depth of the routing table; designate a chip responsible for consistency management as the management chip, configure routing tables for each chip according to the depth of the routing table configured by the registers, connect all chips to each other, and specify the number of slow peripheral interrupts that each chip is responsible for managing; S102, when the interrupt controller of a chip receives an interrupt, it dispatches the interrupt to the processor core in the corresponding management chip or directly to the processor core in the chip itself via the on-chip network or high-speed interconnect interface according to the interrupt route configured in the routing table; the processor core calls the interrupt handler to process the interrupt and returns an interrupt confirmation; The routing table is stored inside the interrupt controller, and each chip has a copy of the routing table. The information of the copy of the routing table in each chip must always be consistent. When the slow peripheral interrupt group allocation information or connection status of any chip changes, the synchronization operation of the copy of the routing table is triggered: S401, the chip where the slow peripheral interrupt group allocation information and connection status configuration change occurs sends its configuration information to the management chip responsible for consistency management; S402, after receiving the request, the management chip responsible for consistency management updates the routing table; S403, the management chip responsible for consistency management sends the new routing table information to all connected chips to update the copy of the routing table inside the interrupt controller of each chip; The routing table groups multiple slow peripheral interrupts into one group. Step S102 further includes dispatching the interrupt to the corresponding processor core in the management chip through the on-chip network and the high-speed interconnect interface according to the interrupt route configured in the routing table when the interrupt is a slow peripheral interrupt. S601, obtaining configuration information of the slow peripheral interrupt group of the current chip, and adding the minimum value of the slow peripheral interrupt group to the number of slow peripheral interrupt groups as the maximum value of the slow peripheral interrupt group; S602, comparing the minimum value of the slow peripheral interrupt hardwired line plus the slow peripheral interrupt group with the maximum value of the slow peripheral interrupt group; S603: If the speed is less than the maximum value of the slow peripheral interrupt group, then the routing information is obtained and sent to the designated processor core for processing via the on-chip network and the high-speed interconnect interface, and the process jumps to step S604; if the speed is greater than the maximum value of the slow peripheral interrupt group, then an error is reported, and the process ends and exits. S604: The processor core acknowledges the interrupt and returns a response, and the interrupt controller sets the interrupt status to active. S605: The processor core completes the processing and clears the active state of the interrupt.

2. The method for supporting consistent multi-chip interconnect interruption according to claim 1, characterized in that: The following configurations of the management chip and the remaining chips remain consistent: the bit width of the routing attribute, the total number of slow peripheral interrupt groups, whether high-speed peripheral interrupts are supported, security disable settings, the total number of chips supported, the chip address bit width, the number of routing attribute layers of the chip, and the number of cores supported by each chip.

3. The method for supporting consistent multi-chip interconnect interruption according to claim 2, characterized in that: The routing table configured in step S101 is composed of a set of registers that specify the connection relationship between any number of chips, wherein the configured information includes: chip registers, which are used to describe the address for controlling cross-chip routing during cross-chip transmission, the starting value of the slow peripheral interrupt group managed by the chip, the number of slow peripheral interrupt groups managed by the chip, the status of routing table updates, and the chip connection status; chip default registers, which are used to describe the management chip responsible for managing consistency and information about the routing table update status; chip status registers, which are used to describe the routing table consistency status. Configuring the routing table and connecting all chips to each other in step S101 includes: S301, configure the chip default register and designate a management chip to be responsible for managing consistency; S302, configuring the chip register responsible for managing the consistency chip and specifying the slow peripheral interrupt group managed by the chip; S303: Read the chip status register of the chip responsible for managing consistency until the routing table is in a consistent state; read the number of chips supported by the register configuration, and determine the addresses of each chip based on the chip's cross-chip parameters. Traverse and select a chip from the set of chips other than the management chip as the chip to be connected; S304, configuring the chip register of the chip to be connected; S305, reading the chip default register until the routing table is updated and the chip to be connected is determined to be connected; S306, determine whether there are still chips in the chip set other than the management chip that have not been traversed. If there are still chips that have not been traversed, continue to traverse the chip set other than the management chip and select one chip as the chip to be connected, and jump to step S304; otherwise, determine that all chips are connected to each other.

4. The method for supporting consistent multi-chip interconnect interruption according to claim 1, wherein: In step S102, when the interrupt controller of a certain chip receives an interrupt, it includes determining the type of interrupt. If the interrupt type is a slow peripheral interrupt, a high-speed peripheral interrupt, or a software interrupt type interrupt, the interrupt is determined to be a cross-chip interrupt and is dispatched to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnection interface according to the interrupt route configured in the routing table; otherwise, if the interrupt type is a private peripheral interrupt, the interrupt is determined to be a non-cross-chip interrupt and is directly dispatched to the processor core in the current chip according to the interrupt route configured in the routing table.

5. The method for supporting consistent multi-chip interconnect interruption according to claim 4, characterized in that: Step S102 also includes dispatching the interrupt directly to the processor core in the current chip according to the interrupt route configured in the routing table when the interrupt is not a cross-chip interrupt, including: S501, the interrupt controller in the chip processes the interrupt by sending the interrupt to the processor core that initiates the private peripheral interrupt in the chip; S502: The processor core acknowledges the interrupt and returns a response, and the interrupt controller sets its state to active. S503: After the processor core completes the processing, the active state of the interrupt is cleared.

6. The method for supporting consistent multi-chip interconnect interruption according to claim 4, characterized in that: Step S102 also includes dispatching the interrupt to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnect interface according to the interrupt route configured in the routing table when the interrupt is a high-speed peripheral interrupt, including: S701, obtaining the physical interrupt number and routing of the high-speed peripheral interrupt through the interrupt converter in the interrupt controller; S702, the interrupt controller sends the information to the corresponding management chip through the on-chip network and the high-speed interconnection interface according to the routing information; S703, read the interrupt configuration table to obtain the enable and priority information of the high-speed peripheral interrupt; S704, the interrupt controller sends the interrupt to the designated processor core for processing; S705, the processor core acknowledges the interrupt, and the interrupt controller clears the pending state of the high-speed peripheral interrupt; Step S102 also includes dispatching the interrupt to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnect interface according to the interrupt route configured in the routing table when the interrupt is a software interrupt, including: S801: The interrupt controller receives a command to generate a software interrupt and returns a response to the processor core that initiated the software interrupt. S802, the interrupt controller sends the software interrupt to the designated processor core for processing according to the routing information; S803: The processor core acknowledges the interrupt and returns a response, and the interrupt controller sets the interrupt status to active. S804: The processor core completes the processing and clears the active state of the interrupt.

7. A device supporting consistent multi-chip interconnect interruption, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the method for supporting consistent multi-chip interconnect interruption according to any one of claims 1 to 6.

8. A computer-readable storage medium storing a computer program, wherein: The computer program is used to be programmed or configured by a microprocessor to execute the method for supporting consistent multi-chip interconnect interruption according to any one of claims 1 to 6.

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