AHB bus-based UART communication realization method and system
By directly realizing communication between UART modules under the AHB bus protocol, the problem of UART module design complexity in low-speed peripherals is solved, more stable and efficient data transmission is achieved, and chip design resources are saved.
Patent Information
- Application Number
- CN202510127286.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-03
- Publication Date
- 2025-05-27
AI Technical Summary
In some special customization fields, when low-speed peripherals only have one UART module, the introduction of AHB to APB conversion bridges appears redundant, increasing the complexity of system design and unnecessary functional expenses.
By directly implementing communication between UART modules under the AHB bus protocol, avoiding protocol conversion using bridges, simplifying hardware design and reducing unnecessary expenses.
It improves the stability and real-time nature of data transmission, reduces unnecessary expenses in specific chip designs, and saves chip design area.
Smart Images
Figure CN120045490A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and particularly to an implementation method and system for UART communication based on the AHB bus. Background Art
[0002] The AHB (Advanced High-performance Bus) protocol has functions such as complex burst transmission and multi-master arbitration. The protocol is relatively complex, with high data transmission efficiency, and is suitable for communication between high-performance modules. The APB protocol is relatively simple, mainly used to connect low-speed peripherals, and does not support complex functions such as burst transmission. Under normal circumstances, a bridge is required to implement communication between the AHB and APB protocols. The bridge has two interfaces, one connected to the AHB bus and the other connected to the APB bus. It is responsible for signal conversion, data format conversion, and protocol conversion between the two buses. This conversion process not only increases the complexity of the system but may also affect the stability and real-time performance of data transmission.
[0003] In some special customized fields, low-speed peripherals often do not require a variety of functional modules. When there is only one UART module, introducing an AHB to APB conversion bridge at this time seems redundant, increasing unnecessary functional expenses and the complexity of system design.
[0004] Based on this, a new technical solution is needed. Summary of the Invention
[0005] To overcome the above problems, this application proposes a UART communication method based on the AHB bus. By directly implementing communication between UART modules under the AHB bus protocol, the complexity of using a bridge for protocol conversion is avoided, thereby improving the stability and real-time performance of data transmission, reducing unnecessary expenses in specific chip designs, and saving chip design area.
[0006] To achieve the above objects and other advantages of the present invention, the embodiments of this specification provide the following technical solutions: The first object of the present invention is to provide an implementation method for UART communication based on the AHB bus, which is applied to an ARM host, a RAM slave, an AHB bus, and a UART module. The UART module includes a UART host, a UART slave, a UART transmission module, and a UART reception module, and specifically includes the following steps: The ARM host outputs the operation address for writing to the UART to the HADDR of the AHB bus at the rising edge of T0, and outputs the write operation information to the Control of the AHB bus; At the rising edge of T1, the UART slave receives the operation address for writing to the UART and the write operation information, and prepares for an acknowledgment. The ARM host prepares the data to be written to the UART through HWDATA of the AHB bus. The UART slave finishes preparing for the acknowledgment and changes the HREADY signal on the bus. At the rising edge of T2, the UART slave obtains the data to be written to the UART from HWDATA. At the rising edge of T3, the UART transmission module sends the data to be written to the UART out through the TXD pin in the manner of the UART protocol, completing the write operation of the UART communication based on the AHB bus protocol.
[0007] Further, before the rising edge of T0, it also includes: The ARM host sends a request to access the UART slave to the AHB bus. The UART slave responds to the request through the AHB bus, and then the ARM host obtains the permission to access the UART slave.
[0008] Further, it also includes: There is one clock cycle between the rising edge of T0 and the rising edge of T1; there is at least one clock cycle between the rising edge of T1 and the rising edge of T2; there is at least one clock cycle between the rising edge of T2 and the rising edge of T3.
[0009] The second object of the present invention is to provide a method for implementing UART communication based on the AHB bus, which is applied to an ARM host, a RAM slave, an AHB bus, and a UART module. The UART module includes a UART host, a UART slave, a UART transmission module, and a UART reception module, and specifically includes the following steps: At the rising edge of T5, the UART host writes the operation address of the RAM to the output of HADDR of the AHB bus and writes the write operation information to the Control of the AHB bus. At the rising edge of T6, the RAM slave receives the operation address for writing to the RAM and the write operation information, and prepares for an acknowledgment. The UART host prepares the data obtained from TXD through HWDATA of the AHB bus. The RAM slave finishes preparing for the acknowledgment and changes the HREADY signal on the bus. At the rising edge of T7, the RAM slave receives the data obtained from TXD from HWDATA of the AHB bus and stores the data obtained from TXD in a register. The ARM host obtains the data obtained from TXD through the AHB bus, completing the read operation of the UART communication based on the AHB bus protocol.
[0010] Further, before the rising edge of T5, it also includes: From the rising edge of T4 to the rising edge of T5, the RXD pin of the UART receiving module receives the communication signal input by the UART; the UART host sends a request to occupy the bus to access the RAM slave through the AHB bus, and the RAM slave responds to the request through the AHB bus, then the UART host obtains the permission to access the RAM slave.
[0011] Further, it also includes: There are multiple clock cycles between the rising edge of T4 and the rising edge of T5; there is one clock cycle between the rising edge of T5 and the rising edge of T6; there is at least one clock cycle between the rising edge of T6 and the rising edge of T7.
[0012] The third object of the present invention is to provide an implementation system for UART communication based on the AHB bus, which is applied to an ARM host, a RAM slave, an AHB bus, and a UART module. The UART module includes a UART host, a UART slave, a UART sending module, and a UART receiving module, and specifically includes: An access request unit, specifically including: the ARM host sends a request to access the UART slave to the AHB bus; the UART slave responds to the request through the AHB bus, then the ARM host obtains the permission to access the UART slave; A data writing unit, specifically including: at the rising edge of T0, the ARM host outputs the operation address for writing the UART to the HADDR of the AHB bus, and outputs the write operation information to the Control of the AHB bus; At the rising edge of T1, the UART slave receives the operation address for writing the UART and the write operation information, and prepares for an answer. The ARM host prepares the data to be written to the UART through the HWDATA of the AHB bus; The UART slave completes the answer preparation and changes the HREADY signal on the bus; at the rising edge of T2, the UART slave obtains the data to be written to the UART from the HWDATA; A data transmission unit, specifically including: at the rising edge of T3, the UART sending module sends the data to be written to the UART outward in the form of a UART protocol through the TXD pin, and completes the UART communication write operation based on the AHB bus protocol.
[0013] Further, it also includes: The rising edge moment of T0 is separated from the rising edge moment of T1 by one clock cycle; the rising edge moment of T1 is separated from the rising edge moment of T2 by at least one clock cycle; the rising edge moment of T2 is separated from the rising edge moment of T3 by at least one clock cycle.
[0014] The fourth object of the present invention is to provide an implementation system for UART communication based on the AHB bus, which is applied to an ARM host, a RAM slave, an AHB bus, and a UART module. The UART module includes a UART host, a UART slave, a UART transmission module, and a UART reception module, and specifically includes: An access request unit, specifically including: from the rising edge moment of T4 to the rising edge moment of T5, the RXD pin of the UART reception module receives a UART communication signal; the UART host sends a request to the AHB bus to occupy the bus to access the RAM slave, and if the RAM slave responds to the request through the AHB bus, then the UART host obtains the permission to access the RAM slave.
[0015] A data acquisition unit, specifically including: at the rising edge moment of T5, the UART host writes the operation address of the RAM to the output of the AHB bus HADDR, and writes the write operation information to the Control of the AHB bus; At the rising edge moment of T6, the RAM slave receives the operation address of the write RAM and the write operation information, and prepares for an answer. The UART host prepares the data obtained by TXD through the HWDATA of the AHB bus; A data reading unit, specifically including: the RAM slave completes the answer preparation and changes the HREADY signal on the bus; at the rising edge moment of T7, the RAM slave receives the data obtained by TXD from the HWDATA of the AHB bus, and stores the data obtained by TXD in a register; The ARM core obtains the data obtained by TXD through the AHB bus, and completes the UART communication read operation based on the AHB bus protocol.
[0016] Furthermore, it further includes: The rising edge moment of T4 is separated from the rising edge moment of T5 by multiple clock cycles; the rising edge moment of T5 is separated from the rising edge moment of T6 by one clock cycle; the rising edge moment of T6 is separated from the rising edge moment of T7 by at least one clock cycle. The second object of the present invention is to provide a system that applies a method.
[0017] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the embodiments of this specification at least include: The ARM host realizes the communication write operation and / or read operation with the UART module through the AHB bus, avoiding the use of a bridge, simplifying the hardware design, reducing unnecessary expenses in specific chip designs, and saving chip design area. Brief Description of the Drawings
[0018] To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0019] Figure 1 It is a schematic structural diagram of an implementation method of UART communication based on the AHB bus provided by an embodiment of the present invention; Figure 2 It is a flowchart of a communication write operation method in an implementation method of UART communication based on the AHB bus provided by an embodiment of the present invention; Figure 3 It is a timing diagram of a communication write operation in an implementation method of UART communication based on the AHB bus provided by an embodiment of the present invention; Figure 4 It is a flowchart of a communication read operation method in an implementation method of UART communication based on the AHB bus provided by an embodiment of the present invention; Figure 5 It is a timing diagram of a communication read operation in an implementation method of UART communication based on the AHB bus provided by an embodiment of the present invention; Figure 6 It is a schematic structural diagram of a communication write operation in an implementation system of UART communication based on the AHB bus provided by an embodiment of the present invention; Figure 7 It is a schematic structural diagram of a communication read operation in an implementation system of UART communication based on the AHB bus provided by an embodiment of the present invention; Detailed Description of the Embodiments
[0020] The embodiments of the present application will be described in detail below with reference to the drawings.
[0021] The following describes the implementation modes of the present application through specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all embodiments. The present application can also be implemented or applied through other different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope protected by the present application.
[0022] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects described herein can be used to implement the device and / or practice the method. Additionally, this device and / or this method can be implemented using other structures and / or functions in addition to one or more of the aspects described herein. Embodiment
[0023] This embodiment of the specification proposes a method for implementing UART communication based on the AHB bus, as Figure 1 , applied to an ARM host 100, a RAM slave 200, an AHB bus 300, and a UART module 400, where the UART module 400 includes a UART host 403, a UART slave 401, a UART transmission module 402, and a UART reception module 404, as Figure 2 , specifically including the following steps: S10: At the rising edge of T0, the ARM host outputs the operation address for writing to the UART to the HADDR of the AHB bus, and outputs the write operation information to the Control of the AHB bus; As Figure 3 , the rising edge of T0 refers to the moment when the clock signal of the ARM host changes from low level to high level, marking the start of the write operation. The HADDR signal provides the target address for the write operation to ensure the accuracy of data transmission. The Control signal carries the operation type information, and the operation type information here is to guide the AHB bus to perform the corresponding write operation.
[0024] S11: At the rising edge of T1, the ARM host prepares the data to be written to the UART through HWDATA of the AHB bus; The HWDATA signal includes the data content to be written, ensuring that the data is transmitted to the UART module completely and correctly. The rising edge of T1 marks that the data is ready, laying the foundation for the subsequent write operation.
[0025] In this embodiment, the data content to be written by the HWDATA signal is the data to be written to the UART.
[0026] The rising edge of T0 and the rising edge of T1 are separated by one clock cycle, ensuring the synchronization and stability of data transmission.
[0027] S12: The UART slave completes the response preparation and changes the HREADY signal on the bus; at the rising edge of T2, the UART slave obtains the data to be written to the UART from HWDATA; After receiving the address and write control signal, the UART slave will perform some internal preparation work, such as preparing the data buffer and checking whether its own status allows receiving data. During this process, the HREADY signal is usually low, indicating that the UART slave is not ready yet. When the UART slave completes the preparation work and can receive the data sent by the ARM host, it will set the HREADY signal to high and feedback it to the master device through the bus.
[0028] The rising edge of T2 marks the start of data reception, ensuring that the UART slave accurately obtains the data in the HWDATA signal and completes the write operation.
[0029] It should be noted that the rising edge of T1 and the rising edge of T2 are separated by at least one clock cycle to ensure that the UART slave has enough time to complete the internal preparation and avoid data transmission errors. This timing design enhances the stability of the system and the reliability of data transmission, reflecting a fine hardware cooperation mechanism.
[0030] S13: At the rising edge of T3, the UART transmission module sends the data to be written to the UART outward through the TXD pin in the manner of the UART protocol, completing the UART communication write operation based on the AHB bus protocol.
[0031] The rising edge of T3 marks the start of data transmission. The TXD pin sends data bit by bit according to the UART protocol, ensuring that the data is transmitted stably at the predetermined format and baud rate until all data bits (start bit, data bit, parity bit, and stop bit) are completely sent. This process strictly follows the UART protocol specification, not only ensuring the integrity of the data, but also improving the anti-interference ability of the system, making the data transmission still stable and reliable even in a complex environment.
[0032] The time interval between the rising edge of T2 and the rising edge of T3 is at least one clock cycle. That is, there is no specific requirement for the starting time of sending data. In this embodiment, it is assumed that the data is sent immediately in the next clock cycle after receiving the data.
[0033] It should be noted that before the rising edge of T0, there also includes: The ARM host sends a request to access the UART slave to the AHB bus; the UART slave responds to the request through the AHB bus, and then the ARM host obtains the permission to access the UART slave.
[0034] Before performing the write operation, an access request machine is also required to ensure the orderly nature of permission control and data access.
[0035] In a preferred embodiment, when multiple master devices simultaneously request the bus, this process needs to be implemented through the arbitration mechanism of the AHB bus. The ARM host uses the bus request signal on the AHB bus to indicate to the bus arbiter that it hopes to obtain the bus usage right to access the UART slave. The bus arbiter decides whether to grant the bus usage right to the ARM host when multiple master devices simultaneously request the bus according to the preset arbitration algorithm. If the priority of the ARM host is higher or it is its turn to use the bus according to the arbitration rules, the arbiter will send a bus grant signal to the ARM host. After receiving the bus grant signal, the ARM host indicates that it has obtained the permission to access the UART slave and can start sending an access request to the UART slave on the bus. The arbitration mechanism ensures the reasonable allocation of bus resources, avoids conflicts, and improves the system resource efficiency.
[0036] It can be understood that the ARM host in this embodiment can also be other processors with an AHB bus interface, such as the Cortex-M series, which can achieve efficient communication through a similar mechanism, further expanding the application scenarios. The UART module can also be other low-speed devices such as I2C, SPI, etc. The RAM slave can also be other storage devices with corresponding interfaces, such as DDR, SRAM, etc.
[0037] In this embodiment, the ARM host realizes the communication write operation with the UART module through the AHB bus, avoiding the use of a bridge, simplifying the hardware design, reducing unnecessary expenses in specific chip designs, and saving chip design area. Embodiment
[0038] This embodiment of the specification proposes an implementation method for UART communication based on the AHB bus, such as Figure 1, applied to the ARM host 100, RAM slave 200, AHB bus 300 and UART module 400, where the UART module 400 includes a UART host 403, a UART slave 401, a UART transmit module 402 and a UART receive module 404, as Figure 4 , specifically including the following steps: S20: At the rising edge of T5, the UART host writes the operation address of writing RA M to the output of the HADDR of the AHB bus, and writes the operation information to the Control of the AHB bus; Such as Figure 5 , the rising edge of T5 refers to the moment when the UART host clock signal changes from low level to high level, marking the start of the write operation. The HADDR signal provides the target address for the write operation to ensure the accuracy of data transmission. The Control signal carries the operation type information, and the operation type information here is to guide the AHB bus to perform the corresponding write operation.
[0039] S21: At the rising edge of T6, the RAM slave receives the operation address and write operation information for writing RAM, and prepares for an answer. The UART host prepares the data obtained by TXD through the HWDATA of the AHB bus; The rising edge of T5 and the rising edge of T6 are separated by one clock cycle, ensuring the synchronization and stability of data transmission. After receiving the operation address and write operation information for writing RAM, the RAM slave quickly adjusts its internal state to prepare to receive data, reflecting the high-efficiency response ability of the system.
[0040] S22: The RAM slave completes the answer preparation and changes the HREADY signal on the bus; at the rising edge of T7, the RAM slave receives the data obtained by TXD from the HWDATA of the AHB bus and stores the data obtained by TXD in the register; The rising edge of T6 and the rising edge of T7 are separated by at least one clock cycle, that is, there is no clear requirement for the start time of receiving the data obtained by TXD. The change of the HREADY signal marks the start of data reception.
[0041] The above steps achieve directly storing the data obtained by TXD into the RAM register without additional processing, ensuring the efficiency and real-time nature of data transmission. The change of the HREADY signal marks the completion of data reception, further enhancing the stability and reliability of communication.
[0042] S23: The ARM host reads the data obtained by TXD through the AHB bus to complete the UART communication read operation based on the AHB bus protocol.
[0043] It should be noted that before the rising edge of T5, it also includes: From the rising edge of T4 to the rising edge of T5, the RXD pin of the UART receiving module receives the communication signal input by the UART; the UART host sends a request to occupy the bus to access the RAM slave through the AHB bus, and the RAM slave responds to the request through the AHB bus, then the UART host obtains the permission to access the RAM slave.
[0044] There are multiple clock cycles between the rising edge of T4 and the rising edge of T5, and the RXD continuously receives data to ensure the integrity of the information. The UART host obtains the access permission first. This process ensures that the communication link is established and the data transmission is ready before the rising edge of T5, improving the communication efficiency.
[0045] It can be understood that the ARM host in this embodiment can also be other processors with an AHB bus interface, such as the Cortex-M series, which can achieve efficient communication through a similar mechanism, further expanding the application scenarios. The UART module can also be other low-speed devices such as I2C and SPI. The RAM slave can also be other storage devices with corresponding interfaces, such as DDR and SRAM.
[0046] In this embodiment, the ARM host realizes the communication read operation with the UART module through the AHB bus, avoiding the use of a bridge, simplifying the hardware design, reducing unnecessary expenses in specific chip designs, and saving the chip design area. Embodiment
[0047] An implementation system 500 for UART communication based on the AHB bus, as Figure 1 , is applied to the ARM host 100, the RAM slave 200, the AHB bus 300, and the UART module 400, where the UART module 400 includes the UART host 403, the UART slave 401, the UART sending module 402, and the UART receiving module 404, as Figure 6 , specifically including: An access request unit 501, specifically including: the ARM host sends a request to access the UART slave through the AHB bus; the UART slave responds to the request through the AHB bus, then the ARM host obtains the permission to access the UART slave; A data writing unit 502, specifically including: the ARM host outputs the operation address for writing to the UART to the HADDR of the AHB bus at the rising edge of T0, and outputs the write operation information to the Control of the AHB bus; At the rising edge of T1, the UART slave receives the operation address for writing to the UART and the write operation information, and prepares for an answer. The ARM host prepares the data to be written to the UART through the HWDATA of the AHB bus; among them, there is one clock cycle between the rising edge of T0 and the rising edge of T1; The UART slave finishes the response preparation and changes the HREADY signal on the bus; at the rising edge of T2, the UART slave obtains the data to be written by the UART from HWDATA; wherein, the rising edge of T1 and the rising edge of T2 are separated by at least one clock cycle. The data transmission unit 503 specifically includes: at the rising edge of T3, the UART transmission module sends the data to be written by the UART out through the TXD pin in the manner of the UART protocol, and completes the UART communication write operation based on the AHB bus protocol. Wherein, the rising edge of T2 and the rising edge of T3 are separated by at least one clock cycle.
[0048] It can be understood that the ARM host in this embodiment can also be other processors with an AHB bus interface, such as the Cortex-M series, which can achieve efficient communication through a similar mechanism, further expanding the application scenarios. The UART module can also be other low-speed devices such as I2C, SPI, etc. The RAM slave can also be other storage devices with corresponding interfaces, such as DDR, SRAM, etc.
[0049] In this embodiment, the ARM host realizes the communication write operation with the UART module through the AHB bus, avoiding the use of a bridge, simplifying the hardware design, reducing unnecessary expenses in specific chip designs, and saving chip design area. Embodiment
[0050] An implementation system 600 for UART communication based on the AHB bus, such as Figure 1 is applied to the ARM host 100, the RAM slave 200, the AHB bus 300 and the UART module 400, wherein the UART module 400 includes a UART host 403, a UART slave 401, a UART transmission module 402 and a UART reception module 404, such as Figure 7 specifically includes: The access request unit 601 specifically includes: from the rising edge of T4 to the rising edge of T5, the RXD pin of the UART reception module receives the UART communication signal; the UART host sends a request to occupy the bus to access the RAM slave to the AHB bus, and the RAM slave responds to the request through the AHB bus, then the UART host obtains the permission to access the RAM slave. Wherein, the rising edge of T4 and the rising edge of T5 are separated by multiple clock cycles; The data acquisition unit 602 specifically includes: at the rising edge of T5, the UART host writes the operation address of the RAM to the output of the AHB bus HADDR and writes the operation information to the Control of the AHB bus; At the rising edge of T6, the RAM slave receives the operation address and write operation information for writing to the RAM, and prepares for an acknowledgment. The UART master prepares the data obtained by TXD through HWDATA on the AHB bus; among them, the rising edge of T5 and the rising edge of T6 are separated by one clock cycle. The data reading unit 603 specifically includes: the RAM slave completes the acknowledgment preparation and changes the HREADY signal on the bus; at the rising edge of T7, the RAM slave receives the data obtained by TXD from HWDATA on the AHB bus and stores the data obtained by TXD into a register; among them, the rising edge of T6 and the rising edge of T7 are separated by at least one clock cycle.
[0051] The ARM core obtains the data obtained by TXD through the AHB bus and completes the UART communication read operation based on the AHB bus protocol.
[0052] It can be understood that the ARM master in this embodiment can also be other processors with an AHB bus interface, such as the Cortex-M series, which can achieve efficient communication through a similar mechanism, further expanding the application scenarios. The UART module can also be other low-speed devices such as I2C, SPI, etc. The RAM slave can also be other storage devices with corresponding interfaces, such as DDR, SRAM, etc.
[0053] In this embodiment, the ARM master realizes the communication read operation with the UART module through the AHB bus, avoiding the use of a bridge, simplifying the hardware design, reducing unnecessary expenses in specific chip designs, and saving chip design area.
[0054] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A method for implementing UART communication based on AHB bus, characterized in that: Applicable to ARM host, RAM slave, AHB bus and UART module, wherein the UART module includes UART host, UART slave, UART sending module and UART receiving module, specifically including the following steps: The ARM host outputs the operation address of writing UART to HADDR of the AHB bus at the rising edge of T0, and outputs the write operation information to Control of the AHB bus; At the rising edge of T1, the UART slave receives the operation address and the write operation information of the write UART, and prepares for response, and the ARM host prepares the data to be written by the UART through the HWDATA of the AHB bus; The UART slave completes the response preparation and changes the HREADY signal on the bus; at the rising edge of T2, the UART slave obtains the data to be written by the UART from HWDATA; At the rising edge of T3, the UART sending module sends the data to be written by the UART to the outside in the UART protocol through the TXD pin, completing the UART communication write operation based on the AHB bus protocol.
2. The method for implementing UART communication based on AHB bus according to claim 1, characterized in that: The method further includes before the rising edge of T0: The ARM host sends a request to the AHB bus to access the UART slave; the UART slave responds to the request through the AHB bus, and the ARM host obtains permission to access the UART slave.
3. The method for implementing UART communication based on AHB bus according to claim 1, characterized in that: Also includes: The rising edge time of T0 is separated from the rising edge time of T1 by one clock cycle; The rising edge time of T1 is separated from the rising edge time of T2 by at least one clock cycle; The T2 rising edge time is separated from the T3 rising edge time by at least one clock cycle.
4. A method for implementing UART communication based on AHB bus, characterized in that: Applicable to ARM host, RAM slave, AHB bus and UART module, wherein the UART module includes UART host, UART slave, UART sending module and UART receiving module, specifically including the following steps: At the rising edge of T5, the UART host outputs the write RAM operation address to the AHB bus HADDR and outputs the write operation information to the AHB bus Control; At the rising edge of T6, the RAM slave receives the operation address of the write RAM and the write operation information, and prepares for response, and the UART host prepares the data obtained by TXD through HWDATA of the AHB bus; The RAM slave completes the response preparation and changes the HREADY signal on the bus; at the rising edge of T7, the RAM slave receives the data obtained by TXD from HWDATA of the AHB bus, and stores the data obtained by TXD into a register; The ARM host obtains the data obtained by the TXD through the AHB bus, and completes the UART communication read operation based on the AHB bus protocol.
5. The method for implementing UART communication based on AHB bus according to claim 4, characterized in that: The method further includes before the rising edge of T5: From the rising edge time of T4 to the rising edge time of T5, the RXD pin of the UART receiving module receives the communication signal input by the UART; the UART host sends a request to the AHB bus to occupy the bus to access the RAM slave, and the RAM slave responds to the request through the AHB bus, then the UART host obtains permission to access the RAM slave.
6. The method for implementing UART communication based on AHB bus according to claim 5, characterized in that: Also includes: The rising edge time of T4 is separated from the rising edge time of T5 by multiple clock cycles; The rising edge time of T5 is separated from the rising edge time of T6 by one clock cycle; The T6 rising edge time is separated from the T7 rising edge time by at least one clock cycle.
7. A UART communication implementation system based on AHB bus, characterized in that: Applicable to ARM host, RAM slave, AHB bus and UART module, where the UART module includes UART host, UART slave, UART sending module and UART receiving module, specifically including: The access request unit specifically includes: the ARM host sends a request to the AHB bus to access the UART slave; the UART slave responds to the request through the AHB bus, and the ARM host obtains permission to access the UART slave; The data writing unit specifically comprises: the ARM host outputs the operation address of writing UART to the HADDR of the AHB bus at the rising edge time of T0, and outputs the writing operation information to the Control of the AHB bus; At the rising edge of T1, the UART slave receives the operation address and the write operation information of the write UART, and prepares for response, and the ARM host prepares the data to be written by the UART through the HWDATA of the AHB bus; The UART slave completes the response preparation and changes the HREADY signal on the bus; at the rising edge of T2, the UART slave obtains the data to be written by the UART from HWDATA; The data transmission unit specifically includes: at the rising edge of T3, the UART sending module sends the data to be written by the UART to the outside in the UART protocol through the TXD pin, completing the UART communication write operation based on the AHB bus protocol.
8. The system for implementing UART communication based on AHB bus according to claim 7, characterized in that: Also includes: The T0 rising edge time is separated from the T1 rising edge time by one clock cycle; the T1 rising edge time is separated from the T2 rising edge time by at least one clock cycle; The T2 rising edge time is separated from the T3 rising edge time by at least one clock cycle.
9. A UART communication implementation system based on AHB bus, characterized in that: Applicable to ARM host, RAM slave, AHB bus and UART module, where the UART module includes UART host, UART slave, UART sending module and UART receiving module, specifically including: The access request unit specifically includes: from the rising edge time of T4 to the rising edge time of T5, the RXD pin of the UART receiving module receives the UART communication signal; the UART host sends a request to the AHB bus to occupy the bus to access the RAM slave, and the RAM slave responds to the request through the AHB bus, and then the UART host obtains permission to access the RAM slave; The data acquisition unit specifically includes: at the rising edge time of T5, the UART host outputs the operation address of writing RAM to the AHB bus HADDR, and outputs the write operation information to the Control of the AHB bus; At the rising edge of T6, the RAM slave receives the operation address of the write RAM and the write operation information, and prepares for response, and the UART host prepares the data obtained by TXD through HWDATA of the AHB bus; The data reading unit specifically includes: the RAM slave completes the response preparation and changes the HREADY signal on the bus; at the rising edge of T7, the RAM slave receives the data obtained by the TXD from the HWDATA of the AHB bus, and stores the data obtained by the TXD into a register; The ARM core obtains the data obtained by the TXD through the AHB bus, and completes the UART communication read operation based on the AHB bus protocol.
10. The system for implementing UART communication based on AHB bus according to claim 9, characterized in that: Also includes: The rising edge time of T4 is separated from the rising edge time of T5 by multiple clock cycles; The rising edge time of T5 is separated from the rising edge time of T6 by one clock cycle; The T6 rising edge time is separated from the T7 rising edge time by at least one clock cycle.